Hardware Design Guide, Revision 3 September 18, 2003 TMXF33625 HypermapperTM 622/155 Mbits/s SONET/SDH x DS3/E3/DS0/E0 1 Introduction The last issue of this data sheet was July 23, 2003. Red change bars have been installed on all text, figures, and tables that were added or changed. All changes to the text are highlighted in red. Changes within figures, and the figure title itself, are highlighted in red, if feasible. See Section 12 on page 73 for a list of changes. The documentation package for the TMXF33625 Hypermapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS0/E0 system chip consists of the following documents: The Register Description and the System Design Guide. These documents are available on a password protected website. The Hypermapper Product Description and the Hypermapper Hardware Design Guide (this document). These documents are available on the public website shown below (select Mappers/MUXes). http://www.agere.com/enterprise_metro_access/index.html This document describes the hardware interfaces of the Agere Systems TMXF33625 Hypermapper device. Information relevant to the use of the device in a board design is covered. Pin descriptions, dc electrical characteristics, timing diagrams, ac timing parameters, packaging, and operating conditions are covered. To contact Agere Systems, see the last page of this document or contact your Agere representative. 622/155 Mbits/s SONET/SDH ADM Front End 622/155Mb/s High-Speed IF DS3/E3/DS1/E1/DS0 PDH Tributary Termination LOPOH Clock & Data W 8 P 8 Clock/Sync 6 24 LOPOH CDR STSPP A CDR STS XC A TMUX-A Clock & Data W 8 P 8 Clock/Sync 6 Clock & Data W 8 P 8 Clock/Sync 6 CDR STSPP B CDR STS XC B B C D A STSPP C CDR STS XC C C CDR STSPP D CDR STS XC B C D Miscellaneous 54 5 JTAG IF B C D 48 (x12) (x24) DS3/E3 (x12) STS-1 B 96 C D 3 1 3 E13 MUX (x12) A B C D A B C D 51 CS A,B,C,D (x12) NSMI (x12) STS-1 (Total of 3 STS-1 max/partition) DS1/J1/E1 VT/TU DS3/E3 144 CHI/PSB 1 M13 MUX (x12) DS1/E1 DJA x28/x21 (x12) DS3/E3 DJA x6 (x4) A B A B C D C D MPU A B C D Mate Interconnect A 168 A AB CD MCDR JTAG VTMPR (x12) x28/x21 D A FRM PLL IF System Interfaces MRXC B D TMUX-D 8 C D STS1LT x12 TMUX-C Clock & Data Partitions (A, B, C, and D) W 8 are totally separate and can- P 8 not be interconnected internally. For example, a Clock/Sync 6 DS1 out of a VTMPR from partition A, cannot be sent to the MRXC of partition B. A 5 CG A B SPEMPR x12 (0-2) TMUX-B CDR TPGM (x4) SPEMPR x12 (3-5) CHI/PSB Rx/Tx Clocks/Syncs FRM (x12) x28/x21 DS1/J1/E1 A B C D From/To TMUX A,B,C,D DS1XCLK, E1XCLK 24 24 4 TOAC POAC MPU IF Figure 1-1. Hypermapper Block Diagram and High-Level Interface Definition 2 DS3XCLK, E3XCLK Power & GND pins not shown 032303 TMXF33625 Hypermapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS0/E0 Hardware Design Guide, Revision 3 September 18, 2003 Table of Contents Contents Page 1 Introduction ........................................................................................................................................................................1 2 Pin Information ...................................................................................................................................................................6 2.1 Ball Diagram ................................................................................................................................................................6 2.2 Pin Assignments ..........................................................................................................................................................7 2.3 Pin Matrix ...................................................................................................................................................................20 2.4 Pin Types ...................................................................................................................................................................24 2.5 Pin Definitions ............................................................................................................................................................25 3 Absolute Maximum Ratings .............................................................................................................................................44 3.1 Handling Precautions ................................................................................................................................................44 4 Electrical Characteristics .................................................................................................................................................45 4.1 Recommended Operating Voltages ..........................................................................................................................45 4.2 Recommended Powerup Sequence ..........................................................................................................................45 4.3 Power Consumption ..................................................................................................................................................45 4.4 ac and dc Characteristics ..........................................................................................................................................46 4.4.1 LVCMOS Interface Characteristics ..................................................................................................................46 4.4.2 LVDS Interface Characteristics ........................................................................................................................48 5 Timing ..............................................................................................................................................................................49 5.1 TMUX High-Speed Interface Timing ..........................................................................................................................49 5.2 THSSYNC Characteristics .........................................................................................................................................50 5.3 STS-3/STM-1 Mate Interconnect Timing ...................................................................................................................51 5.4 TOAC, POAC, and LOPOH Timing ...........................................................................................................................52 5.5 DS3/E3/STS-1 Timing ...............................................................................................................................................53 5.6 NSMI Timing ..............................................................................................................................................................54 5.7 CHI Timing .................................................................................................................................................................58 5.8 Parallel System Bus (PSB) Timing ............................................................................................................................61 6 Reference Clocks ............................................................................................................................................................62 7 Microprocessor Interface Timing .....................................................................................................................................66 7.1 Synchronous Write Mode ..........................................................................................................................................66 7.2 Synchronous Read Mode ..........................................................................................................................................67 7.3 Asynchronous Write Mode ........................................................................................................................................68 7.4 Asynchronous Read Mode ........................................................................................................................................69 7.5 Accessing the Same Register Sequentially Across Multiple Partitions ......................................................................70 8 Other Timing ....................................................................................................................................................................71 9 Hardware Design File References ...................................................................................................................................71 10 Ordering Information ......................................................................................................................................................71 11 1152-Pin PBGA Diagrams ..............................................................................................................................................72 12 Change History ...............................................................................................................................................................73 12.1 Navigating Through an Adobe Acrobat (R) Document ...............................................................................................73 13 Glossary .........................................................................................................................................................................74 14 Appendix ........................................................................................................................................................................75 14.1 Input Capacitances ..................................................................................................................................................75 2 Agere Systems Inc. Hardware Design Guide, Revision 3 September 18, 2003 TMXF33625 Hypermapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS0/E0 Table of Contents (continued) Tables Page Table 2-1. Pin Assignments....................................................................................................................................................7 Table 2-2. Pin Matrix ............................................................................................................................................................20 Table 2-3. Pin Types ............................................................................................................................................................24 Table 2-4. TMUX Blocks, High-Speed Interface I/O.............................................................................................................25 Table 2-5. TMUX Blocks, Protection Link I/O .......................................................................................................................27 Table 2-6. TMUX Blocks, Clock and Sync I/O......................................................................................................................28 Table 2-7. STS Cross Connect (STSXC) Blocks, STS-3/STM-1 Mate Interconnect............................................................29 Table 2-8. Multirate Cross Connect (MRXC) Blocks, TOAC Input and Output Channels ....................................................30 Table 2-9. Multirate Cross Connect (MRXC) Blocks, POAC Input and Output Channels ....................................................31 Table 2-10. DS3/E3/STS-1 Out ............................................................................................................................................32 Table 2-11. DS3/E3/STS-1 In...............................................................................................................................................33 Table 2-12. NSMI/STS-1 In ..................................................................................................................................................34 Table 2-13. NSMI/STS-1 Out ...............................................................................................................................................35 Table 2-14. TDM Concentration Highway (CHI) In...............................................................................................................35 Table 2-15. TDM Concentration Highway (CHI) Out ............................................................................................................36 Table 2-16. Framer (FRM) Blocks, CHI/Parallel System Bus (PSB) Clock and Sync ..........................................................36 Table 2-17. Reference Clocks ..............................................................................................................................................37 Table 2-18. Low-Order Path Overhead Access, Transmit Direction ....................................................................................37 Table 2-19. Low-Order Path Overhead Access, Receive Direction .....................................................................................38 Table 2-20. Clock Generator ................................................................................................................................................38 Table 2-21. Microprocessor Interface...................................................................................................................................38 Table 2-22. Boundary Scan (IEEE 1149.1) ........................................................................................................................40 Table 2-23. General-Purpose Interface ................................................................................................................................40 Table 2-24. CDR Interface....................................................................................................................................................41 Table 2-25. Analog Power and Ground Signals ...................................................................................................................41 Table 2-26. No Connects......................................................................................................................................................42 Table 2-27. Digital Power and Ground Signals ....................................................................................................................42 Table 3-1. Absolute Maximum Ratings.................................................................................................................................44 Table 3-2. ESD Tolerance ....................................................................................................................................................44 Table 4-1. Recommended Operating Conditions .................................................................................................................45 Table 4-2. Typical Power Consumption by Application ........................................................................................................45 Table 4-3. Typical Power Consumption Per Block ...............................................................................................................46 Table 4-4. LVCMOS Inputs Specifications 1 ........................................................................................................................46 Table 4-5. LVCMOS Inputs Specifications 2 ........................................................................................................................47 Table 4-6. LVCMOS Inputs Specifications 3 ........................................................................................................................47 Table 4-7. LVCMOS Outputs Specifications ........................................................................................................................47 Table 4-8. LVCMOS Bidirectionals Specifications................................................................................................................47 Table 4-9. LVDS Interface dc Characteristics ......................................................................................................................48 Table 5-1. High-Speed Interface Inputs Specifications ........................................................................................................49 Table 5-2. Protection Link Inputs Specifications...................................................................................................................49 Table 5-3. High-Speed Interface Outputs Specifications......................................................................................................50 Table 5-4. Protection Link Outputs Specifications................................................................................................................50 Table 5-5. STS-3/STM-1 Mate Interconnect Inputs Specifications.......................................................................................51 Table 5-6. STS-3/STM-1 Mate Interconnect Outputs Specifications....................................................................................51 Table 5-7. TOAC, POAC, and LOPOH Input Specifications ................................................................................................52 Table 5-8. TOAC, POAC, and LOPOH Output Specifications..............................................................................................52 Table 5-9. DS3/E3 Input Specifications................................................................................................................................53 Table 5-10. STS-1 Input Specifications ................................................................................................................................53 Table 5-11. DS3/E3/STS-1 Output Specifications................................................................................................................53 Table 5-12. NSMI Input Specifications .................................................................................................................................57 Table 5-13. NSMI Output Specifications ..............................................................................................................................57 Table 5-14. CHIRXGCLK and CHITXGCLK Timing Specifications......................................................................................58 Table 5-15. CHI Interface Timing Specifications ..................................................................................................................58 Table 5-16. PSB Input Specifications ...................................................................................................................................61 Table 5-17. PSB Output Specifications ................................................................................................................................61 Agere Systems Inc. 3 TMXF33625 Hypermapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS0/E0 Hardware Design Guide, Revision 2 September 18, 2003 Table of Contents (continued) Tables Page Table 6-1. High-Speed Interface Input Clocks Specifications ..............................................................................................62 Table 6-2. Protection Link Input Clock Specifications ..........................................................................................................62 Table 6-3. DS3/E3/STS-1 Input Clocks Specifications.........................................................................................................62 Table 6-4. DS1/E1 DJA Input Clocks Specifications ............................................................................................................62 Table 6-5. DS3/E3 DJA Input Clocks Specifications ............................................................................................................63 Table 6-6. LOPOH Input Clock Specifications......................................................................................................................63 Table 6-7. Microprocessor Interface Input Clocks Specifications.........................................................................................63 Table 6-8. Framer PLL Input Clocks Specifications .............................................................................................................63 Table 6-9. CHI Input Clocks Specifications ..........................................................................................................................63 Table 6-10. PSB Input Clocks Specifications .......................................................................................................................63 Table 6-11. High-Speed Interface Output Clocks Specifications..........................................................................................63 Table 6-12. Protection Link Output Clocks Specifications....................................................................................................64 Table 6-13. Line Timing Interface Output Clocks Specifications ..........................................................................................64 Table 6-14. TOAC Output Clocks Specifications..................................................................................................................64 Table 6-15. POAC Output Clocks Specifications .................................................................................................................65 Table 6-16. DS3/E3/STS-1 Output Clocks Specifications ....................................................................................................65 Table 6-17. LOPOH Output Clock Specifications.................................................................................................................65 Table 6-18. NSMI Output Clocks Specifications...................................................................................................................65 Table 6-19. Framer PLL Output Clocks Specifications.........................................................................................................65 Table 6-20. NSMI Input/Output Clocks Specifications..........................................................................................................65 Table 7-1. Microprocessor Interface Synchronous Write Cycle Specifications ....................................................................66 Table 7-2. Microprocessor Interface Synchronous Read Cycle Specifications ....................................................................67 Table 7-3. Microprocessor Interface Asynchronous Write Cycle Specifications ..................................................................69 Table 7-4. Microprocessor Interface Asynchronous Read Cycle Specifications ..................................................................70 Table 8-1. General-Purpose Inputs Specifications ...............................................................................................................71 Table 8-2. Miscellaneous Output Specifications...................................................................................................................71 Table 8-3. General-Purpose Output Specifications ..............................................................................................................71 Table 10-1. Ordering Information .........................................................................................................................................71 Table 12-1. Document Changes...........................................................................................................................................73 Table 14-1. Input Capacitances for Specific LVCMOS Input Pins.......................................................................................75 4 Agere Systems Inc. Hardware Design Guide, Revision 3 September 18, 2003 TMXF33625 Hypermapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS0/E0 Table of Contents (continued) Figures Page Figure 1-1. Hypermapper Block Diagram and High-Level Interface Definition.......................................................................1 Figure 2-1. Hypermapper Pin-Package Diagram (Top View) .................................................................................................6 Figure 5-1. TMUX LVDS Signal Rise/Fall Timing.................................................................................................................49 Figure 5-2. TMUX LVDS Clock and Data Timing .................................................................................................................49 Figure 5-3. THSSYNC Timing Diagram (MPU_MASTER_SLAVE = 1)................................................................................50 Figure 5-4. THSSYNC Timing Diagram (MPU_MASTER_SLAVE = 0)................................................................................50 Figure 5-5. STS-3/STM-1 Mate Rise/Fall Timing .................................................................................................................51 Figure 5-6. STS-3/STM-1 Mate Clock and Data Timing.......................................................................................................51 Figure 5-7. TOAC, POAC Timing .........................................................................................................................................52 Figure 5-8. LOPOH Timing...................................................................................................................................................52 Figure 5-9. DS3/E3 Interface Diagram in M13/E13 Block ....................................................................................................53 Figure 5-10. NSMI Clock and Data Timing for the STS-1 Mode ..........................................................................................54 Figure 5-11. NSMI Clock and Data Diagram for SPEMPR NSMI Mode...............................................................................54 Figure 5-12. NSMI Clock and Data Diagram for M13 NSMI Mode (NSMI <---> M13 <---> DS3 External I/O).....................55 Figure 5-13. NSMI Clock and Data Diagram for E13 NSMI Mode 1 (NSMI <---> E13 <---> E3 External I/O)......................55 Figure 5-14. NSMI Clock and Data Diagram for E13 NSMI Mode 2 (NSMI <--> E13 <--> SPEMPR <--> STM-N) .............56 Figure 5-15. NSMI Clock and Data Diagram for Framer (FRM) NSMI Mode .......................................................................57 Figure 5-16. CHI Clock Timing .............................................................................................................................................58 Figure 5-17. CHI Bus Timing ................................................................................................................................................58 Figure 5-18. Typical Receive CHI Timing (Non-CMS Mode--FRM_CMS = 0) ....................................................................59 Figure 5-19. Transmit CHI Timing (Non-CMS Mode--FRM_CMS = 0)................................................................................59 Figure 5-20. Typical Receive CHI Timing (CMS Mode--FRM_CMS = 1) ............................................................................60 Figure 5-21. Transmit CHI Timing (CMS Mode--FRM_CMS = 1) .......................................................................................60 Figure 5-22. PSB Clock and Data Timing.............................................................................................................................61 Figure 7-1. Microprocessor Interface Synchronous Write Cycle (MPMODE = 1).................................................................66 Figure 7-2. Microprocessor Interface Synchronous Read Cycle (MPMODE = 1) ................................................................67 Figure 7-3. Microprocessor Interface Asynchronous Write Cycle (MPMODE = 0)...............................................................68 Figure 7-4. Microprocessor Interface Asynchronous Read Cycle (MPMODE = 0)...............................................................69 Figure 11-1. 1152-Pin PBGA Physical Dimensions..............................................................................................................72 Agere Systems Inc. 5 TMXF33625 Hypermapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS0/E0 Hardware Design Guide, Revision 3 September 18, 2003 2 Pin Information 2.1 Ball Diagram The TMXF33625 Hypermapper is housed in an 1152-pin plastic ball grid array (PBGA), which is 45 mm2 with a 1.27 mm2 ball pitch. Figure 2-1 shows the ball assignment viewed from the top of the package. 2 8 6 4 10 14 12 16 18 20 22 24 30 28 26 32 34 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL AM AN AP A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL AM AN AP 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 Figure 2-1. Hypermapper Pin-Package Diagram (Top View) 6 Agere Systems Inc. Hardware Design Guide, Revision 3 September 18, 2003 TMXF33625 Hypermapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS0/E0 2.2 Pin Assignments Table 2-1. Pin Assignments (continued) Table 2-1. Pin Assignments Signal Name MPMODE MPCLK CSN_A CSN_B CSN_D CSN_C ADSN RWN DSN ADDR[0] ADDR[1] ADDR[2] ADDR[3] ADDR[4] ADDR[5] ADDR[6] ADDR[7] ADDR[8] ADDR[9] ADDR[10] ADDR[11] ADDR[12] ADDR[13] ADDR[14] ADDR[15] ADDR[16] ADDR[17] ADDR[18] ADDR[19] ADDR[20] DATA[0] DATA[1] DATA[2] DATA[3] DATA[4] DATA[5] DATA[6] DATA[7] DATA[8] DATA[9] DATA[10] DATA[11] DATA[12] DATA[13] Agere Systems Inc. Pin AG20 AG21 D15 R31 AL20 Y4 AE21 AJ20 T28 AH19 AJ21 AH21 R29 R27 AF21 AH20 AE22 T26 R28 AD22 T27 R26 AJ22 AC22 P29 AG22 N24 N25 N29 AB22 Y8 P28 L22 AA6 P25 AA8 M22 AB6 AA7 AF22 P27 P26 AB8 AB9 Signal Name DATA[14] DATA[15] PAR[0] PAR[1] DTN HP_INTN_1 HP_INTN_2 LP_INTN_1 LP_INTN_2 APS_INTN_A APS_INTN_B APS_INTN_D APS_INTN_C DS3POSDATAIN_A[1] DS3POSDATAIN_B[1] DS3POSDATAIN_D[1] DS3POSDATAIN_C[1] DS3NEGDATAIN_A[1] DS3NEGDATAIN_B[1] DS3NEGDATAIN_D[1] DS3NEGDATAIN_C[1] DS3DATAINCLK_A[1] DS3DATAINCLK_B[1] DS3DATAINCLK_D[1] DS3DATAINCLK_C[1] DS3POSDATAIN_A[2] DS3POSDATAIN_B[2] DS3POSDATAIN_D[2] DS3POSDATAIN_C[2] DS3NEGDATAIN_A[2] DS3NEGDATAIN_B[2] DS3NEGDATAIN_D[2] DS3NEGDATAIN_C[2] DS3DATAINCLK_A[2] DS3DATAINCLK_B[2] DS3DATAINCLK_D[2] DS3DATAINCLK_C[2] DS3POSDATAIN_A[3] DS3POSDATAIN_B[3] DS3POSDATAIN_D[3] DS3POSDATAIN_C[3] DS3NEGDATAIN_A[3] DS3NEGDATAIN_B[3] DS3NEGDATAIN_D[3] DS3NEGDATAIN_C[3] DS3DATAINCLK_A[3] Pin N22 N26 AB23 N23 AB24 AB10 M33 F13 AB11 G14 J33 AN26 AC2 A14 P34 AP21 AA1 E11 L30 AK24 AD5 C11 L32 AM24 AD3 A13 N34 AP22 AB1 A12 M34 AP23 AC1 H12 M27 AG23 AC8 B11 L33 AN24 AD2 C10 K32 AM25 AE3 F11 7 TMXF33625 Hypermapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS0/E0 Table 2-1. Pin Assignments (continued) Signal Name DS3DATAINCLK_B[3] DS3DATAINCLK_D[3] DS3DATAINCLK_C[3] DS3POSDATAIN_A[4] DS3POSDATAIN_B[4] DS3POSDATAIN_D[4] DS3POSDATAIN_C[4] DS3NEGDATAIN_A[4] DS3NEGDATAIN_B[4] DS3NEGDATAIN_D[4] DS3NEGDATAIN_C[4] DS3DATAINCLK_A[4] DS3DATAINCLK_B[4] DS3DATAINCLK_D[4] DS3DATAINCLK_C[4] DS3POSDATAIN_A[5] DS3POSDATAIN_B[5] DS3POSDATAIN_D[5] DS3POSDATAIN_C[5] DS3NEGDATAIN_A[5] DS3NEGDATAIN_B[5] DS3NEGDATAIN_D[5] DS3NEGDATAIN_C[5] DS3DATAINCLK_A[5] DS3DATAINCLK_B[5] DS3DATAINCLK_D[5] DS3DATAINCLK_C[5] DS3POSDATAIN_A[6] DS3POSDATAIN_B[6] DS3POSDATAIN_D[6] DS3POSDATAIN_C[6] DS3NEGDATAIN_A[6] DS3NEGDATAIN_B[6] DS3NEGDATAIN_D[6] DS3NEGDATAIN_C[6] DS3DATAINCLK_A[6] DS3DATAINCLK_B[6] DS3DATAINCLK_D[6] DS3DATAINCLK_C[6] DS3POSDATAOUT_A[1] DS3POSDATAOUT_B[1] DS3POSDATAOUT_D[1] DS3POSDATAOUT_C[1] DS3NEGDATAOUT_A[1] DS3NEGDATAOUT_B[1] DS3NEGDATAOUT_D[1] 8 Hardware Design Guide, Revision 3 September 18, 2003 Table 2-1. Pin Assignments (continued) Pin L29 AJ24 AD6 G11 L28 AH24 AD7 A11 L34 AP24 AD1 B10 K33 AN25 AE2 D10 K31 AL25 AE4 A10 K34 AP25 AE1 C9 J32 AM26 AF3 E10 K30 AK25 AE5 A9 J34 AP26 AF1 A8 H34 AP27 AG1 F10 K29 AJ25 AE6 B8 H33 AN27 Signal Name DS3NEGDATAOUT_C[1] DS3RXCLKOUT_A[1] DS3RXCLKOUT_B[1] DS3RXCLKOUT_D[1] DS3RXCLKOUT_C[1] DS3DATAOUTCLK_A[1] DS3DATAOUTCLK_B[1] DS3DATAOUTCLK_D[1] DS3DATAOUTCLK_C[1] DS3POSDATAOUT_A[2] DS3POSDATAOUT_B[2] DS3POSDATAOUT_D[2] DS3POSDATAOUT_C[2] DS3NEGDATAOUT_A[2] DS3NEGDATAOUT_B[2] DS3NEGDATAOUT_D[2] DS3NEGDATAOUT_C[2] DS3RXCLKOUT_A[2] DS3RXCLKOUT_B[2] DS3RXCLKOUT_D[2] DS3RXCLKOUT_C[2] DS3DATAOUTCLK_A[2] DS3DATAOUTCLK_B[2] DS3DATAOUTCLK_D[2] DS3DATAOUTCLK_C[2] DS3POSDATAOUT_A[3] DS3POSDATAOUT_B[3] DS3POSDATAOUT_D[3] DS3POSDATAOUT_C[3] DS3NEGDATAOUT_A[3] DS3NEGDATAOUT_B[3] DS3NEGDATAOUT_D[3] DS3NEGDATAOUT_C[3] DS3RXCLKOUT_A[3] DS3RXCLKOUT_B[3] DS3RXCLKOUT_D[3] DS3RXCLKOUT_C[3] DS3DATAOUTCLK_A[3] DS3DATAOUTCLK_B[3] DS3DATAOUTCLK_D[3] DS3DATAOUTCLK_C[3] DS3POSDATAOUT_A[4] DS3POSDATAOUT_B[4] DS3POSDATAOUT_D[4] DS3POSDATAOUT_C[4] DS3NEGDATAOUT_A[4] Pin AG2 C8 H32 AM27 AG3 A7 G34 AP28 AH1 H11 L27 AG24 AD8 B7 G33 AN28 AH2 A6 F34 AP29 AJ1 E9 J30 AK26 AF5 C7 G32 AM28 AH3 B6 F33 AN29 AJ2 E8 H30 AK27 AG5 A5 E34 AP30 AK1 A4 D34 AP31 AL1 C6 Agere Systems Inc. Hardware Design Guide, Revision 3 September 18, 2003 TMXF33625 Hypermapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS0/E0 Table 2-1. Pin Assignments (continued) Table 2-1. Pin Assignments (continued) Signal Name DS3NEGDATAOUT_B[4] DS3NEGDATAOUT_D[4] DS3NEGDATAOUT_C[4] DS3RXCLKOUT_A[4] DS3RXCLKOUT_B[4] DS3RXCLKOUT_D[4] DS3RXCLKOUT_C[4] DS3DATAOUTCLK_A[4] DS3DATAOUTCLK_B[4] DS3DATAOUTCLK_D[4] DS3DATAOUTCLK_C[4] DS3POSDATAOUT_A[5] DS3POSDATAOUT_B[5] DS3POSDATAOUT_D[5] DS3POSDATAOUT_C[5] DS3NEGDATAOUT_A[5] DS3NEGDATAOUT_B[5] DS3NEGDATAOUT_D[5] DS3NEGDATAOUT_C[5] DS3RXCLKOUT_A[5] DS3RXCLKOUT_B[5] DS3RXCLKOUT_D[5] DS3RXCLKOUT_C[5] DS3DATAOUTCLK_A[5] DS3DATAOUTCLK_B[5] DS3DATAOUTCLK_D[5] DS3DATAOUTCLK_C[5] DS3POSDATAOUT_A[6] DS3POSDATAOUT_B[6] DS3POSDATAOUT_D[6] DS3POSDATAOUT_C[6] DS3NEGDATAOUT_A[6] DS3NEGDATAOUT_B[6] DS3NEGDATAOUT_D[6] DS3NEGDATAOUT_C[6] DS3RXCLKOUT_A[6] DS3RXCLKOUT_B[6] DS3RXCLKOUT_D[6] DS3RXCLKOUT_C[6] DS3DATAOUTCLK_A[6] DS3DATAOUTCLK_B[6] DS3DATAOUTCLK_D[6] DS3DATAOUTCLK_C[6] REF10_A REF10_B REF10_D Agere Systems Inc. Pin F32 AM29 AJ3 D7 G31 AL28 AH4 B4 D33 AN31 AL2 C5 E32 AM30 AK3 A3 C34 AP32 AM1 G10 K28 AH25 AE7 A2 B34 AP33 AN1 B3 C33 AN32 AM2 C4 D32 AM31 AL3 E7 G30 AK28 AH5 D5 E31 AL30 AK4 F4 D29 AJ31 Signal Name REF10_C REF14_A REF14_B REF14_D REF14_C RESHI_A RESHI_B RESHI_D RESHI_C RESLO_A RESLO_B RESLO_D RESLO_C RHSC_AP RHSC_BP RHSC_DP RHSC_CP RHSC_AN RHSC_BN RHSC_DN RHSC_CN CTAPRH_A CTAPRH_B CTAPRH_D CTAPRH_C RHSD_AP RHSD_BP RHSD_DP RHSD_CP RHSD_AN RHSD_BN RHSD_DN RHSD_CN THSCO_AP THSCO_BP THSCO_DP THSCO_CP THSCO_AN THSCO_BN THSCO_DN THSCO_CN CTAPTH_A CTAPTH_B CTAPTH_D CTAPTH_C THSD_AP Pin AL6 G9 J28 AH26 AF7 F9 J29 AJ26 AF6 G8 H28 AH27 AG7 E4 D30 AK31 AL5 E3 C30 AK32 AM5 F6 F29 AJ29 AJ6 D3 C31 AL32 AM4 C3 C32 AM32 AM3 B2 B33 AN33 AN2 B1 A33 AN34 AP2 F7 G29 AJ28 AH6 C2 9 TMXF33625 Hypermapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS0/E0 Table 2-1. Pin Assignments (continued) Signal Name THSD_BP THSD_DP THSD_CP THSD_AN THSD_BN THSD_DN THSD_CN THSC_AP THSC_BP THSC_DP THSC_CP THSC_AN THSC_BN THSC_DN THSC_CN RPSD_AP RPSD_BP RPSD_DP RPSD_CP RPSD_AN RPSD_BN RPSD_DN RPSD_CN CTAPRP_A CTAPRP_B CTAPRP_D CTAPRP_C RPSC_AP RPSC_BP RPSC_DP RPSC_CP RPSC_AN RPSC_BN RPSC_DN RPSC_CN TPSC_AP TPSC_BP TPSC_DP TPSC_CP TPSC_AN TPSC_BN TPSC_DN TPSC_CN TPSD_AP TPSD_BP TPSD_DP 10 Hardware Design Guide, Revision 3 September 18, 2003 Table 2-1. Pin Assignments (continued) Pin B31 AL33 AN4 C1 A31 AL34 AP4 E2 B30 AK33 AN5 E1 A30 AK34 AP5 F3 C29 AJ32 AM6 G3 C28 AH32 AM7 G7 G28 AH28 AH7 H4 D27 AG31 AL8 G4 D28 AH31 AL7 G2 B28 AH33 AN7 G1 A28 AH34 AP7 H2 B27 AG33 Signal Name TPSD_CP TPSD_AN TPSD_BN TPSD_DN TPSD_CN RLSDATA_AP[1] RLSDATA_BP[1] RLSDATA_DP[1] RLSDATA_CP[1] RLSDATA_AN[1] RLSDATA_BN[1] RLSDATA_DN[1] RLSDATA_CN[1] RLSDATA_AP[2] RLSDATA_BP[2] RLSDATA_DP[2] RLSDATA_CP[2] RLSDATA_AN[2] RLSDATA_BN[2] RLSDATA_DN[2] RLSDATA_CN[2] TLSDATA_AP[3] TLSDATA_BP[3] TLSDATA_DP[3] TLSDATA_CP[3] TLSDATA_AN[3] TLSDATA_BN[3] TLSDATA_DN[3] TLSDATA_CN[3] RLSDATA_AP[3] RLSDATA_BP[3] RLSDATA_DP[3] RLSDATA_CP[3] RLSDATA_AN[3] RLSDATA_BN[3] RLSDATA_DN[3] RLSDATA_CN[3] TLSDATA_AP[1] TLSDATA_BP[1] TLSDATA_DP[1] TLSDATA_CP[1] TLSDATA_AN[1] TLSDATA_BN[1] TLSDATA_DN[1] TLSDATA_CN[1] VDD15A_CDR2_A Pin AN8 H1 A27 AG34 AP8 J1 A26 AF34 AP9 K1 A25 AE34 AP10 L1 A24 AD34 AP11 M1 A23 AC34 AP12 H7 G27 AG28 AH8 H8 H27 AG27 AG8 M2 B23 AC33 AN12 L2 B24 AD33 AN11 H3 C27 AG32 AM8 J3 C26 AF32 AM9 H5 Agere Systems Inc. Hardware Design Guide, Revision 3 September 18, 2003 TMXF33625 Hypermapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS0/E0 Table 2-1. Pin Assignments (continued) Table 2-1. Pin Assignments (continued) Signal Name VDD15A_CDR2_B VDD15A_CDR2_D VDD15A_CDR2_C VSSA_CDR2_A VSSA_CDR2_B VSSA_CDR2_D VSSA_CDR2_C TLSDATA_AP[2] TLSDATA_BP[2] TLSDATA_DP[2] TLSDATA_CP[2] TLSDATA_AN[2] TLSDATA_BN[2] TLSDATA_DN[2] TLSDATA_CN[2] CTAPTL_A CTAPTL_B CTAPTL_D CTAPTL_C VSSA_CDR1_A VSSA_CDR1_B VSSA_CDR1_D VSSA_CDR1_C VDD15A_CDR1_A VDD15A_CDR1_B VDD15A_CDR1_D VDD15A_CDR1_C RTOACCLK_A RTOACCLK_B RTOACCLK_D RTOACCLK_C RTOACDATA_A RTOACDATA_B RTOACDATA_D RTOACDATA_C TLSCLK_A TLSCLK_B TLSCLK_D TLSCLK_C RLSCLK_A RLSCLK_B RLSCLK_D RLSCLK_C THSSYNC_A THSSYNC_B THSSYNC_D Agere Systems Inc. Pin E27 AG30 AK8 J4 D26 AF31 AL9 J2 B26 AF33 AN9 K2 B25 AE33 AN10 H9 J27 AG26 AF8 K3 C25 AE32 AM10 L3 C24 AD32 AM11 K4 D25 AE31 AL10 J5 E26 AF30 AK9 L4 D24 AD31 AL11 H10 K27 AG25 AE8 K5 E25 AE30 Signal Name THSSYNC_C BYPASS_1 BYPASS_2 TSTPHASE ECSEL_1 ECSEL_2 ETOGGLE_1 ETOGGLE_2 EXDNUP_1 EXDNUP_2 TSTMODE TSTSFTLD VDD15A_X4PLL_A VDD15A_X4PLL_B VDD15A_X4PLL_D VDD15A_X4PLL_C VSSA_X4PLL_A VSSA_X4PLL_B VSSA_X4PLL_D VSSA_X4PLL_C RTOACSYNC_A RTOACSYNC_B RTOACSYNC_D RTOACSYNC_C TTOACCLK_A TTOACCLK_B TTOACCLKD TTOACCLK_C TTOACSYNC_A TTOACSYNC_B TTOACSYNC_D TTOACSYNC_C TTOACDATA_A TTOACDATA_B TTOACDATA_D TTOACDATA_C RPOACCLK_A RPOACCLK_B RPOACCLK_D RPOACCLK_C RPOACDATA_A RPOACDATA_B RPOACDATA_D RPOACDATA_C RPOACSYNC_A RPOACSYNC_B Pin AK10 H13 AN23 J13 H15 AH29 J14 AF28 K13 D31 H14 J15 K7 G25 AE28 AH10 K6 F25 AE29 AJ10 K8 H25 AE27 AG10 J6 F26 AF29 AJ9 L6 F24 AD29 AJ11 L7 G24 AD28 AH11 M6 F23 AC29 AJ12 J8 H26 AF27 AG9 M5 E23 11 TMXF33625 Hypermapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS0/E0 Table 2-1. Pin Assignments (continued) Table 2-1. Pin Assignments (continued) Signal Name RPOACSYNC_D RPOACSYNC_C TPOACCLK_A TPOACCLK_B TPOACCLK_D TPOACCLK_C TPOACDATA_A TPOACDATA_B TPOACDATA_D TPOACDATA_C TPOACSYNC_A TPOACSYNC_B TPOACSYNC_D TPOACSYNC_C E1XCLK_1 E1XCLK_2 DS1XCLK_1 DS1XCLK_2 LOSEXT_A LOSEXT_B LOSEXT_D LOSEXT_C RHSFSYNCN_A RHSFSYNCN_B RHSFSYNCN_D RHSFSYNCN_C RSTN_A RSTN_B RSTN_D RSTN_C PMRST TCK TDI TMS_1 TMS_2 TRST TDO IC3STATEN SCK1_1 SCK1_2 SCK2_1 SCK2_2 SCAN_EN SCANMODE_1 SCANMODE_2 IDDQ_A 12 Hardware Design Guide, Revision 3 September 18, 2003 Pin AC30 AK12 N5 E22 AB30 AK13 N7 G22 AB28 AH13 M3 C23 AC32 AM12 W9 F28 AA11 E33 L8 H24 AD27 AG11 N2 B22 AB33 AN13 N1 A22 AB34 AP13 N14 AC21 P15 Y6 AC31 L14 AD21 M13 W8 AA31 W7 AL26 N13 L13 AK30 N3 Signal Name IDDQ_B IDDQ_D IDDQ_C NSMIRXDATA_A[1] NSMIRXDATA_B[1] NSMIRXDATA_D[1] NSMIRXDATA_C[1] NSMIRXCLK_A[1] NSMIRXCLK_B[1] NSMIRXCLK_D[1] NSMIRXCLK_C[1] NSMIRXSYNC_A[1] NSMIRXSYNC_B[1] NSMIRXSYNC_D[1] NSMIRXSYNC_C[1] RXDATAEN_A[1] RXDATAEN_B[1] RXDATAEN_D[1] RXDATAEN_C[1] NSMIRXDATA_A[2] NSMIRXDATA_B[2] NSMIRXDATA_D[2] NSMIRXDATA_C[2] NSMIRXCLK_A[2] NSMIRXCLK_B[2] NSMIRXCLK_D[2] NSMIRXCLK_C[2] NSMIRXSYNC_A[2] NSMIRXSYNC_B[2] NSMIRXSYNC_D[2] NSMIRXSYNC_C[2] RXDATAEN_A[2] RXDATAEN_B[2] RXDATAEN_D[2] RXDATAEN_C[2] NSMIRXDATA_A[3] NSMIRXDATA_B[3] NSMIRXDATA_D[3] NSMIRXDATA_C[3] NSMIRXCLK_A[3] NSMIRXCLK_B[3] NSMIRXCLK_D[3] NSMIRXCLK_C[3] NSMIRXSYNC_A[3] NSMIRXSYNC_B[3] NSMIRXSYNC_D[3] Pin C22 AB32 AM13 P1 A21 AA34 AP14 M7 G23 AC28 AH12 P2 B21 AA33 AN14 P3 C21 AA32 AM14 P6 F21 AA29 AJ14 N6 F22 AB29 AJ13 R1 A20 Y34 AP15 R2 B20 Y33 AN15 R3 C20 Y32 AM15 M8 H23 AC27 AG12 P5 E21 AA30 Agere Systems Inc. Hardware Design Guide, Revision 3 September 18, 2003 TMXF33625 Hypermapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS0/E0 Table 2-1. Pin Assignments (continued) Table 2-1. Pin Assignments (continued) Signal Name NSMIRXSYNC_C[3] RXDATAEN_A[3] RXDATAEN_B[3] RXDATAEN_D[3] RXDATAEN_C[3] NSMITXDATA_A[1] NSMITXDATA_B[1] NSMITXDATA_D[1] NSMITXDATA_C[1] NSMITXCLK_A[1] NSMITXCLK_B[1] NSMITXCLK_D[1] NSMITXCLK_C[1] NSMITXSYNC_A[1] NSMITXSYNC_B[1] NSMITXSYNC_D[1] NSMITXSYNC_C[1] TXDATAEN_A[1] TXDATAEN_B[1] TXDATAEN_D[1] TXDATAEN_C[1] NSMITXDATA_A[2] NSMITXDATA_B[2] NSMITXDATA_D[2] NSMITXDATA_C[2] NSMITXCLK_A[2] NSMITXCLK_B[2] NSMITXCLK_D[2] NSMITXCLK_C[2] NSMITXSYNC_A[2] NSMITXSYNC_B[2] NSMITXSYNC_D[2] NSMITXSYNC_C[2] TXDATAEN_A[2] TXDATAEN_B[2] TXDATAEN_D[2] TXDATAEN_C[2] NSMITXDATA_A[3] NSMITXDATA_B[3] NSMITXDATA_D[3] NSMITXDATA_C[3] NSMITXCLK_A[3] NSMITXCLK_B[3] NSMITXCLK_D[3] NSMITXCLK_C[3] NSMITXSYNC_A[3] Agere Systems Inc. Pin AK14 T1 A19 W34 AP16 T2 B19 W33 AN16 P7 G21 AA28 AH14 R7 G20 Y28 AH15 R6 F20 Y29 AJ15 U1 A18 V34 AP17 R5 E20 Y30 AK15 R4 D20 Y31 AL15 V1 A17 U34 AP18 U2 B18 V33 AN17 P8 H21 AA27 AG14 T3 Signal Name NSMITXSYNC_B[3] NSMITXSYNC_D[3] NSMITXSYNC_C[3] TXDATAEN_A[3] TXDATAEN_B[3] TXDATAEN_D[3] TXDATAEN_C[3] CHITXDATA_A[1] CHITXDATA_B[1] CHITXDATA_D[1] CHITXDATA_C[1] CHITXDATA_A[2] CHITXDATA_B[2] CHITXDATA_D[2] CHITXDATA_C[2] CHITXDATA_A[3] CHITXDATA_B[3] CHITXDATA_D[3] CHITXDATA_C[3] CHITXDATA_A[4] CHITXDATA_B[4] CHITXDATA_D[4] CHITXDATA_C[4] MODE2_PLL CHITXDATA_A[5] CHITXDATA_B[5] CHITXDATA_D[5] CHITXDATA_C[5] CHITXDATA_A[6] CHITXDATA_B[6] CHITXDATA_D[6] CHITXDATA_C[6] CHITXDATA_A[7] CHITXDATA_B[7] CHITXDATA_D[7] CHITXDATA_C[7] CG_PLLCLKOUT_A CG_PLLCLKOUT_B CG_PLLCLKOUT_D CG_PLLCLKOUT_C MODE0_PLL VDD33A_SFPLL_A VDD33A_SFPLL_B VDD33A_SFPLL_D VDD33A_SFPLL_C CLKIN_PLL Pin C19 W32 AM16 U3 C18 V32 AM17 N9 J22 AB26 AF13 V2 B17 U33 AN18 T4 D19 W31 AL16 V3 C17 U32 AM18 F15 N10 K22 AB25 AE13 V4 D17 U31 AL18 U4 D18 V31 AL17 P9 J21 AA26 AF14 F14 T7 G19 W28 AH16 G16 13 TMXF33625 Hypermapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS0/E0 Table 2-1. Pin Assignments (continued) Table 2-1. Pin Assignments (continued) Signal Name VSSA_SFPLL_A VSSA_SFPLL_B VSSA_SFPLL_D VSSA_SFPLL_C MODE1_PLL CHITXDATA_A[8] CHITXDATA_B[8] CHITXDATA_D[8] CHITXDATA_C[8] CHITXDATA_A[9] CHITXDATA_B[9] CHITXDATA_D[9] CHITXDATA_C[9] CHITXDATA_A[10] CHITXDATA_B[10] CHITXDATA_D[10] CHITXDATA_C[10] CHITXDATA_A[11] CHITXDATA_B[11] CHITXDATA_D[11] CHITXDATA_C[11] CHITXDATA_A[12] CHITXDATA_B[12] CHITXDATA_D[12] CHITXDATA_C[12] CHITXDATA_A[13] CHITXDATA_B[13] CHITXDATA_D[13] CHITXDATA_C[13] CHITXDATA_A[14] CHITXDATA_B[14] CHITXDATA_D[14] CHITXDATA_C[14] CHITXDATA_A[15] CHITXDATA_B[15] CHITXDATA_D[15] CHITXDATA_C[15] CHITXDATA_A[16] CHITXDATA_B[16] CHITXDATA_D[16] CHITXDATA_C[16] CHITXDATA_A[17] CHITXDATA_B[17] CHITXDATA_D[17] CHITXDATA_C[17] CHITXDATA_A[18] 14 Hardware Design Guide, Revision 3 September 18, 2003 Pin U5 E18 V30 AK17 AD13 R8 H20 Y27 AG15 T6 F19 W29 AJ16 V5 E17 U30 AK18 T8 H19 W27 AG16 U6 F18 V29 AJ17 V6 F17 U29 AJ18 R9 J20 Y26 AF15 U7 G18 V28 AH17 P10 K21 AA25 AE14 N11 L21 AA24 AD14 R10 Signal Name CHITXDATA_B[18] CHITXDATA_D[18] CHITXDATA_C[18] CHITXGCLK CHITXGFS CHIRXGTCLK CHIRXGCLK CHIRXGFS CHIRXDATA_A[1] CHIRXDATA_B[1] CHIRXDATA_D[1] CHIRXDATA_C[1] CHIRXDATA_A[2] CHIRXDATA_B[2] CHIRXDATA_D[2] CHIRXDATA_C[2] CHIRXDATA_A[3] CHIRXDATA_B[3] CHIRXDATA_D[3] CHIRXDATA_C[3] CHIRXDATA_A[4] CHIRXDATA_B[4] CHIRXDATA_D[4] CHIRXDATA_C[4] CHIRXDATA_A[5] CHIRXDATA_B[5] CHIRXDATA_D[5] CHIRXDATA_C[5] CHIRXDATA_A[6] CHIRXDATA_B[6] CHIRXDATA_D[6] CHIRXDATA_C[6] CHIRXDATA_A[7] CHIRXDATA_B[7] CHIRXDATA_D[7] CHIRXDATA_C[7] CHIRXDATA_A[8] CHIRXDATA_B[8] CHIRXDATA_D[8] CHIRXDATA_C[8] CHIRXDATA_A[9] CHIRXDATA_B[9] CHIRXDATA_D[9] CHIRXDATA_C[9] CHIRXDATA_A[10] CHIRXDATA_B[10] Pin K20 Y25 AE15 AF20 AG19 AF19 AC13 AB13 P11 L20 Y24 AC14 T10 K19 W25 AE16 U10 K18 V25 AE17 R11 L19 AA23 AD15 T11 M21 W24 AD16 N12 M20 AA22 AA13 P12 N21 Y23 AB14 R12 P22 Y22 AC15 T12 M19 W23 Y14 P13 N20 Agere Systems Inc. Hardware Design Guide, Revision 3 September 18, 2003 TMXF33625 Hypermapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS0/E0 Table 2-1. Pin Assignments (continued) Table 2-1. Pin Assignments (continued) Signal Name CHIRXDATA_D[10] CHIRXDATA_C[10] CHIRXDATA_A[11] CHIRXDATA_B[11] CHIRXDATA_D[11] CHIRXDATA_C[11] CHIRXDATA_A[12] CHIRXDATA_B[12] CHIRXDATA_D[12] CHIRXDATA_C[12] CHIRXDATA_A[13] CHIRXDATA_B[13] CHIRXDATA_D[13] CHIRXDATA_C[13] CHIRXDATA_A[14] CHIRXDATA_B[14] CHIRXDATA_D[14] CHIRXDATA_C[14] CHIRXDATA_A[15] CHIRXDATA_B[15] CHIRXDATA_D[15] CHIRXDATA_C[15] CHIRXDATA_A[16] CHIRXDATA_B[16] CHIRXDATA_D[16] CHIRXDATA_C[16] CHIRXDATA_A[17] CHIRXDATA_B[17] CHIRXDATA_D[17] CHIRXDATA_C[17] CHIRXDATA_A[18] CHIRXDATA_B[18] CHIRXDATA_D[18] CHIRXDATA_C[18] LOPOHCLKIN_A LOPOHCLKIN_B LOPOHCLKIN_D LOPOHCLKIN_C LOPOHDATAIN_A LOPOHDATAIN_B LOPOHDATAIN_D LOPOHDATAIN_C LOPOHVALIDIN_A LOPOHVALIDIN_B LOPOHVALIDIN_D LOPOHVALIDIN_C Agere Systems Inc. Pin Y21 AC16 R13 P21 AA19 AB15 U12 M18 V23 AC17 P14 R21 Y20 AA14 R14 P20 W22 AB16 T13 N19 W21 AA15 T14 P19 W20 AA16 R15 R20 Y19 Y15 T15 R19 W19 Y16 T16 T19 AA20 W16 R16 T20 AA21 W15 P16 T21 AB19 W14 Signal Name LOPOHCLKOUT_A LOPOHCLKOUT_B LOPOHCLKOUT_D LOPOHCLKOUT_C LOPOHDATAOUT_A LOPOHDATAOUT_B LOPOHDATAOUT_D LOPOHDATAOUT_C LOPOHVALIDOUT_A LOPOHVALIDOUT_B LOPOHVALIDOUT_D LOPOHVALIDOUT_C VDD15A_DS3PLL_A VDD15A_DS3PLL_B VDD15A_DS3PLL_D VDD15A_DS3PLL_C DS3XCLK VSSA_DS3PLL_A VSSA_DS3PLL_B VSSA_DS3PLL_D VSSA_DS3PLL_C VDD15A_E3PLL_A VDD15A_E3PLL_B VDD15A_E3PLL_D VDD15A_E3PLL_C E3XCLK VSSA_E3PLL_A VSSA_E3PLL_B VSSA_E3PLL_D VSSA_E3PLL_C VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 Pin N16 T22 AC19 W13 M16 T23 AB20 W12 N15 R22 AB21 Y13 M15 R23 AC20 Y12 P23 L15 R24 AD20 Y11 K15 R25 AE20 Y10 P24 K16 T25 AE19 W10 A15 A16 AA9 AA18 AB7 AB12 AB17 AB27 AC7 AC12 AC18 AC26 AD30 AF18 AG4 AG29 15 TMXF33625 Hypermapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS0/E0 Table 2-1. Pin Assignments (continued) Signal Name VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 NC NC NC VDD15 NC NC VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 16 Hardware Design Guide, Revision 3 September 18, 2003 Table 2-1. Pin Assignments (continued) Pin AH22 AH23 AJ5 AJ8 AJ19 AJ30 AK2 AK6 AK11 AK16 AK29 AL4 AL14 AM19 AN19 AN20 AN30 AP19 AP20 B5 B12 B15 B16 C16 D8 D21 E6 E19 E24 E29 F5 F16 F27 F30 G12 G13 G15 H6 H16 H31 J16 J17 L5 M14 M17 M28 Signal Name VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 Pin N18 N28 P4 P17 R17 R33 R34 T5 T17 T29 T32 T33 T34 U13 U19 U20 U21 U23 U26 V9 V12 V14 V15 V16 V22 W1 W2 W3 W6 W18 W30 Y1 Y2 Y7 Y9 Y18 AA5 AA10 AA12 AB5 AB18 AB31 AC5 AC6 AD17 AD18 Agere Systems Inc. Hardware Design Guide, Revision 3 September 18, 2003 TMXF33625 Hypermapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS0/E0 Table 2-1. Pin Assignments (continued) Table 2-1. Pin Assignments (continued) Signal Name VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 Agere Systems Inc. Pin AE18 AE26 AF2 AF4 AF10 AF11 AF17 AF26 AG6 AG17 AH18 AH30 AJ23 AJ27 AK5 AK7 AK19 AK22 AK23 AL13 AL19 AL21 AL27 AL31 B9 D4 D9 D14 D16 D22 E5 E12 E13 E16 E28 E30 F8 F12 G5 G17 H18 H29 J18 J25 J26 J31 Signal Name VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VSS VSS VSS VSS VSS VSS VSS VSS Pin K9 K14 K17 L9 L17 L18 M29 M30 N4 N17 N30 P31 R18 T30 T31 U8 U9 U11 U15 U17 U18 U22 U24 U25 U28 V7 V10 V11 V13 V17 V18 V20 V24 V26 V27 W4 W5 Y17 A29 A32 AA2 AA3 AA4 AA17 AB2 AB3 17 TMXF33625 Hypermapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS0/E0 Table 2-1. Pin Assignments (continued) Signal Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS 18 Hardware Design Guide, Revision 3 September 18, 2003 Table 2-1. Pin Assignments (continued) Pin AB4 AC3 AC4 AC9 AC10 AC11 AC23 AC24 AC25 AD4 AD9 AD10 AD11 AD12 AD19 AD23 AD24 AD25 AD26 AE9 AE10 AE11 AE12 AE23 AE24 AE25 AF9 AF12 AF16 AF23 AF24 AF25 AG13 AG18 AH9 AJ4 AJ7 AJ33 AJ34 AK20 AK21 AL12 AL22 AL23 AL24 AL29 Signal Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Pin AM20 AM21 AM22 AM23 AM33 AM34 AN3 AN6 AN21 AN22 AP3 AP6 B13 B14 B29 B32 C12 C13 C14 C15 D1 D2 D6 D11 D12 D13 D23 E14 E15 F1 F2 F31 G6 G26 H17 H22 J7 J9 J10 J11 J12 J19 J23 J24 K10 K11 Agere Systems Inc. Hardware Design Guide, Revision 3 September 18, 2003 TMXF33625 Hypermapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS0/E0 Table 2-1. Pin Assignments (continued) Table 2-1. Pin Assignments (continued) Signal Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Agere Systems Inc. Pin K12 K23 K24 K25 K26 L10 L11 L12 L16 L23 L24 L25 L26 L31 M4 M9 M10 M11 M12 M23 M24 M25 M26 M31 M32 N8 N27 Signal Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Pin N31 N32 N33 P18 P30 P32 P33 R30 R32 T9 T18 T24 U14 U16 U27 V8 V19 V21 W11 W17 W26 Y3 Y5 19 VDD15 VDD15 DS3POSDATAIN_C[1] DS3POSDATAIN_C[2] DS3NEGDATAIN_C[2] DS3NEGDATAIN_C[4] DS3NEGDATAIN_C[5] DS3NEGDATAIN_C[6] DS3DATAINCLK_C[6] DS3DATAOUTCLK_C[1] DS3RXCLKOUT_C[2] DS3DATAOUTCLK_C[3] DS3POSDATAOUT_C[4] DS3NEGDATAOUT_C[5] DS3DATAOUTCLK_C[5] W Y AA AB AC AD AE AF AG AH AJ AK AL AM AN 20 -- TXDATAEN_A[2] V AP RXDATAEN_A[3] NSMITXDATA_A[2] NSMIRXSYNC_A[2] R U NSMIRXDATA_A[1] P T RLSDATA_AN[2] RSTN_A N L M RLSDATA_AN[1] RLSDATA_AP[2] K RLSDATA_AP[1] J F TPSC_AN VSS E TPSD_AN THSC_AN D H VSS C 1 -- G THSCO_AN THSD_AN B A Table 2-2. Pin Matrix 2.3 Pin Matrix THSCO_CN THSCO_CP DS3POSDATAOUT_C[6] DS3DATAOUTCLK_C[4] VDD15 DS3NEGDATAOUT_C[3] DS3NEGDATAOUT_C[2] DS3NEGDATAOUT_C[1] VDD33 DS3DATAINCLK_C[4] DS3POSDATAIN_C[3] APS_INTN_C VSS VSS VDD15 VDD15 CHITXDATA_A[2] NSMITXDATA_A[3] NSMITXDATA_A[1] RXDATAEN_A[2] NSMIRXSYNC_A[1] RHSFSYNCN_A RLSDATA_AP[3] RLSDATA_AN[3] TLSDATA_AN[2] TLSDATA_AP[2] TPSD_AP TPSC_AP VSS THSC_AP VSS THSD_AP THSCO_AP DS3DATAOUTCLK_A[5] 2 VSS VSS RHSD_CN DS3NEGDATAOUT_C[6] DS3POSDATAOUT_C[5] DS3NEGDATAOUT_C[4] DS3POSDATAOUT_C[3] DS3RXCLKOUT_C[1] DS3DATAINCLK_C[5] DS3NEGDATAIN_C[3] DS3DATAINCLK_C[1] VSS VSS VSS VSS VDD15 CHITXDATA_A[4] TXDATAEN_A[3] NSMITXSYNC_A[3] NSMIRXDATA_A[3] RXDATAEN_A[1] IDDQ_A TPOACSYNC_A VDD15A_CDR1_A VSSA_CDR1_A TLSDATA_AN[1] TLSDATA_AP[1] RPSD_AN RPSD_AP RHSC_AN RHSD_AP RHSD_AN DS3POSDATAOUT_A[6] DS3NEGDATAOUT_A[5] 3 4 THSD_CN THSD_CP RHSD_CP VDD15 DS3DATAOUTCLK_C[6] VSS DS3RXCLKOUT_C[4] VDD15 VDD33 DS3POSDATAIN_C[5] VSS VSS VSS VSS CSN_C VDD33 CHITXDATA_A[6] CHITXDATA_A[7] CHITXDATA_A[3] NSMITXSYNC_A[2] VDD15 VDD33 VSS TLSCLK_A RTOACCLK_A VSSA_CDR2_A RPSC_AP RPSC_AN REF10_A RHSC_AP VDD33 DS3NEGDATAOUT_A[6] DS3DATAOUTCLK_A[4] DS3POSDATAOUT_A[4] TMXF33625 Hypermapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS0/E0 5 THSC_CN THSC_CP RHSC_CN RHSC_CP VDD33 VDD15 DS3RXCLKOUT_C[6] DS3RXCLKOUT_C[3] DS3DATAOUTCLK_C[2] DS3POSDATAIN_C[6] DS3NEGDATAIN_C[1] VDD33 VDD33 VDD33 VSS VDD33 CHITXDATA_A[10] VSSA_SFPLL_A VDD15 NSMITXCLK_A[2] NSMIRXSYNC_A[3] TPOACCLK_A RPOACSYNC_A VDD15 THSSYNC_A RTOACDATA_A VDD15A_CDR2_A VDD33 VDD15 VDD33 DS3DATAOUTCLK_A[6] DS3POSDATAOUT_A[5] VDD15 DS3DATAOUTCLK_A[3] 6 VSS VSS RPSD_CP REF10_C VDD15 CTAPRH_C CTAPTH_C VDD33 RESHI_C DS3POSDATAOUT_C[1] DS3DATAINCLK_C[3] VDD33 DATA[7] DATA[3] TMS_1 VDD15 CHITXDATA_A[13] CHITXDATA_A[12] CHITXDATA_A[9] TXDATAEN_A[1] NSMIRXDATA_A[2] NSMIRXCLK_A[2] RPOACCLK_A TTOACSYNC_A VSSA_X4PLL_A TTOACCLK_A VDD15 VSS CTAPRH_A VDD15 VSS DS3NEGDATAOUT_A[4] DS3NEGDATAOUT_A[3] DS3RXCLKOUT_A[2] TPSC_CN TPSC_CP RPSD_CN RPSC_CN VDD33 VSS CTAPRP_C RESLO_C REF14_C DS3RXCLKOUT_C[5] DS3POSDATAIN_C[4] VDD15 VDD15 DATA[8] VDD15 SCK2_1 VDD33 CHITXDATA_A[15] VDD33A_SFPLL_A NSMITXSYNC_A[1] NSMITXCLK_A[1] TPOACDATA_A NSMIRXCLK_A[1] TTOACDATA_A VDD15A_X4PLL_A VSS TLSDATA_AP[3] CTAPRP_A CTAPTH_A DS3RXCLKOUT_A[6] DS3RXCLKOUT_A[4] DS3POSDATAOUT_A[3] DS3NEGDATAOUT_A[2] DS3DATAOUTCLK_A[1] 7 TPSD_CN TPSD_CP TLSDATA_CP[1] RPSC_CP VDD15A_CDR2_C VDD15 TLSDATA_CP[3] TLSDATA_CN[3] CTAPTL_C RLSCLK_C 9 RLSDATA_CP[1] TLSDATA_CP[2] TLSDATA_CN[1] VSSA_CDR2_C RTOACDATA_C TTOACCLK_C VSS RPOACDATA_C VSS VSS VSS VSS DATA[13] VDD15 VDD15 E1XCLK_1 VDD15 VDD33 VSS CHITXDATA_A[14] CG_PLLCLKOUT_A CHITXDATA_A[1] VSS VDD33 VDD33 VSS CTAPTL_A REF14_A RESHI_A DS3DATAOUTCLK_A[2] VDD33 DS3DATAINCLK_A[5] VDD33 DS3NEGDATAIN_A[6] Agere Systems Inc. DS3POSDATAOUT_C[2] DS3DATAINCLK_C[2] DATA[12] DATA[5] DATA[0] SCK1_1 VSS VDD33 CHITXDATA_A[11] CHITXDATA_A[8] NSMITXCLK_A[3] VSS NSMIRXCLK_A[3] LOSEXT_A RTOACSYNC_A RPOACDATA_A TLSDATA_AN[3] RESLO_A VDD33 DS3RXCLKOUT_A[3] VDD15 DS3RXCLKOUT_A[1] DS3NEGDATAOUT_A[1] DS3DATAINCLK_A[6] 8 Hardware Design Guide, Revision 3 September 18, 2003 DS3RXCLKOUT_A[5] RLSCLK_A VSS VSS VSS F G H J K L VDD33 HP_INTN_1 VSS VSS VSS VDD33 RTOACSYNC_C VDD15A_X4PLL_C VSSA_X4PLL_C THSSYNC_C RTOACCLK_C Y AA AB AC AD AE AF AG AH AJ AK AL Agere Systems Inc. RLSDATA_CN[1] VDD15A_E3PLL_C W AP VSSA_E3PLL_C V VSSA_CDR1_C VDD33 U TLSDATA_CN[2] CHIRXDATA_A[3] T AN CHIRXDATA_A[2] R AM CHITXDATA_A[16] CHITXDATA_A[18] P VSS DS3POSDATAOUT_A[1] E CHITXDATA_A[5] DS3POSDATAIN_A[6] D N DS3POSDATAIN_A[5] C M DS3DATAINCLK_A[4] DS3NEGDATAIN_A[3] B DS3NEGDATAIN_A[5] A 10 RLSDATA_CP[2] RLSDATA_CN[3] VDD15A_CDR1_C TLSCLK_C VDD15 TTOACSYNC_C TTOACDATA_C LOSEXT_C VDD33 VSS VSS VSS LP_INTN_2 DS1XCLK_1 VSSA_DS3PLL_C VSS VDD33 VDD33 CHIRXDATA_A[5] CHIRXDATA_A[4] CHIRXDATA_A[1] CHITXDATA_A[17] VSS VSS VSS VSS DS3POSDATAOUT_A[2] DS3POSDATAIN_A[4] DS3DATAINCLK_A[3] DS3NEGDATAIN_A[1] VSS DS3DATAINCLK_A[1] DS3POSDATAIN_A[3] DS3NEGDATAIN_A[4] 11 Table 2-2. Pin Matrix (continued) 12 RLSDATA_CN[2] RLSDATA_CP[3] TPOACSYNC_C VSS RPOACSYNC_C RPOACCLK_C NSMIRXCLK_C[1] NSMIRXCLK_C[3] VSS VSS VSS VDD15 VDD15 VDD33 VDD15A_DS3PLL_C LOPOHDATAOUT_C VDD15 CHIRXDATA_A[12] CHIRXDATA_A[9] CHIRXDATA_A[8] CHIRXDATA_A[7] CHIRXDATA_A[6] VSS VSS VSS VSS DS3DATAINCLK_A[2] VDD15 VDD33 VDD33 VSS VSS VDD15 DS3NEGDATAIN_A[2] Hardware Design Guide, Revision 3 September 18, 2003 13 RSTN_C RHSFSYNCN_C IDDQ_C VDD33 TPOACCLK_C NSMIRXCLK_C[2] TPOACDATA_C VSS CHITXDATA_C[1] CHITXDATA_C[5] MODE1_PLL CHIRXGCLK CHIRXGFS CHIRXDATA_C[6] LOPOHVALIDOUT_C LOPOHCLKOUT_C VDD33 VDD15 CHIRXDATA_A[15] CHIRXDATA_A[11] CHIRXDATA_A[10] SCAN_EN IC3STATEN SCANMODE_1 EXDNUP_1 TSTPHASE BYPASS_1 VDD15 LP_INTN_1 VDD33 VSS VSS VSS DS3POSDATAIN_A[2] 14 NSMIRXDATA_C[1] NSMIRXSYNC_C[1] RXDATAEN_C[1] VDD15 NSMIRXSYNC_C[3] NSMIRXDATA_C[2] NSMITXCLK_C[1] NSMITXCLK_C[3] CG_PLLCLKOUT_C CHITXDATA_C[16] CHITXDATA_C[17] CHIRXDATA_C[1] CHIRXDATA_C[7] CHIRXDATA_C[13] CHIRXDATA_C[9] LOPOHVALIDIN_C VDD15 VSS CHIRXDATA_A[16] CHIRXDATA_A[14] CHIRXDATA_A[13] PMRST VDD15 TRST VDD33 ETOGGLE_1 TSTMODE APS_INTN_A MODE0_PLL VSS VDD33 VSS VSS DS3POSDATAIN_A[1] 15 NSMIRXSYNC_C[2] RXDATAEN_C[2] NSMIRXDATA_C[3] NSMITXSYNC_C[2] NSMITXCLK_C[2] TXDATAEN_C[1] NSMITXSYNC_C[1] CHITXDATA_C[8] CHITXDATA_C[14] CHITXDATA_C[18] CHIRXDATA_C[4] CHIRXDATA_C[8] CHIRXDATA_C[11] CHIRXDATA_C[15] CHIRXDATA_C[17] LOPOHDATAIN_C VDD15 VDD33 CHIRXDATA_A[18] CHIRXDATA_A[17] TDI LOPOHVALIDOUT_A VDD15A_DS3PLL_A VSSA_DS3PLL_A VDD15A_E3PLL_A TSTSFTLD ECSEL_1 VDD15 MODE2_PLL VSS CSN_A VSS VDD15 VDD15 16 RXDATAEN_C[3] NSMITXDATA_C[1] NSMITXSYNC_C[3] CHITXDATA_C[3] VDD15 CHITXDATA_C[9] VDD33A_SFPLL_C CHITXDATA_C[11] VSS CHIRXDATA_C[2] CHIRXDATA_C[5] CHIRXDATA_C[10] CHIRXDATA_C[14] CHIRXDATA_C[16] CHIRXDATA_C[18] LOPOHCLKIN_C VDD15 VSS LOPOHCLKIN_A LOPOHDATAIN_A LOPOHVALIDIN_A LOPOHCLKOUT_A LOPOHDATAOUT_A VSS VSSA_E3PLL_A VDD15 VDD15 CLKIN_PLL VDD15 VDD33 VDD33 VDD15 VDD15 VDD15 NSMITXDATA_C[2] NSMITXDATA_C[3] TXDATAEN_C[3] CHITXDATA_C[7] VSSA_SFPLL_C CHITXDATA_C[12] CHITXDATA_C[15] VDD33 VDD33 CHIRXDATA_C[3] VDD33 CHIRXDATA_C[12] VDD15 VSS VDD33 VSS VDD33 VDD33 VDD15 VDD15 VDD15 VDD33 VDD15 VDD33 VDD33 VDD15 VSS VDD33 CHITXDATA_B[13] CHITXDATA_B[10] CHITXDATA_B[6] CHITXDATA_B[4] CHITXDATA_B[2] TXDATAEN_B[2] 17 TXDATAEN_C[2] CHITXDATA_C[2] CHITXDATA_C[4] CHITXDATA_C[6] CHITXDATA_C[10] CHITXDATA_C[13] VDD33 VSS VDD15 VDD33 VDD33 VDD15 VDD33 VDD15 VDD15 VDD15 VDD33 VDD33 VSS VDD33 VSS VDD15 CHIRXDATA_B[12] VDD33 CHIRXDATA_B[3] VDD33 VDD33 CHITXDATA_B[15] CHITXDATA_B[12] VSSA_SFPLL_B CHITXDATA_B[7] TXDATAEN_B[3] NSMITXDATA_B[3] NSMITXDATA_B[2] 18 21 TMXF33625 Hypermapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS0/E0 NC NC NC AM AN AP 22 VDD33 CHIRXGTCLK AF AL VSSA_E3PLL_D AE VDD33 VSS AD VDD15 LOPOHCLKOUT_D AC AK LOPOHVALIDIN_D AB AJ CHIRXDATA_D[11] AA CHITXGFS CHIRXDATA_D[17] Y ADDR[0] CHIRXDATA_D[18] W AH VSS V AG LOPOHCLKIN_B VDD15 CHIRXDATA_B[18] R U CHIRXDATA_B[16] T CHIRXDATA_B[15] P J N VSS H CHIRXDATA_B[9] CHITXDATA_B[11] G M VDD33A_SFPLL_B F CHIRXDATA_B[2] CHITXDATA_B[9] E CHIRXDATA_B[4] VDD15 D L CHITXDATA_B[3] C K NSMITXDATA_B[1] NSMITXSYNC_B[3] B RXDATAEN_B[3] A 19 NC NC VSS CSN_D VSS RWN ADDR[6] MPMODE CHITXGCLK VDD15A_E3PLL_D VSSA_DS3PLL_D VDD15A_DS3PLL_D LOPOHDATAOUT_D LOPOHCLKIN_D CHIRXDATA_D[13] CHIRXDATA_D[16] VDD33 VDD15 LOPOHDATAIN_B CHIRXDATA_B[17] CHIRXDATA_B[14] CHIRXDATA_B[10] CHIRXDATA_B[6] CHIRXDATA_B[1] CHITXDATA_B[18] CHITXDATA_B[14] CHITXDATA_B[8] NSMITXSYNC_B[1] TXDATAEN_B[1] NSMITXCLK_B[2] NSMITXSYNC_B[2] NSMIRXDATA_B[3] RXDATAEN_B[2] NSMIRXSYNC_B[2] 20 Table 2-2. Pin Matrix (continued) DS3POSDATAIN_D[1] VSS VSS VDD33 VSS ADDR[1] ADDR[2] MPCLK ADDR[5] ADSN TDO TCK LOPOHVALIDOUT_D LOPOHDATAIN_D CHIRXDATA_D[10] CHIRXDATA_D[15] VSS VDD15 LOPOHVALIDIN_B CHIRXDATA_B[13] CHIRXDATA_B[11] CHIRXDATA_B[7] CHIRXDATA_B[5] CHITXDATA_B[17] CHITXDATA_B[16] CG_PLLCLKOUT_B NSMITXCLK_B[3] NSMITXCLK_B[1] NSMIRXDATA_B[2] NSMIRXSYNC_B[3] VDD15 RXDATAEN_B[1] NSMIRXSYNC_B[1] NSMIRXDATA_B[1] 21 22 DS3POSDATAIN_D[2] VSS VSS VSS VDD33 ADDR[13] VDD15 ADDR[16] DATA[9] ADDR[7] ADDR[10] ADDR[14] ADDR[20] CHIRXDATA_D[6] CHIRXDATA_D[8] CHIRXDATA_D[14] VDD15 VDD33 LOPOHCLKOUT_B LOPOHVALIDOUT_B CHIRXDATA_B[8] DATA[14] DATA[6] DATA[2] CHITXDATA_B[5] CHITXDATA_B[1] VSS TPOACDATA_B NSMIRXCLK_B[2] TPOACCLK_B VDD33 IDDQ_B RHSFSYNCN_B RSTN_B TMXF33625 Hypermapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS0/E0 23 DS3NEGDATAIN_D[2] BYPASS_2 VSS VSS VDD33 VDD33 VDD15 DS3DATAINCLK_D[2] VSS VSS VSS VSS PAR[0] CHIRXDATA_D[4] CHIRXDATA_D[7] CHIRXDATA_D[9] CHIRXDATA_D[12] VDD15 LOPOHDATAOUT_B VDD15A_DS3PLL_B DS3XCLK PAR[1] VSS VSS VSS VSS NSMIRXCLK_B[3] NSMIRXCLK_B[1] RPOACCLK_B RPOACSYNC_B VSS TPOACSYNC_B RLSDATA_BP[3] RLSDATA_BN[2] 24 DS3NEGDATAIN_D[4] DS3POSDATAIN_D[3] DS3DATAINCLK_D[1] VSS DS3NEGDATAIN_D[1] DS3DATAINCLK_D[3] DS3POSDATAIN_D[4] DS3POSDATAOUT_D[2] VSS VSS VSS VSS DTN CHITXDATA_D[17] CHIRXDATA_D[1] CHIRXDATA_D[5] VDD33 VDD33 VSS VSSA_DS3PLL_B E3XCLK ADDR[17] VSS VSS VSS VSS LOSEXT_B TTOACDATA_B TTOACSYNC_B VDD15 TLSCLK_B VDD15A_CDR1_B RLSDATA_BN[3] RLSDATA_BP[2] 25 DS3NEGDATAIN_D[5] DS3DATAINCLK_D[4] DS3NEGDATAIN_D[3] DS3POSDATAIN_D[5] DS3POSDATAIN_D[6] DS3POSDATAOUT_D[1] DS3RXCLKOUT_D[5] RLSCLK_D VSS VSS VSS VSS CHITXDATA_D[5] CHITXDATA_D[16] CHITXDATA_D[18] CHIRXDATA_D[2] CHIRXDATA_D[3] VDD33 VSSA_E3PLL_B VDD15A_E3PLL_B DATA[4] ADDR[18] VSS VSS VSS VDD33 RTOACSYNC_B VDD15A_X4PLL_B VSSA_X4PLL_B THSSYNC_B RTOACCLK_B VSSA_CDR1_B TLSDATA_BN[2] RLSDATA_BN[1] DS3NEGDATAIN_D[6] APS_INTN_D DS3DATAINCLK_D[5] SCK2_2 DS3DATAOUTCLK_D[2] RESHI_D REF14_D CTAPTL_D VDD33 VDD33 VSS VDD15 CHITXDATA_D[1] CG_PLLCLKOUT_D CHITXDATA_D[14] VSS VDD33 VDD15 ADDR[8] ADDR[12] DATA[11] DATA[15] VSS VSS VSS VDD33 RPOACDATA_B VSS TTOACCLK_B RTOACDATA_B VSSA_CDR2_B TLSDATA_BN[1] TLSDATA_BP[2] RLSDATA_BP[1] 26 27 Agere Systems Inc. DS3DATAINCLK_D[6] DS3NEGDATAOUT_D[1] DS3RXCLKOUT_D[1] VDD33 DS3RXCLKOUT_D[3] VDD33 RESLO_D TLSDATA_DN[3] RPOACDATA_D RTOACSYNC_D LOSEXT_D NSMIRXCLK_D[3] VDD15 NSMITXCLK_D[3] CHITXDATA_D[8] CHITXDATA_D[11] VDD33 VSS ADDR[11] ADDR[4] DATA[10] VSS DS3DATAINCLK_B[2] DS3POSDATAOUT_B[2] RLSCLK_B CTAPTL_B TLSDATA_BN[3] TLSDATA_BP[3] VDD15 VDD15A_CDR2_B RPSC_BP TLSDATA_BP[1] TPSD_BP TPSD_BN Hardware Design Guide, Revision 3 September 18, 2003 CTAPRP_D CTAPTH_D AH AJ DS3DATAOUTCLK_D[1] AN AP Agere Systems Inc. DS3POSDATAOUT_D[3] DS3NEGDATAOUT_D[2] AM DS3RXCLKOUT_D[6] TLSDATA_DP[3] AG DS3RXCLKOUT_D[4] ETOGGLE_2 AF AL VDD15A_X4PLL_D AE AK TTOACDATA_D AD NSMITXCLK_D[1] AA TPOACDATA_D NSMITXSYNC_D[1] Y NSMIRXCLK_D[1] VDD33A_SFPLL_D W AC CHITXDATA_D[15] V AB VDD33 U DS3POSDATAIN_B[4] L DSN DS3RXCLKOUT_B[5] K ADDR[9] REF14_B J T RESLO_B H R CTAPRP_B G DATA[1] E1XCLK_2 F P VDD33 E VDD15 RPSC_BN D VDD15 RPSD_BN C N TPSC_BP B M TPSC_BN A 28 29 DS3RXCLKOUT_D[2] DS3NEGDATAOUT_D[3] DS3NEGDATAOUT_D[4] VSS VDD15 CTAPRH_D ECSEL_2 VDD15 TTOACCLK_D VSSA_X4PLL_D TTOACSYNC_D RPOACCLK_D NSMIRXCLK_D[2] NSMIRXDATA_D[2] TXDATAEN_D[1] CHITXDATA_D[9] CHITXDATA_D[12] CHITXDATA_D[13] VDD15 ADDR[3] ADDR[15] ADDR[19] VDD33 DS3DATAINCLK_B[3] DS3POSDATAOUT_B[1] RESHI_B VDD33 CTAPTH_B CTAPRH_B VDD15 REF10_B RPSD_BP VSS VSS Table 2-2. Pin Matrix (continued) Hardware Design Guide, Revision 3 September 18, 2003 30 DS3DATAOUTCLK_D[3] VDD15 DS3POSDATAOUT_D[5] DS3DATAOUTCLK_D[6] SCANMODE_2 VDD15 VDD33 VDD15A_CDR2_D RTOACDATA_D THSSYNC_D VDD15 RPOACSYNC_D TPOACCLK_D NSMIRXSYNC_D[3] NSMITXCLK_D[2] VDD15 VSSA_SFPLL_D CHITXDATA_D[10] VDD33 VSS VSS VDD33 VDD33 DS3NEGDATAIN_B[1] DS3POSDATAIN_B[6] DS3DATAOUTCLK_B[2] DS3RXCLKOUT_B[3] DS3RXCLKOUT_B[6] VDD15 VDD33 RHSC_BP RHSC_BN THSC_BP THSC_BN 31 DS3POSDATAOUT_D[4] DS3DATAOUTCLK_D[4] DS3NEGDATAOUT_D[6] VDD33 RHSC_DP REF10_D RPSC_DN RPSC_DP VSSA_CDR2_D RTOACCLK_D TLSCLK_D TMS_2 VDD33 SCK1_2 NSMITXSYNC_D[2] CHITXDATA_D[3] CHITXDATA_D[7] CHITXDATA_D[6] VDD33 CSN_B VDD33 VSS VSS VSS DS3POSDATAIN_B[5] VDD33 VDD15 DS3RXCLKOUT_B[4] VSS DS3DATAOUTCLK_B[6] EXDNUP_2 RHSD_BP THSD_BP THSD_BN 32 DS3NEGDATAOUT_D[5] DS3POSDATAOUT_D[6] RHSD_DN RHSD_DP RHSC_DN RPSD_DP RPSD_DN TLSDATA_DP[1] TLSDATA_DN[1] VSSA_CDR1_D VDD15A_CDR1_D TPOACSYNC_D IDDQ_D RXDATAEN_D[1] NSMIRXDATA_D[3] NSMITXSYNC_D[3] TXDATAEN_D[3] CHITXDATA_D[4] VDD15 VSS VSS VSS VSS DS3DATAINCLK_B[1] DS3NEGDATAIN_B[3] DS3DATAINCLK_B[5] DS3RXCLKOUT_B[1] DS3POSDATAOUT_B[3] DS3NEGDATAOUT_B[4] DS3POSDATAOUT_B[5] DS3NEGDATAOUT_B[6] RHSD_BN VSS VSS 33 DS3DATAOUTCLK_D[5] THSCO_DP VSS THSD_DP THSC_DP VSS TPSC_DP TPSD_DP TLSDATA_DP[2] TLSDATA_DN[2] RLSDATA_DN[3] RLSDATA_DP[3] RHSFSYNCN_D NSMIRXSYNC_D[1] RXDATAEN_D[2] NSMITXDATA_D[1] NSMITXDATA_D[3] CHITXDATA_D[2] VDD15 VDD15 VSS VSS HP_INTN_2 DS3POSDATAIN_B[3] DS3DATAINCLK_B[4] APS_INTN_B DS3NEGDATAOUT_B[1] DS3NEGDATAOUT_B[2] DS3NEGDATAOUT_B[3] DS1XCLK_2 DS3DATAOUTCLK_B[4] DS3POSDATAOUT_B[6] THSCO_BP THSCO_BN THSCO_DN VSS THSD_DN THSC_DN VSS TPSC_DN TPSD_DN -- RLSDATA_DP[1] RLSDATA_DN[1] RLSDATA_DP[2] RLSDATA_DN[2] RSTN_D NSMIRXDATA_D[1] NSMIRXSYNC_D[2] RXDATAEN_D[3] NSMITXDATA_D[2] TXDATAEN_D[2] VDD15 VDD15 DS3POSDATAIN_B[1] DS3POSDATAIN_B[2] DS3NEGDATAIN_B[2] DS3NEGDATAIN_B[4] DS3NEGDATAIN_B[5] DS3NEGDATAIN_B[6] DS3DATAINCLK_B[6] DS3DATAOUTCLK_B[1] DS3RXCLKOUT_B[2] DS3DATAOUTCLK_B[3] DS3POSDATAOUT_B[4] DS3NEGDATAOUT_B[5] DS3DATAOUTCLK_B[5] -- 34 23 TMXF33625 Hypermapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS0/E0 TMXF33625 Hypermapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS0/E0 Hardware Design Guide, Revision 3 September 18, 2003 2.4 Pin Types Table 2-3 describes each type of input, output, and I/O pin used in the Hypermapper. Table 2-3. Pin Types Type Label I LVCMOS Input, LVTTL Switching Thresholds. I pd LVCMOS Input, LVTTL Switching Thresholds with Internal 50 k Pull-Down Resistor. I pd 1 LVCMOS Input, LVTTL Switching Thresholds with Internal 25 k Pull-Down Resistor. I pd 2 LVCMOS Input, LVTTL Switching Thresholds with Internal 12.5 k Pull-Down Resistor. LVCMOS Input, LVTTL Switching Thresholds with Internal 50 k Pull-Up Resistor. I pu I pu 1 LVCMOS Input, LVTTL Switching Thresholds with Internal 25 k Pull-Up Resistor. I pu 2 LVCMOS Input, LVTTL Switching Thresholds with Internal 12.5 k Pull-Up Resistor. O O od LIN LOUT I/O I/O pd -- 24 Description LVCMOS Output. Open-Drain Output. LVDS Inputs. LVDS Outputs. Bidirectional Pin. LVCMOS input with LVTTL switching thresholds and LVCMOS output. Bidirectional Pin. LVCMOS input with LVTTL switching thresholds with internal 50 k pull-down resistor and LVCMOS output. Power, Ground, Analog Inputs for External Resistors, Capacitors, Voltage References, etc. Agere Systems Inc. Hardware Design Guide, Revision 3 September 18, 2003 TMXF33625 Hypermapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS0/E0 2.5 Pin Definitions This section describes the function of each of the device pins. All LVDS input buffers have built-in 100 terminating resistor with a center tap pin available for external capacitor connection. All unused LVDS inputs may be left unconnected. Pin functionality is descriptive information. The actual functionality is dependent upon the device configuration via the registers. Table 2-4. TMUX Blocks, High-Speed Interface I/O Symbol Pin Type RHSD_AP D3 LIN RHSD_BP C31 RHSD_CP AM4 Receive High-Speed Data. 622/155 Mbits/s input data; also, input to internal clock and data recovery (CDR). CDR may be bypassed in 155 Mbits/s mode. The internal CDR must be used in 622 Mbits/s mode. RHSD_DP AL32 RHSD_AN C3 RHSD_BN C32 RHSD_CN AM3 RHSD_DN AM32 RHSC_AP E4 LIN RHSC_BP D30 Receive High-Speed Clock. 155 MHz input clock for 155 Mbits/s data if CDR is bypassed. Not used in 622 Mbits/s mode. RHSC_CP AL5 RHSC_DP AK31 RHSC_AN E3 RHSC_BN C30 RHSC_CN AM5 -- Center Tap RH. LVDS buffer terminator center tap for RHSDP/N and RHSCP/N. An optional 0.1 F capacitor, connected between CTAP pin and ground, will improve the common-mode rejection of the LVDS input buffers. I pu External Loss of Signal Input. Active level is programmable by register TMUX_LOSEXT_LEVEL, defaults to active-low. This pin can be part of the high-priority interrupt when active. Usually connected to optical transceiver to indicate loss of signal. RHSC_DN AK32 CTAPRH_A F6 CTAPRH_B F29 CTAPRH_C AJ6 CTAPRH_D AJ29 LOSEXT_A L8 LOSEXT_B H24 LOSEXT_C AG11 LOSEXT_D AD27 THSD_AP C2 THSD_BP B31 THSD_CP AN4 THSD_DP AL33 THSD_AN C1 THSD_BN A31 THSD_CN AP4 THSD_DN AL34 Agere Systems Inc. Name/Description LOUT Transmit High-Speed Data. 622/155 Mbits/s output data. The frame location in slave mode is determined by THSSYNC and transmit high-speed control parameter register (TMUX_TFRAMEOFFSETA). In master mode, the frame timing is arbitrary. 25 TMXF33625 Hypermapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS0/E0 Hardware Design Guide, Revision 3 September 18, 2003 Table 2-4. TMUX Blocks, High-Speed Interface I/O (continued) Symbol Pin Type THSCO_AP B2 LOUT Transmit High-Speed Clock Output. 622/155 MHz transmit output clock associated with THSDP/N. THSCO_BP B33 THSCO_CP AN2 THSCO_DP AN33 THSCO_AN B1 THSCO_BN A33 THSCO_CN AP2 THSCO_DN AN34 RESHI_A F9 RESHI_B J29 RESHI_C AF6 RESHI_D AJ26 RESLO_A G8 RESLO_B H28 RESLO_C AG7 RESLO_D AH27 * F4 * D29 REF10_C* AL6 REF10_A REF10_B * AJ31 * G9 REF10_D REF14_A * REF14_B J28 REF14_C* AF7 REF14_D* AH26 -- Name/Description Resistor. A 100 , 1% resistor is required between the RESHI_X and RESLO_X pins as a reference for the LVDS input buffer termination. I Reference 1.0 V. External 1 V reference voltage pin. (Optional.) I Reference 1.4 V. External 1.4 V reference voltage pin. (Optional.) * Optional: selected by MPU/top-level register. External reference voltage can be sourced from a low-impedance resistor (less than 1 k) divider circuit decoupled with a 0.1 F capacitor. 26 Agere Systems Inc. Hardware Design Guide, Revision 3 September 18, 2003 TMXF33625 Hypermapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS0/E0 Table 2-5. TMUX Blocks, Protection Link I/O Symbol Pin Type Name/Description RPSD_AP RPSD_BP RPSD_CP RPSD_DP RPSD_AN RPSD_BN RPSD_CN RPSD_DN RPSC_AP RPSC_BP RPSC_CP RPSC_DP RPSC_AN RPSC_BN RPSC_CN RPSC_DN CTAPRP_A CTAPRP_B CTAPRP_C CTAPRP_D TPSD_AP TPSD_BP TPSD_CP TPSD_DP TPSD_AN TPSD_BN TPSD_CN TPSD_DN TPSC_AP TPSC_BP TPSC_CP TPSC_DP TPSC_AN TPSC_BN TPSC_CN TPSC_DN F3 C29 AM6 AJ32 G3 C28 AM7 AH32 H4 D27 AL8 AG31 G4 D28 AL7 AH31 G7 G28 AH7 AH28 H2 B27 AN8 AG33 H1 A27 AP8 AG34 G2 B28 AN7 AH33 G1 A28 AP7 AH34 LIN Receive Protection High-Speed Data. 622/155 Mbits/s protection input data; also input to internal protection CDR. CDR may be bypassed in 155 Mbits/s mode. The internal CDR must be used in 622 Mbits/s mode. LIN Receive Protection High-Speed Clock. 155 MHz input clock for 155 Mbits/s data if protection CDR is bypassed. Not used in 622 Mbits/s mode. -- Center Tap RP. LVDS buffer terminator center tap for RPSDP/N and RPSCP/N. An optional 0.1 F capacitor, connected between the CTAP pin and ground, will improve the common-mode rejection of the LVDS input buffers. Agere Systems Inc. LOUT Transmit Protection High-Speed Data. 622/155 Mbits/s protection output data. LOUT Transmit Protection High-Speed Clock. 622/155 MHz transmit output clock associated with TPSDP/N. 27 TMXF33625 Hypermapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS0/E0 Hardware Design Guide, Revision 3 September 18, 2003 Table 2-6. TMUX Blocks, Clock and Sync I/O Symbol THSC_AP THSC_BP THSC_CP THSC_DP THSC_AN THSC_BN THSC_CN THSC_DN CTAPTH_A CTAPTH_B CTAPTH_C CTAPTH_D RHSFSYNCN_A RHSFSYNCN_B RHSFSYNCN_C RHSFSYNCN_D RLSCLK_A RLSCLK_B RLSCLK_C RLSCLK_D TLSCLK_A TLSCLK_B TLSCLK_C TLSCLK_D THSSYNC_A THSSYNC_B THSSYNC_C THSSYNC_D Pin Type E2 LIN B30 AN5 AK33 E1 A30 AP5 AK34 F7 -- G29 AH6 AJ28 N2 O B22 AN13 AB33 H10 O K27 AE8 AG25 L4 O D24 AL11 AD31 K5 I/O pd E25 AK10 AE30 Name/Description Transmit High-Speed Clock. 622/155 MHz input clock for the transmit 622/155 Mbits/s data; also used as a reference clock for all CDRs. There are five CDR circuits per partition (A--D). The high-speed data and protection high-speed data have CDRs that operate at 155 MHz or 622 MHz. The mate inputs have three CDRs that operate at 155 MHz. The clock on this pin is also internally routed to the DS1/E1 framers and is used as an internal master clock. Note: A 622 MHz clock must be supplied when the device operates in 622 Mbits/s mode. A 155 MHz clock must be supplied when the device operates in 155 Mbits/s mode. Center Tap TH. LVDS buffer terminator center tap for THSCP/N. An optional 0.1 F capacitor, connected between the CTAP pin and ground, will improve the common-mode rejection of the LVDS input buffers. Receive High-Speed Frame Sync. This output indicates the start of the frame in the high-speed data input. Only present when a valid frame signal is detected on the RHSDP/N inputs. It is an active-low pulse with width almost equal to one E1 clock period or approximately 500 ns. Receive Low-Speed Clock. 19.44 MHz receive output clock divided down from either RHSCP/N or the recovered high-speed clock (when the CDR is used). May be used as a system timing reference. Transmit Low-Speed Clock. 19.44 MHz transmit output clock divided down from THSCP/N. Transmit High-Speed Frame Sync. 2 kHz/8 kHz composite frame sync signal that identifies the locations of the J0, J1-1, J1-2, J1-3 . . . J1-12, and V1-1 bytes. This signal is used to align transmit frames before multiplexing. Note: J0, J1-1, J1-2, and J1-3 . . . , J1-12 occur every 125 s. V1-1 occurs every 500 s. If the register MPU_MASTER_SLAVE = 1, THSSYNC is an output; otherwise, THSSYNC is an input. The positive 8 kHz and 2 kHz pulses are synchronized to TLSCLK. The rising edge is referenced for frame location. For master/slave configuration, the THSSYNC of Hypermapper partitions (A, B, C, and D; up to four) must be connected together. The master can be one of the Hypermapper partitions (A, B, C, or D), and it sources the frame sync pulse to other Hypermapper partitions. All Hypermapper partitions (A, B, C, and D) can also be configured as slaves and receive frame sync from the external system frame sync. 28 Agere Systems Inc. Hardware Design Guide, Revision 3 September 18, 2003 TMXF33625 Hypermapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS0/E0 Table 2-7. STS Cross Connect (STSXC) Blocks, STS-3/STM-1 Mate Interconnect Symbol RLSDATA_AP[3:1] RLSDATA_BP[3:1] RLSDATA_CP[3:1] RLSDATA_DP[3:1] RLSDATA_AN[3:1] RLSDATA_BN[3:1] RLSDATA_CN[3:1] RLSDATA_DN[3:1] TLSDATA_AP[3:1] TLSDATA_BP[3:1] TLSDATA_CP[3:1] TLSDATA_DP[3:1] TLSDATA_AN[3:1] TLSDATA_BN[3:1] TLSDATA_CN[3:1] TLSDATA_DN[3:1] CTAPTL_A CTAPTL_B CTAPTL_C CTAPTL_D Agere Systems Inc. Pin Type M2, L1, J1 LOUT B23, A24, A26 AN12, AP11, AP9 AC33, AD34, AF34 L2, M1, K1 B24, A23, A25 AN11, AP12, AP10 AD33, AC34, AE34 H7, J2, H3 LIN G27, B26, C27 AH8, AN9, AM8 AG28, AF33, AG32 H8, K2, J3 H27, B25, C26 AG8, AN10, AM9 AG27, AE33, AF32 H9 -- J27 AF8 AG26 Name/Description Receive Low-Speed Data. These pins are only used in 622 Mbits/s applications. They are used only on the master partition (A, B, C, or D). Connect these pins to the high-speed data inputs (RHSDP/N) of the slave partitions. This 155 Mbits/s signal uses a SONET structure. The overheads supported are the A1/A2 and B2 bytes and line RDI. The data is scrambled. Data from the RHSD is routed via the STSXC. Transmit Low-Speed Data. These pins are only used in 622 Mbits/s applications. They are used only on the master partition (A, B, C, or D). Connect these pins to the high-speed data outputs (THSDP/N) of the slave partitions. This 155 Mbits/s input receives data from the slave high-speed outputs. These inputs have built-in clock and data recovery (CDR). The frame location expects a fixed relationship to the high-speed transmit frame sync (THSSYNC). Center Tap TL. LVDS buffer terminator center tap for TLSDATAP/N. An optional 0.1 F capacitor, connected between the CTAP pin and ground, will improve the common-mode rejection of the LVDS input buffers. 29 TMXF33625 Hypermapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS0/E0 Hardware Design Guide, Revision 3 September 18, 2003 Table 2-8. Multirate Cross Connect (MRXC) Blocks, TOAC Input and Output Channels Symbol Pin Type RTOACCLK_A RTOACCLK_B RTOACCLK_C RTOACCLK_D RTOACDATA_A RTOACDATA_B RTOACDATA_C RTOACDATA_D RTOACSYNC_A RTOACSYNC_B RTOACSYNC_C RTOACSYNC_D TTOACCLK_A TTOACCLK_B TTOACCLK_C TTOACCLK_D TTOACDATA_A TTOACDATA_B TTOACDATA_C TTOACDATA_D TTOACSYNC_A TTOACSYNC_B TTOACSYNC_C TTOACSYNC_D K4 D25 AL10 AE31 J5 E26 AK9 AF30 K8 H25 AG10 AE27 J6 F26 AJ9 AF29 L7 G24 AH11 AD28 L6 F24 AJ11 AD29 O Receive Transport Overhead Access Channel Clock. The frequency of this clock is determined by the TOAC provisioning registers. O Receive Transport Overhead Access Channel Data. 622/155 Mbits/s transport overhead bytes are output on this pin. The content is determined by the TOAC provisioning registers. O Receive Transport Overhead Access Channel Sync. Active-high 8 kHz frame sync. It is active during the clock period of the first bit of each frame. O Transmit Transport Overhead Access Channel Clock. The frequency of this clock is determined by the TOAC provisioning registers. 30 Name/Description I pd Transmit Transport Overhead Access Channel Data. Input for the transport overhead bytes. O Transmit Transport Overhead Access Channel Sync. Active-high 8 kHz frame sync. It is active during the clock period of the first bit of each frame. Agere Systems Inc. Hardware Design Guide, Revision 3 September 18, 2003 TMXF33625 Hypermapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS0/E0 Table 2-9. Multirate Cross Connect (MRXC) Blocks, POAC Input and Output Channels Symbol Pin RPOACCLK_A M6 RPOACCLK_B F23 RPOACCLK_C AJ12 RPOACCLK_D AC29 RPOACDATA_A J8 RPOACDATA_B H26 RPOACDATA_C AG9 RPOACDATA_D AF27 RPOACSYNC_A M5 RPOACSYNC_B E23 RPOACSYNC_C AK12 RPOACSYNC_D AC30 TPOACCLK_A N5 TPOACCLK_B E22 TPOACCLK_C AK13 TPOACCLK_D AB30 TPOACDATA_A N7 TPOACDATA_B G22 TPOACDATA_C AH13 TPOACDATA_D AB28 TPOACSYNC_A M3 TPOACSYNC_B C23 TPOACSYNC_C AM12 TPOACSYNC_D AC32 Agere Systems Inc. Type Name/Description O Receive Path Overhead Access Channel Clock. Output for the path overhead bytes. This is a 3-state output pin controlled by register provisioning. O Receive Path Overhead Access Channel Data. Output for the path overhead bytes. This pin can be 3-stated. O Receive Path Overhead Access Channel Sync. Output for POAC channel. Activehigh during the first bit of each frame. This pin can be individually 3-stated. O Transmit Path Overhead Access Channel Clock. Serial access channel clock output for the path overhead bytes. This pin can be individually 3-stated. I pd Transmit Path Overhead Access Channel Data. Serial access channel data input for the path overhead bytes. O Transmit Path Overhead Access Channel Sync. Sync output for POAC channel. Active-high during the first bit of each frame. This pin can be individually 3-stated. 31 TMXF33625 Hypermapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS0/E0 Hardware Design Guide, Revision 3 September 18, 2003 Table 2-10. DS3/E3/STS-1 Out Symbol DS3POSDATAOUT_A[6:1] DS3POSDATAOUT_B[6:1] DS3POSDATAOUT_C[6:1] DS3POSDATAOUT_D[6:1] DS3NEGDATAOUT_A[6:1] DS3NEGDATAOUT_B[6:1] DS3NEGDATAOUT_C[6:1] DS3NEGDATAOUT_D[6:1] DS3DATAOUTCLK_A[6:1] DS3DATAOUTCLK_B[6:1] DS3DATAOUTCLK_C[6:1] DS3DATAOUTCLK_D[6:1] DS3RXCLKOUT_A[6:1] DS3RXCLKOUT_B[6:1] DS3RXCLKOUT_C[6:1] DS3RXCLKOUT_D[6:1] 32 Pin Type B3, C5, A4, C7, H11, O F10 C33, E32, D34, G32, L27, K29 AM2, AK3, AL1, AH3, AD8, AE6 AN32, AM30, AP31, AM28, AG24, AJ25 C4, A3, C6, B6, B7, B8 O D32, C34, F32, F33, G33, H33 AL3, AM1, AJ3, AJ2, AH2, AG2 AM31, AP32, AM29, AN29, AN28, AN27 D5, A2, B4, A5, E9, A7 I pd E31, B34, D33, E34, J30, G34 AK4, AN1, AL2, AK1, AF5, AH1 AL30, AP33, AN31, AP30, AK26, AP28 E7, G10, D7, E8, A6, C8 G30, K28, G31, H30, F34, H32 AH5, AE7, AH4, AG5, AJ1, AG3 AK28, AH25, AL28, AK27, AP29, AM27 O Name/Description DS3/E3/STS-1 Positive Data Output. Either contains the positive-rail of the B3ZS/HDB3 encoded output data, or single-rail NRZ data. DS3/E3/STS-1 Negative Data Output. Negative-rail B3ZS/ HDB3 encoded output data. Not used in single-rail mode (held low in this case). DS3/E3/STS-1 Data Output Clock. 44.736 MHz, 34.368 MHz, or 51.84 MHz clock input. This clock is required for M13, E13, or STS1LT applications and is typically connected to a crystal oscillator or clocking chip. For DS3/E3 to SONET/SDH mapping applications, the DS3/ E3 DJA is used, and this clock is therefore not required. DS3XCLK/E3XCLK is needed for DS3/E3 DJA in this case. For STS-1 to SONET mapping applications, the TMUX can be used to supply the STS-1 rate DATAOUT clock and therefore this clock is not needed. For STS-1 PDH applications, a 51.84 MHz clock must be supplied at this pin. DS3/E3/STS-1 Receive Clock Output. 44.736 MHz DS3, 34.368 MHz E3, and 51.84 MHz STS-1 clock out to external circuit. Agere Systems Inc. Hardware Design Guide, Revision 3 September 18, 2003 TMXF33625 Hypermapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS0/E0 Table 2-11. DS3/E3/STS-1 In Symbol Pin DS3POSDATAIN_A[6:1] E10, D10, G11, B11, A13, A14 DS3POSDATAIN_B[6:1] K30, K31, L28, L33, N34, P34 DS3POSDATAIN_C[6:1] AE5, AE4, AD7, AD2, AB1, AA1 DS3POSDATAIN_D[6:1] AK25, AL25, AH24, AN24, AP22, AP21 DS3NEGDATAIN_A[6:1] A9, A10, A11, C10, A12, E11 DS3NEGDATAIN_B[6:1] J34, K34, L34, K32, M34, L30 DS3NEGDATAIN_C[6:1] AF1, AE1, AD1, AE3, AC1, AD5 DS3NEGDATAIN_D[6:1] AP26, AP25, AP24, AM25, AP23, AK24 DS3DATAINCLK_A[6:1] A8, C9, B10, F11, H12, C11 DS3DATAINCLK_B[6:1] H34, J32, K33, L29, M27, L32 DS3DATAINCLK_C[6:1] AG1, AF3, AE2, AD6, AC8, AD3 DS3DATAINCLK_D[6:1] AP27, AM26, AN25, AJ24, AG23, AM24 Agere Systems Inc. Type Name/Description I pd DS3/E3/STS-1 Positive Data Input. Either contains the positive rail of the B3ZS/HDB3 encoded input data or single-rail NRZ data. I pd DS3/E3/STS-1 Negative Data Input. Either contains the negative rail of the B3ZS/HDB3 encoded input data or, in single-rail mode, this input may be used to count bipolar violations. I pd DS3/E3/STS-1 Data Input Clock. 44.736 MHz, 34.368 MHz, or 51.84 MHz clock for the DS3/E3/STS-1 positive and negative data inputs. 33 TMXF33625 Hypermapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS0/E0 Hardware Design Guide, Revision 3 September 18, 2003 Table 2-12. NSMI/STS-1 In Symbol Pin Type NSMIRXDATA_A[3:1] NSMIRXDATA_B[3:1] NSMIRXDATA_C[3:1] NSMIRXDATA_D[3:1] R3, P6, P1 C20, F21, A21 AM15, AJ14, AP14 Y32, AA29, AA34 I pd NSMIRXCLK_A[3:1] NSMIRXCLK_B[3:1] NSMIRXCLK_C[3:1] NSMIRXCLK_D[3:1] NSMIRXSYNC_A[3:1] NSMIRXSYNC_B[3:1] NSMIRXSYNC_C[3:1] NSMIRXSYNC_D[3:1] RXDATAEN_A[3:1] RXDATAEN_B[3:1] RXDATAEN_C[3:1] RXDATAEN_D[3:1] M8, N6, M7 H23, F22, G23 AG12, AJ13, AH12 AC27, AB29, AC28 P5, R1, P2 E21, A20, B21 AK14, AP15, AN14 AA30, Y34, AA33 T1, R2, P3 A19, B20, C21 AP16, AN15, AM14 W34, Y33, AA32 Name/Description Network Serial Multiplex Interface (NSMI) Receive* Data. Used in the following applications: 51.84 Mbits/s serial data input that is used to bring in multiplexed DS1 or E1 channels to FRM. STS-1 rate clear-channel receive data to SPEMPR. DS3/E3 rate clear-channel receive data to M13/E13. Additionally, it could be used as a SONET compliant STS-1 input signal to STS1LT from external LIU. I/O pd NSMI Receive Clock. Used in the following applications: Input (51.84 MHz) for the DS1/E1 application. Output (51.84 MHz) for the STS-1 rate clear-channel application. Output (44.736 MHz/34.368 MHz) for the DS3/E3 application. Additionally, it could be used as an input clock for SONET compliant STS-1 to STS1LT from external LIU. I/O pd NSMI Receive Frame Sync. Used in the following applications: O Input receive NSMI control for FRM. Output receive control frame sync signal for M13/E13. Output receive control frame sync signal for SPEMPR. Additionally, it could be used to carry STS-1 input transmit clock for STS1LTs. NSMI Receive Data Enable. This is used for an 8-pin NSMI mode receive clock. More information will be published in a separate operational guide. * The transmit path is toward the high-speed fiber output and the receive path is from the high-speed input. Low-speed inputs, e.g., NSMIRXDATA, on the transmit path are labeled receive. Low-speed outputs, e.g., NSMITXDATA, on the receive path are labeled transmit. 34 Agere Systems Inc. Hardware Design Guide, Revision 3 September 18, 2003 TMXF33625 Hypermapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS0/E0 Table 2-13. NSMI/STS-1 Out Symbol Pin Type NSMITXDATA_A[3:1] U2, U1, T2 NSMITXDATA_B[3:1] B18, A18, B19 NSMITXDATA_C[3:1] AN17, AP17, AN16 NSMITXDATA_D[3:1] V33, V34, W33 NSMITXCLK_A[3:1] P8, R5, P7 NSMITXCLK_B[3:1] H21, E20, G21 NSMITXCLK_C[3:1] AG14, AK15, AH14 NSMITXCLK_D[3:1] AA27, Y30, AA28 NSMITXSYNC_A[3:1] T3, R4, R7 NSMITXSYNC_B[3:1] C19, D20, G20 NSMITXSYNC_C[3:1] AM16, AL15, AH15 NSMITXSYNC_D[3:1] W32, Y31, Y28 TXDATAEN_A[3:1] U3, V1, R6 TXDATAEN_B[3:1] C18, A17, F20 TXDATAEN_C[3:1] AM17, AP18, AJ15 TXDATAEN_D[3:1] V32, U34, Y29 Name/Description O NSMI Transmit Data. NSMI outputs or STS-1 Tx data outputs from STS1LTs. NSMI output data from either the FRM, SPEMPR, or M13/E13 block. O NSMI Transmit Clock Output or STS-1 Tx Clock Outputs from STS1LTs. Output clock at 51.84 MHz for the DS1/E1 application, the (51.84 MHz) STS-1 rate clear-channel application, or a (44.736 MHz/34.368 MHz) output clock for the DS3/E3 application. O Transmit System Frame Sync Output. Output transmit control frame sync signal from FRM, M13/E13 or SPEMPR. O Transmit Data Enable for NSMI Mode. This is used for an 8-pin NSMI mode transmit control frame sync. More information will be published in a separate operational guide. Note: The transmit path is toward the high-speed fiber output and the receive path is from the high-speed input. Low-speed inputs, e.g., NSMIRXDATA, on the transmit path are labeled receive. Low-speed outputs, e.g., NSMITXDATA, on the receive path are labeled transmit. Table 2-14. TDM Concentration Highway (CHI) In Symbol CHIRXDATA_A[18:1] Pin T15, R15, T14, T13, R14, P14, U12, R13, P13, T12, R12, P12, N12, T11, R11, U10, T10, P11 CHIRXDATA_B[18:1] R19, R20, P19, N19, P20, R21, M18, P21, N20, M19, P22, N21, M20, M21, L19, K18, K19, L20 CHIRXDATA_C[18:1] Y16, Y15, AA16, AA15, AB16, AA14, AC17, AB15, AC16, Y14, AC15, AB14, AA13, AD16, AD15, AE17, AE16, AC14 CHIRXDATA_D[18:1] W19, Y19, W20, W21, W22, Y20, V23, AA19, Y21, W23, Y22, Y23, AA22, W24, AA23, V25, W25, Y24 Type Name/Description I pd CHI Receive Data [18:1]. Configurable synchronous TDM inputs to the internal multirate cross connect. Can be used in one of the following modes: CHI mode: Receive TDM input highways. Can be configured to operate at 8.192 Mbits/s or 16.384 Mbits/s. Parallel system bus mode: The parallel system bus is a 16-bit wide 19.44 Mbits/s synchronous TDM highway. Bits [16:9] are used for time-slot data. Bits [8:11] are used for robbed-bit signaling data in an ASM like fashion and are optional. CHIRXGFS is the frame synchronization input for the parallel system bus, and CHIRXGCLK is the 19.44 MHz clock input. CHIRXDATA[18:17] are not used. Note: The transmit path is toward the high-speed fiber output and the receive path is from the high-speed input. Low-speed inputs, e.g., CHIRXDATA, on the transmit path are labeled receive. Low-speed outputs, e.g., CHITXDATA, on the receive path are labeled transmit. Agere Systems Inc. 35 TMXF33625 Hypermapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS0/E0 Hardware Design Guide, Revision 3 September 18, 2003 Table 2-15. TDM Concentration Highway (CHI) Out Symbol Pin CHITXDATA_A[18:1] R10, N11, P10, U7, R9, V6, U6, T8, V5, T6, R8, U4, V4, N10, V3, T4, V2, N9 CHITXDATA_B[18:1] K20, L21, K21, G18, J20, F17, F18, H19, E17, F19, H20, D18, D17, K22, C17, D19, B17, J22 CHITXDATA_C[18:1] AE15, AD14, AE14, AH17, AF15, AJ18, AJ17, AG16, AK18, AJ16, AG15, AL17, AL18, AE13, AM18, AL16, AN18, AF13 CHITXDATA_D[18:1] Y25, AA24, AA25, V28, Y26, U29, V29, W27, U30, W29, Y27, V31, U31, AB25, U32, W31, U33, AB26 Type Name/Description O CHI Transmit Data [18:1]. Configurable synchronous TDM outputs from the internal multirate cross connect. Can be used in one of the following modes: CHI mode: Transmit TDM output highways. Can be configured to operate at 8.192 Mbits/s or at 16.384 Mbits/s. Parallel system bus mode: The parallel system bus is a 16-bit wide 19.44 Mbits/s synchronous TDM highway. Bits [16:9] are used for time-slot data. Bits [8:1] are used for robbed-bit signaling data in an ASM like fashion and are optional. CHITXGFS is the frame synchronization input for the parallel system bus, and CHITXGCLK is the 19.44 MHz clock input. CHITXDATA[18:17] are not used. Each of these outputs comes from the internal MRXC and can be individually set to high impedance. Note: The transmit path is toward the high-speed fiber output and the receive path is from the high-speed input. Low-speed inputs, e.g., CHIRXDATA, on the transmit path are labeled receive. Low-speed outputs, e.g., CHITXDATA, on the receive path are labeled transmit. Table 2-16. Framer (FRM) Blocks, CHI/Parallel System Bus (PSB) Clock and Sync Symbol Pin CHIRXGTCLK AF19 CHIRXGCLK AC13 CHIRXGFS AB13 CHITXGFS CHITXGCLK 36 AG19 AF20 Type Name/Description I pd 2 Global Transmit Line Clock. This is the transmit line clock for the DS1 or E1 framer. Normally, this input is not used and the transmit clock is generated by an internal phase-lock loop, which uses CLKIN_PLL as a reference. Note that if this input is used, all transmit framers must run at the same rate, either 1.544 MHz or 2.048 MHz. This signal could be used for both CHI and parallel system buses. I pd 2 Receive Global System Clock. This signal is used for both CHI and parallel system buses. In CHI mode, it is a 8.192 MHz or a 16.384 MHz TDM clock. In parallel system bus mode, it is a 19.44 MHz clock. I pd 2 Receive System Frame Sync. This signal is used for both CHI and parallel system buses. In CHI mode, it is an 8 kHz pulse that references the location of time slots in the receive CHI inputs. Its polarity, sampling edge, and offset from time slots in the concentration highways may all be programmed. In parallel system bus mode, it is an 8 kHz reference for time slots within the parallel system bus input highways. In this mode, the frame strobe is a positive pulse with an active edge provisioned by a register. I pd 2 Transmit System Frame Sync. This signal is used for both CHI and parallel system buses. In CHI mode, it is an 8 kHz pulse that references the location of time slots in the transmit CHI outputs. Its polarity, sampling edge, and offset from time slots in the concentration highways may all be programmed. In parallel system bus mode, it is an 8 kHz reference for time slots within the parallel system bus output highways. In this mode, the frame strobe is a positive pulse with active edge provisioned by a register. I pd 2 Transmit Global System Clock. This signal is used for both CHI and parallel system buses. In CHI mode, it is an 8.192 MHz or a 16.384 MHz TDM clock. In parallel system bus mode, it is a 19.44 MHz clock. Agere Systems Inc. Hardware Design Guide, Revision 3 September 18, 2003 TMXF33625 Hypermapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS0/E0 Table 2-17. Reference Clocks Symbol Pin Type Name/Description E1XCLK_1 E1XCLK_2 W9 F28 I pd 1 E1 X Clock. This clock signal is used for three purposes as follows: To generate E1 AIS (all 1s). As a reference to the E1 DJA. As a clock source for the E1 test pattern generator and test pattern monitor. This input may be provided by a 2.048 MHz, a 32.768 MHz, or a 65.536 MHz 50 ppm free-running crystal oscillator, or clocking chip. E1XCLK_1 and E1XCLK_2 should be tied together. DS1XCLK_1 DS1XCLK_2 Note: For the E1 DJA, an input of 32.768 MHz or 65.536 MHz must be used. AA11 I pd 1 DS1 X Clock. This clock signal is used for three purposes as follows: E33 To generate DS1 AIS (all 1s). As a reference to the DS1 DJA. As a clock source for the DS1 test pattern generator and test pattern monitor. This input may be provided by a 1.544 MHz, a 24.704 MHz, or a 49.408 MHz 32 ppm free-running crystal oscillator, or clocking chip. DS1XCLK_1 and DS1XCLK_2 should be tied together. DS3XCLK P23 E3XCLK P24 Note: For the DS1 DJA, an input of 24.704 MHz or 49.408 MHz must be used. I pd 2 DS3 X Clock. A 44.736 MHz 20 ppm clock input for DS3 DJA and TPG. This input may be provided by a 44.736 MHz 20 ppm free-running crystal oscillator, or clocking chip. I pd 2 E3 X Clock. A 34.368 MHz 20 ppm clock input for E3 DJA and TPG. This input may be provided by a 34.368 MHz 20 ppm free-running crystal oscillator, or clocking chip. Table 2-18. Low-Order Path Overhead Access, Transmit Direction Symbol Pin Type LOPOHCLKIN_A LOPOHCLKIN_B LOPOHCLKIN_C LOPOHCLKIN_D LOPOHDATAIN_A LOPOHDATAIN_B LOPOHDATAIN_C LOPOHDATAIN_D LOPOHVALIDIN_A LOPOHVALIDIN_B LOPOHVALIDIN_C LOPOHVALIDIN_D T16 T19 W16 AA20 R16 T20 W15 AA21 P16 T21 W14 AB19 I pd Low-Order Path Overhead Clock. 19.44 MHz clock supplied from external circuits that provides the low-order path overhead data. I pd Low-Order Path Overhead Data. The following parts of the low-order (VT) overhead are presented at these pins: communication channel bits (O bits), V5, J2, Z6/N2, Z7, and K4 byte. I pd Low-Order Path Overhead Data Input Valid. This signal is a mask that indicates the location of the overhead bytes in the LOPOHDATAIN. Agere Systems Inc. Name/Description 37 TMXF33625 Hypermapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS0/E0 Hardware Design Guide, Revision 3 September 18, 2003 Table 2-19. Low-Order Path Overhead Access, Receive Direction Symbol Pin Type Name/Description LOPOHCLKOUT_A LOPOHCLKOUT_B LOPOHCLKOUT_C LOPOHCLKOUT_D LOPOHDATAOUT_A LOPOHDATAOUT_B LOPOHDATAOUT_C LOPOHDATAOUT_D LOPOHVALIDOUT_A LOPOHVALIDOUT_B LOPOHVALIDOUT_C LOPOHVALIDOUT_D N16 T22 W13 AC19 M16 T23 W12 AB20 N15 R22 Y13 AB21 O Low-Order Path Overhead Clock. 19.44 MHz clock supplied to external circuits that receive the low-order path overhead data. O Low-Order Path Overhead Data. (Line and path REI and RDI, O bits, V5, J2, Z6/N2, and Z7/K4 byte.) O Low-Order Path Overhead Data Output Valid. This signal is a mask that indicates the location of the overhead bytes in the LOPOHDATAOUT. Table 2-20. Clock Generator Symbol Pin Type Name/Description CLKIN_PLL G16 I pd 2 Transmit Line Clock Generator Reference Input. The clock generator is used to derive the transmit line clocks for DS1/E1 synchronized to CLKIN_PLL. The derived clock is used in the DS1/E1 transmit framer sections. O Framer PLL Test Mode Output. Framer PLL clock (1.544 MHz, 2.048 MHz) selected by device register. CG_PLLCLKOUT_A P9 CG_PLLCLKOUT_B J21 CG_PLLCLKOUT_C AF14 CG_PLLCLKOUT_D AA26 MODE[2:0]_PLL F15, AD13, I pd 2 Framer PLL Input Clock Mode Select Bits. The settings of these mode F14 select pins must correspond to the frequency of CLKIN_PLL as shown below. MODE[2:0]_PLL CLKIN_PLL MODE[2:0]_PLL CLKIN_PLL 000 001 010 011 Reserved 51.840 MHz 26.624 MHz 19.440 MHz 100 101 110 111 16.384 MHz 8.192 MHz 4.096 MHz 2.048 MHz Table 2-21. Microprocessor Interface Symbol Pin Type Name/Description MPCLK AG21 I MPMODE AG20 I Microprocessor Clock. This clock is required to properly sample address, data, and control signals from the microprocessor in both asynchronous and synchronous modes of operation. Microprocessor Mode. If the microprocessor interface is synchronous, MPMODE should be set to 1. If the microprocessor interface is asynchronous, MPMODE should be set to 0. 38 Agere Systems Inc. Hardware Design Guide, Revision 3 September 18, 2003 TMXF33625 Hypermapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS0/E0 Table 2-21. Microprocessor Interface (continued) Symbol Pin CSN_A CSN_B CSN_C CSN_D D15 R31 Y4 AL20 ADSN AE21 RWN AJ20 DSN T28 ADDR[20:0] AB22, N29, N25, N24, AG22, P29, AC22, AJ22, R26, T27, AD22, R28, T26, AE22, AH20, AF21, R27, R29, AH21, AJ21, AH19 DATA[15:0] PAR[1:0] N26, N22, AB9, AB8, P26, P27, AF22, AA7, AB6, M22, AA8, P25, AA6, L22, P28, Y8 N23, AB23 DTN AB24 HP_INTN_1 HP_INTN_2 LP_INTN_1 LP_INTN_2 AB10 M33 F13 AB11 APS_INTN_A APS_INTN_B APS_INTN_C APS_INTN_D G14 J33 AC2 AN26 Agere Systems Inc. Type Name/Description I pu Chip Select. Active-low, high-order address signals. Chip select must be set low at the beginning of any read or write access and returned high at the end of the cycle. There are four chip selects in the Hypermapper to determine which partition is being addressed (A, B, C, or D). Only one of these can be active-low at any time. I Address Strobe. Active-low address strobe that indicates the beginning of a read or write access. It is a one MPCLK cycle-wide pulse for synchronous mode. In asynchronous mode, it is active for the entire read/write cycle. Address bus signals, ADDR[20:0], are available to the Hypermapper when ADSN is low. The address bus should remain valid for the duration of ADSN. I Read/Write. RWN is set high during a read cycle, or set low during a write cycle. I Data Strobe. For a read cycle, the contents of the internal register will be output on DATA [15:0]; and for a write cycle, the DATA [15:0] will be clocked into the internal register. To initiate the start of the read/write operation, DSN must be low during the entire read/write cycle. This signal should only be used for asynchronous mode. I Address [20:0]. ADDR[20] is the most significant bit and ADDR[0] is the least significant bit for addressing all the internal registers during microprocessor access cycles. All addresses are 21-bit word addresses; hence, in a typical application, ADDR[0] of the TMXF33625 device would be connected to address bit 1 of a byte addressable system address bus. Note: The Hypermapper is little endian, i.e., the least significant byte is stored in the lowest address and the most significant byte is stored in the highest address. Care must be exercised when connecting to microprocessors that use big endian byte ordering. I/O Data [15:0]. 16-bit data bus input for write operations and output for read operations. DATA[15] is the MSB, and DATA[0] is the LSB. I/O Data Parity. Byte-wide parity bits for data. PAR[1] is the parity for DATA[15:8], and PAR[0] is the parity for DATA[7:0] O Data Transfer Acknowledge. The delay associated with DTN going low depends on the Hypermapper block being accessed. In asynchronous mode, when ADSN or DSN is deasserted, the deassertion will drive the DTN signal high. When inactive, CSN will drive DTN to be 3-stated. The microprocessor should wait after DTN is deasserted before starting the next operation. O od High-Priority and Low-Priority Interrupts. Active-low. Each of the functional blocks contain their individual low-priority interrupts. High-priority interrupts are generated by TMUX, STS1LT, and E13 blocks. Each interrupt is individually maskable. Requires an external 5 k pull-up resistor. HP_INTN_1 and HP_INTN_2 should be tied together; LP_INTN_1 and LP_INTN_2 should be tied together. O od Automatic Protection Switch Interrupts. Active-low. See the TMUX and STS1LT sections in the Register Description document for specific interrupts. Each interrupt is individually maskable. Requires an external 5 k pull-up resistor. 39 TMXF33625 Hypermapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS0/E0 Hardware Design Guide, Revision 3 September 18, 2003 Table 2-22. Boundary Scan (IEEE 1149.1) Symbol Pin TCK TDI TMS_1 TMS_2 TRST AC21 P15 Y6 AC31 L14 TDO AD21 Type Name/Description I Test Clock. This signal provides timing for boundary-scan test operations. I pu 2 Test Data In. Boundary-scan test data input signal, sampled on the rising edge of TCK. I pu 1 Test Mode Select. Controls boundary-scan test operations. TMS is sampled on the rising edge of TCK. TMS_1 and TMS_2 must be connected to each other. I pu 2 Test Reset (Active-Low). This signal provides an asynchronous reset for the boundaryscan TAP controller. O Test Data Out. Boundary-scan test data output signal is updated on the falling edge of TCK. The TDO output will be high-impedance, except when transmitting test data. Table 2-23. General-Purpose Interface Symbol Pin Type Name/Description RSTN_A RSTN_B RSTN_C RSTN_D PMRST N1 A22 AP13 AB34 N14 I pu Global Hardware Reset. Active-low. Initializes all internal registers to their default state. This is an asynchronous reset, which occurs on the falling edge, but RSTN should be held low for at least 1 s. RSTN should be held low until both power supplies (1.5 V and 3.3 V) are stabilized upon powerup. IC3STATEN M13 SCK1_1 SCK1_2 SCK2_1 SCK2_2 SCAN_EN SCANMODE_1 SCANMODE_2 IDDQ_A IDDQ_B IDDQ_C IDDQ_D W8 AA31 W7 AL26 N13 L13 AK30 N3 C22 AM13 AB32 40 I/O pd Performance Monitor Reset. Resets error counters. When enabled as an input, it is a 1s square wave that forces an update of PM counters upon the rising edge. When the PMRST is generated internally from the MPU clock, this pin is an output. I pu 2 Output Enable. When high, output buffers will operate normally. When low, all outputs will be forced to a high-impedance state. IC3STATEN should be held low until both power supplies (1.5 V and 3.3 V) are stabilized upon powerup. I pd 1 Scan Clock 1. Reserved. Do not connect. I pd 1 Scan Clock 2. Reserved. Do not connect. I pd 2 Scan Enable. Reserved. Do not connect. I pd 1 Serial Scan Input for Testing. Reserved. Do not connect. I IDDQ Input. This pin must be externally pulled down with a 1 k resistor. Agere Systems Inc. Hardware Design Guide, Revision 3 September 18, 2003 TMXF33625 Hypermapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS0/E0 Table 2-24. CDR Interface Symbol Pin BYPASS_1 BYPASS_2 TSTPHASE ECSEL_1 ECSEL_2 ETOGGLE_1 ETOGGLE_2 EXDNUP_1 EXDNUP_2 TSTMODE TSTSFTLD H13 AN23 J13 H15 AH29 J14 AF28 K13 D31 H14 J15 Type Name/Description I pd 1 High-Speed CDR Bypass. Reserved. Do not connect. I pd 2 Test Phase. Reserved. Do not connect. I pd 1 External Clock Select. Reserved. Do not connect. I pd 1 External Toggle. Reserved. Do not connect. I pd 1 External Down Up. Reserved. Do not connect. I pd 2 Test Mode. Reserved. Do not connect. I pd 2 Test Shift Load. Reserved. Do not connect. Table 2-25. Analog Power and Ground Signals Symbol Pin Type VSSA_CDR1_A VSSA_CDR1_B VSSA_CDR1_C VSSA_CDR1_D VSSA_CDR2_A VSSA_CDR2_B VSSA_CDR2_C VSSA_CDR2_D VSSA_X4PLL_A VSSA_X4PLL_B VSSA_X4PLL_C VSSA_X4PLL_D VSSA_SFPLL_A VSSA_SFPLL_B VSSA_SFPLL_C VSSA_SFPLL_D VSSA_DS3PLL_A VSSA_DS3PLL_B VSSA_DS3PLL_C VSSA_DS3PLL_D VSSA_E3PLL_A VSSA_E3PLL_B VSSA_E3PLL_C VSSA_E3PLL_D VDD15A_CDR1_A VDD15A_CDR1_B VDD15A_CDR1_C VDD15A_CDR1_D K3 C25 AM10 AE32 J4 D26 AL9 AF31 K6 F25 AJ10 AE29 U5 E18 AK17 V30 L15 R24 Y11 AD20 K16 T25 W10 AE19 L3 C24 AM11 AD32 -- CDR1 Ground. Isolated ground for the internal CDR1. -- CDR2 Ground. Isolated ground for the internal CDR2. -- X4PLL Ground. Isolated ground for the internal X4PLL. -- SFPLL Ground. Isolated ground for the internal SFPLL. -- DS3PLL Ground. Isolated ground for the internal DS3PLL. -- E3PLL Ground. Isolated ground for the internal E3PLL. -- CDR1 Power. 1.5 V power supply for the internal CDR1, which is used by the high-speed receive CDR, the protection receive CDR and the three CDRs associated with the mate interconnect ports. Good engineering practice needs to be applied; refer to the evaluation board schematic. Agere Systems Inc. Name/Description 41 TMXF33625 Hypermapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS0/E0 Hardware Design Guide, Revision 3 September 18, 2003 Table 2-25. Analog Power and Ground Signals (continued) Symbol Pin Type Name/Description VDD15A_CDR2_A VDD15A_CDR2_B VDD15A_CDR2_C VDD15A_CDR2_D VDD15A_X4PLL_A VDD15A_X4PLL_B VDD15A_X4PLL_C VDD15A_X4PLL_D VDD15A_DS3PLL_A VDD15A_DS3PLL_B VDD15A_DS3PLL_C VDD15A_DS3PLL_D VDD15A_E3PLL_A VDD15A_E3PLL_B VDD15A_E3PLL_C VDD15A_E3PLL_D VDD33A_SFPLL_A VDD33A_SFPLL_B VDD33A_SFPLL_C VDD33A_SFPLL_D H5 E27 AK8 AG30 K7 G25 AH10 AE28 M15 R23 Y12 AC20 K15 R25 Y10 AE20 T7 G19 AH16 W28 -- CDR2 Power. 1.5 V power supply for the internal CDR2, which is used by the high-speed receive CDR, the protection receive CDR and the three CDRs associated with the mate interconnect ports. Good engineering practice needs to be applied; refer to the evaluation board schematic. -- X4PLL Power. 1.5 V power supply for the internal X4PLL, which is used for the transmit protection 1 + 1 port. Good engineering practice needs to be applied; refer to the evaluation board schematic. -- DS3PLL Power. 1.5 V power supply for the internal DS3PLL, which is used by the DS3DJA. Good engineering practice needs to be applied; refer to the evaluation board schematic. -- E3PLL Power. 1.5 V power supply for the internal E3PLL, which is used by the E3DJA. Good engineering practice needs to be applied; refer to the evaluation board schematic. -- SFPLL Power. 3.3 V power supply for the internal SFPLL, which is used by the CG block (framer PLL). Good engineering practice needs to be applied; refer to the evaluation board schematic. Table 2-26. No Connects Symbol Pin No Connect AM19, AN19, AN20, AP19, AP20* Type NC Name/Description No Connects. These pins are not used in the Hypemapper. * These five balls are connected together and are not connected to the chip. Table 2-27. Digital Power and Ground Signals Pin A15, A16, AA9, AA18, AB7, AB12, AB17, AB27, AC7, AC12, AC18, AC26, AD30, AF18, AG4, AG29, AH22, AH23, AJ5, AJ8, AJ19, AJ30, AK2, AK6, AK11, AK16, AK29, AL4, AL14, AN30, B5, B12, B15, B16, C16, D8, D21, E6, E19, E24, E29, F5, F16, F27, F30, G12, G13, G15, H6, H16, H31, J16, J17, L5, M14, M17, M28, N18, N28, P4, P17, R17, R33, R34, T5, T17, T29, T32, T33, T34, U13, U19, U20, U21, U23, U26, V9, V12, V14, V15, V16, V22, W1, W2, W3, W6, W18, W30, Y1, Y2, Y7, Y9, Y18 AA5, AA10, AA12, AB5, AB18, AB31, AC5, AC6, AD17, AD18, AE18, AE26, AF2, AF4, AF10, AF11, AF17, AF26, AG6, AG17, AH18, AH30, AJ23, AJ27, AK5, AK7, AK19, AK22, AK23, AL13, AL19, AL21, AL27, AL31, B9, D4, D9, D14, D16, D22, E5, E12, E13, E16, E28, E30, F8, F12, G5, G17, H18, H29, J18, J25, J26, J31, K9, K14, K17, L9, L17, L18, M29, M30, N4, N17, N30, P31, R18, T30, T31, U8, U9, U11, U15, U17, U18, U22, U24, U25, U28, V7, V10, V11, V13, V17, V18, V20, V24, V26, V27, W4, W5, Y17 42 Symbol Type Name/Description VDD15 -- Common power signals for 1.5 V VDD. VDD33 -- Common power signals for 3.3 V VDD. Agere Systems Inc. Hardware Design Guide, Revision 3 September 18, 2003 TMXF33625 Hypermapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS0/E0 Table 2-27. Digital Power and Ground Signals (continued) Pin A29, A32, AA2, AA3, AA4, AA17, AB2, AB3, AB4, AC3, AC4, AC9, AC10, AC11, AC23, AC24, AC25, AD4, AD9, AD10, AD11, AD12, AD19, AD23, AD24, AD25, AD26, AE9, AE10, AE11, AE12, AE23, AE24, AE25, AF9, AF12, AF16, AF23, AF24, AF25, AG13, AG18, AH9, AJ4, AJ7, AJ33, AJ34, AK20, AK21, AL12, AL22, AL23, AL24, AL29, AM20, AM21, AM22, AM23, AM33, AM34, AN3, AN6, AN21, AN22, AP3, AP6, B13, B14, B29, B32, C12, C13, C14, C15, D1, D2, D6, D11, D12, D13, D23, E14, E15, F1, F2, F31, G6, G26, H17, H22, J7, J9, J10, J11, J12, J19, J23, J24, K10, K11, K12, K23, K24, K25, K26, L10, L11, L12, L16, L23, L24, L25, L26, L31, M4, M9, M10, M11, M12, M23, M24, M25, M26, M31, M32, N8, N27, N31, N32, N33, P18, P30, P32, P33, R30, R32, T9, T18, T24, U14, U16, U27, V8, V19, V21, W11, W17, W26, Y3, Y5 Agere Systems Inc. Symbol Type VSS -- Name/Description Common ground signals. 43 TMXF33625 Hypermapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS0/E0 Hardware Design Guide, Revision 3 September 18, 2003 3 Absolute Maximum Ratings Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of the data sheet. Exposure to absolute maximum ratings for extended periods can adversely affect device reliability. Table 3-1. Absolute Maximum Ratings Parameter Supply Voltage (VDD33) Supply Voltage (VDD15) Input Voltage: LVCMOS LVDS Power Dissipation Storage Temperature Range Min -0.5 -0.3 Max 4.2 2.0 Unit V V -0.3 -0.3 -- -65 5.25 VDD33 + 0.3 -- 125 V V mW C 3.1 Handling Precautions Although electrostatic discharge (ESD) protection circuitry has been designed into this device, proper precautions must be taken to avoid exposure to ESD and electrical overstress (EOS) during all handling, assembly, and test operations. Agere employs both a human-body model (HBM) and a charged-device model (CDM) qualification requirement in order to determine ESD-susceptibility limits and protection design evaluation. ESD voltage thresholds are dependent on the circuit parameters used in each of the models, as defined by JEDEC's JESD22-A114 (HBM) and JESD22-C101 (CDM) standards. Table 3-2. ESD Tolerance Device TMXF33625 44 Minimum Threshold HBM 2000 V CDM 500 V Agere Systems Inc. Hardware Design Guide, Revision 3 September 18, 2003 TMXF33625 Hypermapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS0/E0 4 Electrical Characteristics 4.1 Recommended Operating Voltages The following table lists the voltages, along with the tolerances, required for proper operation of the TMXF33625 device. Table 4-1. Recommended Operating Conditions Parameter 3.3 V Power Supply 1.5 V Power Supply Ground 1.0 V: LVDS Reference* 1.4 V: LVDS Reference* Ambient Temperature Symbol Min Typ Max Unit VDD33 VDD15 VSS REF10 REF14 TA 3.14 1.4 -- -- -- -40 3.3 1.5 0.0 1.0 1.4 -- 3.47 1.6 -- -- -- 85 V V V V V C Internal reference voltage is used if bit LVDS_REF_SEL = 1, or else external voltage is used. 4.2 Recommended Powerup Sequence The Hypermapper device requires dual power supplies, a 3.3 V supply for the I/O, and a 1.5 V supply for the core. During powerup, RSTN should be held low (holding the device in reset) and IC3STATEN should be held low (3-stating all output buffers). After the 3.3 V and 1.5 V supplies are stable, MPCLK (which affects the device reset) should be applied and must be present for at least two clock cycles before RSTN and IC3STATEN are released. It is then recommended that IC3STATEN be released concurrent with, or after, the release of RSTN. There are no constraints as to which supply (3.3 V or 1.5 V) must come up first, nor does it matter how long it takes the second supply to come up after the first supply. 4.3 Power Consumption The thermal resistance (JA) between junction and ambient with zero airflow is 7.8 C/Watt. JA 1 m/s = 5.4 C/Watt; JA 2.5 m/s = 3.9 C/Watt. The thermal resistance (JB) between junction and board is 3.8 C/W. The thermal resistance (JC) between junction and case is 1.0 C/W. The power consumption of the device is application dependent since it is not possible to use all the device features simultaneously. The nominal measured values for power per block are shown in Table 4-3. Table 4-2. Typical Power Consumption by Application Application TBD Agere Systems Inc. Conditions -- Typ Unit -- -- 45 TMXF33625 Hypermapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS0/E0 Hardware Design Guide, Revision 3 September 18, 2003 Typical power by block refers to all instances being used. Table 4-3. Typical Power Consumption Per Block Block Maximum Instance Typical, Per Single Instance Unit 4 4 4 4 24 12 12 12 12 4 12 12 4 4 4 60 12 24 0.120 0.020 0.200 0.050 0.009 0.028 0.015 0.013 0.013 TBD 0.195 0.026 0.050 0.420* 0.150 0.020 0.032 0.050 W W W W W W W W W W W W W W W W W W TMUX STSPP STSXC MRXC SPEMPR STS1LT VTMPR E13 M13 TPG/TPM FRM DS1DJA DS3DJA MPU CDR/PLL LVDS I/O NSMI I/O DS3 I/O * Measured with a 50 MHz MPCLK. With a 25 MHz MPCLK, the typical per single instance value of MPU power is approximately 0.2 W. Testing has shown that, on the average, approximately 0.35 W can be saved by utilizing the divide by 16 MPU clock power down feature. Please refer to MPU register 0x0019 in the Ultramapper Register Description document for further information. Additional MPU clock divisor options are available. Additional power can be saved by powering down unused LVDS buffers. For details, please see MPU register 0x0026 in the Ultramapper Register Description document. 4.4 ac and dc Characteristics 4.4.1 LVCMOS Interface Characteristics The following table applies to pins with the designations I, Ipd, and Ipu. Table 4-4. LVCMOS Inputs Specifications 1 Parameter Input Leakage Current High-input Voltage Low-input Voltage Input Capacitance Symbol Conditions Min Typ Max Unit II VIH VIL CI VSS < VIN < VDD33 -- -- -- -- 2.0 VSS -- -- -- -- -- 1.0* -- 0.8 1.5 A V V pF * Excludes current due to pull-up or pull-down resistors. The following pins have input leakage current of 4 A: ADDR[20:0], DATA[15:0], ADSN, DSN, MPCLK, MPMODE, PAR[1:0], PMRST, RWN, and TCK. Please refer to Table 14-1 for the input capacitances of the following pins: ADDR[20:0], DATA[15:0], ADSN, DSN, MPCLK, MPMODE, PAR[1:0], PMRST, RWN, and TCK. The following table applies to pins with the designations Ipd 1 and Ipu 1. 46 Agere Systems Inc. Hardware Design Guide, Revision 3 September 18, 2003 TMXF33625 Hypermapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS0/E0 Table 4-5. LVCMOS Inputs Specifications 2 Parameter Symbol Conditions Min Typ Max Unit II VIH VIL CI VSS < VIN < VDD33 -- -- -- -- 2.0 VSS -- -- -- -- -- 2.0* -- 0.8 12 A V V pF Input Leakage Current High-input Voltage Low-input Voltage Input Capacitance * Excludes current due to pull-up or pull-down resistors. The following table applies to pins with the designations Ipd 2 and Ipu 2. Table 4-6. LVCMOS Inputs Specifications 3 Parameter Symbol Conditions Min Typ Max Unit II VIH VIL CI VSS < VIN < VDD33 -- -- -- -- 2.0 VSS -- -- -- -- -- 4.0* -- 0.8 16 A V V pF Input Leakage Current High-input Voltage Low-input Voltage Input Capacitance * Excludes current due to pull-up or pull-down resistors. The following pins have different input capacitances: CLKIN_PLL = 20 pF, MODE0_PLL = 23 pF, MODE1_PLL = 19 pF, MODE2_PLL = 21 pF. Table 4-7. LVCMOS Outputs Specifications Parameter Symbol Conditions Min Typ Output Voltage Low VOL Output Voltage High VOH Output Current Low Output Current High Max Unit IOL = max VSS IOL = max VDD - 0.5 -- 0.5 V -- VDD V IOL -- -- -- 6* mA IOH -- -- -- -6* mA Output Capacitance CO -- -- 3 HIZ Output Leakage Current IOZ -- -- -- -- pF 10 A * Output current is 10 mA max for NSMITXCLK[3:1], CHITXDATA[1, 3, 4, 5, 6, 10, and 11]. Output leakage current of 20 A for HP_INTN_1, HP_INTN_2, LP_INTN_1, and LP_INTN_2. Output leakage current of 40 A for DTN. Output capacitance of 6 pF for HP_INTN_1, HP_INTN_2, LP_INTN_1, and LP_INTN_2. Output capacitance of 12 pF for DTN. Table 4-8. LVCMOS Bidirectionals Specifications Parameter Symbol Conditions Min Typ Max Unit IL VSS < VIN < VDD33 -- -- 11 A High-input Voltage VIH -- 2.0 -- VDD33 + 0.3 V Low-input Voltage VIL -- VSS -- 0.8 V 5.0 -- pF Leakage Current Biput Capacitance CIB -- Output Voltage Low VOL IOL = -6 mA -- -- 0.5 V Output Voltage High VOH IOH = 6 mA 2.4 -- -- V Output Current Low IOL -- -- -- 6 mA Output Current High IOH -- -- -- -6* mA -- * Output current is 10 mA max for NSMIRXCLK[3:1]. Output leakage current of 44 A for DATA[15:1], PAR[1:0], and PMRST. Biput capacitance of 20 pF for DATA[15:1], PAR[1:0], and PMRST. Agere Systems Inc. 47 TMXF33625 Hypermapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS0/E0 Hardware Design Guide, Revision 3 September 18, 2003 4.4.2 LVDS Interface Characteristics 3.3 V 5% VDD, -40 C to +125 C junction temperature. . Table 4-9. LVDS Interface dc Characteristics Parameter Symbol Test Conditions Min Typ Max Unit -- 0 -- -- 2.4 -- V V Input Buffer Parameters Input Voltage Range High (VIA or VIB) Low (VIA or VIB) VI VIH VIL |VGPD| < 925 mV, dc--1 MHz Input Differential Threshold VIDTH dc-- 450 MHz -100 -- 100 mV Input Differential Hysteresis VHYST (+VIDTH) - (-VIDTH) -- -- --* mV With build-in termination, center-tapped 80 100 120 Receiver Differential Input Impedance RIN Output Buffer Parameters Output Voltage: High (VOA or VOB) Low (VOA or VOB) VOH VOL RLOAD = 100 1% RLOAD = 100 1% -- 0.925 -- -- 1.475 -- V V Output Differential Voltage |VOD| RLOAD = 100 1% 0.25 -- 0.45 V Output Offset Voltage VOS RLOAD = 100 1% 1.125 -- 1.275 V Output Impedance, Single Ended RO VCM = 1.0 V and 1.4 V 80 100 120 RO RO Mismatch Between A and B VCM = 1.0 V and 1.4 V -- -- 10 % Change in Differential Voltage Between Complementary States |VOD| RLOAD = 100 1% -- -- 25 mV Change in Output Offset Voltage Between Complementary States VOS RLOAD = 100 1% -- -- 25 mV Output Current ISA, ISB Driver shorted to VSS -- -- 24 mA Output Current ISAB Drivers shorted together -- -- 12 mA * The buffer will not produce output transitions when input is open-circuited. When the true and complement inputs are floating, the input buffer will not oscillate. 48 Agere Systems Inc. Hardware Design Guide, Revision 3 September 18, 2003 TMXF33625 Hypermapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS0/E0 5 Timing 5.1 TMUX High-Speed Interface Timing 80% 20% tR tF Figure 5-1. TMUX LVDS Signal Rise/Fall Timing 50% RHSCP/N tSU RHSDP/N tH 50% 50% THSCOP/N tPD THSDP/N 50% Figure 5-2. TMUX LVDS Clock and Data Timing Table 5-1. High-Speed Interface Inputs Specifications Name Reference Edge Rising/Falling Max Rise Time (ns) Max Fall Time (ns) Min Setup (ns) Min Hold (ns) RHSDP/N (622 MHz)* Asynchronous -- 0.5 0.5 -- -- * RHSDP/N (155 MHz) Asynchronous -- 0.5 0.5 -- -- RHSDP/N (155 MHz) RHSCP/N R/F 1.0 1.0 2 0 THSSYNC THSCP/N (155.52 MHz) R 1.0 1.0 2 1.5 THSSYNC THSCP/N (622.08 MHz) R 1.0 1.0 1.7 1.5 * Input serial data stream should have minimum eye opening of 0.4 UIp-p, and no more than 60 consecutive bits that have no transitional edge within one minute. It must meet 100 ps maximum phase variation limit over a 200 ns interval; this translates to a frequency change of 500 ppm. When MPU_MASTER_SLAVE = 0, then refer to Figure 5-4. Table 5-2. Protection Link Inputs Specifications Name Reference Edge Rising/Falling Max Rise Time (ns) Max Fall Time (ns) Min Setup (ns) Min Hold (ns) 0.5 0.5 -- -- RPSDP/N (622 MHz)* Asynchronous -- MHz)* Asynchronous -- 0.5 0.5 -- -- RPSCP/N R 1.0 1.0 2 0 RPSDP/N (155 RPSDP/N (155 MHz) * Input serial data stream should have minimum eye opening of 0.4 UIp-p, and no more than 60 consecutive bits that have no transitional edge within one minute. It must meet 100 ps maximum phase variation limit over a 200 ns interval; this translates to a frequency change of 500 ppm. Agere Systems Inc. 49 TMXF33625 Hypermapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS0/E0 Hardware Design Guide, Revision 3 September 18, 2003 Table 5-3. High-Speed Interface Outputs Specifications Name Edge Rising/Falling Reference THSDP/N (622.08 MHz or 155.52 MHz) THSSYNC (MPU_MASTER_SLAVE = 1) THSCOP/N TLSCLK Propagation Delay Min (ns) Max (ns) 0.3 -0.5 0.8 0.2 R -- Table 5-4. Protection Link Outputs Specifications Name Reference TPSDP/N (622.08 MHz or 155.52 MHz) Edge Rising/Falling TPSCP/N Propagation Delay Min (ns) Max (ns) 0.3 0.8 R 5.2 THSSYNC Characteristics THSSYNC is an 8 kHz composite frame sync pulse for STS-3 or STS-12. THSSYNC contains J0, J1, and V1-1 information as shown in Figure 5-3. The time delay from any rising edge of a J0 (8 kHz) to the rising edge of the next J0 is 125 s. The time delay between any two V1-1 (2 kHz) pulses is 500 s. This is true whether in STS-3 or in STS-12 mode. When MPU_MASTER_SLAVE = 1, then THSSYNC is according to Figure 5-3. J1-1 STS-3 J0 J1-3 J1-2 50 ns J1-1 V1-2 V1-1 V1-3 FIRST FRAME J0 J1-3 J1-1 J0 J1-2 SECOND FRAME J1-3 J1-1 J0 J1-2 THIRD FRAME J1-3 J1-2 FOURTH FRAME 12.5 ns STS-12 J0 SECOND FRAME J0 THIRD FRAME J1-11 J1-9 J1-7 J1-5 J1-3 J1-1 FIRST FRAME J0 J1-11 J1-9 J1-7 J1-5 J1-3 J1-1 V1-3 J1-12 J1-10 J1-8 J1-6 J1-4 J1-2 J1-12 J1-10 J1-8 J1-6 J1-4 J1-2 V1-1 J1-11 J1-9 J1-7 J1-5 J1-3 J1-1 J1-11 J1-9 J1-7 J1-5 J1-3 J1-1 50 ns J1-12 J1-10 J1-8 J1-6 J1-4 J1-2 J1-12 J1-10 J1-8 J1-6 J1-4 J1-2 J0 V1-2 FOURTH FRAME Figure 5-3. THSSYNC Timing Diagram (MPU_MASTER_SLAVE = 1) When MPU_MASTER_SLAVE = 0, then THSSYNC (supplied from an external source) can be according to Figure 5-4. 125 s STS-3 J0 50 ns J0 FIRST FRAME J0 J0 THIRD FRAME SECOND FRAME FOURTH FRAME 50 ns STS-12 J0 J0 J0 125 s FIRST FRAME SECOND FRAME J0 THIRD FRAME FOURTH FRAME Figure 5-4. THSSYNC Timing Diagram (MPU_MASTER_SLAVE = 0) 50 Agere Systems Inc. Hardware Design Guide, Revision 3 September 18, 2003 TMXF33625 Hypermapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS0/E0 When supplied externally, the 8 kHz THSSYNC may have a 50/50 duty cycle since the signal will only be sampled on the rising edge. In this case, THSSYNC should be synchronous to THSC. However, if the system needs to synchronize VTs, generated from different Hypermappers or other external devices, then THSSYNC needs to look like the waveform representation in Figure 5-3, i.e., THSSYNC must be composed of both the 8 kHz and the 2 kHz sync components (J0 + J1-1--J1-12 + V1-1); V1-2 and V1-3 are not needed. 5.3 STS-3/STM-1 Mate Interconnect Timing 80% 20% tR tF Figure 5-5. STS-3/STM-1 Mate Rise/Fall Timing 50% CLOCK tSU TLSDATAP/N tH 50% 50% CLOCK tPD RLSDATAP/N 50% Figure 5-6. STS-3/STM-1 Mate Clock and Data Timing Table 5-5. STS-3/STM-1 Mate Interconnect Inputs Specifications Name TLSDATAP/N[3:1] Reference Asynchronous Max Rise Time (ns) Max Fall Time (ns) Min Setup (ns) Min Hold (ns) -- -- -- -- Table 5-6. STS-3/STM-1 Mate Interconnect Outputs Specifications Name RLSDATAP/N[3:1] Agere Systems Inc. Reference Asynchronous Propagation Delay Min (ns) Max (ns) -- -- 51 TMXF33625 Hypermapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS0/E0 Hardware Design Guide, Revision 3 September 18, 2003 5.4 TOAC, POAC, and LOPOH Timing The relationships between data, clock, and sync signals are specific to the TOAC and POAC operation mode selected. This is explained in detail in the TOAC/POAC chapter of the System Design Guide. TTOACCLK TPOACCLK W68 W+ TTOACDATA TPOACDATA RTOACCLK RPOACCLK tPD RTOACDATA RPOACDATA Note: For information pertaining to the output clock duty cycle (in various TOAC/POAC modes of operation), please refer toTable 6-14 and Table 6-15. Figure 5-7. TOAC, POAC Timing LOPOHCLKIN W68 W+ LOPOHDATAIN LOPOHCLKOUT tPD LOPOHDATAOUT Note: For all modes, SYNC signals are high during the clock period of the first bit of each frame. Figure 5-8. LOPOH Timing Table 5-7. TOAC, POAC, and LOPOH Input Specifications Name Reference Edge Max Rise Max Fall Min Setup Min Hold Rising/Falling Time (ns) Time (ns) (ns) (ns) TTOACDATA TTOACCLK (output) R 10 10 3.5 0 TPOACDATA TPOACCLK (output) R 10 10 3.5 0 F 8 8 5 5 LOPOHDATAIN and LOPOHVALIDIN LOPOHCLKIN * Preliminary estimate, additional simulation underway. Table 5-8. TOAC, POAC, and LOPOH Output Specifications Name RTOACDATA, RTOACSYNC TTOACSYNC RPOACDATA, RPOACSYNC TPOACSYNC LOPOHDATAOUT and LOPOHVALIDOUT 52 Reference RTOACCLK TTOACCLK RPOACCLK TPOACCLK LOPOHCLKOUT Edge Rising/Falling R R R R R Propagation Delay Min (ns) Max (ns) 0 0 0 0 0 3.5 3.5 3.5 3.5 5 Agere Systems Inc. Hardware Design Guide, Revision 3 September 18, 2003 TMXF33625 Hypermapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS0/E0 5.5 DS3/E3/STS-1 Timing Figure 5-9 shows a simplified representation of the DS3/E3/STS-1 I/O. M13/E13 BLOCK DEMUX MUX DS3RXCLKOUT Q CLK CLK D D Q DS3DATAINCLK DS3POSDATAOUT DS3POSDATAIN DS3NEGDATAOUT DS3DATAOUTCLK DS3NEGDATAIN Figure 5-9. DS3/E3 Interface Diagram in M13/E13 Block Table 5-9. DS3/E3 Input Specifications Name DS3POSDATAIN[6:1] DS3NEGDATAIN[6:1] Reference DS3DATAINCLK Edge Rising/Falling R/F Max Rise Time (ns) 5 Max Fall Time (ns) 5 Min Setup (ns) 3 Min Hold (ns) 3 Edge Rising/Falling F Max Rise Time (ns) 5 Max Fall Time (ns) 5 Min Setup (ns) 3 Min Hold (ns) 3 Table 5-10. STS-1 Input Specifications Name DS3POSDATAIN[6:1] DS3NEGDATAIN[6:1] Reference DS3DATAINCLK Table 5-11. DS3/E3/STS-1 Output Specifications Name DS3POSDATAOUT[6:1] DS3NEGDATAOUT[6:1] Agere Systems Inc. Reference DS3RXCLKOUT Edge Rising/Falling R/F Propagation Delay Min (ns) Max (ns) 0 3 53 TMXF33625 Hypermapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS0/E0 Hardware Design Guide, Revision 3 September 18, 2003 5.6 NSMI Timing NSMIRXCLK 160,7;&/. W68 W+ NSMIRXDATA tPD NSMITXDATA Figure 5-10. NSMI Clock and Data Timing for the STS-1 Mode 125 s Separation depends on pointer Z3 SONET Frame (for info only) Z3 TOH TOH Z4 J1 TOH C2 NSMI_TXCLK (51.84 MHz output) NSMI_TXDATAEN (output) 89 Columns NSMI_TXDATA (output) NSMI_TXSYNC (output) Position of above pulse is provisionable 0-89 bytes + 0-7 bits before J1 125 s Z4 SONET Frame (for info only) Z4 TOH J1 TOH C2 TOH G1 NSMI_RXCLK (51.84 MHz output) NSMI_RXDATAEN (output) 89 Columns NSMI_RXDATA (input) NSMI_RXSYNC (Output) Position of above pulse is provisionable 0-89 bytes + 0-7 bits before J1 Note: Tx and Rx J1 are not aligned. Transmit path pointer is fixed at 522. Notes: Clock from SPEMPR is at 51.84 MHz rate and is not gapped. TXDATAEN is provided to mark the POH time of the SPE. J1 can occur anywhere in the frame and its position is optionally marked by TXSYNC, which is provisioned to be N columns (bytes) plus M bits earlier in time than J1. During periods where the POH is present, the TXDATAEN signal goes high. Figure 5-11. NSMI Clock and Data Diagram for SPEMPR NSMI Mode 54 Agere Systems Inc. Hardware Design Guide, Revision 3 September 18, 2003 TMXF33625 Hypermapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS0/E0 4760 bits DS3 frame (for info only) X2 X1 M1 M3 X1 NSMI_TXCLK 44.736 MHz NSMI_TXDATAEN NSMI_TXDATA NSMI_TXSYNC Position of this pulse is provisionable 0-256 bits before M1 4760 bits DS3 Frame X2 X1 M1 M3 X1 NSMI_RXCLK 44.736 MHz Output NSMI_RXDATAEN NSMI_RXDATA NSMI_RXSYNC Position of this pulse is provisionable 0-256 bits before M1 Notes: Clock from M13 is at 44.736 MHz rate and is not gapped. TXDATAEN is provided to mark the DS3 frame overhead times. M1 can occur asynchronously and its position is optionally marked by TXSYNC, which is provisioned to be 0 to 255 bits before the M1 bit. TXDATAEN goes low during DS3 frame overhead bits. Figure 5-12. NSMI Clock and Data Diagram for M13 NSMI Mode (NSMI <---> M13 <---> DS3 External I/O) 1536 bits E3 frame (for info only) C11 = 0 FRAME, RAI, RSVD Cj3 = 0 Stuff = data Frame NSMI_TXCLK (34.368 MHz output) NSMI_TXDATAEN (output) NSMI_TXDATA (output) NSMI_TXSYNC (output) Position of this pulse is provisionable 0-256 bits before C11 1536 bits E3 Frame (For Info only) FRAME, RAI, RSVD C11 = 0 Cj3 = 0 Stuff = data Frame NSMI_RXCLK (34.368 MHz output) NSMI_RXDATAEN (output) NSMI_RXDATA (input) NSMI_RXSYNC (output) Position of this pulse is provisionable 0-256 bits before C11 Notes: Clock from E13 is at 34.368 MHz rate and is not gapped. TXDATAEN is provided to mark the overhead time and control bits time of the E3 frame. C11's (the first C bit of the first tributary) position is optionally marked by TXSYNC, which is provisioned to be 0 to 255 bits before C11 (bit 385 of the E3 frame). During periods where the OH is present, the TXDATAEN signal goes low. All C bits are zero and the stuff bits are used for data. Figure 5-13. NSMI Clock and Data Diagram for E13 NSMI Mode 1 (NSMI <---> E13 <---> E3 External I/O) Agere Systems Inc. 55 TMXF33625 Hypermapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS0/E0 Hardware Design Guide, Revision 3 September 18, 2003 1536 bits E3 frame (for info only) C11 = 0 FRAME, RAI, RSVD Cj3 = 0 Stuff = data Frame NSMI_TXCLK (51.84 MHz output) NSMI_TXDATAEN (output) NSMI_TXDATA (output) NSMI_TXSYNC (output) Position of this pulse is provisionable 0-256 bits before C11 1536 bits E3 frame (For info only) FRAME, RAI, RSVD C11 = 0 Cj3 = 0 Stuff = data Frame NSMI_RXCLK (51.84 MHz output) NSMI_RXDATAEN (output) NSMI_RXDATA (Input) NSMI_RXSYNC (output) Position of this pulse is provisionable 0-256 bits before C11 Notes: Clock from E13 is at 51.84 MHz rate and is not gapped. TXDATAEN is the combination of an internal clock enable and data enable from SPEMPR. TXDATAEN is used to mark the overhead time and control bits time of the E3 frame. Clock enable is used to gap the clock rate to 34.368 MHz. C11's (the first C bit of the first tributary) position is optionally marked by TXSYNC, which is provisioned to be 0 to 255 bits before C11 (bit 385 of the E3 frame). During periods where the OH is present, the TXDATAEN signal goes low. All C bits are zero and the stuff bits are used for data. Figure 5-14. NSMI Clock and Data Diagram for E13 NSMI Mode 2 (NSMI <--> E13 <--> SPEMPR <--> STM-N) 56 Agere Systems Inc. Hardware Design Guide, Revision 3 September 18, 2003 TMXF33625 Hypermapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS0/E0 NSMI_TXCLK Data Byte (Timeslot) for a DS0/E0 Link NSMI_TXDATA MSB NSMI_TXSYNC LSB START FSYNC LSB MSB RSVD Link number[0:4] NSMI_TXCLK 51.84 MHz NSMI_TXDATA DATA Link#, Byte# DATA 1, 1 DATA 2, 1 DATA 2, 2 DATA 5, 1 DATA 5, 2 DATA 5, 3 DATA 1, 2 NSMI_TXSYNC 01100000 01010000 } Binary Value 00010000 00100000 01101000 Link number provisionable 1:28 or 0:27 for DS1 FSYNC high signifies 1st byte of link N Start goes low to signify data, high otherwise Links may appear in any order, bytes per link are sequential Note: The 193rd bit of a DS1 frame is not transmitted on the NSMI but is used to locate the FSYNC position. As a consequence of this, signaling bits are not transported in Hypermapper. Figure 5-15. NSMI Clock and Data Diagram for Framer (FRM) NSMI Mode Table 5-12. NSMI Input Specifications Name NSMIRXDATA[3:1] NSMIRXSYNC[3:1] Reference NSMIRXCLK NSMIRXCLK Edge Rising/Falling R R Max Rise Time (ns) 3.5 3.5 Max Fall Time (ns) 3.5 3.5 Min Setup (ns) 5 5 Min Hold (ns) 0 0 Table 5-13. NSMI Output Specifications Name NSMITXDATA[3:1] NSMITXSYNC[3:1] RXDATAEN[3:1] TXDATAEN[3:1] NSMIRXSYNC[3:1] Agere Systems Inc. Reference NSMITXCLK NSMITXCLK NSMIRXCLK NSMITXCLK NSMIRXCLK Edge Rising/Falling R R R R R Propagation Delay Min (ns) Max (ns) 0.5 0.5 0.5 0.5 0.5 8.75 8.75 8.75 8.75 8.75 57 TMXF33625 Hypermapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS0/E0 Hardware Design Guide, Revision 3 September 18, 2003 5.7 CHI Timing W2 W t3 9,+ 9'' 9,+ 9,/ 50% 9,/ t4 Figure 5-16. CHI Clock Timing Table 5-14. CHIRXGCLK and CHITXGCLK Timing Specifications Parameter Description Min Typ Max Unit -- 2 7 ns t1 Rise Time t2 Width (8.192 MHz)* 48.84 -- 73.24 ns t2 Width (16.384 MHz)* 24.42 -- 36.62 ns t3 Fall Time -- 2 7 ns t4 Period (8.192 MHz) -- 122.07 -- ns t4 Period (16.384 MHz) -- 61.03 -- ns * VIH to VIH or VIL to VIL. CHIRXGFS CHITXGFS W5 W6 W7 W8 &+,RXG&/. &+,TXG&/. CHIRXDATA W9 CHITXDATA Note: This figure assumes TMXF33625 is programmed to sample the frame sync signal on the rising edge of the bit clock. Figure 5-17. CHI Bus Timing Table 5-15. CHI Interface Timing Specifications Parameter 58 Description Min Max Unit 15 -- ns t5 Frame Sync Setup Time to Active CHI Clock Edge t5 Frame Sync Hold Time from Active CHI Clock Edge 4 -- ns t7 CHIRXDATA Setup to Active CHI Clock Edge 15 -- ns t8 CHIRXDATA Hold Time from Active CHI Clock Edge 4 -- ns t9 CHITXDATA Propagation Delay from Active CHI Clock Edge 4 30 ns Agere Systems Inc. Hardware Design Guide, Revision 3 September 18, 2003 TMXF33625 Hypermapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS0/E0 CHIRXGFS CHIRXGCLK w/ 0 offset w/ 1/2 bit offset w/ bit offset = 1 TS0 B0 TS0 B1 data sampled TS0 B2 TS0 B0 TS0 B1 data sampled TS0 B0 data sampled TS0 B3 TS0 B2 TS0 B1 TS0 B4 TS0 B3 TS0 B2 TS0 B5 TS0 B4 TS0 B3 TS0 B5 TS0 B4 TS0 B 0 w/ bit offset = 7 TS0 B1 data sampled w/ TS offset = 1, bit offset = 0 TS0 B0 data sampled Note: For this timing diagram, it is assumed that the frame sync signal has been programmed to be active-high and to be sampled by the rising edge of the bit clock. Figure 5-18. Typical Receive CHI Timing (Non-CMS Mode--FRM_CMS = 0) CHIRXGFS CHIRXGCLK w/ 0 offset TS0 B0 w/ 1/2 bit offset TS0 B0 w/ bit offset = 1 w/ TS offset = 1, bit offset = 0 w/ TS offset = 255, bit offset = 71/2 TS0 B1 TS255 B0 TS0 B0 TS0 B2 TS0 B1 TS0 B3 TS0 B2 TS0 B4 TS0 B3 TS0 B5 TS0 B4 TS0 B0 TS0 B1 TS0 B2 TS0 B3 TS0 B4 TS255 B1 TS255 B2 TS255 B3 TS255 B4 TS255 B5 TS0 B1 TS0 B2 TS0 B3 TS0 B4 TS0 B5 Note: For this timing diagram, it is assumed that the frame sync signal has been programmed to be active-high and to be sampled by the rising edge of the bit clock. Figure 5-19. Transmit CHI Timing (Non-CMS Mode--FRM_CMS = 0) Agere Systems Inc. 59 TMXF33625 Hypermapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS0/E0 Hardware Design Guide, Revision 3 September 18, 2003 CHIRXGFS CHIRXGCLK w/ 0 offset TSn B7 TS0 B0 TS0 B1 TS0 B2 TS0 B3 TS0 B4 data sampled w/ 1/4 bit offset TSn B7 TS0 B0 TS0 B1 TS0 B2 TS0 B3 TS0 B4 data sampled w/ 1/2 bit offset TSn B7 TS0 B0 TS0 B1 TS0 B2 TS0 B3 data sampled w/ 3/4 bit offset TSn B6 TSn B7 TS0 B0 TS0 B1 TS0 B2 TS0 B3 data sampled w/ bit offset = 1 TSn B6 TSn B7 TS0 B0 TS0 B1 TS0 B2 TS0 B3 data sampled w/ 23/4 bit offset TSn B4 TSn B5 TSn B6 TSn B7 TS0 B0 TS0 B1 data sampled w/ bit offset = 7 TSn B0 TSn B1 TSn B2 TSn B3 TSn B4 TSn B5 TSn B1 TSn B2 TSn B3 TSn B4 data sampled w/ TS offset = 1, bit offset = 0 TSn - 1 B7 data sampled w/ TS offset = 13, bit offset = 31/4 w/ TS offset = 127, bit offset = 73/4 TSn B0 TSn - 13 B4 TSn - 13 B5 TSn - 13 B6 TSn - 13 B7 TSn - 12 B0 TSn - 12 B1 data sampled TSn B7 TS0 B0 TS0 B1 TS0 B2 TS0 B3 TS0 B4 data sampled Notes: n = 127 at 16 MHz and n = 63 at 8 MHz. For this timing diagram, it is assumed that the frame sync signal has been programmed to be active-high and to be sampled by the rising edge of the bit clock. CMS mode (FRM_CMS = 1). Figure 5-20. Typical Receive CHI Timing (CMS Mode--FRM_CMS = 1) CHIRXGFS CHIRXGCLK w/ 0 offset TSn B6 w/ 1/4 bit offset TSn B7 TSn B6 w/ 1/2 bit offset TS0 B0 TSn B7 TSn B6 TS0 B1 TS0 B0 TSn B7 TS0 B2 TS0 B1 TS0 B0 TS0 B3 TS0 B3 TS0 B2 TS0 B1 TS0 B2 TS0 B3 w/ bit offset = 1 TSn B5 TSn B6 TSn B7 TS0 B0 TS0 B1 TS0 B2 w/ TS offset = 1, bit offset = 0 TSn - 1 B6 TSn - 1 B7 TSn B0 TSn B1 TSn B2 TSn B3 w/ TS offset = 127, bit offset = 73/4 TSn B7 TS0 B0 TS0 B1 TS0 B2 TS0 B3 Notes: For this timing diagram, it is assumed that the frame sync signal has been programmed to be active-high and to be sampled by the rising edge of the bit clock. CMS mode (FRM_CMS = 1). Figure 5-21. Transmit CHI Timing (CMS Mode--FRM_CMS = 1) 60 Agere Systems Inc. Hardware Design Guide, Revision 3 September 18, 2003 TMXF33625 Hypermapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS0/E0 5.8 Parallel System Bus (PSB) Timing CHIRXGCLK &+,7;*&/. &+,5;*)6 &+,7;*)6 10 ns 0 ns tSU tH CHIRXDATA tPD CHITXDATA Figure 5-22. PSB Clock and Data Timing Table 5-16. PSB Input Specifications Name CHIRXDATA[16:1] (PSB mode) CHIRXGFS (PSB mode) CHITXGFS (PSB mode) Reference CHIRXGCLK Edge Rising/Falling R/F Max Rise Time (ns) 10 Max Fall Time (ns) 10 Min Setup (ns) 10 Min Hold (ns) 0 CHIRXGCLK CHITXGCLK R/F R/F 10 10 10 10 10 10 0 0 Table 5-17. PSB Output Specifications Name CHITXDATA[16:1] (PSB mode) Agere Systems Inc. Reference CHITXGCLK Edge Rising/Falling R/F Propagation Delay Min (ns) Max (ns) 4 22 61 TMXF33625 Hypermapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS0/E0 Hardware Design Guide, Revision 3 September 18, 2003 6 Reference Clocks Table 6-1. High-Speed Interface Input Clocks Specifications Clock Name Period (ns) Frequency Accuracy (ppm) Jitter Rise Fall (ns) (ns) Min/ Max RHSCP/N 6.43 155.52 MHz 20 -- 0.4 0.4 Nominal 50% 5% THSCP/N 6.43 155.52 MHz 20 0.01 UIp-p or 64 psp-p or 0.001 UIrms (12 kHz--5 MHz) 0.4 0.4 Nominal 50% 5% THSCP/N 1.6 622.08 MHz 20 0.04 UIp-p or 64 psp-p (12 kHz--5 MHz) -- -- 50% 5% -- Duty Cycle Table 6-2. Protection Link Input Clock Specifications Clock Name Period (ns) 6.43 RPSCP/N Frequency 155.52 MHz Accuracy (ppm) 20 Jitter -- Rise Fall Min/Max (ns) (ns) 0.4 0.4 Nominal Duty Cycle 50% 5% Table 6-3. DS3/E3/STS-1 Input Clocks Specifications Clock Name DS3DATAOUTCLK[6:1] (DS3) Period Frequency Accuracy (ns) (ppm) 22.353 44.736 MHz 20 DS3DATAINCLK[6:1] (DS3) DS3DATAOUTCLK[6:1] (E3) 22.353 44.736 MHz 29.090 34.368 MHz 20 20 DS3DATAINCLK [6:1] (E3) 29.090 34.368 MHz DS3DATAOUTCLK[6:1] (STS-1) 19.290 51.840 MHz 20 20 DS3DATAINCLK[6:1] (STS-1) 20 19.290 51.840 MHz Jitter Rise Fall Min/ Duty Cycle (ns) (ns) Max 5 5 Max 50% 10% 0.05 UIp-p or 1.12 nsp-p (10 kHz--400 kHz) -- 3.5 0.03 UIp-p or 5 0.87 nsp-p (100 kHz--800 kHz) -- 3.5 5 0.01 UIp-p or 0.19 nsp-p or 0.001 UIrms (12 kHz--400 kHz) -- 3.5 2.5 Max 50% 5% 5 Max 50% 10% 2.5 Max 50% 5% 5 Max 50% 10% 2.5 Max 50% 5% Table 6-4. DS1/E1 DJA Input Clocks Specifications Clock Name Period Frequency Accuracy (ns) (ppm) E1XCLK 15.25 65.536 MHz 50 DS1XCLK 20.20 49.408 MHz 32 E1XCLK 30.52 32.768 MHz 50 DS1XCLK 40.40 24.704 MHz 32 62 Jitter 0.1 UIp-p or 1.5 nsp-p (20 kHz--100 kHz) 0.1 UIp-p or 2.0 nsp-p (10 kHz--40 kHz) 0.1 UIp-p or 3.0 nsp-p (20 kHz--100 kHz) 0.1 UIp-p or 4.0 nsp-p (10 kHz--40 kHz) Rise Fall Min/Max Duty Cycle (ns) (ns) 3.5 3.5 Max 50% 10% 3.5 3.5 Max 50% 10% 3.5 3.5 Max 50% 10% 3.5 3.5 Max 50% 10% Agere Systems Inc. Hardware Design Guide, Revision 3 September 18, 2003 TMXF33625 Hypermapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS0/E0 Table 6-5. DS3/E3 DJA Input Clocks Specifications Clock Name DS3XCLK Period (ns) 22.35 Frequency 44.736 MHz Accuracy (ppm) 20 E3XCLK 29.09 34.368 MHz 20 Jitter 0.01 UIp-p or 0.22 nsp-p (10 kHz--400 kHz) 0.01 UIp-p or 0.29 nsp-p (100 kHz--800 kHz) Rise Fall Min/Max (ns) (ns) 3.5 3.5 Max 3.5 3.5 Max Duty Cycle 50% 5% 50% 5% Table 6-6. LOPOH Input Clock Specifications Clock Name LOPOHCLKIN Period (ns) 51.44 Frequency 19.44 MHz Accuracy (ppm) -- Jitter -- Rise Fall Min/Max (ns) (ns) 8 8 Max Duty Cycle Rise Fall Min/Max (ns) (ns) Duty Cycle 50% 5% Table 6-7. Microprocessor Interface Input Clocks Specifications Clock Name Period (ns) Frequency Accuracy (ppm) Jitter MPCLK (min)* 62.50 16 MHz -- -- 4 4 Min 50% 10% MPCLK (max) 15.15 66 MHz -- -- 4 4 Max 50% 10% * If DTN is used, then the maximum frequency for MPCLK is determined by the processor's setup specification for DTN. MPU maximum bus operating frequency = 1/(MPU DTN setup time + tDTNVPD). For example, an 8 ns setup time would limit MPCLK to 50 MHz for reliable DTN detection. Table 6-8. Framer PLL Input Clocks Specifications Clock Name Period Frequency Accuracy (ns) (ppm) CLKIN_PLL 19.20 51.84 MHz 20 CHIRXGTCLK (DS1 mode) 647.66 1.544 MHz 32 CHIRXGTCLK (E1 mode) 488.28 2.048 MHz 50 Jitter Rise Fall Min/Max Duty Cycle (ns) (ns) GR-499 and G.823 -- -- -- 50% 10% GR-499 10 10 Max 50% 10% G.823 10 10 Max 50% 10% Table 6-9. CHI Input Clocks Specifications Clock Name CHIRXGCLK (CHI mode) CHIRXGCLK (CHI mode) CHITXGCLK (CHI mode) CHITXGCLK (CHI mode) Period (ns) 122.070 61.035 122.070 61.035 Frequency 8.192 MHz 16.384 MHz 8.192 MHz 16.384 MHz Accuracy (ppm) 50 50 50 50 Jitter Accuracy (ppm) 20 20 Jitter -- -- -- -- Rise Fall Min/Max (ns) (ns) 10 10 Max 10 10 Max 10 10 Max 10 10 Max Duty Cycle Rise Fall Min/Max (ns) (ns) 10 10 Max 10 10 Max Duty Cycle Rise Fall Min/Max (ns) (ns) -- -- -- -- -- -- Duty Cycle 50% 10% 50% 10% 50% 10% 50% 10% Table 6-10. PSB Input Clocks Specifications Clock Name CHIRXGCLK (PSB mode) CHITXGCLK (PSB mode) Period (ns) 51.44 51.44 Frequency 19.44 MHz 19.44 MHz -- -- 50% 10% 50% 10% Table 6-11. High-Speed Interface Output Clocks Specifications Clock Name THSCOP/N THSCOP/N Agere Systems Inc. Period (ns) 6.43 1.6 Frequency 155.52 MHz 622 MHz Accuracy (ppm) 20 20 Jitter 0.1 UIp-p 0.1 UIp-p 50% 5% 50% 5% 63 TMXF33625 Hypermapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS0/E0 Hardware Design Guide, Revision 3 September 18, 2003 Table 6-12. Protection Link Output Clocks Specifications Clock Name TPSCP/N TPSCP/N Period (ns) 6.43 1.60 Frequency 155.52 MHz 622.08 MHz Accuracy (ppm) 20 20 Jitter -- -- Rise Fall Min/Max (ns) (ns) -- -- -- -- -- -- Duty Cycle Rise Fall Min/Max (ns) (ns) 1.5 1.5 Nominal 1.5 1.5 Nominal Duty Cycle 50% 5% 50% 5% Table 6-13. Line Timing Interface Output Clocks Specifications Clock Name RLSCLK TLSCLK Period (ns) 51.44 51.44 Frequency 19.44 MHz 19.44 MHz Accuracy (ppm) 20 20 Jitter -- -- 50% 5% 50% 5% Table 6-14. TOAC Output Clocks Specifications Clock Name Frequency Accuracy Jitter Rise Fall Min/Max (ppm) (ns) (ns) Duty Cycle 578 1.728 MHz -- -- 1.5 1.5 Nominal 50% 10% RTOACCLK (TMUX; STS-12 D1-3 mode) 5.2 (s) 192 kHz -- -- 1.5 1.5 Nominal 37% 10%* RTOACCLK (TMUX; STS-12 D4-12 mode) 1.73 (s) 576 kHz -- -- 1.5 1.5 Nominal 53% 10%* RTOACCLK (TMUX; STS-12 full access) 48.22 20.736 MHz -- -- 1.5 1.5 Nominal 33% 10%* RTOACCLK (TMUX; STS-3 D1-3 mode) 5.2 (s) 192 kHz -- -- 1.5 1.5 Nominal 58% 10%* RTOACCLK (TMUX; STS-3 D4-12 mode) 1.73 (s) 576 kHz -- -- 1.5 1.5 Nominal 52% 10%* 192.9 5.184 MHz -- -- 1.5 1.5 Nominal 33% 10%* 578 1.728 MHz -- -- 1.5 1.5 Nominal 50% 10% TTOACCLK (TMUX; STS-12 D1-3 mode) 5.2 (s) 192 kHz -- -- 1.5 1.5 Nominal 37% 10%* TTOACCLK (TMUX; STS-12 D4-12 mode) 1.73 (s) 576 kHz -- -- 1.5 1.5 Nominal 53% 10%* TTOACCLK (TMUX; STS-12 full access) 48.22 20.736 MHz -- -- 1.5 1.5 Nominal 33% 10%* TTOACCLK (TMUX-STS-3 D1-3 mode) 5.2 (s) 192 kHz -- -- 1.5 1.5 Nominal 58% 10%* TTOACCLK (TMUX-STS-3 D4-12 mode) 1.73 (s) 576 kHz -- -- 1.5 1.5 Nominal 52% 10%* 192.9 5.184 MHz -- -- 1.5 1.5 Nominal 33% 10%* RTOACCLK (STS1LT; full access) RTOACCLK (TMUX; STS-3 full access) TTOACCLK (STS1LT; full access) TTOACCLK (TMUX-STS-3 full access) Period (ns) * Positive duty cycle. 64 Agere Systems Inc. Hardware Design Guide, Revision 3 September 18, 2003 TMXF33625 Hypermapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS0/E0 Table 6-15. POAC Output Clocks Specifications Clock Name RPOACCLK (TMUX) RPOACCLK (STS1LT) RPOACCLK (SPEMPR) TPOACCLK (TMUX) TPOACCLK (STS1LT) TPOACCLK (SPEMPR) Period Frequency 1.73 s 1.73 s 1.73 s 1.73 s 1.73 s 1.73 s 576 kHz 576 kHz 576 kHz 576 kHz 576 kHz 576 kHz Accuracy (ppm) -- -- -- -- -- -- Jitter Rise Fall Min/Max (ns) (ns) 1.5 1.5 Nominal 1.5 1.5 Nominal 1.5 1.5 Nominal 1.5 1.5 Nominal 1.5 1.5 Nominal 1.5 1.5 Nominal -- -- -- -- -- -- Duty Cycle 50% 10% 50% 10% 50% 10% 50% 10% 50% 10% 50% 10% Table 6-16. DS3/E3/STS-1 Output Clocks Specifications Clock Name Period (ns) Frequency 22.353 29.090 19.290 44.736 MHz 34.368 MHz 51.840 MHz DS3RXCLKOUT [6:1] (DS3) DS3RXCLKOUT [6:1] (E3) DS3RXCLKOUT [6:1] (STS-1) Accuracy (ppm) 20 20 20 Jitter Rise Fall Min/Max (ns) (ns) GR-253 1.5 1.5 Nominal G.783 1.5 1.5 Nominal GR-253 1.5 1.5 Nominal Duty Cycle 50% 5% 50% 5% 50% 5% Table 6-17. LOPOH Output Clock Specifications Clock Name Period (ns) LOPOHCLKOUT 51.44 Frequency Accuracy (ppm) Jitter Rise (ns) Fall (ns) Min/Max 19.44 MHz 20 -- 1.5 1.5 Nominal Duty Cycle 50% 5% Table 6-18. NSMI Output Clocks Specifications Clock Name Period (ns) Frequency 19.29 19.29 51.84 MHz 51.84 MHz RXDATAEN (FRM-NSMI mode) NSMITXCLK Accuracy (ppm) 20 20 Jitter -- -- Rise (ns) 1.5 1.5 Fall Min/ Duty Cycle (ns) Max 1.5 Nominal 50% 5% 1.5 Nominal 50% 5% Table 6-19. Framer PLL Output Clocks Specifications Clock Name CG_PLLCLKOUT CG_PLLCLKOUT Period (ns) Frequency Accuracy (ppm) Jitter 647.66 488.28 1.544 MHz 2.048 MHz 32 50 GR-499 G.823 Rise Fall Min/Max (ns) (ns) -- -- -- -- -- -- Duty Cycle 50% 5% 50% 5% Table 6-20. NSMI Input/Output Clocks Specifications Clock Name NSMIRXCLK (FRM) NSMIRXCLK (STS1LT) NSMIRXCLK (M13) NSMIRXCLK (E13) NSMIRXCLK (SPEMPR) Agere Systems Inc. Period (ns) Frequency 19.29 19.29 22.35 29.09 19.29 51.840 MHz 51.840 MHz 44.736 MHz 34.368 MHz 51.840 MHz Accuracy (ppm) 20 20 20 20 20 Jitter -- -- -- -- -- Rise Fall Min/Max (ns) (ns) 3.5 3.5 Max 3.5 3.5 Max 1.5 1.5 Nominal 1.5 1.5 Nominal 3.5 3.5 Max Duty Cycle 50% 5% 50% 5% 50% 5% 50% 5% 50% 5% 65 TMXF33625 Hypermapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS0/E0 Hardware Design Guide, Revision 3 September 18, 2003 7 Microprocessor Interface Timing 7.1 Synchronous Write Mode The synchronous microprocessor interface mode is selected when MPMODE = 1. In this mode, MPCLK used for the Hypermapper is the same as the microprocessor clock. Interface timing for the synchronous mode write cycle is given in Figure 7-1 and in Table 7-1, and for the read cycle in Figure 7-2 and in Table 7-2. T0 T1 T2 T3 Tn - 2 Tn - 1 Tn MPCLK tADDRVS tAPD tCSNVS tAPD ADDR[20:0] CSN tWS tAIPD ADSN tAPD tWS RWN tAPD tWS DATA[15:0] (INPUT) tDTNIPD tDTNVPD DTN Notes: MPCLK ADDR [20:0] CSN (Input) ADSN (Input) RWN (Input) DATA[15:0] DTN (Output) HIGH Z tADSNVDTF HIGH Z Input clock to Hypermapper MPU block. The address will be available throughout the entire cycle. Chip select is an active-low signal. Address strobe is active-low. ADSN must be one MPCLK clock period wide. The read (H) write (L) signal is always high except during a write cycle. Data will be available during cycle T1. Data transfer acknowledge is active-low for one clock and then driven high before entering a high-impedance state. (This is done with an I/O pad using the input as feedback to qualify the 3-state term.) DTN will become 3-stated when CSN is high. Typically, DTN is active for four or five MPCLK cycles after ADSN is low. Figure 7-1. Microprocessor Interface Synchronous Write Cycle (MPMODE = 1) Table 7-1. Microprocessor Interface Synchronous Write Cycle Specifications Symbol MPCLK Parameter Setup (Min) Hold (Min) Delay (Min) Delay (Max) -- -- -- -- MPCLK 16 MHz Min--66* MHz Max Frequency ADSN, RWN, DATA (write) Valid to MPCLK 6.7 -- -- -- tWS MPCLK to ADDR, RWN, DATA, CSN (write) Invalid -- 0 -- -- tAPD 6 -- -- -- tCSNVS CSN Valid to MPCLK 3.5 -- -- -- tADDRVS ADDR Valid to MPCLK MPCLK to ADSN Invalid -- 0 -- -- tAIPD -- -- 2.5 12 tDTNVPD MPCLK to DTN Valid -- -- 2.5 12 tDTNIPD MPCLK to DTN Invalid TADSNVDTF ADSN Valid to DTN Falling -- -- -- -- Unit ns ns ns ns ns ns ns ns ns * If DTN is used, then the maximum frequency for MPCLK is determined by the processor's setup specification for DTN. MPU maximum bus operating frequency = 1/(MPU DTN setup time + tDTNVPD). For example, a 8 ns setup time would limit MPCLK to 50 MHz for reliable DTN detection. DTN fall is variable, depending on the block selected for access and in some cases the state of the SONET frame. This interval is typically in the 100 ns to 200 ns range, but can be several hundred ns. In lab measurements, it has never exceeded 1000 ns. 66 Agere Systems Inc. Hardware Design Guide, Revision 3 September 18, 2003 TMXF33625 Hypermapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS0/E0 7.2 Synchronous Read Mode T0 T1 T2 Tn - 4 Tn - 3 Tn - 2 Tn - 1 Tn MPCLK tAPD tAVS ADDR[20:0] tCSNSU CSN tADSNSU ADSN tSNIPD RWN tDNVPD HIGH Z DTN tDNIPD tADSNVDTF HIGH Z tDAIPD DATA[15:0] (OUTPUT) Notes: MPCLK ADDR [20:0] CSN (Input) ADSN (Input) RWN (Input) DTN (Output) DATA [15:0] Input clock to Hypermapper MPU block. The address will be available throughout the entire cycle, and must be stable before ADSN turns high. Chip select is an active-low signal. Address strobe is active-low. ADSN must be one MPCLK clock period wide. The read (H) write (L) signal is always high during the read cycle. Data transfer acknowledge on the host bus interface is initiated on T6. This signal is active for one clock, and then driven high before entering a high-impedance state. (This is done with an I/O pad using the input as feedback to qualify the 3-state term.) DTN will become 3-stated when CSN is high. Typically, DTN is active four or five MPCLK cycles after ADSN is low. Read data is stable in Tn - 1. Figure 7-2. Microprocessor Interface Synchronous Read Cycle (MPMODE = 1) Table 7-2. Microprocessor Interface Synchronous Read Cycle Specifications Symbol Parameter Setup (Min) Hold (Min) Delay (Min) Delay (Max) Unit MPCLK MPCLK 16 MHz Min--66* MHz Max Frequency -- -- -- -- ns tAVS ADDR Valid to MPCLK 3.5 -- -- -- ns tAPD MPCLK to ADDR Invalid -- 0 -- -- ns tCSNSU CSN Active to MPCLK 6 -- -- -- ns tADSNSU ADSN Valid to MPCLK 6 -- -- -- ns tSNIPD MPCLK to ADSN Inactive -- 0 -- -- ns tDNVPD MPCLK to DTN Valid -- -- 2.5 12 ns tDNIPD MPCLK to DTN Invalid -- -- 2.5 12 ns tDAIPD MPCLK to DATA 3-state -- -- 3.5 15 ns -- ns tADSNVDTF ADSN Valid to DTN Falling -- -- -- * If DTN is used, then the maximum frequency for MPCLK is determined by the processor's setup specification for DTN. MPU maximum bus operating frequency = 1/(MPU DTN setup time + tDNVPD). For example, an 8 ns setup time would limit MPCLK to 50 MHz for reliable DTN detection. DTN fall is variable, depending on the block selected for access and in some cases the state of the SONET frame. This interval is typically in the 100 ns to 200 ns range, but can be several hundred ns. In lab measurements, it has never exceeded 1000 ns. Agere Systems Inc. 67 TMXF33625 Hypermapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS0/E0 Hardware Design Guide, Revision 3 September 18, 2003 7.3 Asynchronous Write Mode The asynchronous microprocessor interface mode is selected when MPMODE = 0. Interface timing for the asynchronous mode write cycle is given in Figure 7-3 and in Table 7-3, and for the read cycle in Figure 7-4 and in Table 7-4. Although this is an asynchronous interface, an MPCLK is still required. This clock can be different (asynchronous) from the MPU clock. Internal to the chip, RWN, ADSN, and DSN will be sampled by MPCLK. For the asynchronous microprocessor mode of operation, it is recommended that the MPCLK applied to this device does not exceed 50 MHz when the clock applied to the MPCLK pin is asynchronous to the microprocessor's clock. For the case where the microprocessor's clock and the clock applied to this device's MPCLK pin are synchronous, the maximum MPCLK rate is 66 MHz. ADDR[20:0] tCSFDSF tAICSR CSN tAVADSF tADSRAI ADSN tAVDSF tDSNRAI DSN tRWFDSF tDSRRWR RWN tDSRDI tDVDSF DATA[15:0] (INPUT) tCSFDTR DTN HIGH Z tADSRDTR tCSRDT3 tDSFDTF HIGH Z Notes: ADDR [20:0] Address is asynchronously passed from the host bus to the internal bus. The address will be available throughout the entire cycle. ADDR must be held constant while ADSN and DSN are valid (low). CSN (Input) Chip select is an active-low signal. CSN must be held low (active) until ADSN and DSN are deasserted. ADSN (Input) Address strobe is active-low. ADSN must be stable the entire period. ADSN and CSN may be connected and driven from the same source. DSN (Input) Data strobe is active-low. DATA [15:0] Write data is asynchronously passed from the host bus to the internal bus. Data will be available throughout the entire cycle. DATA must be held constant while DSN is valid (low). RWN (Input) The read/write signal should be high for a read cycle and low for a write cycle. It should always be held high, except during a write cycle. RWN must be held low (write) until DSN is deasserted (high). DTN (Output) Data transfer acknowledge (active-low). DTN is driven out of 3-state to inactive-high on the assertion of CSN. When the internal transaction is complete, DTN goes active-low. DTN is then driven high again when either ADSN or DSN is deasserted. DTN will become 3-stated when CSN is high. DTN fall is variable, depending on the block selected for access and in some cases the state of the SONET frame. This interval is typically in the 100 ns to 200 ns range, but can be several hundred ns. In lab measurements, it has never exceeded 1000 ns. Figure 7-3. Microprocessor Interface Asynchronous Write Cycle (MPMODE = 0) 68 Agere Systems Inc. Hardware Design Guide, Revision 3 September 18, 2003 TMXF33625 Hypermapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS0/E0 Table 7-3. Microprocessor Interface Asynchronous Write Cycle Specifications Symbol Setup (Min) Hold (Min) Delay (Min) Delay (Max) Unit CSN Fall Setup and Hold to DSN Fall 0 -- -- -- ns CSN Rise to ADDR Invalid -- 0 -- -- ns tAVADSF ADDR Valid Setup and Hold to ADSN Fall 1.0 -- -- -- ns tADSRAI ADSN Rise to ADDR Invalid -- 1.42 -- -- ns tAVDSF ADDR Valid Setup and Hold to DSN Fall 0 -- -- -- ns tDSNRAI DSN Rise to ADDR Invalid -- 0 -- -- ns tRWFDSF RWN Fall Setup and Hold to DSN Fall tCSFDSF tAICSR Parameter tDSRRWR DSN Rise to RWN Rise 0 -- -- -- ns -- 0 -- -- ns tDVDSF DATA Valid Setup and Hold to DSN Fall 0 -- -- -- ns tDSRDI DSN Rise to DATA Invalid -- 0 -- -- ns tCSFDTR CSN Fall to DTN Rise -- -- 5.2 16.0 ns tDSFDTF DSN Fall to DTN Fall -- 0 -- -- ns tADSRDTR ADSN or DSN Rise to DTN Rise -- -- 2.9 13.3 ns -- -- 2.9 13 ns tCSRDT3 CSN Rise to DTN 3-State 7.4 Asynchronous Read Mode ADDR[20:0] tAICSR tCSFDSF CSN tADSRAI tAVADSF ADSN tDSNRAI tAVDSF DSN RWN tCSFDTR tADSRDTR tDSFDTF HIGH Z DTN HIGH Z tDTVDV HIGH Z DATA[15:0] Notes: ADDR [20:0] CSN (Input) ADSN (Input) DSN (Input) RWN (Input) DTN (Output) DATA [15:0] tCSRDT3 tADSRD3 HIGH Z Address is asynchronously passed from the host bus to the internal bus. The address will be available throughout the entire cycle. Chip select is an active-low signal. Address strobe is active-low. Data strobe is active-low. The read (H) write (L) signal is always high during a read cycle. Data transfer acknowledge (active-low). DTN is driven out of 3-state to inactive-high on the assertion of CSN. When the internal transaction is complete, DTN goes active-low. DTN is then driven high again when either ADSN or DSN is deasserted. DTN will become 3-stated when CSN is high. 16-bit data bus. Figure 7-4. Microprocessor Interface Asynchronous Read Cycle (MPMODE = 0) Agere Systems Inc. 69 TMXF33625 Hypermapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS0/E0 Hardware Design Guide, Revision 3 September 18, 2003 Table 7-4. Microprocessor Interface Asynchronous Read Cycle Specifications Symbol tCSFDSF tAICSR Parameter Setup (Min) Hold (Min) Delay (Min) Delay (Max) Unit CSN Fall Setup and Hold to DSN Fall 0 --* -- -- ns CSN Rise to ADDR Invalid -- 0 -- -- ns -- -- ns -- -- ns -- -- ns tAVADSF ADDR Valid Setup and Hold to ADSN Fall 1.0 -- tADSRAI ADSN Rise to ADDR Invalid -- 1.42 tAVDSF ADDR Valid Setup and Hold to DSN Fall 0 -- tDSNRAI DSN Rise to ADDR Invalid -- 0 -- -- ns tCSFDTR CSN Fall to DTN Rise -- -- 5.2 16.0 ns tDSFDTF DSN Fall to DTN Fall -- 0 -- -- ns tADSRDTR ADSN or DSN Rise to DTN Rise -- -- 2.9 13.3 ns 2.9 13.0 ns tCSRDT3 CSN Rise to DTN 3-State -- -- tDTVDV DTN Valid to DATA Valid -- -- -- 0 ns tADSRD3 ADSN Rise to DATA 3-State -- -- 2.9 14 + MPCLK ns * CSN must be held low (active) until ADSN and DSN are deasserted. ADDR must be held constant while ADSN and DSN are valid (low). DTN fall is variable, depending on the block selected for access and in some cases, the state of the SONET frame. This interval is typically in the 100 ns to 200 ns range, but can be several hundred ns. In lab measurements, it has never exceeded 1000 ns. DATA[15:0] is enabled by a retimed version of the ADSN. 7.5 Accessing the Same Register Sequentially Across Multiple Partitions Each partition (A, B, C, and D) must be accessed (read or write) independently (treated as individual subsections of the overall device). The address bus may be held stable, but each access (for each partition) must be accompanied by the assertion of both an address strobe and chip select. 70 Agere Systems Inc. Hardware Design Guide, Revision 3 September 18, 2003 TMXF33625 Hypermapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS0/E0 8 Other Timing This interface may be used as either synchronous or asynchronous mode. Table 8-1. General-Purpose Inputs Specifications Name RSTN PMRST TDI and TMS Reference Async Async TCLK Edge Rising/Falling -- -- R Rise Time (ns) -- -- 5 Fall Time (ns) -- -- 5 Setup (ns) -- -- 19.5 Hold (ns) -- -- 6.4 Table 8-2. Miscellaneous Output Specifications Name RHSFSYNCN Reference Asynchronous Edge Rising/Falling -- Propagation Delay Min (ns) Max (ns) -- -- Table 8-3. General-Purpose Output Specifications Name TDO Reference TCLK Edge Rising/Falling F Propagation Delay Min (ns) Max (ns) 12.5 45 9 Hardware Design File References (IBIS, Spice, BSDL, etc.) Available upon request. 10 Ordering Information Table 10-1. Ordering Information Device Package Comcode TMXF336251BL-21 1152-pin PBGA 700054131 Agere Systems Inc. 71 TMXF33625 Hypermapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS0/E0 Hardware Design Guide, Revision 3 September 18, 2003 11 1152-Pin PBGA Diagrams Figure 11-1. 1152-Pin PBGA Physical Dimensions 72 Agere Systems Inc. Hardware Design Guide, Revision 3 September 18, 2003 TMXF33625 Hypermapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS0/E0 12 Change History Changes that were made to this document since the July 23, 2003 issue are listed in the table below. Table 12-1. Document Changes Page page 71 12.1 Navigating Through an Adobe Acrobat Document If the reader displays this document in Adobe Acrobat Reader, clicking on any blue entry in the text will bring the reader to that reference point. Clicking on the back arrow in Acrobat Reader will bring the reader back to the starting point. Agere Systems Inc. 73 TMXF33625 Hypermapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS0/E0 13 Glossary AIS Alarm indication signal AMI Alternate mark inversion APS Automatic protection switch ASM Associated signaling mode BER Bit error rate BOM Bit-oriented message BPV Bipolar violation B8ZS Binary 8 zero code suppression CCI Common channel signaling CDR Clock and data recovery CHI Concentrated highway interface CMI Coded mark inversion CRC Cyclic redundancy check CRV Coding rule violation DACS Digital access cross connects DJA Digital jitter attenuation ESF Extended superframe EXZ Excessive zeros FCS Frame check sequence FDL Facility data link FEAC Far-end alarm and control FEBE Far-end block error HDB3 High-density bipolar of order three 74 Hardware Design Guide, Revision 3 September 18, 2003 HDLC High-level data link control LIU Line interface unit LOC Loss of clock LOF Loss of frame LOS Loss of signal LOPOH Low-order path overhead MCDR Mate clock and data recovery MRXC Multirate cross connect NSMI Network serial multiplexed interface OOF Out of frame PBGA Pin ball grid array POAC Path overhead access channel PRBS Pseudorandom bit sequence PRM Performance report message QRSS Quasirandom signal source RAI Remote alarm indicator RDI Remote defect indication RPOAC Receive path overhead access channel REI Remote error indication SDH Synchronous digital hierarchy SEF Severely errored frame SONET Synchronous optical network TCM Tandem connection monitoring TOAC Transport overhead access channels UPSR Unidirectional path switch ring Agere Systems Inc. Hardware Design Guide, Revision 3 September 18, 2003 TMXF33625 Hypermapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS0/E0 14 Appendix 14.1 Input Capacitances Table 14-1. Input Capacitances for Specific LVCMOS Input Pins Pin Input Capacitance (pF) Pin Input Capacitance (pF) Pin Input Capacitance (pF) Pin Input Capacitance (pF) ADDR[0] 16 ADDR[12] 24 DATA[2] 21 DATA[14] 21 ADDR[1] 22 ADDR[13] 25 DATA[3] 24 DATA[15] 29 ADDR[2] 31 ADDR[14] 26 DATA[4] 22 DSN 21 ADDR[3] 21 ADDR[15] 19 DATA[5] 22 MPCLK 22 ADDR[4] 22 ADDR[16] 21 DATA[6] 19 MPMODE 22 ADDR[5] 23 ADDR[17] 21 DATA[7] 21 PAR[0] 27 ADDR[6] 24 ADDR[18] 21 DATA[8] 25 PAR[1] 21 ADDR[7] 27 ADDR[19] 20 DATA[9] 21 PMRST 21 ADDR[8] 18 ADDR[20] 31 DATA[10] 23 RWN 20 ADDR[9] 24 ADSN 25 DATA[11] 25 TCK 25 ADDR[10] 28 DATA[0] 17 DATA[12] 24 -- -- ADDR[11] 18 DATA[1] 22 DATA[13] 23 -- -- Agere Systems Inc. 75 IEEE is a registered trademark of The Institute of Electrical and Electronics Engineers, Inc. Adobe Acrobat and Acrobat Reader are registered trademarks of Adobe Systems Incorporated. For additional information, contact your Agere Systems Account Manager or the following: INTERNET: http://www.agere.com E-MAIL: docmaster@agere.com N. AMERICA: Agere Systems Inc., Lehigh Valley Central Campus, Room 10A-301C, 1110 American Parkway NE, Allentown, PA 18109-9138 1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106) ASIA: Agere Systems Hong Kong Ltd., Suites 3201 & 3210-12, 32/F, Tower 2, The Gateway, Harbour City, Kowloon Tel. (852) 3129-2000, FAX (852) 3129-2020 CHINA: (86) 21-5047-1212 (Shanghai), (86) 755-25881122 (Shenzhen) JAPAN: (81) 3-5421-1600 (Tokyo), KOREA: (82) 2-767-1850 (Seoul), SINGAPORE: (65) 778-8833, TAIWAN: (886) 2-2725-5858 (Taipei) EUROPE: Tel. (44) 1344 296 400 Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. Agere is a registered trademark of Agere Systems Inc. Agere Systems, Hypermapper, Ultramapper, Supermapper and the Agere logo are trademarks of Agere Systems Inc. Copyright (c) 2003 Agere Systems Inc. All Rights Reserved September 18, 2003 DS03-049MPIC-3 (Replaces DS03-049MPIC-2)