REV. 0
Information furnished by Analog Devices is believed to be accurate and
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use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
a
AD5260/AD5262
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 2002
1-/2-Channel
15 V Digital Potentiometers
FEATURES
256 Positions
AD5260 – 1-Channel
AD5262 – 2-Channel (Independently Programmable)
Potentiometer Replacement
20 k⍀, 50 k⍀, 200 k⍀
Low Temperature Coefficient 35 ppm/ⴗC
4-Wire SPI-Compatible Serial Data Input
5 V to 15 V Single-Supply; ⴞ5.5 V Dual-Supply Operation
Power ON Mid-Scale Preset
APPLICATIONS
Mechanical Potentiometer Replacement
Instrumentation: Gain, Offset Adjustment
Stereo Channel Audio Level Control
Programmable Voltage to Current Conversion
Programmable Filters, Delays, Time Constants
Line Impedance Matching
Low Resolution DAC Replacement
GENERAL DESCRIPTION
The AD5260/AD5262 provide a single- or dual-channel, 256-
position, digitally controlled variable resistor (VR) device.* These
devices perform the same electronic adjustment function as a
potentiometer or variable resistor. Each channel of the AD5260/
AD5262 contains a fixed resistor with a wiper contact that taps the
fixed resistor value at a point determined by a digital code loaded
into the SPI-compatible serial-input register. The resistance between
the wiper and either end point of the fixed resistor varies linearly
with respect to the digital code transferred into the VR latch. The
variable resistor offers a completely programmable value of resistance,
between the A terminal and the wiper or the B terminal and the wiper.
The fixed A to B terminal resistance of 20 kW, 50 kW, or 200 kW has
a nominal temperature coefficient of 35 ppm/∞C. Unlike the majority
of the digital potentiometers in the market, these devices can operate
up to 15 V or ±5 V provided proper supply voltages are furnished.
Each VR has its own VR latch, which holds its programmed resistance
value. These VR latches are updated from an internal serial-to-parallel
shift register, which is loaded from a standard 3-wire serial-input
digital interface. The AD5260 contains an 8-bit serial register
while the AD5262 contains a 9-bit serial register. Each bit is clocked
into the register on the positive edge of the CLK. The AD5262
address bit determines the corresponding VR latch to be loaded
with the last 8 bits of the data word during the positive edging of
CS strobe. A serial data output pin at the opposite end of the serial
register enables simple daisy chaining in multiple VR applications
without additional external decoding logic. An optional reset pin
(PR) forces the wiper to the mid-scale position by loading 80
H
into
the VR latch.
*The terms digital potentiometers, VR, and RDAC are used interchangeably.
FUNCTIONAL BLOCK DIAGRAMS
RDAC
REGISTER
LOGIC
8
POWER-ON
RESET
SERIAL INPUT REGISTER
AD5260
S
HDN
V
DD
CS
CLK
SDI
GND
AWB
SDO
PR
V
SS
V
L
RDAC1 REGISTER
LOGIC
8
AD5262
S
HDN
V
DD
V
SS
CLK
SDI
GND
RDAC2 REGISTER
A1 W1 B1
V
L
CS
SDO
PR
A2 W2 B2
POWER-ON
RESET
SERIAL INPUT REGISTER
R
WB
R
WA
CODE – Decimal
100
064128192 256
PERCENT OF NOMINAL
END-TO-END RESISTANCE – % R
AB
75
50
25
0
Figure 1. R
WA
and R
WB
vs. Code
The AD5260/AD5262 are available in thin surface-mount TSSOP-14
and TSSOP-16 packages. All parts are guaranteed to operate over
the extended industrial temperature range of –40∞C to +85∞C.
REV. 0
–2–
AD5260/AD5262–SPECIFICATIONS
(VDD = +15 V, VSS = 0 V or, VDD = +5 V, VSS = –5 V, VL = +5 V, VA = +5 V,
VB = 0 V, – 40ⴗC < TA < +85ⴗC unless otherwise noted.)
ELECTRICAL CHARACTERISTICS 20 kW, 50 kW, 200 kW VERSIONS
Parameter Symbol Conditions Min Typ
1
Max Unit
DC CHARACTERISTICS RHEOSTAT MODE Specifications apply to all VRs
Resistor Differential NL
2
R-DNL R
WB
, V
A
=NC –1 ±1/4 +1 LSB
Resistor Nonlinearity
2
R-INL R
WB
, V
A
=NC –1 ±1/2 +1 LSB
Nominal Resistor Tolerance
3
R
AB
T
A
= 25∞C–30 30 %
Resistance Temperature Coefficient R
AB
/TWiper = No Connect 35 ppm/∞C
Wiper Resistance R
W
I
W
= 1 V/R
AB
60 150 W
Channel Resistance Matching (AD5262 only) R
WB
/R
WB
Ch 1 and 2 R
WB,
D
X
=
80
H
0.1 %
Resistance Drift R
AB
0.05 %
DC CHARACTERISTICS POTENTIOMETER DIVIDER MODE Specifications apply to all VRs
Resolution N 8 Bits
Differential Nonlinearity
4
DNL –1 ±1/4 +1 LSB
Integral Nonlinearity
4
INL –1 ±1/2 +1 LSB
Voltage Divider Temperature Coefficient DV
W
/DTCode = 80
H
5ppm/∞C
Full-Scale Error V
WFSE
Code = FF
H
–2 –1 +0 LSB
Zero-Scale Error V
WZSE
Code = 00
H
01 2LSB
RESISTOR TERMINALS
Voltage Range
5
V
A, B, W
V
SS
V
DD
V
Capacitance
6
Ax, Bx C
A,B
f = 5 MHz, 25 pF
measured to GND, Code = 80
H
Capacitance
6
Wx C
W
f = 1 MHz, 55 pF
measured to GND, Code = 80
H
Common-Mode Leakage Current I
CM
V
A
=V
B
= V
DD
/2 1 nA
Shut Down Current
7
I
SHDN
5mA
DIGITAL INPUTS and OUTPUTS
Input Logic High V
IH
2.4 V
Input Logic Low V
IL
0.8 V
Input Logic High V
IH
V
L
= 3 V, V
SS
= 0 V 2.1 V
Input Logic Low V
IL
V
L
= 3 V, V
SS
= 0 V 0.6 V
Output Logic High (SDO) V
OH
R
PULL-UP
= 2 kW to 5 V 4.9 V
Output Logic Low (SDO) V
OL
I
OL
= 1.6 mA, V
LOGIC
= 5 V 0.4 V
Input Current
8
I
IL
V
IN
= 0 V or 5 V ±1mA
Input Capacitance
6
C
IL
5pF
POWER SUPPLIES
Logic Supply V
L
2.7 5.5 V
Power Single-Supply Range V
DD RANGE
V
SS
= 0 V 4.5 16.5 V
Power Dual-Supply Range V
DD/SS RANGE
±4.5 ±5.5 V
Logic Supply Current I
L
V
L
=5 V 60 mA
Positive Supply Current I
DD
V
IH
= 5 V or V
IL
= 0 V 1 mA
Negative Supply Current I
SS
V
SS
= –5 V 1 mA
Power Dissipation
9
P
DISS
V
IH
= 5 V or V
IL
= 0 V, 0.3 mW
V
DD
= +5 V, V
SS
= –5 V
Power Supply Sensitivity PSS DV
DD
= +5 V, ±10% 0.003 0.01 %/%
DYNAMIC CHARACTERISTICS
6, 10
Bandwidth –3 dB BW R
AB
= 20 kW/50 kW/200 kW310/130/30 kHz
Total Harmonic Distortion THD
W
V
A
= 1 V
RMS
, V
B
= 0 V, 0.014 %
f=1 kHz, R
AB
= 20 kW
V
W
Settling Time t
S
V
A
= +5 V, V
B
= –5 V, 5 ms
±1 LSB error band, R
AB
= 20 kW
Crosstalk
11
C
T
V
A
= V
DD
, V
B
=0 V,
Measure V
W
with Adjacent
RDAC Making Full-Scale 1 nV–s
Code Change (AD5262 only)
Analog Crosstalk C
TA
V
A1
= V
DD
, V
B1
=0V,
Measure V
W1
with
V
W2
= 5 V p-p @ f = 10 kHz, –64 dB
R
AB
= 20 kW/200 kW (AD5262 only)
Resistor Noise Voltage e
N_WB
R
WB
= 20 kW13 nV/÷Hz
f = 1 kHz
REV. 0 –3–
AD5260/AD5262
Parameter Symbol Conditions Min Typ Max Unit
INTERFACE TIMING CHARACTERISTICS apply to all parts
6, 12
Clock Frequency f
CLK
25 MHz
Input Clock Pulsewidth t
CH
, t
CL
Clock level high or low 20 ns
Data Setup Time t
DS
10 ns
Data Hold Time t
DH
10 ns
CLK to SDO Propagation Delay
13
t
PD
R
L
= 1 kΩ, C
L
< 20pF 1 160 ns
CS Setup Time t
CSS
5ns
CS High Pulsewidth t
CSW
20 ns
Reset Pulsewidth t
RS
50 ns
CLK Fall to CS Rise Hold Time t
CSH
0ns
CS Rise to Clock Rise Setup t
CS1
10 ns
NOTES
The AD5260/AD5262 contains 1,968 transistors. Die Size: 89 mil. × 105 mil. 9,345 sq. mil.
1
Typicals represent average readings at 25°C and V
DD
= +5 V, V
SS
= –5 V.
2
Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions.
R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. I
W
= V
DD
/R for both V
DD
= +5 V, V
SS
=–5V.
3
V
AB
= V
DD
, Wiper (V
W
) = No connect.
4
INL and DNL are measured at V
W
with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = V
DD
and V
B
= 0V. DNL
specification limits of ±1 LSB maximum are Guaranteed Monotonic operating conditions.
5
Resistor terminals A, B, W have no limitations on polarity with respect to each other.
6
Guaranteed by design and not subject to production test.
7
Measured at the Ax terminals. All Ax terminals are open-circuit in shutdown mode.
8
Worst-case supply current consumed when input all logic-input levels set at 2.4 V, standard characteristic of CMOS logic.
9
P
DISS
is calculated from (I
DD
⫻ V
DD
). CMOS logic level inputs result in minimum power dissipation.
10
All dynamic characteristics use V
DD
= +5 V, V
SS
= –5 V, V
L
= +5 V.
11
Measured at a V
W
pin where an adjacent V
W
pin is making a full-scale voltage change.
12
See timing diagram for location of measured values. All input control voltages are specified with t
R
=t
F
= 2ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V.
Switching characteristics are measured using V
L
= 5 V.
13
Propagation delay depends on value of V
DD
, R
L
, and C
L
.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS
1
(T
A
= 25°C, unless otherwise noted.)
V
DD
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +15 V
V
SS
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, –7 V
V
DD
to V
SS
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 V
V
A
, V
B
, V
W
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . V
SS
, V
DD
A
X
– B
X
, A
X
– W
X
, B
X
– W
X
Intermittent
2
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±5 mA
Digital Inputs and Output Voltage to GND . . . . . . . 0 V, 7 V
Operating Temperature Range . . . . . . . . . . . . –40°C to +85°C
Maximum Junction Temperature (T
J MAX
) . . . . . . . . . . . 150°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . 300°C
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
Thermal Resistance
3
θ
JA
TSSOP-14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206°C/W
TSSOP-16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C/W
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause permanent
damage to the device. This is a stress rating only; functional operation of the device
at these or any other conditions above those listed in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
2
Maximum terminal current is bounded by the maximum current handling of the
switches, maximum power dissipation of the package, and maximum applied
voltage across any two of the A, B, and W terminals at a given resistance setting.
3
Package Power Dissipation = (T
J MAX
– T
A
)/ θ
JA
REV. 0
–4–
AD5260/AD5262
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD5260/AD5262 features proprietary ESD protection circuitry, permanent damage may occur
on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions
are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
ORDERING GUIDE
Package Package No. of Parts Branding
Model R
AB
(kW)Temperature Description Option per Container Information
*
AD5260BRU20 20 –40∞C to +85∞CTSSOP-14 RU-14 96 AD5260B20
AD5260BRU20-REEL7 20 –40∞C to +85∞CTSSOP-14 RU-14 1000 AD5260B20
AD5260BRU50 50 –40∞C to +85∞CTSSOP-14 RU-14 96 AD5260B50
AD5260BRU50-REEL7 50 –40∞C to +85∞CTSSOP-14 RU-14 1000 AD5260B50
AD5260BRU200 200 –40∞C to +85∞CTSSOP-14 RU-14 96 AD5260B200
AD5260BRU200-REEL7 200 –40∞C to +85∞CTSSOP-14 RU-14 1000 AD5260B200
AD5262BRU20 20 –40∞C to +85∞CTSSOP-16 RU-16 96 AD5262B20
AD5262BRU20-REEL7 20 –40∞C to +85∞CTSSOP-16 RU-16 1000 AD5262B20
AD5262BRU50 50 –40∞C to +85∞CTSSOP-16 RU-16 96 AD5262B50
AD5262BRU50-REEL7 50 –40∞C to +85∞CTSSOP-16 RU-16 1000 AD5262B50
AD5262BRU200 200 –40∞C to +85∞CTSSOP-16 RU-16 96 AD5262B200
AD5262BRU200-REEL7 200 –40∞C to +85∞CTSSOP-16 RU-16 1000 AD5262B200
*
Line 1 contains part number, line 2 contains differentiating detail by part type and ADI logo symbol, line 3 contains date code YWW.
REV. 0 –5–
AD5260/AD5262
Table I. AD5260 8-Bit Serial-Data Word Format
DATA
B7 B6 B5 B4 B3 B2 B1 B0
D7 D6 D5 D4 D3 D2 D1 D0
MSB LSB
2
7
2
0
CLK 1
0
V
OUT
1
0
RDAC REGISTER LOAD
CS 1
0
D7 D6 D5 D4 D3 D2 D1 D0
SDI 1
0
Figure 2a. AD5260 Timing Diagram
1
0
1
0
RDAC REGISTER LOAD
1
0
D7 D6 D5 D4 D3 D2 D1 D0A0
1
0
CLK
V
OUT
CS
SDI
Figure 2b. AD5262 Timing Diagram
Table II. AD5262 9-Bit Serial-Data Word Format
ADDR DATA
B8 B7 B6 B5 B4 B3 B2 B1 B0
A0 D7 D6 D5 D4 D3 D2 D1 D0
MSB LSB
2
8
2
7
2
0
SDI
(DATA IN)
SDO
(DATA OUT)
1
0
1
0
1
0
1
0
V
DD
0V
CLK
CS
V
OUT
Ax OR Dx Dx
A
ⴕ
x OR D
ⴕ
xD
ⴕ
x
tCSS
tDH
tPD_MAX
ⴞ1 LSB ERROR BAND
ⴞ1 LSB
tCSH
tCH
tCSW
tS
tCL
tDS
tCS1
Figure 2c. Detail Timing Diagram
PR
V
OUT
1
0
V
DD
0V
t
RS
ⴞ1 LSB ERROR BAND ⴞ1 LSB
t
S
Figure 2d. Preset Timing Diagram
REV. 0
–6–
AD5260/AD5262
AD5260 PIN CONFIGURATION
TOP VIEW
(Not to Scale)
1
2
3
4
5
6
7
A
W
B
VDD
SHDN
CLK
SDI
SDO
VL
VSS
AD5260
14
13
12
11
10
9
8
NC
GND
PR
CS
AD5260 PIN FUNCTION DESCRIPTIONS
Pin
Number Mnemonic Description
1A A Terminal
2W Wiper Terminal
3B B Terminal
4V
DD
Positive power supply, specified
for operation at both 5 V or 15 V.
(Sum of |V
DD
| + |V
SS
| £ 15 V)
5SHDN Active low input. Terminal A
open-circuit. Shutdown controls.
Variable Resistors of RDAC.
6CLK Serial Clock Input, positive edge
triggered.
7SDI Serial Data Input
8CS Chip Select Input, Active Low.
When CS returns high, data will
be loaded into the RDAC register.
9PR Active low preset to mid-scale; sets
RDAC registers to 80
H
.
10 GND Ground
11 V
SS
Negative Power Supply, specified
for operation from 0 V to –5 V.
12 V
L
Logic Supply Voltage, needs to be
same voltage as the digital logic
controlling the AD5260.
13 NC No Connect (Users should not
connect anything other than dummy
pad on this pin)
14 SDO Serial Data Output, Open Drain
transistor requires pull-up resistor.
AD5262 PIN CONFIGURATION
TOP VIEW
(Not to Scale)
1
2
3
4
5
6
7
8
A2
A1
W1
VDD
SHDN
CLK
SDI
SDO
VL
VSS
AD5262
16
15
14
13
12
11
10
9
GND
PR
CS
B1
B2
W2
AD5262 PIN FUNCTION DESCRIPTIONS
Pin
Number Mnemonic Description
1SDO Serial Data Output, Open Drain
transistor requires pull-up resistor.
2A1A Terminal RDAC #1
3W1 Wiper RDAC #1, address A0 = 0
2
4B1B Terminal RDAC #1
5V
DD
Positive power supply, specified for
operation at both 5 V or 15 V.
(Sum of |V
DD
|+|V
SS
|£ 15 V)
6SHDN Active low input. Terminal A
open-circuit. Shutdown controls
Variable Resistors #1 through #2.
7CLK Serial Clock Input, positive edge
triggered.
8SDI Serial Data Input.
9CS Chip Select Input, Active Low.
When CS returns high, data in
the serial input register is decoded,
based on the address Bit A
0
, and
loaded into the target RDAC register.
10 PR Active low preset to mid-scale sets
RDAC registers to 80
H
.
11 GND Ground
12 V
SS
Negative Power Supply, specified
for operation at both 0 V or –5 V
(Sum of |V
DD
| + |V
SS
| <15 V).
13 V
L
Logic Supply Voltage, needs to be
same voltage as the digital logic
controlling the AD5262.
14 B2 B Terminal RDAC #2
15 W2 Wiper RDAC #2, address A0 = 1
2
16 A2 A Terminal RDAC #2
REV. 0 –7–
AD5260/AD5262
THEORY OF OPERATION
The AD5260/AD5262 provide a single- or dual-channel, 256-position
digitally controlled variable resistor (VR) device and operate up to
15 V maximum voltage. Changing the programmed VR settings
is accomplished by clocking an 8-/9-bit serial data word into the
SDI (Serial Data Input) pin. For the AD5262, the format of this
data word is one address bit. A0 represents the first bit B8, then
followed by eight data bits B7–B0 with MSB first. Tables I and II
provide the serial register data word format. See Table III for the
AD5262 address assignment to decode the location of the VR latch
receiving the serial register data in bits B7 through B0. VR outputs
can be changed one at a time in random sequence. The AD5260/
AD5262 presets to a mid-scale, simplifying fault condition recov-
ery at power-up. Mid-scale can also be achieved at any time by
asserting the PR pin. Both parts have an internal power ON preset
that places the wiper in a mid-scale preset condition at power ON.
Operation of the power ON preset function depends only on the
state of the V
L
pin.
The AD5260/AD5262 contains a power shutdown SHDN pin,
which places the RDAC in an almost zero power consumption
state where terminals Ax are open circuited, and the wiper W is con-
nected to B, resulting in only leakage currents being consumed in
the VR structure. In the shutdown mode, the VR latch settings are
maintained so that, returning to operational mode from power
shutdown, the VR settings return to their previous resistance values.
Table III. AD5262 Address Decode Table
A0 Latch Loaded
0RDAC#1
1RDAC#2
DIGITAL INTERFACING
The AD5260/AD5262 contains a 4-wire SPI-compatible
digital interface (SDI, SDO, CS, and CLK). For the AD5260,
the 8-bit serial word must be loaded with MSB first, and the
format of the word is shown in Table I. For the AD5262, the
9-bit serial word must be loaded with address bit A0 first, then
MSB of the data. The format of the word is shown in Table II.
A0
SER
REG
D7
D6
D5
D4
D3
D2
D1
D0
A1
W1
B1
VDD
CS
CLK
SDO
A2
W2
B2
GND
RDAC
LATCH
#1
RDAC
LATCH
#2
PR
VSS
PR
SDI
VL
SHDN
POWER-
ON
PRESET
EN
ADDR
DEC
PR
Figure 3. AD5262 Block Diagram
The positive-edge sensitive CLK input requires clean transitions
to avoid clocking incorrect data into the serial input register.
Standard logic families work well. If mechanical switches are used
for product evaluation, they should be debounced by a flip-flop or
other suitable means. Figure 3 shows more detail of the internal
digital circuitry. When CS is low, the clock loads data into the
serial register on each positive clock edge (see Table IV).
Table IV. Truth Table
CLK CS PR SHDN Register Activity
LLHH No SR effect, enables SDO pin
≠*LHHShift one bit in from the SDI pin.
The eighth previously entered bit is
shifted out of the SDO pin.
X≠HH Load SR data into RDAC latch
XHHH No Operation
XXLH Sets all RDAC latches to Mid-Scale,
wiper centered, and SDO latch
cleared.
XH≠HLatches all RDAC latches to 80
H
.
XHHL Open circuits all resistor A–terminals,
connects W to B, turns off SDO
output transistor.
*≠ = positive edge, X = don’t care, SR = shift register
The data setup and data hold times in the specification table
determine the data valid time requirements. The AD5260 uses
an 8-bit serial input data register word that is transferred to the
internal RDAC register when the CS line returns to logic high.
For the AD5262 the last 9 bits of the data word entered into the
serial register are held when CS returns high. Any extra bits are
ignored. At the same time CS goes high, it gates the address
decoder enabling AD5262 one of two positive edge-triggered
AD5262 RDAC latches (see Figure 4).
RDAC 1
RDAC 2
AD5260/AD5262
SDI
CLK
CS
ADDR
DECODE
SERIAL
REGISTER
Figure 4. Equivalent Input Control Logic
The target RDAC latch is loaded with the last 8 bits of the serial data
word completing one RDAC update. For the AD5262, two separate
9-bit data words must be clocked in to change both VR settings.
During shutdown (SHDN) the SDO output pin is forced to the
off (logic high state) to disable power dissipation in the pull-up
resistor. See Figure 5 for equivalent SDO output circuit schematic.
SDI
CLK
CS
SHDN
PR
SERIAL
REGISTER
DQ
CK RS
SDO
Figure 5. Detail SDO Output Schematic of the AD5260
REV. 0
AD5260/AD5262
–8–
All digital inputs are protected with a series input resistor and
parallel Zener ESD structure as shown in Figure 6. This applies
to digital input pins CS, SDI, SDO, PR, SHDN, and CLK.
340⍀
LOGIC
Figure 6. ESD Protection of Digital Pins
A, B, W
V
SS
Figure 7. ESD Protection of Resistor Terminals
LAYOUT AND POWER SUPPLY BYPASSING
It is a good practice to employ compact, minimum-lead length
layout design. The leads to the input should be as direct as pos-
sible
with a minimum conductor length. Ground paths should
have low resistance and low inductance.
Similarly, it is also a good practice to bypass the power supplies
with quality capacitors for optimum stability. Supply leads to the
device should be bypassed with 0.01 mF–0.1 mF disc or chip ceram-
ics
capacitors. Low-ESR 1 mF to 10 mF tantalum or electrolytic
capaci
tors should also be applied at the supplies to minimize any
transient
disturbance (see Figure 8). Notice the digital ground
should also be joined remotely to the analog ground to minimize
the ground bounce.
VSS
C3
C4
C1
C2
10␮F
VSS
VDD
0.1␮F
GND
VDD
0.1␮F
10␮F
ⴙ
ⴙ
Figure 8. Power Supply Bypassing
TERMINAL VOLTAGE OPERATING RANGE
The AD5260/AD5262 positive V
DD
and negative V
SS
power
supply defines the boundary conditions for proper 3-terminal
digital potentiometer operation. Supply signals present on termi-
nals A, B, and W that exceed V
DD
or V
SS
will be clamped by the
internal forward biased diodes (see Figure 9).
V
DD
A
W
B
V
SS
Figure 9. Maximum Terminal Voltages Set by V
DD
and V
SS
The ground pin of the AD5260/AD5262 device is primarily used
as a digital ground reference, which needs to be tied to the PCB’s
common ground. The digital input control signals to the AD5260/
AD5262 must be referenced to the device ground pin (GND),
and must satisfy the logic level defined in the specification table
of this data sheet. An internal level shift circuit ensures that the
common-mode voltage range of the three terminals extends
from V
SS
to V
DD
regardless of the digital input level.
POWER-UP SEQUENCE
Since there are diodes to limit the voltage compliance at termi-
nals A, B, and W (see Figure 9), it is important to power V
DD
/V
SS
first before applying any voltage to terminals A, B, and W. Other-
wise, the diode will be forward biased such that V
DD
/V
SS
will be
powered unintentionally and may affect the rest of the user’s circuit.
The ideal power-up sequence is in the following order: GND,
V
DD
, V
SS
, V
L
,
Digital Inputs, and V
A/B/W
. The order of powering
V
A
, V
B
, V
W
, and Digital Inputs is not important as long as they
are powered after V
DD
/V
SS
.
Daisy-Chain Operation
The serial-data output (SDO) pin contains an open drain
n-channel FET. This output requires a pull-up resistor to trans-
fer data to the next package’s SDI pin. This allows for daisy
chaining several RDACs from a single processor serial data line.
The pull-up resistor termination voltage can be larger than the V
DD
supply voltage. It is recommended to increase the Clock period
when using a pull-up resistor to the SDI pin of the following device
in series because capacitive loading at the daisy-chain node
SDO-SDI between devices may induce time delay to subsequent
devices. Users should be aware of this potential problem to achieve
data transfer successfully (see Figure 10). If two AD5260s are daisy-
chained, this requires a total of 16 bits of data. The first 8 bits,
complying with the format shown in Table I, go to U2, and the
second 8 bits with the same format go to U1. The CS should be
kept low until all 16 bits are clocked into their respective serial
registers, and the CS is then pulled high to complete the operation.
CS CLK
SDOSDI
V
DD
CS CLK
SDOSDIMOSI␮C
SCLK SS
R
P
2.2k⍀
AD5260 AD5260
U1 U2
Figure 10. Daisy-Chain Configuration
RDAC STRUCTURE
The RDAC contains a string of equal resistor segments, with an
array of analog switches, that act as the wiper connection. The
number of positions is the resolution of the device. The AD5260/
AD5262 have 256 connection points allowing it to provide better
than 0.4% set-ability resolution. Figure 11 shows an equivalent
structure of the connections between the three terminals that
make up one channel of the RDAC. The SW
A
and SW
B
will
always be ON, while one of the switches SW(0) to SW(2
N
– 1)
will be ON one at a time depending on the resistance position
decoded from the data bits. Since the switch is not ideal, there is
a 60 W wiper resistance, R
W
. Wiper resistance is a function of
supply voltage and temperature. The lower the supply voltage, the
higher the wiper resistance. Similarly, the higher the temperature,
the higher the wiper resistance. Users should be aware of the
contribution of the wiper resistance when accurate prediction of
the output resistance is needed.
REV. 0 –9–
AD5260/AD5262
D7
D6
D5
D4
D3
D2
D1
D0
RDAC
LATCH
AND
DECODE
Ax
Wx
Bx
R
S
= R
AB
/2
N
R
S
R
S
R
S
R
S
S
HDN
DIGITAL CIRCUITRY
OMITTED FOR CLARITY
Figure 11. Simplified RDAC Architecture
PROGRAMMING THE VARIABLE RESISTOR
Rheostat Operation
The nominal resistances of the RDAC between terminals A and B
are available with values of 20 kW, 50 kW, and 200 kW. The final
three digits of the part number determine the nominal resistance
value, e.g., 20 kW = 20; 50 kW = 50; 200 kW = 200. The nominal
resistance (R
AB
) of the VR has 256 contact points accessed by the
wiper terminal, plus the B terminal contact. The 8-bit data in the
RDAC latch is decoded to select one of the 256 possible settings.
Assuming a 20 kW part is used, the wiper’s first connection starts
at the B terminal for data 00
H
. Since there is a 60 W wiper contact
resistance, such connection yields a minimum of 60 W resistance
between terminals W and B. The second connection is the first tap
point corresponds to 138 W (R
WB
= R
AB
/256 R
W
= 78 W 60 W)
for data 01
H
. The third connection is the next tap point represent-
ing 216 W (78 2 60) for data 02
H
and so on. Each LSB data
value increase moves the wiper up the resistor ladder until the last
tap point is reached at 19982 W [R
AB
1 LSB R
W
]. The wiper
does not directly connect to the B terminal. See Figure 11 for a
simplified diagram of the equivalent RDAC circuit.
The general equation determining the digitally programmed
output resistance between W and B is:
RD DRR
WB AB W
()
=¥+
256
(1)
where D is the decimal equivalent of the binary code which is
loaded in the 8-bit RDAC register, and R
AB
is the nominal end-
to-end resistance.
For example, R
AB
= 20 kW, when V
B
= 0 V and A–terminal is
open circuit, the following output resistance values R
WB
will be
set for the following RDAC latch codes. The result will be the
same if terminal A is tied to W:
DR
WB
(DEC) (W)Output State
256 19982 Full-Scale (R
AB
– 1 LSB + R
W
)
128 10060 Mid-Scale
1138 1 LSB
060Zero-Scale (wiper contact resistance)
Note that in the zero-scale condition a finite wiper resistance of
60 W is present. Care should be taken to limit the current flow
between W and B in this state to no more than 20 mA to avoid
degradation or possible destruction of the internal switches.
Like the mechanical potentiometer the RDAC replaces, the
AD5260/AD5262 parts are totally symmetrical. The resistance
between the wiper W and terminal A also produces a digitally
controlled complementary resistance R
WA
. Figure 12 shows the
symmetrical programmability of the various terminal connections.
When R
WA
is used, the B–terminal can be let floating or tied to the
wiper. Setting the resistance value for R
WA
starts at a maximum
value of resistance and decreases as the data loaded in the latch
is increased in value. The general equation for this operation is:
RD DRR
WA AB W
()
=-¥+
256
256
(2)
For example, R
AB
= 20 kW, when V
A
= 0 V and B–terminal is open,
the following output resistance R
WA
will be set for the following
RDAC latch codes. The result will be the same if terminal B is
tied to W:
DR
WA
(DEC) (W)Output State
256 60 Full-Scale
128 10060 Mid-Scale
119982 1 LSB
020060 Zero-Scale
R
WB
R
WA
R
AB
= 20K⍀
D – CODE in decimal
20
064128192 256
R
WA
(D), R
WB
(D) ⴚ k⍀
16
12
8
4
0
Figure 12. AD5260/AD5262 Equivalent RDAC Circuit
The typical distribution of the nominal resistance R
AB
from
channel to channel matches within ±1%. Device-to-device match-
ing is process lot dependent with the worst case of ±30% variation.
On the other hand, since the resistance element is processed in
thin film technology, the change in R
AB
with temperature has a
low 35 ppm/∞C temperature coefficient.
REV. 0
AD5260/AD5262
–10–
CODE – Decimal
RHEOSTAT MODE INL – LSB
0256
–0.2 32 64 96 128 160 192 224
–0.1
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0
ⴙ5V
ⴙ12V
ⴞ5V
ⴙ15V
TPC 1. R-INL vs. Code vs.
Supply Voltages
CODE – Decimal
POTENTIOMETER MODE DNL – LSB
0256
–0.5 32 64 96 128 160 192 224
–0.4
–0.2
–0.1
0.1
0.3
0.5
–0.3
0
0.2
0.4
TA = ⴙ125ⴗC
TA = ⴙ85ⴗC
TA = ⴙ25ⴗC
TA = ⴚ40ⴗC
TPC 4. DNL vs. Code,
V
DD
/V
SS
=
±
5 V
VDD – VSS – V
POTENTIOMETER MODE INL – LSB
020
–1.0 51015
1.0
–0.5
0
0.5
AVG +3␴
AVG
AVG –3␴
TPC 7. INL vs. Supply Voltages
CODE – Decimal
RHEOSTAT MODE DNL – LSB
0256
–0.25 32 64 96 128 160 192 224
–0.20
–0.10
–0.05
0
0.05
0.10
–0.15
ⴙ5V
ⴙ12V ⴞ5V ⴙ15V
TPC 2. R-DNL vs. Code vs.
Supply Voltages
CODE – Decimal
POTENTIOMETER MODE INL – LSB
025632 64 96 128 160 192 224
–0.4
–0.2
–0.1
0.1
0.2
–0.3
0
ⴞ5V
0.3
ⴙ15V
ⴙ5V
TPC 5. INL vs. Code vs.
Supply Voltages
VDD – VSS – V
RHEOSTAT MODE INL – LSB
020
–2.0 51015
2.0
–1.0
0
1.0
AVG +3␴
AVG
1.5
–1.5
–0.5
0.5
AVG –3␴
TPC 8. R-INL vs. Supply Voltages
CODE – Decimal
POTENTIOMETER MODE INL – LSB
0256
–1.0 32 64 96 128 160 192 224
–0.8
–0.4
–0.2
0.2
0.6
1.0
–0.6
0
0.4
0.8
VDD = ⴙ5V
VSS = ⴚ5V
RAB = 20k⍀
TA = ⴙ25ⴗC
TA = ⴚ40ⴗC
TA = ⴙ125ⴗC
TA = ⴙ85ⴗC
TPC 3. INL vs. Code, V
DD
/V
SS
=
±
5 V
CODE – Decimal
POTENTIOMETER MODE DNL – LSB
025632 64 96 128 160 192 224
–0.5
–0.3
–0.2
0.1
0.3
–0.4
–0.1
ⴞ5V
0.5
ⴙ15V
ⴙ5V
0.2
0.4
0
TPC 6. DNL vs. Code vs.
Supply Voltages
VDD – V
WIPER RESISTANCE – ⍀
ⴚ515
4ⴚ13 11
124
44
84
24
64
104
RON @ VDD/VSS = ⴙ5V/0V
7
RON @ VDD/VSS = ⴙ15V/0V
RON @ V DD/VSS = ⴙ5V/ⴚ5V
TPC 9. Wiper ON Resistance vs.
Bias Voltage
—Typical Performance Characteristics
REV. 0 –11–
AD5260/AD5262
TEMPERATURE – ⴗC
FSE – LSB
–40 100
–2.5
–20 20 80
0
–2.0
–1.0
–1.5
–0.5
40
V
DD
/V
SS
= +15V/0V
060
V
DD
/V
SS
= +5V/0V
V
DD
/V
SS
= ⴞ5V
TPC 10. Full-Scale Error
TEMPERATURE – ⴗC
I
LOGIC
– ␮A
–40 125
24.5
–7 26 92
28.0
25.5
26.5
59
V
DD
/V
SS
= +15V/0V
25.0
26.0
27.5
V
DD
/V
SS
= ⴞ5V
27.0
TPC 13. I
LOGIC
vs. Temperature
TEMPERATURE – ⴗC
ZSE – LSB
–40 100
0
–20 20 80
2.5
0.5
1.5
1.0
2.0
40
060
V
DD
/V
SS
= +5V/0V
V
DD
/V
SS
= ⴞ5V
V
DD
/V
SS
= +15V/0V
TPC 11. Zero-Scale Error
V
IH
– V
I
LOGIC
– ␮A
0 5
10
1k
100
V
DD
/V
SS
= 5V/0V V
LOGIC
= 5V
V
DD
/V
SS
= 5V/0V V
LOGIC
= 3V
1234
TPC 14. I
LOGIC
vs. Digital Input
Voltage
TEMPERATURE – ⴗC
I
DD
/I
SS
SUPPLY CURRENT – ␮A
–40 125
0.001
–7 26 92
1
0.01
0.1
59
V
DD
/V
SS
= ⴙ15V/0V
V
DD
/V
SS
= ⴞ5V
V
LOGIC
= ⴙ5V
V
IH
= ⴙ5V
V
IL
= 0V
TPC 12. Supply Current vs.
Temperature
CODE – Decimal
RHEOSTAT MODE TEMPCO – ppm/ⴗC
0256
–20
80
20k⍀
64 96 160 224
–10
19212832
0
10
20
30
40
50
60
70
50k⍀
200k⍀
TPC 15. Rheostat Mode Tempco
D
R
WB
/
D
T vs. Code
CODE – Decimal
POTENTIOMETER MODE TEMPCO – ppm/ⴗC
0256
–60
120
20k⍀
64 96 160 224
–40
19212832
–20
0
20
40
60
80
100
50k⍀
200k⍀
TPC 16. Potentiometer Mode
D
V
WB
/
D
T vs. Code
FREQUENCY – Hz
GAIN – dB
1k 1M
–54
6
–48
–42
–36
–30
–24
–18
–12
–6
0
10k 100k
CODE = FFH
01H
02H
04H
08H
10H
20H
40H
80H
TA = 25ⴗC
TPC 17. Gain vs. Frequency vs.
Code, R
AB
= 20 k
W
REV. 0
AD5260/AD5262
–12–
FREQUENCY – Hz
GAIN – dB
1k 1M
–54
6
–48
–42
–36
–30
–24
–18
–12
–6
0
10k 100k
CODE = FF
H
01
H
02
H
04
H
08
H
10
H
20
H
40
H
80
H
T
A
= 25ⴗC
TPC 18. Gain vs. Frequency vs. Code
R
AB
= 50 k
W
FREQUENCY – Hz
NORMALIZED GAIN FLATNESS – 0.1dB/DIV
0dB
100 100k1k 10k
CODE = 80
H
V
DD
/V
SS
= ⴞ5V
T
A
= 25ⴗC
R = 20k⍀
R = 200k⍀
R = 50k⍀
TPC 21. Normalized Gain
Flatness vs. Frequency
20mV/DIV
1␮s/DIV
5V/DIV
TPC 24. Mid-Scale Glitch
Energy, Code 80
H
to 7F
H
FREQUENCY – Hz
GAIN – dB
1k 100k
–54
6
–48
–42
–36
–30
–24
–18
–12
–6
0
10k
CODE = FF
H
01
H
02
H
04
H
08
H
10
H
20
H
40
H
80
H
T
A
= 25ⴗC
TPC 19. Gain vs. Frequency vs.
Code R
AB
= 200 k
W
FREQUENCY – Hz
ILOGIC – ␮A
10k 10M
0
600
1M
100
100k
200
300
400
500
CODE FFH
VDD/VSS = +5V/0V
VDD/VSS = ⴞ5V
CODE 55H
TPC 22. I
LOGIC
vs. Frequency
5V/DIV
20␮s/DIV
5V/DIV
TPC 25. Large Signal Settling Time
FREQUENCY – Hz
GAIN – dB
1k 1M
–54
6
–48
–42
–36
–30
–24
–18
–12
–6
0
10k 100k
–3dB
BANDWIDTHS
V
IN
= 50mV rms
V
DD
/V
SS
= ⴞ5V
f
–3dB
= 310kHz, R = 20k⍀
f
–3dB
= 131kHz, R = 50k⍀
f
–3dB
= 30kHz, R = 200k⍀
TPC 20. –3 dB Bandwidth
FREQUENCY – Hz
PSRR – dB
100 1M
0
600
10k
100
1k
200
300
400
500
100k
–PSRR @ V
DD
= ⴞ5V DC ⴞ 10% p-p AC
+PSRR @ V
DD
= ⴞ5V DC ⴞ 10% p-p AC
CODE = 80
H
, V
A
= V
DD
, V
B
= 0V
TPC 23. PSRR vs. Frequency
10mV/DIV
40ns/DIV
TPC 26. Digital Feedthrough vs. Time
REV. 0 –13–
AD5260/AD5262
CODE – Decimal
THEORETICAL IWB_MAX – mA
0256
0.01
100
0.1
1
10
32 64 96 128 160 192 224
RAB = 200k⍀
VA = VB = OPEN
TA = 25ⴗC
RAB = 50k⍀
RAB = 20k⍀
TPC 27. I
MAX
vs. Code
HOURS OF OPERATION AT 150ⴗC
CHANGE IN TERMINAL RESISTANCE – %
0500
–0.20
0.10
–0.10
0
0.05
100 200 250 300 350 400 450
AVG –3␴
CODE = 80
H
V
DD
= V
SS
= ⴞ5V
SS = 135 UNITS
50 150
–0.05
–0.15
AVG +3␴
AVG
TPC 28. Long-Term Resistance Drift
CHANNEL-TO-CHANNEL R
AB
MATCH – %
FREQUENCY
–0.50
0
40
30
CODE SET TO MID-SCALE
T
A
= 150ⴗC
3 LOTS
SAMPLE SIZE = 135
20
10
–0.40 –0.30 –0.20 –0.10 0 0.10 0.20
TPC 29. Channel-to-Channel
Resistance Matching (AD5262)
V
MS
AW
B
DUT
Vⴙ
V+ = VDD
1LSB = V+/2N
Test Circuit 1. Potentiometer Divider
Nonlinearity Error (INL, DNL)
NC
IW
V
MS
AW
B
DUT NC = NO CONNECT
Test Circuit 2. Resistor Position Nonlinearity Error
(Rheostat Operation; R-INL, R-DNL)
VMS1
IW = VDD /RNOMINAL
VMS2
VW
RW = [VMS1 – VMS2]/IW
AW
B
DUT
Test Circuit 3. Wiper Resistance
⌬V
MS
%
⌬V
DD
%
PSS (%/%) =
V+ = V
DD
10%
PSRR (dB) = 20 LOG
⌬V
MS
⌬V
DD
( )
V
DD
V
A
V
MS
AW
B
V+
Test Circuit 4. Power Supply Sensitivity (PSS, PSSR)
+13V
–13V
W
A
B
V
OUT
OFFSET
GND
DUT
AD8610
V
IN
Test Circuit 5. Gain vs. Frequency
W
B
V
SS
TO V
DD
DUT
I
SW
CODE = 00
H
R
SW
=0.1V
I
SW
0.1V
A = NC
Test Circuit 6. Incremental ON Resistance
W
BV
CM
I
CM
A
NC
GND
NC
V
SS
V
DD
DUT
Test Circuit 7. Common-Mode Leakage Current
TEST CIRCUITS
Test Circuits 1 to 9 define the test conditions used in the product specification table.
REV. 0
–14–
AD5260/AD5262
TEST CIRCUITS (continued)
SDI
CLK
CS
LOGIC
I
LOGIC
DIGITAL INPUT
VOLTAGE
Test Circuit 8. V
LOGIC
Current vs. Digital Input Voltage
W
BV
CM
I
CM
A
NC
GND
NC
V
SS
V
DD
DUT
Test Circuit 9. Analog Crosstalk
PROGRAMMING THE POTENTIOMETER DIVIDER
Voltage Output Operation
The digital potentiometer easily generates output voltages at wiper-
to-B and wiper-to-A to be proportional to the input voltage at
A-to-B. Ignore the effect of the wiper resistance at the moment.
For example, connecting A-terminal to 5 V and B-terminal to
ground produces an output voltage at the wiper-to-B starting at
zero volts up to 1 LSB less than 5 V. Each LSB of voltage is equal
to the voltage applied across terminal AB divided by the 256 posi-
tion of the potentiometer divider. Since the AD5260/AD5262
operates from dual supplies, the general equation defining the
output voltage at V
W
with respect to ground for any given input
voltage applied to terminals AB is:
VD DVV
WABB
()
=¥+
256 (3)
Operation of the digital potentiometer in the divider mode results
in more accurate operation over temperature. Unlike the rheostat
mode, the output voltage is dependent on the ratio of the internal
resistors R
WA
and R
WB
and not the absolute values; therefore, the
drift reduces to 5 ppm/∞C.
APPLICATIONS
Bipolar DC or AC Operation from Dual Supplies
The AD5260/AD5262 can be operated from dual supplies enabling
control of ground referenced AC signals or bipolar operation.
The AC signal, as high as V
DD
/V
SS
, can be applied directly across
terminals A–B with output taken from terminal W. See Figure 13
for a typical circuit connection.
VSS
+5.0V
CLK
CS
GND
VDD
SDI
GND
VDD
–5.0V
SCLK
MOSI
␮C
SS ⴞ5V p-p
ⴞ2.5V p-p
D = 80H
Figure 13. Bipolar Operation from Dual Supplies
Gain Control Compensation
Digital potentiometers are commonly used in gain control as in
the noninverting gain amplifier shown in Figure 14.
U1
V
O
W
BA
R2
200k⍀
C2
4.7pF
V
i
R1
47k⍀
C1
25pF
Figure 14. Typical Noninverting Gain Amplifier
Notice that when the RDAC B terminal parasitic capacitance is
connected to the op amp noninverting node, it introduces a zero
for the 1/b
O
term with +20 dB/dec, whereas a typical op amp GBP
has –20 dB/dec characteristics. A large R2 and finite C1 can cause
this Zero’s frequency to fall well below the crossover frequency.
Hence the rate of closure becomes 40 dB/dec and the system has
0∞ phase margin at the crossover frequency. The output may ring
or oscillate if the input is a rectangular pulse or step function.
Similarly, it is also likely to ring when switching between two
gain values because this is equivalent to a step change at the input.
Depending on the op amp GBP, reducing the feedback resistor
may extend the Zero’s frequency far enough to overcome the prob-
lem. A better approach, however, is to include a compensation
capacitor C2 to cancel the effect caused by C1. Optimum compen-
sation occurs when R1 C1 = R2 C2. This is not an option
because of the variation of R2. As a result, one may use the relation-
ship above and scale C2 as if R2 is at its maximum value. Doing so
may overcompensate and compromise the performance slightly
when R2 is set at low values. However, it will avoid the ringing or
oscillation at the worst case. For critical applications, C2 should
be found empirically to suit the need. In general, C2 in the range
of a few pF to no more than a few tenths of pF is usually adequate
for the compensation.
Similarly, there are W and A terminal capacitances connected to
the output (not shown). Fortunately their effect at this node is less
significant, and the compensation can be avoided in most cases.
Programmable Voltage Reference
For voltage divider mode operation, Figure 15, it is common
to buffer the output of the digital potentiometer unless the load is
much larger than R
WB
. Not only does the buffer serve the pur-
pose of impedance conversion, but it also allows a heavier load
to be driven.
REV. 0 –15–
AD5260/AD5262
A1
VO
5V
VIN
GND
VOUT
5V
AD1582
U1
AD8601
1
2
3AW
B
AD5260
Figure 15. Programmable Voltage Reference
8-Bit Bipolar DAC
Figure 16 shows a low cost 8-bit bipolar DAC. It offers the same
number of adjustable steps but not the precision of conventional
DACs. The linearity and temperature coefficients, especially at low
values codes, are skewed by the effects of the digital potentiometer
wiper resistance. The output of this circuit is:
VDV
O REF
=-
Ê
Ë
Áˆ
¯
˜¥
2
256 1(4)
ⴚ5VREF
OP2177
A2 –5V
OP2177
BA
W
W1
A1
VO
+5V
–5V
+5V
U2
+5VREF
VIN
GND
VOUT
TRIM
AD5260
Vi
ADR425
R R
U1
Figure 16. 8-Bit Bipolar DAC
Bipolar Programmable Gain Amplifier
For applications that require bipolar gain, Figure 17 shows one
implementation. Digital potentiometer U1 sets the adjustment
range. The wiper voltage at W2 can therefore be programmed
between V
i
and –KV
i
at a given U2 setting. Configuring A2
in
the noninverting mode allows linear gain and attenuation. The
transfer function is:
V
V
R
R
DKK
O
i
=+
Ê
Ë
Áˆ
¯
˜¥¥+
()
-
Ê
Ë
Áˆ
¯
˜
12
1
2
256 1
(5)
where K is the ratio of R
WB1
/R
WA1
set by U1.
–KVi
A1 B1
OP2177
A2
VDD
VSS
R1
R2
VDD
VSS
OP2177
A2 B2
W2
U2
AD5262
U1
AD5262
W1
A1
Vi
VO
C1
Figure 17. Bipolar Programmable Gain Amplifier
Similar to the previous example, in the simpler (and much more
usual) case, where K = 1, a single digital pot AD5260, and U1
is replaced by a matched pair of resistors to apply V
i
and – V
i
at
the ends of the digital pot. The relationship becomes:
VR
R
DV
Oi
=+
Ê
Ë
Áˆ
¯
˜-
Ê
Ë
Áˆ
¯
˜¥12
1
22
256 1
(6)
If R2 is large, a few picofarad compensation capacitors may be
needed to avoid any gain peaking.
Table VIII shows the result of adjusting D, with A2 configured as a
unity gain, a gain of 2, and a gain of 10. The result is a bipolar
amplifier with linearly programmable gain and 256-step resolution.
Table VIII. Result of Bipolar Gain Amplifier
DR1
= •, R2 = 0 R1
= R2 R2
= 9R1
0–1 –2 –10
64 –0.5 –1 –5
128 0 0 0
192 0.5 1 5
255 0.968 1.937 9.680
Programmable Voltage Source with Boosted Output
For applications that require high current adjustment such as a
laser diode driver or turnable laser, a boosted voltage source can
be considered (see Figure 18).
Vi
A1
VO
W
U1
A
B
CC
5V
SIGNAL LO
N1
R1 10k⍀P1 RBIAS
IL
U1= AD5260
A1= AD8601, AD8605, AD8541
P1= FDP360P, NDS9430
N1= FDV301N, 2N7002
Figure 18. Programmable Boosted Voltage Source
In this circuit, the inverting input of the op amp forces the V
O
to be
equal to the wiper voltage set by the digital potentiometer. The
load current is then delivered by the supply via the P-Ch FET P1.
The N-Ch FET N
1
simplifies the op amp driving requirement.
A1 needs to be the rail-to-rail input type. Resistor R1 is needed to
prevent P1 from not turning off once it is on. The choice of R1 is a
balance between the power loss of this resistor and the output turn-
off time. N1 can be any general-purpose signal FET; on the other
hand, P1 is driven in the saturation state, and therefore its power
handling must be adequate to dissipate (V
i
– V
O
) I
L
power. This
circuit can source a maximum of 100 mA at 5 V supply. Higher
current can be achieved with P1 in a larger package. Note, a single
N-Ch FET can replace P1, N1, and R1 altogether. However, the out-
put swing will be limited unless separate power supplies are used.
For precision application, a voltage reference such as ADR423,
ADR292, and AD1584 can be applied at the input of the digital
potentiometer.
Programmable 4-to-20 mA Current Source
A programmable 4-to-20 mA current source can be implemented
with the circuit shown in Figure 19. REF191 is a unique low
supply headroom and high current handling precision reference
REV. 0
–16–
AD5260/AD5262
that can deliver 20 mA at 2.048 V. The load current is simply the
voltage across terminals B-to-W of the digital pot divided by R
S
.
IVD
R
L
REF
S
=¥
(7)
–5V
V
OUT
OP1177
+
–
U2
+5V
R
L
100⍀
R
S
102⍀
V
L
I
L
A
BW
AD5260
C1
1␮F
GND
REF191
SLEEP
V
IN
ⴙ5V
2U1
3
4
60 TO (2.048 ⴙ V
L
)
–2.048V TO V
L
Figure 19. Programmable 4-to-20 mA Current Source
The circuit is simple, but be aware that dual-supply op amps are
ideal because the ground potential of REF191 can swing from
–2.048 V at zero scale to V
L
at full scale of the potentiometer
setting. Although the circuit works under single supply, the pro-
grammable resolution of the system will be reduced.
Programmable Bidirectional Current Source
For applications that require bidirectional current control or higher
voltage compliance, a Howland current pump can be a solution
(see Figure 20). If the resistors are matched, the load current is:
IRA RB R
RB V
LW
=+
()
¥
221
2
/
(8)
–5V
+5V
AD8016
–15V
+15V
–15V
OP2177
AD5260
A1
V
L
W
A
B
C2
10pF
I
L
R1
150k⍀
R1
150k⍀
A2
C1
10pF
R2
15k⍀
R2A
14.95k⍀R
L
500⍀
R
L
50⍀
+15V
Figure 20. Programmable Bidirectional Current Source
Programmable Low-Pass Filter
Digital potentiometer AD5262 can be used to construct a second
order Sallen Key Low-Pass Filter (see Figure 21). The design
equations are:
V
VSQS
O
i
O
OO
=
++
w
ww
2
22
(9)
wORR CC
=1
1212 (10)
QRC R C
=+
1
11
1
22
(11)
Users can first select some convenient values for the capacitors.
To achieve maximally flat bandwidth where Q = 0.707, let C1 be
twice the size of C2
and let R1 = R2. As a result, users can adjust
R1 and R2 to the same settings to achieve the desirable bandwidth.
AB
Vi
AD8601
+2.5V
VO
–2.5V
W
R
R2R1
AB
W
R
C1
C2
ADJUSTED TO
SAME SETTINGS
Figure 21. Sallen Key Low-Pass Filter
Programmable Oscillator
In a classic Wien-bridge oscillator, Figure 22, the Wien network
(R, R’, C, C’) provides positive feedback, while R1 and R2
provide negative feedback. At the resonant frequency, f
o
, the
overall phase shift is zero, and the positive feedback causes the
circuit to oscillate. With R = R’, C = C’, and R2 = R2A//(R2B+
R
DIODE
), the oscillation frequency is:
wp
OO
RC fRC
==
11
2
or (12)
where R is equal to R
WA
such that:
RDRAB
=256
256
–
(13)
At resonance, setting
R
R
2
12=
(14)
balances the bridge. In practice, R2/R1 should be set slightly larger
than 2 to ensure the oscillation can start. On the other hand, the
alternate turn-on of the diodes D1 and D2 ensures R2/R1 to be
smaller than 2 momentarily and therefore stabilizes the oscillation.
Once the frequency is set, the oscillation amplitude can be tuned
by R2B since:
2
32VIRBV
OD D
=+
(15)
REV. 0 –17–
AD5260/AD5262
V
O
, I
D
, and V
D
are interdependent variables. With proper selection
of R2B, an equilibrium will be reached such that V
O
converges. R2B
can be in series with a discrete resistor to increase the amplitude,
but the total resistance cannot be too large to saturate the output.
In both circuits in Figures 21 and 22, the frequency tuning requires
that both RDACs be adjusted to the same settings. Since the two
channels will be adjusted one at a time, an intermediate state will
occur that may not be acceptable for certain applications. As a
result, different devices can also be used in daisy-chained mode so
that parts can be programmed to the same setting simultaneously.
+5V
OP1177 V
O
–5V
R2A
2.1k⍀D1
D2
R2B
10k⍀
VN
R1
1k⍀
AB
W
R1 = R1 = R2B = AD5262
D1 = D2 = 1N4148
AD5262
C
2.2nF R
10k⍀
AB
W
VP
C
2.2nF
FREQUENCY
ADJUSTMENT
R
10k⍀
A
B
W
U1
AMPLITUDE
ADJUSTMENT
Figure 22. Programmable Oscillator with
Amplitude Control
Resistance Scaling
The AD5260/AD5262 offer 20 kW, 50 kW, and 200 kW nominal
resistance. For users who need lower resistance and still maintain the
numbers of step adjustment, they can parallel multiple devices. For
example, Figure 23 shows a simple scheme of paralleling both
channels of the AD5262. To adjust half of the resistance linearly
per step, users need to program both channels coherently with
the same settings.
W1
A1
B1 W2
A2
B2
LD
VDD
Figure 23. Reduce Resistance by Half with Linear
Adjustment Characteristics
In voltage divider mode, a much lower resistance can be achieved
by paralleling a discrete resistor as shown in Figure 24. The equiva-
lent resistance becomes:
RDRR R
WB eq W_=§§
()
+
256 12 (16)
RDRR R
WA eq W_
=-
Ê
Ë
Áˆ
¯
˜§§
()
+1256 12
(17)
W
A
B
R2 R1
R2 << R1
Figure 24. Lowering the Nominal Resistance
Figures 23 and 24 show that the digital potentiometers change steps
linearly. On the other hand, log taper adjustment is usually pre-
ferred in applications like audio control. Figure 25 shows another
way of resistance scaling. In this circuit, the smaller the R2 with
respect to R
AB
, the more the pseudo-log taper characteristic behaves.
V
O
A
B
R1
R2
V
i
W
Figure 25. Resistor Scaling with Log Adjustment
Characteristics
RDAC CIRCUIT SIMULATION MODEL
The internal parasitic capacitances and the external capacitive
loads dominate the ac characteristics of the RDACs. Configured
as a potentiometer divider, the –3 dB bandwidth of the AD5260
(20 kW resistor) measures 310 kHz at half scale. TPC 20 provides
the large signal BODE plot characteristics of the three available
resistor versions 20 kW, 50 kW, and 200 kW. A parasitic simulation
model is shown in Figure 26. Listing I provides a macro model
net list for the 20 kW RDAC.
AB
55pF
CA
25pF
CB
25pF
CW
RDAC
20k⍀
W
Figure 26. RDAC Circuit Simulation Model for RDAC = 20 k
W
Listing I. Macro Model Net List for RDAC
PARAM D=256, RDAC=20E3
*
SUBCKT DPOT (A,W,B)
*
CA A 0 25E-12
RWA A W {(1-D/256)*RDAC+60}
CW W 0 55E-12
RWB W B {D/256*RDAC+60}
CB B 0 25E-12
*
.ENDS DPOT
REV. 0
–18–
AD5260/AD5262
DIGITAL POTENTIOMETER FAMILY SELECTION GUIDE
1
Number Terminal Interface Nominal Resolution Power Supply
Part of VRs per Voltage Data Resistance (No. of Wiper Current
Number Package Range (V) Control (k⍀)Positions) (I
DD
) (␮A) Packages Comments
AD5201 1±3, 5.5 3-Wire 10, 50 33 40 mSOIC-10 Full AC Specs, Dual
Supply, Power-On-
Reset, Low Cost
AD5220 15.5 UP/DOWN 10, 50, 100 128 40 PDIP, SO-8, No Rollover,
mSOIC-8 Power-On-Reset
AD7376 1±15, 28 3-Wire 10, 50, 100, 128 100 PDIP-14, Single 28 V or Dual
1000 SOL-16, ±15 V Supply Operation
TSSOP-14
AD5200 1±3, 5.5 3-Wire 10, 50 256 40 mSOIC-10 Full AC Specs, Dual
Supply, Power-On-Reset
AD8400 15.5 3-Wire 1, 10, 50, 100 256 5 SO-8 Full AC Specs
AD5260 1±5, 15 3-Wire 20, 50, 200 256 60 TSSOP-14 5 V to 15 V or ±5 V
Operation,
TC < 50 ppm/∞C
AD5241 1±3, 5.5 2-Wire 10, 100, 256 50 SO-14, I
2
C Compatible,
1000 TSSOP-14 TC < 50 ppm/∞C
AD5231 1±2.75, 5.5 3-Wire 10, 50, 100 1024 20 TSSOP-16 Nonvolatile Memory,
Direct Program, I/D,
±6 dB settability
AD5222 2±3, 5.5 UP/DOWN 10, 50, 100, 128 80 SO-14, No Rollover, Stereo,
1000 TSSOP-14 Power-On-Reset,
TC < 50 ppm/∞C
AD8402 25.5 3-Wire 1, 10, 50, 256 5 PDIP, SO-14, Full AC Specs, nA
100 TSSOP-14 Shutdown Current
AD5207 2±3, 5.5 3-Wire 10, 50, 100 256 40 TSSOP-14 Full AC Specs, Dual
Supply, Power-On-
Reset, SDO
AD5232 2±2.75, 5.5 3-Wire 10, 50, 100 256 20 TSSOP-16 Nonvolatile Memory,
Direct Program, I/D,
±6 dB Settability
AD5235
2
2±2.75, 5.5 3-Wire 25, 250 1024 20 TSSOP-16 Nonvolatile Memory,
Direct Program,
TC < 50 ppm/∞C
AD5242 2±3, 5.5 2-Wire 10, 100, 256 50 SO-16, I
2
C Compatible,
1000 TSSOP-16 TC < 50 ppm/∞C
AD5262 2±5, 15 3-Wire 20, 50, 200 256 60 TSSOP-16 5 V to 15 V or ±5 V
Operation,
TC < 50 ppm/∞C
AD5203 45.5 3-Wire 10, 100 64 5 PDIP, SOL-24, Full AC Specs, nA
TSSOP-24 Shutdown Current
AD5233 4±2.75, 5.5 3-Wire 10, 50, 100 64 20 TSSOP-24 Nonvolatile Memory,
Direct Program, I/D,
±6 dB Settability
AD5204 4±3, 5.5 3-Wire 10, 50, 100 256 60 PDIP, SOL-24, Full AC Specs, Dual
TSSOP-24 Supply, Power-On-Reset
AD8403 45.5 3-Wire 1, 10, 50, 100 256 5 PDIP, SOL-24, Full AC Specs, nA
TSSOP-24 Shutdown Current
AD5206 6±3, 5.5 3-Wire 10, 50, 100 256 60 PDIP, SOL-24, Full AC Specs, Dual
TSSOP-24 Supply, Power-On-Reset
1
For the most current information on digital potentiometers, check the website at: www.analog.com/DigitalPotentiometers
2
Future product, consult factory for latest status.
REV. 0 –19–
AD5260/AD5262
14-Lead TSSOP
(RU-14)
14 8
71
0.256 (6.50)
0.246 (6.25)
0.177 (4.50)
0.169 (4.30)
PIN 1
0.201 (5.10)
0.193 (4.90)
SEATING
PLANE
0.006 (0.15)
0.002 (0.05)
0.0118 (0.30)
0.0075 (0.19)
0.0256
(0.65)
BSC
0.0433 (1.10)
MAX
0.0079 (0.20)
0.0035 (0.090)
0.028 (0.70)
0.020 (0.50)
8ⴗ
0ⴗ
16-Lead TSSOP
(RU-16)
16 9
81
0.256 (6.50)
0.246 (6.25)
0.177 (4.50)
0.169 (4.30)
PIN 1
0.201 (5.10)
0.193 (4.90)
SEATING
PLANE
0.006 (0.15)
0.002 (0.05)
0.0118 (0.30)
0.0075 (0.19)
0.0256 (0.65)
BSC
0.0433 (1.10)
MAX
0.0079 (0.20)
0.0035 (0.090)
0.028 (0.70)
0.020 (0.50)
8ⴗ
0ⴗ
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
–20–
C02695–0–3/02(0)
PRINTED IN U.S.A.