AON7405
30V P-Channel MOSFET
General Description Product Summary
V
DS
I
D
(at V
GS
= -10V) -50A
R
DS(ON)
(at V
GS
= -10V) < 6.2mΩ
R
DS(ON)
(at V
GS
= -6V) < 8.9mΩ
100% UIS Tested
100% R
g
Tested
Symbol
V
DS
-30V
The AON7405 uses advanced trench technology to
provide excellent R
DS(ON)
with low gate charge.
This device is ideal for load switch and battery protection
applications.
• RoHS and Halogen-Free Compliant
V
Maximum UnitsParameter
Absolute Maximum Ratings T
A
=25°C unless otherwise noted
Drain-Source Voltage
-30
DFN 3.3x3.3 EP
Top View Bottom
Pin 1
Top View
1
2
3
4
8
7
6
5G
D
S
V
DS
V
GS
I
DM
I
AR
, I
AS
E
AR
, E
AS
T
J
, T
STG
Symbol
t ≤ 10s
Steady-State
Steady-State
R
θJC
Thermal Characteristics
Maximum Junction-to-Case °C/W
°C/W
Maximum Junction-to-Ambient
A D
1.1 55
1.5
Power Dissipation
B
W
Power Dissipation
A
P
DSM
W
T
A
=70°C
83
4
T
A
=25°C
A
T
A
=70°C -25
I
D
-50
-39
T
C
=25°C
T
C
=100°C
A-44
A
V±25Gate-Source Voltage
Continuous Drain
Current
G
T
A
=25°C I
DSM
V
Drain-Source Voltage
-30
Maximum Junction-to-Ambient
°C/W
R
θJA
16
45 20
°C
-210Pulsed Drain Current
C
Units
Repetitive avalanche energy L=0.1mH
C
mJ
Avalanche Current
C
-20
Continuous Drain
Current
97
Parameter Typ Max
T
C
=25°C
6.25
33
T
C
=100°C
Junction and Storage Temperature Range -55 to 150
P
D
Rev.2. 0: May 2013 www.aosmd.com Page 1 of 6
AON7405
Symbol Min Typ Max Units
BV
DSS
-30 V
V
DS
=-30V, V
GS
=0V -1
T
J
=55°C -5
I
GSS
±100 nA
V
GS(th)
Gate Threshold Voltage -1.7 -2.2 -2.8 V
I
D(ON)
-210 A
5.1 6.2
T
J
=125°C 7.6 9.2
V
GS
=-6V, ID=-20A 7.1 8.9 mΩ
10.7 mΩ
g
FS
46 S
V
SD
-0.7 -1 V
I
S
-50 A
C
iss
1960 2450 2940 pF
C
oss
380 550 720 pF
C
rss
220 370 520 pF
R
g
7 14 28 Ω
Q
g
(10V) 33 42 51 nC
Q
g
(4.5V) 16 21 26 nC
Q
gs
5.5 7 8.5 nC
Q
gd
7 12 17 nC
t
9.5
ns
Drain-Source Breakdown Voltage
On state drain current
I
D
=-250µA, V
GS
=0V
V
GS
=-10V, V
DS
=-5V
V
GS
=-10V, I
D
=-20A
Reverse Transfer Capacitance V
GS
=0V, V
DS
=-15V, f=1MHz
SWITCHING PARAMETERS
Electrical Characteristics (T
J
=25°C unless otherwise noted)
STATIC PARAMETERS Parameter Conditions
I
DSS
µA
V
DS
=V
GS
I
D
=-250µA
V
DS
=0V, V
GS
= ±25V
Zero Gate Voltage Drain Current
Gate-Body leakage current
Forward Transconductance
Diode Forward Voltage
R
DS(ON)
Static Drain-Source On-Resistance mΩ
I
S
=-1A,V
GS
=0V
V
DS
=-5V, I
D
=-20A
V
GS
=-4.5V, I
D
=-10A
Gate resistance V
GS
=0V, V
DS
=0V, f=1MHz
Total Gate Charge
V
GS
=-10V, V
DS
=-15V, I
D
=-20A
Gate Source Charge
Gate Drain Charge
Total Gate Charge
Maximum Body-Diode Continuous Current
G
Input Capacitance
Output Capacitance
Turn-On DelayTime
DYNAMIC PARAMETERS
t
D(on)
9.5
ns
t
r
10 ns
t
D(off)
104 ns
t
f
78 ns
t
rr
20 25 30 ns
Q
rr
37 47 57 nC
THIS PRODUCT HAS BEEN DESIGNED AND QUALIFIED FOR THE CONSUMER MARKET. APPLICATIONS OR USES AS CRITICAL
COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS ARE NOT AUTHORIZED. AOS DOES NOT ASSUME ANY LIABILITY ARISING
OUT OF SUCH APPLICATIONS OR USES OF ITS PRODUCTS. AOS RESERVES THE RIGHT TO IMPROVE PRODUCT DESIGN,
FUNCTIONS AND RELIABILITY WITHOUT NOTICE.
Body Diode Reverse Recovery Time I
F
=-20A, dI/dt=500A/µs
Turn-Off Fall Time
Body Diode Reverse Recovery Charge I
F
=-20A, dI/dt=500A/µs
Turn-On DelayTime
Turn-On Rise Time
Turn-Off DelayTime V
GS
=-10V, V
DS
=-15V,
R
L
=0.75Ω, R
GEN
=3Ω
A. The value of RθJA is measured with the device mounted on 1in2FR-4 board with 2oz. Copper, in a still air environment with TA=25°C. The
Power dissipation PDSM is based on R θJA t ≤ 10s value and the maximum allowed junction temperature of 150°C. The value in any given
application depends on the user's specific board design.
B. The power dissipation PDis based on TJ(MAX)=150°C, using junction-to-case thermal resistance, and is more useful in setting the upper
dissipation limit for cases where additional heatsinking is used.
C. Repetitive rating, pulse width limited by junction temperature TJ(MAX)=150°C. Ratings are based on low frequency and duty cycles to keep
initial TJ =25°C.
D. The RθJA is the sum of the thermal impedence from junction to case RθJC and case to ambient.
E. The static characteristics in Figures 1 to 6 are obtained using <300µs pulses, duty cycle 0.5% max.
F. These curves are based on the junction-to-case thermal impedence which is measured with the device mounted to a large heatsink, assuming
a maximum junction temperature of TJ(MAX)=150°C. The SOA curve provides a single pulse rating.
G. The maximum current rating is limited by package.
H. These tests are performed with the device mounted on 1 in2FR-4 board with 2oz. Copper, in a still air environment with TA=25°C.
Rev.2.0 : May 2013 www.aosmd.com Page 2 of 6
AON7405
TYPICAL ELECTRICAL AND THERMAL CHARACTERISTICS
17
5
2
10
0
18
0
20
40
60
80
100
120
123456
-ID(A)
-VGS(Volts)
Figure 2: Transfer Characteristics (Note E)
3
4
5
6
7
8
9
0 5 10 15 20 25 30
RDS(ON) (mΩ
Ω
Ω
Ω)
-ID(A)
Figure 3: On-Resistance vs. Drain Current and Gate
Voltage (Note E)
0.8
1
1.2
1.4
1.6
1.8
0 25 50 75 100 125 150 175
Normalized On-Resistance
Temperature (°C)
Figure 4: On-Resistance vs. Junction Temperature
(Note E)
VGS=-6V
ID=-20A
VGS=-10V
ID=-20A
25°C
125
°
C
V
DS
=-5V
VGS=-6V
VGS=-10V
0
20
40
60
80
100
120
0 1 2 3 4 5
-ID(A)
-VDS (Volts)
Fig 1: On-Region Characteristics (Note E)
VGS=-3.5V
-5V
-6V,-8V,-10V
-4V
40
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
1.0E+00
1.0E+01
1.0E+02
0.0 0.2 0.4 0.6 0.8 1.0
-IS(A)
-VSD (Volts)
Figure 6: Body-Diode Characteristics (Note E)
25°
125°C
(Note E)
1
5
9
13
17
21
345678910
RDS(ON) (mΩ
Ω
Ω
Ω)
-VGS (Volts)
Figure 5: On-Resistance vs. Gate-Source Voltage
(Note E)
ID=-20A
25
°
125
°
Rev.2.0 : May 2013 www.aosmd.com Page 3 of 6
AON7405
TYPICAL ELECTRICAL AND THERMAL CHARACTERISTICS
17
5
2
10
0
18
0
2
4
6
8
10
0 10 20 30 40 50
-VGS (Volts)
Qg(nC)
Figure 7: Gate-Charge Characteristics
0
500
1000
1500
2000
2500
3000
3500
4000
0 5 10 15 20 25 30
Capacitance (pF)
-VDS (Volts)
Figure 8: Capacitance Characteristics
Ciss
0
50
100
150
200
250
300
350
400
0.0001 0.001 0.01 0.1 1 10
Power (W)
Pulse Width (s)
Figure 10: Single Pulse Power Rating Junction
-
to
-
C
oss
C
rss
VDS=-15V
ID=-20A
TJ(Max)=150°C
TC=25°C
10
µ
s
0.0
0.1
1.0
10.0
100.0
1000.0
0.01 0.1 1 10 100
-ID(Amps)
-VDS (Volts)
Figure 9: Maximum Forward Biased Safe
10
µ
DC
RDS(ON)
TJ(Max)=150°C
T
C
=25°C
100
µ
1ms
40
Figure 10: Single Pulse Power Rating Junction
-
to
-
Case (Note F)
0.01
0.1
1
10
0.00001 0.0001 0.001 0.01 0.1 1 10
Zθ
θ
θ
θJC Normalized Transient
Thermal Resistance
Pulse Width (s)
Figure 11: Normalized Maximum Transient Thermal Impedance (Note F)
Single Pulse
D=Ton/T
TJ,PK=TC+PDM.ZθJC.RθJC
T
on
T
P
D
In descending order
D=0.5, 0.3, 0.1, 0.05, 0.02, 0.01, single pulse
Figure 9: Maximum Forward Biased Safe
Operating Area (Note F)
RθJC=1.5°C/W
Rev.2.0 : May 2013 www.aosmd.com Page 4 of 6
AON7405
TYPICAL ELECTRICAL AND THERMAL CHARACTERISTICS
17
5
2
10
0
18
10
100
1000
1 10 100 1000
-IAR (A) Peak Avalanche Current
Time in avalanche, tA(µ
µµ
µs)
Figure 12: Single Pulse Avalanche capability
(Note C)
0
10
20
30
40
50
60
70
80
90
0 25 50 75 100 125 150
Power Dissipation (W)
TCASE (°
°°
°C)
Figure 13: Power De-rating (Note F)
0
10
20
30
40
50
60
0 25 50 75 100 125 150
-Current rating ID(A)
TCASE (°
°°
°C)
Figure 14: Current De
-
rating (Note F)
TA=25°C
1
10
100
1000
10000
0.00001 0.001 0.1 10 1000
Power (W)
Pulse Width (s)
Figure 15: Single Pulse Power Rating Junction
-
to
-
TA=25°C
TA=150°C
TA=100°C
TA=125°C
40
0.0001
0.001
0.01
0.1
1
10
0.0001 0.001 0.01 0.1 1 10 100 1000
Zθ
θ
θ
θJA Normalized Transient
Thermal Resistance
Pulse Width (s)
Figure 16: Normalized Maximum Transient Thermal Impedance (Note H)
Single Pulse
D=Ton/T
TJ,PK=TA+PDM.ZθJA.RθJA
T
on
T
P
D
In descending order
D=0.5, 0.3, 0.1, 0.05, 0.02, 0.01, single pulse
Figure 14: Current De
-
rating (Note F)
Figure 15: Single Pulse Power Rating Junction
-
to
-
Ambient (Note H)
RθJA=55°C/W
Rev.2.0 : May 2013 www.aosmd.com Page 5 of 6
AON7405
VDC
Ig
Vds
DUT
VDC
Vgs
Vgs Qg
Qgs Qgd
Charge
Gate Charge Test Circuit & Waveform
-
+
-
+
-10V
Id Vds
Unclamped Inductive Switching (UIS) Test Circuit & Waveforms
Vds L
2
E = 1/2 LI
AR
AR
BV
VDC
DUT Vdd
Vgs
Vds
Vgs
RL
Rg
Resistive Switching Test Circuit & Waveforms
-
+
Vgs
Vds
tt
t
tt
t
90%
10%
r
on
d(off)
f
off
d(on)
Vdd
Vgs
Vgs
Rg
DUT
VDC
Vgs
Id
Vgs
-
+
BV
DSS
I
AR
Ig
Vgs
-
+
VDC
DUT
L
Vgs
Isd
Diode Recovery Test Circuit & Waveforms
Vds -
Vds +
dI/dt
RM
rr
Vdd
Vdd
Q = - Idt
t
rr
-Isd
-Vds
F
-I
-I
Rev.2.0 : May 2013
www.aosmd.com
Page 6 of 6