®
Data Device Corporation
105 Wilbur Place
Bohemia, New York 11716
631-567-5600 Fax: 631-567-7358
www.ddc-web.com
FOR MORE INFORMATION CONTACT:
Technical Support:
1-800-DDC-5757 ext. 7771
FEATURES
• Fully Integrated 3.3 or 5.0 Volt, 1553
A/B Notice 2 Terminal
• World’s First all 3.3 Volt Terminal
• Transceiver Power-Down Options
• World’s Smallest CQFP MIL-STD-1553
Device
• 80-pin Ceramic Flat/Gull Wing
Package or 324-Ball BGA Package
• Enhanced Mini-ACE Architecture
• Multiple Configurations:
- RT-only, 4K RAM
- BC/RT/Monitor, 4K RAM
- BC/RT/Monitor, 64K RAM
• Supports 1553A/B Notice 2, McAir,
STANAG 3838 Protocols
• MIL-STD-1553, McAir, and MIL-
STD-1760 Transceiver Options
• Highly Flexible Host Side Interface
• Compatible With Mini-ACE and ACE
Generations
• Highly Autonomous BC with Built-In
Message Sequence Controller
• Choice of Single, Double, and
Circular RT Buffering Options
• Selective Message Monitor
• Comprehensive Built-In Self-Test
• Choice Of 10, 12, 16, or 20 MHz Clock
Inputs
• Software Libraries and Drivers
available for Windows® 9x/2000/XP,
Windows NT®, VxWorks® and Linux
• Available with Full Military
Temperature Range and Screening
DESCRIPTION
The Mini-ACE Mark3 and Micro-ACE-TE are the world's first MIL-STD-1553
terminals which can be powered entirely by +3.3 volts, thus eliminating the
need for a +5 volt power supply. With a package body of 0.880 inches square
and a gull wing "toe-to-toe" dimension of 1.110 inches, the Mini-ACE Mark3
is the industry's smallest ceramic gull-lead 1553 terminal. At 0.815 inches
square, the Micro-ACE-TE (BGA package) provides the smallest industry
footprint, enabling its use in applications where PC board space is at a pre-
mium.
These devices integrate dual 3.3 or 5 volt transceivers, 3.3 or 5.0 volt protocol
logic, and either 4K or 64K words of internal RAM. The architecture is identi-
cal to that of the Enhanced Mini-ACE, and most features are functionally and
software compatible with the previous Mini-ACE (Plus) and ACE genera-
tions.
A salient feature of the Mini-ACE Mark3 and Micro-ACE-TE is the advanced
bus controller architecture. This provides methods to control message sched-
uling, the means to minimize host overhead for asynchronous message
insertion, facilitate bulk data transfers and double buffering, and support
various message retry and bus switching strategies.
The remote terminal architecture provides flexibility in meeting all common
MIL-STD-1553 protocols. The choice of RT data buffering and interrupt
options provides robust support for synchronous and asynchronous messag-
ing, while ensuring data sample consistency and supporting bulk data trans-
fers. The monitor mode provides true message monitoring, and supports fil-
tering on an RT address/T-R bit/subaddress basis.
The Mini-ACE Mark3 and Micro-ACE-TE incorporate fully autonomous built-
in self-tests of internal protocol logic and RAM. The terminals provide the
same flexibility in host interface configurations as the ACE/Mini-ACE, along
with a reduction in the host processor's worst case holdoff time.
BU-6474X/6484X/6486X
MINI-ACE® MARK3/MICRO-ACE®*-TE
Make sure the next
Card you purchase
has...
* The technology used in DDC’s Micro-ACE series of products may be
subject to one or more patents pending.
All trademarks are the property of their respective owners.
© 2002 Data Device Corporation
2
Data Device Corporation
www.ddc-web.com
BU-6474X/6484X/6486X
AJ-6/11-0
FIGURE 1. MINI-ACE MARK3 AND MICRO-ACE-TE BLOCK DIAGRAM
TRANSCEIVER
A
CH. A
TRANSCEIVER
B
CH. B
DUAL
ENCODER/DECODER,
MULTIPROTOCOL
AND
MEMORY
MANAGEMENT
RT ADDRESS
SHARED
RAM (1)
ADDRESS BUS
PROCESSOR
AND
MEMORY
INTERFACE
LOGIC
DATA BUS D15-D0
A15-A0
DATA
BUFFERS
ADDRESS
BUFFERS
PROCESSOR
DATA BUS
PROCESSOR
ADDRESS BUS
MISCELLANEOUS
INCMD/MCRST
CLK_IN, TAG_CLK,
MSTCLR, SSFLAG/EXT_TRG, TX-INH_A, TX-INH_B,
SLEEPIN/UPADDREN
RTAD4-RTAD0, RTADP, RTADD_LAT
TRANSPARENT/BUFFERED, STRBD, SELECT,
RD/WR, MEM/REG, TRIGGER_SEL/MEMENA-IN,
MSB/LSB/DTGRT
IOEN, READYD
ADDR_LAT/MEMOE, ZERO_WAIT/MEMWR,
8/16-BIT/DTREQ, POLARITY_SEL/DTACK
INT
PROCESSOR
AND
MEMORY
CONTROL
INTERRUPT
REQUEST
TX/RX_A
TX/RX_A
TX/RX_B
TX/RX_B
1. See Ordering Information for Available Memory Options.
2. Transformer-coupled configuration and ratio shown.
(1:2.038)
(1:2.038)
Vcc
(Note 2)
(Note 2)
Notes:
3
Data Device Corporation
www.ddc-web.com
BU-6474X/6484X/6486X
AJ-6/11-0
V
V
V
V
µA
µA
mA
mA
mA
mA
pF
pF
0.4
0.4
10
10
-3.4
-2.2
2.4
2.4
-10
-10
3.4
2.2
LOGIC (CONT.)
VOH (Vcc=3.0V, VIH=2.7V,
VIL=0.2V, IOH=max)
VOL (Vcc=3.0V, VIH=2.7V,
VIL=0.2V, IOL=max)
VOH (Vcc=4.5V, VIH=2.7V,
VIL=0.2V, IOH=max)
VOL (Vcc=4.5V, VIH=2.7V,
VIL=0.2V, IOL=max)
CLK_IN
IIH
IIL
IOL (Vcc = 4.5V)
IOH (Vcc = 4.5V)
IOL (Vcc = 3.0V)
IOH (Vcc = 3.0V)
CI (Input Capacitance)
CIO (Bi-directional signal input
capacitance)
UNITSMAXTYPMINPARAMETER
TABLE 1. MINI-ACE MARK3 SERIES
SPECIFICATIONS (CONT.)
50
50
V
V
V
V
V
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
3.60
5.5
5.5
3.46
5.25
95
300
500
900
100
205
310
520
40
160
265
370
580
160
276
392
625
69
110
315
515
915
3.00
4.5
4.5
3.14
4.75
POWER SUPPLY REQUIREMENTS
Voltages/Tolerances (Note 12)
• Logic +3.3V
• Logic +5.0V
• RAM +5.0V
• Transceivers +3.3V
• Transceivers +5.0V
Current Drain (Total Hybrid) (Note 14)
BU-64743X8/9-XX0,
BU-64843X8/9-XX0 (1553&McAir)
• Idle
• 25% Duty Transmitter Cycle
• 50% Duty Transmitter Cycle
• 100% Duty Transmitter Cycle
BU-64743F/G3/4-XX0,
BU-64843F/G3/4-XX0 (1553&McAir)
+5V (Ch. A, Ch. B)
• Idle
• 25% Duty Transmitter Cycle
• 50% Duty Transmitter Cycle
• 100% Duty Transmitter Cycle
• +3.3V (Logic)
BU-64745F/G3/4-XX0
BU-64845F/G3/4-XX0 (1553&McAir)
+5V (Logic, RAM, Ch. A, Ch. B)
• Idle
• 25% Duty Transmitter Cycle
• 50% Duty Transmitter Cycle
• 100% Duty Transmitter Cycle
BU-64745F/G3-XX2
BU-64845F/G3-XX2 (1760)
+5V (Logic, RAM, Ch. A, Ch. B)
• Idle
• 25% Duty Transmitter Cycle
• 50% Duty Transmitter Cycle
• 100% Duty Transmitter Cycle
BU-64863X8/9-XX0 (1553&McAir)
• Idle w/ transceiver SLEEPIN enabled
• Idle w/ transceiver SLEEPIN disabled
• 25% Duty Transmitter Cycle
• 50% Duty Transmitter Cycle
• 100% Duty Transmitter Cycle
3.3
5.0
5.0
3.3
5.0
56
246
436
816
65
169
273
481
25
116
222
328
540
116
233
350
584
31
77
267
457
837
V
V
V
V
V
V
µA
µA
µA
µA
µA
µA
0.7
0.2•Vcc
10
-33
-33
10
-50
-50
2.1
0.8•Vcc
0.4
1.0
-10
-350
-350
-10
-350
-350
LOGIC
VIH
All signals except CLK_IN
CLK_IN
VIL
All signals except CLK_IN
CLK_IN
Schmidt Hysteresis
All signals except CLK_IN
CLK_IN
IIH, IIL
All signals except CLK_IN
IIH (Vcc=3.6V, VIN=Vcc)
IIH (Vcc=3.6V, VIN=2.7V)
IIL (Vcc=3.6V, VIN=0.4V)
IIH, IIL
All signals except CLK_IN
IIH (Vcc=5.25V, Vin=Vcc)
IIH (Vcc=5.25V, IIH Vin=2.7V)
IIL (Vcc=5.25V, Vin=0.4V)
Vp-p
Vp-p
Vp-p
mVp-p
mVp
nsec
nsec
9
27
27
10
250
300
300
7
20
21.5
150
250
6
18
20
-250
100
200
TRANSMITTER
Differential Output Voltage
• Direct Coupled Across 35 Ω,
Measured on Bus
• Transformer Coupled Across
70 Ω, Measured on Bus
BU-64XXXXX-XX0
BU-64XXXXX-XX2 (Note 13)
Output Noise, Differential (Direct
Coupled)
Output Offset Voltage, Transformer
Coupled Across 70 Ω
Rise/Fall Time
BU-64XXXX8/3
BU-64XXXX9/4
kΩ
kΩ
pF
pF
Vp-p
Vpeak
25
40
0.860
10
2.5
2.0
0.200
RECEIVER
Differential Input Resistance
(Notes 1-6)
+5.0V
+3.3V
Differential Input Capacitance
(Notes 1-6)
+5.0V
+3.3V
Threshold Voltage, Transformer
Coupled, Measured on Stub
Common-Mode Voltage (Note 7)
V
V
V
V
V
V
V
V
6.0
4.1
6.0
7.0
6.0
4.5
6.0
6.0
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
ABSOLUTE MAXIMUM RATING
Supply Voltage (Note 12)
• Logic +5V
• Logic +3.3V
• RAM +5V
• Transceivers +5V
• Transceivers +3.3V
(not during transmit)
• Transceivers +3.3V
(during transmit)
Logic
• +5V Logic Input Range
• +3.3V Logic Input Range
UNITSMAX
TYPMINPARAMETER
TABLE 1. MINI-ACE MARK3 SERIES
SPECIFICATIONS
4
Data Device Corporation
www.ddc-web.com
BU-6474X/6484X/6486X
AJ-6/11-0
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
100
205
310
520
55
95
315
535
975
100
216
332
565
40
160
276
392
625
100
216
332
565
40
69
110
330
550
990
100
216
332
565
55
180
296
412
645
120
236
352
585
40
40
55
POWER SUPPLY REQUIREMENTS
(CONT.)
BU-64863F/G3/4-XX0 (1553&McAir)
+5V (Ch. A, Ch. B)
• Idle
• 25% Duty Transmitter Cycle
• 50% Duty Transmitter Cycle
• 100% Duty Transmitter Cycle
• +3.3V (Logic, 64K RAM)
BU-64743X8-XX2,
BU-64843X8-XX2 (1760)
• Idle
• 25% Duty Transmitter Cycle
• 50% Duty Transmitter Cycle
• 100% Duty Transmitter Cycle
BU-64743F/G3-XX2,
BU-64843F/G3-XX2 (1760)
+5V (Ch. A, Ch. B)
• Idle
• 25% Duty Transmitter Cycle
• 50% Duty Transmitter Cycle
• 100% Duty Transmitter Cycle
• +3.3V (Logic)
BU-64840B3-X02 (1760)
+5V (Logic, Ch. A, Ch. B)
• Idle
• 25% Duty Transmitter Cycle
• 50% Duty Transmitter Cycle
• 100% Duty Transmitter Cycle
BU-64840B3-X02 (1760)
+5V (Ch. A, Ch. B)
• Idle
• 25% Duty Transmitter Cycle
• 50% Duty Transmitter Cycle
• 100% Duty Transmitter Cycle
• +3.3V (Logic)
BU-64863X8-XX2 (1760)
• Idle w/ transceiver SLEEPIN enabled
• Idle w/ transceiver SLEEPIN disabled
• 25% Duty Transmitter Cycle
• 50% Duty Transmitter Cycle
• 100% Duty Transmitter Cycle
BU-64863F/G3-XX2 (1760)
+5V (Ch. A, Ch. B)
• Idle
• 25% Duty Transmitter Cycle
• 50% Duty Transmitter Cycle
• 100% Duty Transmitter Cycle
• +3.3V (Logic, 64K RAM)
BU-64860B(R)3-X02 (1760)
+5V (Logic, 64K RAM, Ch. A, Ch. B)
• Idle
• 25% Duty Transmitter Cycle
• 50% Duty Transmitter Cycle
• 100% Duty Transmitter Cycle
BU-64860B(R)3-X02 (1760)
+5V (64K RAM, Ch. A, Ch. B)
• Idle
• 25% Duty Transmitter Cycle
• 50% Duty Transmitter Cycle
• 100% Duty Transmitter Cycle
• +3.3V (Logic)
BU-64743X0-XX0,
BU-64843X0-XX0 (Xcvrless)
BU-64863X0-XX0 (Xcvrless)
65
169
273
481
21
55
216
377
699
65
180
295
525
25
116
233
350
584
65
180
295
525
25
27
76
237
398
720
65
180
295
525
21
116
228
340
563
66
174
282
498
25
25
21
UNITSMAXTYPMINPARAMETER
TABLE 1. MINI-ACE MARK3 SERIES
SPECIFICATIONS (CONT.)
UNITSMAXTYPMINPARAMETER
TABLE 1. MINI-ACE MARK3 SERIES
SPECIFICATIONS (CONT.)
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
0.31
0.69
1.04
1.74
0.63
0.85
1.07
1.51
0.88
1.11
1.33
1.97
0.88
1.17
1.46
2.05
0.23
0.36
0.73
1.09
1.79
0.68
0.90
1.12
1.56
0.31
0.71
1.08
1.83
0.63
0.86
1.09
1.56
0.80
1.03
1.26
1.73
0.63
0.86
1.09
1.56
POWER DISSIPATION
TOTAL HYBRID (NOTES 14 AND 15)
BU-64743X8/9-XX0,
BU-64843X8/9-XX0 (1553&McAir)
• Idle
• 25% Duty Transmitter Cycle
• 50% Duty Transmitter Cycle
• 100% Duty Transmitter Cycle
BU-64743F/G3/4-XX0,
BU-64843F/G3/4-XX0 (1553&McAir)
+3.3V (Logic) +5.0V (Ch. A, Ch. B)
• Idle
• 25% Duty Transmitter Cycle
• 50% Duty Transmitter Cycle
• 100% Duty Transmitter Cycle
BU-64745F/G3/4-XX0
BU-64845F/G3/4-XX0 (1553&McAir)
• Idle
• 25% Duty Transmitter Cycle
• 50% Duty Transmitter Cycle
• 100% Duty Transmitter Cycle
BU-64745F/G3-XX2
BU-64845F/G3-XX2 (1760)
• Idle
• 25% Duty Transmitter Cycle
• 50% Duty Transmitter Cycle
• 100% Duty Transmitter Cycle
BU-64863X8/9-XX0 (1553&McAir)
• Idle w/ transceiver SLEEPIN enabled
• Idle w/ transceiver SLEEPIN disabled
• 25% Duty Transmitter Cycle
• 50% Duty Transmitter Cycle
• 100% Duty Transmitter Cycle
BU-64863F/G3/4-XX0 (1553&McAir)
+3.3V (Logic, 64K RAM) +5.0V (Ch.
A, Ch. B)
• Idle
• 25% Duty Transmitter Cycle
• 50% Duty Transmitter Cycle
• 100% Duty Transmitter Cycle
BU-64743X8-XX2,
BU-64843X8-XX2 (1760)
• Idle
• 25% Duty Transmitter Cycle
• 50% Duty Transmitter Cycle
• 100% Duty Transmitter Cycle
BU-64743F/G3-XX2,
BU-64843F/G3-XX2 (1760)
+3.3V (Logic) +5.0V (Ch. A, Ch. B)
• Idle
• 25% Duty Transmitter Cycle
• 50% Duty Transmitter Cycle
• 100% Duty Transmitter Cycle
BU-64840B3-X02 (1760)
+5.0V (Logic, Ch. A, Ch. B)
• Idle
• 25% Duty Transmitter Cycle
• 50% Duty Transmitter Cycle
• 100% Duty Transmitter Cycle
BU-64840B3-X02 (1760)
+3.3V (Logic) +5.0V (Ch. A, Ch. B)
• Idle
• 25% Duty Transmitter Cycle
• 50% Duty Transmitter Cycle
• 100% Duty Transmitter Cycle
0.18
0.57
0.91
1.58
0.41
0.70
0.94
1.40
0.64
0.93
1.22
1.81
0.64
0.99
1.34
2.04
0.10
0.25
0.62
0.97
1.64
0.44
0.74
0.99
1.44
0.18
0.49
0.76
1.31
0.41
0.72
0.97
1.45
0.58
0.87
1.13
1.62
0.41
0.72
0.97
1.45
5
Data Device Corporation
www.ddc-web.com
BU-6474X/6484X/6486X
AJ-6/11-0
°C/W
°C/W
°C
°C
°C
°C
°C
°C
°C
11
15
+125
+85
+70
+100
+150
+300
+245
9
-55
-40
0
-40
-65
THERMAL
FLAT PACK/GULL WING
80-pin Ceramic Package
Thermal Resistance,
Junction-to-Case, Hottest Die (θJC) Note 16
MICRO-ACE-TE BGA
324-ball BGA Package
(see Thermal Management section)
Junction-to-Balls, Hottest Die (θJB)
ALL PACKAGES
Operating Case/Ball Temperature
-1XX, -4XX
-2XX, -5XX
-3XX, -8XX
-EXX
Storage Temperature
SOLDERING/MOUNTING
FLAT PACK/GULL WING
Lead Temperature (soldering, 10 sec.)
324-BALL BGA PACKAGE
The reflow profile detailed in IPC/
JEDEC J-STD-020 is applicable for
both leaded and lead-free products
Refer to DDC’s Application Note #A/N49 “BGA User’s
Guide” for additional important mounting information.
UNITSMAXTYPMINPARAMETER
TABLE 1. MINI-ACE MARK3 SERIES
SPECIFICATIONS (CONT.)
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
0.23
0.36
0.74
1.12
1.87
0.68
0.91
1.14
1.61
0.90
1.13
1.36
1.83
0.73
0.96
1.19
1.66
0.132
0.182
0.02
0.09
0.47
0.82
1.52
0.25
0.47
0.69
1.13
0.02
0.09
0.49
0.85
1.61
0.25
0.48
0.71
1.18
0.13
POWER DISSIPATION (CONT)
TOTAL HYBRID (NOTES 14 AND 15)
BU-64863X8-XX2 (1760)
• Idle w/ transceiver SLEEPIN enabled
• Idle w/ transceiver SLEEPIN disabled
• 25% Duty Transmitter Cycle
• 50% Duty Transmitter Cycle
• 100% Duty Transmitter Cycle
BU-64863F/G3-XX2 (1760)
+3.3V (Logic, 64K RAM) +5.0V (Ch.
A, Ch. B)
• Idle
• 25% Duty Transmitter Cycle
• 50% Duty Transmitter Cycle
• 100% Duty Transmitter Cycle
BU-64860B(R)3-X02 (1760)
+5.0V (Logic, Ch. A, Ch. B, 64K RAM)
• Idle
• 25% Duty Transmitter Cycle
• 50% Duty Transmitter Cycle
• 100% Duty Transmitter Cycle
BU-64860B(R)3-X02 (1760)
+3.3V (Logic) +5.0V (Ch. A, Ch. B,
64K RAM)
• Idle
• 25% Duty Transmitter Cycle
• 50% Duty Transmitter Cycle
• 100% Duty Transmitter Cycle
BU-64743X0-XX0, BU-64843X0-XX0
(Xcvrless)
BU-64863X0-XX0 (Xcvrless)
HOTTEST DIE
BU-64XXXX8/9-XX0 (1553&McAir)
• Idle w/ transceiver SLEEPIN enabled
(BU-64863 only)
• Idle w/ transceiver SLEEPIN disabled
• 25% Duty Transmitter Cycle
• 50% Duty Transmitter Cycle
• 100% Duty Transmitter Cycle
BU-64XXXX3/4-XX0 (1553&McAir)
• Idle
• 25% Duty Transmitter Cycle
• 50% Duty Transmitter Cycle
• 100% Duty Transmitter Cycle
BU-64XXXX8-XX2 (1760)
• Idle w/ transceiver SLEEPIN enabled
(BU-64863 only)
• Idle w/ transceiver SLEEPIN disabled
• 25% Duty Transmitter Cycle
• 50% Duty Transmitter Cycle
• 100% Duty Transmitter Cycle
BU-64XXXX3-XX2 (1760)
• Idle
• 25% Duty Transmitter Cycle
• 50% Duty Transmitter Cycle
• 100% Duty Transmitter Cycle
BU-64XX3X0-XX0 (Xcvrless)
UNITSMAXTYPMINPARAMETER
TABLE 1. MINI-ACE MARK3 SERIES
SPECIFICATIONS (CONT.)
0.09
0.25
0.53
0.93
1.36
0.44
0.76
1.01
1.50
0.64
0.87
1.12
1.60
0.40
0.71
0.95
1.41
0.08
0.07
0.01
0.05
0.39
0.72
1.38
0.16
0.39
0.61
1.06
0.01
0.05
0.39
0.60
1.15
0.16
0.40
0.63
1.11
0.08
MHz
MHz
MHz
MHz
CLOCK INPUT
• Frequency:
Nominal Values
Default Mode
Option
Option
Option
16.0
12.0
10.0
20.0
%
%
%
%
%
-0.01
-0.10
0.001
0.01
60
0.01
0.10
-0.001
-0.01
40
CLOCK INPUT (CONT)
• Long Term Tolerance
1553A Compliance
1553B Compliance
• Short Term Tolerance, 1 second
1553A Compliance
1553B Compliance
Duty Cycle
µs
µs
µs
µs
µs
µs
µs
µs
µs
19.5
23.5
51.5
131
7
17.5
21.5
49.5
127
4
1553 MESSAGE TIMING
Completion of CPU Write
(BC Start)-to-Start of First Message for
Non-enhanced BC Mode
BC Intermessage Gap (Note 8)
Non-enhanced (Mini-ACE compatible)
BC mode
Enhanced BC mode (Note 9)
BC/RT/MT Response Timeout (Note 10)
• 18.5 nominal
• 22.5 nominal
• 50.5 nominal
• 128.0 nominal
RT Response Time
(mid-parity to mid-sync) (Note 11)
Transmitter Watchdog Timeout
2.5
9.5
10 to
10.5
18.0
22.5
50.5
129.5
660.5
See next page for TABLE 1 notes.
in.
(mm)
in.
(mm)
in.
(mm)
0.880 X 0.880 X 0.13
(22.35 X 22.35 X 3.3)
0.815 X 0.815 X 0.12
(20.7 X 20.7 X 3.05)
MSL-3
ESD Class 0
1.110
(28.194)
PHYSICAL CHARACTERISTICS
Package Body Size
80-pin Ceramic Flat pack or Gull Wing
324-ball BGA
Micro-ACE-TE
Moisture Sensitivity Level
Electrostatic Discharge Sensitivity
Lead Toe-to-Toe Distance
80-pin Gull Wing
6
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INTRODUCTION
The Mini-ACE Mark3 is the world's first MIL-STD-1553 terminal
which can be powered entirely by 3.3 volts, thus eliminating the
need for a 5 volt power supply. The BU-6474X RT only, and
BU-6484X/6486X BC/RT/MT Mini-ACE Mark3 family of MIL-
STD-1553 terminals comprise a complete integrated interface
between a host processor and a MIL-STD-1553 bus. The Mini-
ACE Mark3 is available in a 0.88 square inch flat pack or gull
wing package with a "toe-to-toe" dimension of 1.110 inches, as
well as a 324-ball BGA. The Mini-ACE Mark3 is the industry's
smallest ceramic gull-lead 1553 terminal, enabling its use in
applications where PC board space is at a premium. At 0.815
inches square, the Micro-ACE-TE provides the smallest MIL-
STD-1553 footprint in the industry. The Mark3's architecture is
identical to that of the Enhanced Mini-ACE, and most features
are functionally and software compatible with the previous Mini-
ACE (Plus) and ACE generations.
The Mini-ACE Mark3 provides complete multiprotocol support of
MIL-STD-1553A/B/McAir and STANAG 3838. The Mark3 integrates
dual transceiver, protocol logic, and either 4K or 64K words of inter-
nal RAM. The BU-6486X BC/RT/MT terminal includes 64K words of
internal RAM, with built-in parity checking.
The Mini-ACE Mark3 includes dual 3.3 volt or 5.0 volt voltage
source transceivers for improved line driving capability, with
options for MIL-STD-1760 and McAir compatibility. Mark3 ver-
sions with 64K x 17 RAM offer an additional transceiver power-
down (SLEEPIN) option to further reduce device power con-
sumption. To provide further flexibility, the Mini-ACE Mark3 may
operate with a choice of 10, 12, 16, or 20 MHz clock inputs.
One of the new salient features of the Mark3 is its Enhanced bus
controller architecture. The Enhanced BC's highly autonomous
message sequence control engine provides a means for offloading
the host processor for implementing multiframe message schedul-
ing, message retry schemes, data double buffering, and asynchro-
nous message insertion. For the purpose of performing messaging
to the host processor, the Enhanced BC mode includes a General
Purpose Queue, along with user-defined interrupts.
A second major new feature of the Mark3 is the incorporation of
a fully autonomous built-in self-test. This test provides compre-
hensive testing of the internal protocol logic. A separate test
verifies the operation of the internal RAM. Since the self-tests are
fully autonomous, they eliminate the need for the host to write
and read stimulus and response vectors.
The Mini-ACE Mark3 RT offers the same choices of single,
double, and circular buffering for individual subaddresses as the
ACE, Mini-ACE (Plus) and Enhanced Mini-ACE. New enhance-
ments to the RT architecture include a global circular buffering
option for multiple (or all) receive subaddresses, a 50% rollover
interrupt for circular buffers, an interrupt status queue for logging
up to 32 interrupt events, and an option to automatically initialize
oz
(g)
oz
(g)
0.353
(10)
.088
(2.5)
PHYSICAL CHARACTERISTICS
(CONT.)
Weight
80-pin Ceramic Flat pack or Gull Wing
324-ball BGA
UNITSMAXTYPMINPARAMETER
TABLE 1. MINI-ACE MARK3 SERIES
SPECIFICATIONS (CONT.)
TABLE 1 Notes:
Notes 1 through 6 are applicable to the Receiver Differential Resistance
and Receiver Differential Input Capacitance specifications:
(1) Specifications include both transmitter and receiver (tied together
internally).
(2) Impedance parameters are specified directly between pins TX/
RX_A(B) and TX/RX_A(B) of the Mini-ACE Mark3 hybrid.
(3) It is assumed that all power and ground inputs to the hybrid are
connected.
(4) The specifications are applicable for both unpowered and powered
conditions.
(5) The specifications assume a 2 volt rms balanced, differential, sinu-
soidal input. The applicable frequency range is 75 kHz to 1 MHz.
(6) Minimum resistance and maximum capacitance parameters are
guaranteed over the operating range, but are not tested.
(7) Assumes a common-mode voltage within the frequency range of dc
to 2 MHz, applied to pins of the isolation transformer on the stub
side (either direct or transformer coupled), and referenced to hybrid
ground. Transformer must be a DDC recommended transformer or
other transformer that provides an equivalent minimum CMRR.
(8) Typical value for minimum intermessage gap time. Under software
control, this may be lengthened (to 65,535 ms - message time) in
increments of 1 µs. If ENHANCED CPU ACCESS, bit 14 of
Configuration Register #6, is set to logic "1", then host accesses
during BC Start-of-Message (SOM) and End-of-Message (EOM)
transfer sequences could have the effect of lengthening the inter-
message gap time. For each host access during an SOM or EOM
sequence, the intermessage gap time will be lengthened by 6 clock
cycles. Since there are 7 internal transfers during SOM and 5 dur-
ing EOM, this could theoretically lengthen the intermessage gap by
up to 72 clock cycles; i.e., up to 7.2 ms with a 10 MHz clock, 6.0 µs
with a 12 MHz clock, 4.5 µs with a 16 MHz clock, or 3.6 µs with a
20 MHz clock.
(9) For Enhanced BC mode, the typical value for intermessage gap
time is approximately 10 clock cycles longer than for the non-
enhanced BC mode. That is, an addition of 1.0 µs at 10 MHz, 833
ns at 12 MHz, 625 ns at 16 MHz, or 500 ns at 20 MHz.
(10)Software programmable (4 options). Includes RT-to-RT Timeout
(measured mid-parity of transmit Command Word to mid-sync of
transmitting RT Status Word).
(11)Measured from mid-parity crossing of Command Word to mid-sync
crossing of RT's Status Word.
(12)External 10 µF tantalum and 0.1 µF capacitors should be located
as close as possible to the voltage input pins/balls.
(13)MIL-STD-1760 requires a 20 Vp-p minimum output on the stub con-
nection.
(14)Current drain and power dissipation specs are preliminary and sub-
ject to change.
(15)Power dissipation is the input power minus the power delivered to
the 1553 fault isolation resistors, the power delivered to the bus ter-
mination resistors, and the copper losses in the transceiver isolation
transformer and the bus coupling transformer. An illustration of
external power dissipation for transformer coupled configuration
(while transmitting) is: 0.14 watts for the active isolation transformer,
0.08 watts for the active bus coupling transformer, 0.45 watts for
each of the two bus isolation resistors and 0.15 watts for each of
the two bus termination resistors.
(16)θJC is measured to bottom of ceramic case.
7
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to RT mode with the Busy bit set. The interrupt status queue and
50% rollover interrupt features are also included as improve-
ments to the Mark3's Monitor architecture.
To minimize board space and "glue" logic, the Mini-ACE Mark3
terminals provide the same wide choice of host interface con-
figurations as the ACE, Mini-ACE (Plus) and Enhanced Mini-
ACE. This includes support of interfaces to 16-bit or 8-bit proces-
sors, memory or port type interfaces, and multiplexed or non-
multiplexed address/data buses. In addition, with respect to ACE/
Mini-ACE (Plus), the worst case processor wait time has been
significantly reduced. For example, assuming a 16 MHz clock,
this time has been reduced from 2.8 µs to 632 ns for read
accesses, and to 570 ns for write accesses.
The Mini-ACE Mark3 series terminals operate over the full military
temperature range of -55 to +125°C and are available screened to
MIL-PRF-38534C. The terminals are ideal for military and industrial
processor-to-1553 applications powered by 3.3 volts only.
MICRO-ACE-TE IN SIMPLE SYSTEM RT (SSRT) MODE
The Micro-ACE-TE with 4K RAM (BU-64843B(R)8), MIL-
STD-1553 terminal can provide a complete interface between a
simple system and a MIL-STD-1553 bus when configured as an
SSRT. These terminals integrate dual transceiver, protocol logic,
and a FIFO memory for received messages in a 324-ball BGA.
The internal architecture is identical to that of the original
BU-61703/61705 Simple System RT (SSRT).
The SSRT configured Micro-ACE-TE incorporates a built-in self-
test (BIT). This BIT, which is processed following power turn-on
or after receipt of an Initiate self-test mode command, provides
a comprehensive test of the encoders, decoders, protocol, trans-
mitter watchdog timer, and protocol section. The SSRT config-
ured, Micro-ACE-TE also includes an auto-configuration fea-
ture.
The Micro-ACE-TE when configured as an SSRT is ideal for
munitions stores and other simple systems that do not require a
microprocessor. To streamline the interface to simple systems it
includes an internal 32-word FIFO for received data words. This
serves to ensure that only complete, consistent blocks of vali-
dated data words are transferred to a system.
Detailed SSRT configuration information can be found in
Application Note AN/B-37.
TEST COMPONENTS
Daisy chain mechanical samples of the Micro-ACE-TE, 324-ball
BGA (BU-64863B8-600) are available. These are used to verify
both the electrical and mechanical integrity of the solder joints
between the BGA package and the board. Ball pairs are inter-
nally wired so that the user can test for electrical continuity
between balls. Refer to TABLE 70 for interconnection details.
Although these units are inert, they are fully populated with silicon
die so that they closely match the thermal and mechanical charac-
teristics of standard production units. Internal daisy chain intercon-
nections are made by copper PWB traces.
TRANSCEIVERLESS "COMPATIBLE" VERSION OF
MICRO-ACE-TE
All versions of the Micro-ACE-TE, 324-ball BGA are transceiver-
less "Compatible". These devices contain fully functional, dual-
redundant, MIL-STD-1553 transceivers with internal / intermedi-
ate connections brought out to balls. These intermediate connec-
tions allow devices to be used in transceiverless mode for direct
interfacing to MIL-STD-1773 (fiber optic) transceivers. Mandatory
Additional Connections (See TABLE 59) are required if these
devices are not utilized in their transceiverless mode.
BU-61860E3 +5.0V µ-ACE (MICRO-ACE) &
TRANSFORMER EVALUATION BOARD
The BU-61860E3 board is intended to support customers who
are interested in electrically connecting and evaluating the per-
formance of +5.0V Enhanced Mini-ACE and/or +5.0V µ-ACE
series of products. The user will be able to quickly perform func-
tional tests and run their system software utilizing this relatively
small (2.0" x 2.5") evaluation board.
The BU-61860E3 (see FIGURE 19) consists of a PC board incor-
porating a +5.0V µ-ACE (BU-61860B3, BC / RT / MT with 64K x
17 RAM), necessary decoupling capacitors, and associated isola-
tion transformers. The MIL-STD-1760 outputs are user configu-
rable as either Stub (transformer) or Direct coupling. The board
supports the signal fan-out (see TABLE 72) of the +5.0V µ-ACE to
112 pins subdivided into (4) dual inline, berg type pin rows. These
pins (0.025" square max) and their row placement adhere to stan-
dard 0.100" vector board spacing.
BU-64863E8 MINI-ACE MARK3 (+3.3V) &
TRANSFORMER EVALUATION BOARD
The BU-64863E8 board is intended to support customers who
are interested in electrically connecting and evaluating the per-
formance of the +3.3V Mini-ACE Mark3 and/or +3.3V Micro-
ACE-TE series of products. The user will be able to quickly per-
form functional tests and run their system software utilizing this
relatively small (2.0" x 2.5") evaluation board.
The BU-64863E8 (see FIGURE 20) consists of a PC board incor-
porating a +3.3V Mini-ACE Mark3 (BU-64863G8, BC / RT / MT
with 64K x 17 RAM), necessary decoupling capacitors, and asso-
ciated isolation transformers. The MIL-STD-1553 outputs have
been factory configured for Stub (transformer) coupling. The
board supports the signal fan-out (see TABLE 71) of the +3.3V
Mini-ACE Mark3 to 112 pins subdivided into (4) dual inline, berg
type pin rows. These pins (0.025" square max) and their row
placement adhere to standard 0.100" vector board spacing.
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TRANSCEIVERS
The transceivers in the Mini-ACE Mark3 series terminals are fully
monolithic, requiring only a +3.3 or 5.0 volt power input. The trans-
mitters are voltage sources, providing improved line driving capa-
bility over current sources. This serves to improve performance on
long buses with many taps. Mark3 versions with 64K x 17 RAM
offer an additional transceiver power-down (SLEEPIN) option to
further reduce device power consumption. The transmitters also
offer an option that satisfies the MIL-STD-1760 requirement for a
minimum of 20 volts peak-to-peak, transformer coupled output.
Besides eliminating the demand for an additional power supply,
the use of a +3.3 volt only transceiver (5.0 volt available) requires
the use of a step-up, rather than a step-down, isolation trans-
former. This provides the advantage of a higher terminal input
impedance than is possible for a 15V, 12V or 5V transmitter. As
a result, there is a greater margin for the input impedance test,
mandated for the 1553 validation test. This allows for longer
cable lengths between a system connector and the isolation
transformers of an embedded 1553 terminal.
To provide compatibility to McAir specs, the Mini-ACE Mark3 is
available with an option for transmitters with increased rise and
fall times.
The receiver sections of the Mini-ACE Mark3 are fully compliant
with MIL-STD-1553B Notice 2 in terms of front end overvoltage
protection, threshold, common-mode rejection, and word error
rate.
REGISTER AND MEMORY ADDRESSING
The software interface of the Mini-ACE Mark3 to the host proces-
sor consists of 24 internal operational registers for normal opera-
tion, an additional 24 test registers, plus 64K words of shared
memory address space. The Mini-ACE Mark3's 4K X 16 or 64K
X 17 internal RAM resides in this address space.
For normal operation, the host processor only needs to access
the lower 32 register address locations (00-1F). The next 32 loca-
tions (20-3F) should be reserved, since many of these are used
for factory test.
INTERNAL REGISTERS
The address mapping for the Mini-ACE Mark3 registers is illus-
trated in TABLE 2.
BC General Purpose Queue Pointer /
RT-MT Interrupt Status Queue Pointer Register (RD/
WR)
11111
BC General Purpose Flag Register (WR)
Interrupt Mask Register #2 (RD/WR)
RESERVED
1
1
0
1
0
1
0
1
0
1
1
1
1
1
1
Interrupt Status Register #2 (RD)
BC Condition Code Register (RD)
BIT Test Status Register (RD)
Configuration Register #7 (RD/WR)
0
1
0
1
1
1
0
0
1
0
1
0
1
1
1
1
1
1
1
1
Configuration Register #6 (RD/WR)00011
Test Mode Register 711101
Test Mode Register 6
Test Mode Register 4
Test Mode Register 2
0
0
0
1
0
1
1
1
0
0
0
0
1
1
1
Test Mode Register 5
Test Mode Register 3
Test Mode Register 1
1
1
1
0
1
0
1
0
0
0
0
0
1
1
1
Test Mode Register 000001
RT BIT Word Register (RD)11110
RT Status Word Register (RD)01110
Non-Enhanced BC Frame Time / Enhanced BC
Initial Instruction Pointer / RT Last Command /
MT Trigger Word Register (RD/WR)
10110
BC Time Remaining to Next Message Register
(RD)
00110
BC Frame Time Remaining Register (RD)11010
RT / Monitor Data Stack Address Register (RD)01010
Configuration Register #5 (RD/WR)10010
Configuration Register #4 (RD/WR)00010
Configuration Register #3 (RD/WR)11100
Interrupt Status Register #1 (RD)01100
Time Tag Register (RD/WR)10100
BC Control Word /
RT Subaddress Control Word Register (RD/WR)
00100
Non-Enhanced BC/RT Command Stack Pointer /
Enhanced BC Instruction List Pointer Register
(RD)
11000
Start/Reset Register (WR)11000
Configuration Register #2 (RD/WR)01000
Configuration Register #1 (RD/WR)10000
Interrupt Mask Register #1 (RD/WR)00000
A0A1A2A3A4
REGISTER
DESCRIPTION/ACCESSIBILITY
ADDRESS LINES
TABLE 2. ADDRESS MAPPING
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TABLE 3. INTERRUPT MASK REGISTER #1
(READ/WRITE 00H)
BIT DESCRIPTION
15(MSB) RESERVED
14 RAM PARITY ERROR
13 BC/RT TRANSMITTER TIMEOUT
12 BC/RT COMMAND STACK ROLLOVER
11 MT COMMAND STACK ROLLOVER
10 MT DATA STACK ROLLOVER
9 HANDSHAKE FAIL
8 BC RETRY
7 RT ADDRESS PARITY ERROR
6 TIME TAG ROLLOVER
5 RT CIRCULAR BUFFER ROLLOVER
4 BC CONTROL WORD/RT SUBADDRESS CONTROL WORD EOM
3 BC END OF FRAME
2 FORMAT ERROR
1 BC STATUS SET/RT MODE CODE/MT PATTERN TRIGGER
0(LSB) END OF MESSAGE
TABLE 4. CONFIGURATION REGISTER #1
(READ/WRITE 01H)
BIT BC FUNCTION (Bits
11-0 Enhanced Mode Only)
RT WITHOUT ALTERNATE
STATUS
RT WITH ALTERNATE
STATUS (Enhanced Only)
MONITOR FUNCTION
(Enhanced mode only bits 12-0)
15 (MSB) RT/BC-MT (logic 0) (logic 1) (logic 1) (logic 0)
14 MT/BC-RT (logic 0) (logic 0) (logic 0) (logic 1)
13 CURRENT AREA B/A CURRENT AREA B/A CURRENT AREA B/A CURRENT AREA B/A
12 MESSAGE STOP-ON-ERROR MESSAGE MONITOR ENABLED
(MMT)
MESSAGE MONITOR
ENABLED
MESSAGE MONITOR
ENABLED
11 FRAME STOP-ON-ERROR S10 TRIGGER WORD ENABLED
10 STATUS SET
STOP-ON-MESSAGE
BUSY S09 START-ON-TRIGGER
9 STATUS SET
STOP-ON-FRAME
SERVICE REQUEST S08 STOP-ON-TRIGGER
8FRAME AUTO-REPEAT SSFLAG S07 NOT USED
7 EXTERNAL TRIGGER
ENABLED
RTFLAG (Enhanced Mode Only) S06 EXTERNAL TRIGGER
ENABLED
6 INTERNAL TRIGGER ENABLED NOT USED S05 NOT USED
5 INTERMESSAGE GAP TIMER
ENABLED
NOT USED S04 NOT USED
4 RETRY ENABLED NOT USED S03 NOT USED
3 DOUBLED/SINGLE RETRY NOT USED S02 NOT USED
2 BC ENABLED (Read Only) NOT USED S01 MONITOR ENABLED
(Read Only)
1 BC FRAME IN PROGRESS
(Read Only)
NOT USED S00 MONITOR TRIGGERED
(Read Only)
0 (LSB) BC MESSAGE IN PROGRESS
(Read Only)
RT MESSAGE IN PROGRESS
(Enhanced mode only, Read Only)
RT MESSAGE IN
PROGRESS (Read Only)
MONITOR ACTIVE
(Read Only)
DYNAMIC BUS CONTROL
ACCEPTANCE
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SEPARATE BROADCAST DATA0(LSB)
ENHANCED RT MEMORY MANAGEMENT1
CLEAR SERVICE REQUEST2
LEVEL/PULSE INTERRUPT REQUEST3
INTERRUPT STATUS AUTO CLEAR4
LOAD TIME TAG ON SYNCHRONIZE5
CLEAR TIME TAG ON SYNCHRONIZE6
TIME TAG RESOLUTION 0 7
TIME TAG RESOLUTION 1 8
TIME TAG RESOLUTION 2 9
256-WORD BOUNDARY DISABLE10
OVERWRITE INVALID DATA11
RX SA DOUBLE BUFFER ENABLE12
BUSY LOOKUP TABLE ENABLE13
RAM PARITY ENABLE14
ENHANCED INTERRUPTS15(MSB)
DESCRIPTIONBIT
TABLE 5. CONFIGURATION REGISTER #2
(READ/WRITE 02H)
TABLE 6. START/RESET REGISTER
(WRITE 03H)
BIT DESCRIPTION
15(MSB) RESERVED
14 RESERVED
12
13
RESERVED
RESERVED
8
10
9
11
RESERVED
CLEAR SELF-TEST REGISTER
INITIATE RAM SELF-TEST
CLEAR RT HALT
7INITIATE PROTOCOL SELF-TEST
6 BC/MT STOP-ON-MESSAGE
5 BC STOP-ON-FRAME
4 TIME TAG TEST CLOCK
3 TIME TAG RESET
2 INTERRUPT RESET
1 BC/MT START
0(LSB) RESET
COMMAND STACK POINTER 00(LSB)
• •
• •
• •
COMMAND STACK POINTER 1515(MSB)
DESCRIPTIONBIT
TABLE 7. BC/RT COMMAND STACK POINTER REG.
(READ 03H)
RT-to-RT FORMAT0(LSB)
BROADCAST FORMAT1
MODE CODE FORMAT2
SUBSYSTEM FLAG BIT MASK
1553A/B SELECT3
EOM INTERRUPT ENABLE4
MASK BROADCAST BIT5
OFF-LINE SELF-TEST6
BUS CHANNEL A/B7
RETRY ENABLED8
RESERVED BITS MASK9
TERMINAL FLAG BIT MASK10
BUSY BIT MASK12
SERVICE REQUEST BIT MASK13
MESSAGE ERROR MASK14
TRANSMIT TIME TAG FOR SYNCHRONIZE MODE
COMMAND
15(MSB)
DESCRIPTIONBIT
11
TABLE 8. BC CONTROL WORD REGISTER
(READ/WRITE 04H)
BCST: MEMORY MANAGEMENT 0 (MM0)0(LSB)
BCST: MEMORY MANAGEMENT 1 (MM1)1
BCST: MEMORY MANAGEMENT 2 (MM2)2
TX: MEMORY MANAGEMENT 1 (MM1)
BCST: CIRC BUF INT3
BCST: EOM INT4
RX: MEMORY MANAGEMENT 0 (MM0)5
RX: MEMORY MANAGEMENT 1 (MM1)6
RX: MEMORY MANAGEMENT 2 (MM2)7
RX: CIRC BUF INT8
RX: EOM INT9
TX: MEMORY MANAGEMENT 0 (MM0)10
TX: MEMORY MANAGEMENT 2 (MM2)12
TX: CIRC BUF INT13
TX: EOM INT14
RX: DOUBLE BUFFER ENABLE15(MSB)
DESCRIPTIONBIT
11
TABLE 9. RT SUBADDRESS CONTROL WORD
(READ/WRITE 04H)
TIME TAG 00(LSB)
• •
• •
• •
TIME TAG 1515(MSB)
DESCRIPTIONBIT
TABLE 10. TIME TAG REGISTER
(READ/WRITE 05H)
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END OF MESSAGE0(LSB)
BC STATUS SET / RT MODE CODE /
MT PATTERN TRIGGER
1
FORMAT ERROR
2
MT COMMAND STACK ROLLOVER
BC END OF FRAME3
BC CONTROL WORD/RT SUBADDRESS CONTROL WORD
EOM
4
RT CIRCULAR BUFFER ROLLOVER5
TIME TAG ROLLOVER
6
RT ADDRESS PARITY ERROR7
BC RETRY8
HANDSHAKE FAIL
9
MT DATA STACK ROLLOVER10
BC/RT COMMAND STACK ROLLOVER12
TRANSMITTER TIMEOUT13
RAM PARITY ERROR
14
MASTER INTERRUPT15(MSB)
DESCRIPTIONBIT
11
TABLE 11. INTERRUPT STATUS REGISTER #1
(READ 06H)
ENHANCED MODE CODE HANDLING0(LSB)
1553A MODE CODES ENABLE1
RTFAIL / RTFLAG WRAP ENABLE2
MT COMMAND STACK SIZE 0
BUSY RX TRANSFER DISABLE3
ILLEGAL RX TRANSFER DISABLE4
ALTERNATE STATUS WORD ENABLE5
OVERRIDE MODE T/R ERROR6
ILLEGALIZATION DISABLED7
MT DATA STACK SIZE 08
MT DATA STACK SIZE 19
MT DATA STACK SIZE 210
MT COMMAND STACK SIZE 112
BC/RT COMMAND STACK SIZE 013
BC/RT COMMAND STACK SIZE 114
ENHANCED MODE ENABLE15(MSB)
DESCRIPTIONBIT
11
TABLE 12. CONFIGURATION REGISTER #3
(READ/WRITE 07H)
RT ADDRESS PARITY0(LSB)
RT ADDRESS 01
RT ADDRESS 12
EXPANDED CROSSING ENABLED
RT ADDRESS 23
RT ADDRESS 34
RT ADDRESS 45
RT ADDRESS LATCH/TRANSPARENT 6
BROADCAST DISABLED7
GAP CHECK ENABLED8
RESPONSE TIMEOUT SELECT 09
RESPONSE TIMEOUT SELECT 110
EXTERNAL TX INHIBIT B12
EXTERNAL TX INHIBIT A13
SINGLE-ENDED SELECT14
12 / 16 MHZ CLOCK SELECT 15(MSB)
DESCRIPTIONBIT
11
TABLE 14. CONFIGURATION REGISTER #5
(READ/WRITE 09H)
RT / MONITOR DATA STACK ADDRESS 00(LSB)
• •
• •
• •
RT / MONITOR DATA STACK ADDRESS 1515(MSB)
DESCRIPTIONBIT
TABLE 15. RT / MONITOR DATA STACK ADDRESS
REGISTER
(READ/WRITE 0AH)
TEST MODE 00(LSB)
TEST MODE 11
TEST MODE 22
BROADCAST MASK ENA/XOR
LATCH RT ADDRESS WITH CONFIG #53
MT TAG GAP OPTION4
VALID BUSY/NO DATA5
VALID M.E./NO DATA6
2ND RETRY ALT/SAME BUS7
1ST RETRY ALT/SAME BUS8
RETRY IF STATUS SET9
RETRY IF -A AND M.E.10
EXPANDED BC CONTROL WORD ENABLE12
MODE COMMAND OVERRIDE BUSY13
INHIBIT BIT WORD IF BUSY14
EXTERNAL BIT WORD ENABLE15(MSB)
DESCRIPTIONBIT
11
TABLE 13. CONFIGURATION REGISTER #4
(READ/WRITE 08H)
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BC FRAME TIME REMAINING 00(LSB)
• •
• •
• •
BC FRAME TIME REMAINING 1515(MSB)
DESCRIPTIONBIT
TABLE 16. BC FRAME TIME REMAINING REGISTER
(READ/WRITE 0BH)
Note: resolution = 100 µs per LSB
BC MESSAGE TIME REMAINING 00(LSB)
• •
• •
• •
BC MESSAGE TIME REMAINING 1515(MSB)
DESCRIPTIONBIT
TABLE 17. BC MESSAGE TIME REMAINING
REGISTER
(READ/WRITE 0CH)
Note: resolution = 1 µs per LSB
BIT 00(LSB)
• •
• •
• •
BIT 1515(MSB)
DESCRIPTIONBIT
TABLE 18. BC FRAME TIME / RT LAST COMMAND /
MT TRIGGER REGISTER (READ/WRITE 0DH)
TABLE 19. RT STATUS WORD REGISTER
(READ/WRITE 0EH)
11
BIT DESCRIPTION
15(MSB) LOGIC “0”
12 LOGIC “0”
14 LOGIC “0”
13 LOGIC “0”
10 MESSAGE ERROR
9 INSTRUMENTATION
8 SERVICE REQUEST
7 RESERVED
6 RESERVED
5 RESERVED
4 BROADCAST COMMAND RECEIVED
3 BUSY
LOGIC “0”
2 SSFLAG
1 DYNAMIC BUS CONTROL ACCEPT
0(LSB) TERMINAL FLAG
COMMAND WORD CONTENTS ERROR0(LSB)
RT-to-RT 2ND COMMAND WORD ERROR1
RT-to-RT NO RESPONSE ERROR2
TRANSMITTER SHUTDOWN B
RT-to-RT GAP / SYNC / ADDRESS ERROR3
PARITY / MANCHESTER ERROR RECEIVED4
INCORRECT SYNC RECEIVED5
LOW WORD COUNT6
HIGH WORD COUNT7
BIT TEST FAIL8
TERMINAL FLAG INHIBITED9
TRANSMITTER SHUTDOWN A10
HANDSHAKE FAILURE12
LOOP TEST FAILURE A13
LOOP TEST FAILURE B14
TRANSMITTER TIMEOUT
15(MSB)
DESCRIPTIONBIT
11
TABLE 20. RT BIT WORD REGISTER
(READ 0FH)
CLOCK SELECT 00(LSB)
CLOCK SELECT 11
64-WORD REGISTER SPACE2
GLOBAL CIRCULAR BUFFER SIZE 2
RESERVED3
ENHANCED MESSAGE MONITOR4
RT ADDRESS SOURCE5
INTERRUPT STATUS QUEUE ENABLE6
DISABLE VALID MESSAGES TO INTERRUPT STATUS
QUEUE
7
DISABLE INVALID MESSAGES TO INTERRUPT STATUS
QUEUE
8
GLOBAL CIRCULAR BUFFER SIZE 09
GLOBAL CIRCULAR BUFFER SIZE 110
GLOBAL CIRCULAR BUFFER ENABLE12
COMMAND STACK POINTER INCREMENT ON EOM
(RT, MT)
13
ENHANCED CPU ACCESS14
ENHANCED BUS CONTROLLER
15(MSB)
DESCRIPTIONBIT
11
TABLE 21. CONFIGURATION REGISTER #6
(READ/WRITE 18H)
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MODE CODE RESET / INCMD SELECT
0(LSB)
ENHANCED BC WATCHDOG TIMER ENABLED
1
ENHANCED TIMETAG SYNCHRONIZE
2
MEMORY MANAGEMENT BASE ADDRESS 11
1553B RESPONSE TIME3
RT HALT ENABLE
4
RESERVED5
RESERVED6
RESERVED7
RESERVED8
RESERVED9
MEMORY MANAGEMENT BASE ADDRESS 1010
MEMORY MANAGEMENT BASE ADDRESS 1212
MEMORY MANAGEMENT BASE ADDRESS 1313
MEMORY MANAGEMENT BASE ADDRESS 1414
MEMORY MANAGEMENT BASE ADDRESS 15
15(MSB)
DESCRIPTIONBIT
11
TABLE 22. CONFIGURATION REGISTER #7
(READ/WRITE 19H)
LESS THAN FLAG / GENERAL PURPOSE FLAG 10(LSB)
EQUAL FLAG / GENERAL PURPOSE FLAG 11
GENERAL PURPOSE FLAG 22
MESSAGE STATUS SET
GENERAL PURPOSE FLAG 33
GENERAL PURPOSE FLAG 44
GENERAL PURPOSE FLAG 55
GENERAL PURPOSE FLAG 66
GENERAL PURPOSE FLAG 77
NO RESPONSE8
FORMAT ERROR9
GOOD BLOCK TRANSFER10
BAD MESSAGE12
RETRY 013
RETRY 114
LOGIC “1”15(MSB)
DESCRIPTIONBIT
11
TABLE 23. BC CONDITION REGISTER
(READ 1BH)
SET GENERAL PURPOSE FLAG 00(LSB)
SET GENERAL PURPOSE FLAG 11
SET GENERAL PURPOSE FLAG 22
CLEAR GENERAL PURPOSE FLAG 3
SET GENERAL PURPOSE FLAG 33
SET GENERAL PURPOSE FLAG 44
SET GENERAL PURPOSE FLAG 55
SET GENERAL PURPOSE FLAG 66
SET GENERAL PURPOSE FLAG 77
CLEAR GENERAL PURPOSE FLAG 08
CLEAR GENERAL PURPOSE FLAG 19
CLEAR GENERAL PURPOSE FLAG 210
CLEAR GENERAL PURPOSE FLAG 412
CLEAR GENERAL PURPOSE FLAG 513
CLEAR GENERAL PURPOSE FLAG 614
CLEAR GENERAL PURPOSE FLAG 715(MSB)
DESCRIPTIONBIT
11
TABLE 24. BC GENERAL PURPOSE FLAG REGISTER
(WRITE 1BH)
LOGIC “0”0(LSB)
LOGIC “0”1
LOGIC “0”2
PROTOCOL BUILT-IN-TEST COMPLETE / IN-PROGRESS
LOGIC “0”3
LOGIC “0”4
RAM BUILT-IN TEST IN-PASSED5
RAM BUILT-IN TEST IN-PROGRESS6
RAM BUILT-IN TEST COMPLETE7
LOGIC “0”8
LOGIC “0”9
LOGIC “0”10
PROTOCOL BUILT-IN TEST ABORT12
PROTOCOL BUILT-IN TEST PASSED13
PROTOCOL BUILT-IN TEST IN-PROGRESS14
PROTOCOL BUILT-IN TEST COMPLETE15(MSB)
DESCRIPTIONBIT
11
TABLE 25. BIT TEST STATUS FLAG REGISTER
(READ 1CH)
Note: If the Mini-ACE Mark3 is not online in enhanced BC mode (i.e.,
processing instructions), the BC condition code register will always
return a value of 0000.
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NOT USED0(LSB)
BIT TEST COMPLETE1
ENHANCED BC IRQ02
CALL STACK POINTER REGISTER ERROR
ENHANCED BC IRQ13
ENHANCED BC IRQ24
ENHANCED BC IRQ35
MONITOR DATA STACK 50% ROLLOVER6
MONITOR COMMAND STACK 50% ROLLOVER7
RT CIRCULAR BUFFER 50% ROLLOVER8
RT COMMAND STACK 50% ROLLOVER9
BC TRAP OP CODE10
GENERAL PURPOSE QUEUE /
INTERRUPT STATUS QUEUE ROLLOVER
12
RT ILLEGAL COMMAND/MESSAGE MT MESSAGE
RECEIVED
13
BC OP CODE PARITY ERROR14
NOT USED15(MSB)
DESCRIPTIONBIT
11
TABLE 26. INTERRUPT MASK REGISTER #2
(READ/WRITE 1DH)
INTERRUPT CHAIN BIT0(LSB)
BIT TEST COMPLETE1
ENHANCED BC IRQ02
CALL STACK POINTER REGISTER ERROR
ENHANCED BC IRQ13
ENHANCED BC IRQ24
ENHANCED BC IRQ35
MONITOR DATA STACK 50% ROLLOVER6
MONITOR COMMAND STACK 50% ROLLOVER7
RT CIRCULAR BUFFER 50% ROLLOVER8
RT COMMAND STACK 50% ROLLOVER9
BC TRAP OP CODE10
GENERAL PURPOSE QUEUE /
INTERRUPT STATUS QUEUE ROLLOVER
12
RT ILLEGAL COMMAND/MESSAGE MT MESSAGE
RECEIVED
13
BC OP CODE PARITY ERROR14
MASTER INTERRUPT15(MSB)
DESCRIPTIONBIT
11
TABLE 27. INTERRUPT STATUS REGISTER #2
(READ 1EH)
QUEUE POINTER ADDRESS 0
0(LSB)
QUEUE POINTER ADDRESS 11
QUEUE POINTER ADDRESS 22
QUEUE POINTER BASE ADDRESS 11
QUEUE POINTER ADDRESS 33
QUEUE POINTER ADDRESS 44
QUEUE POINTER ADDRESS 55
QUEUE POINTER BASE ADDRESS 66
QUEUE POINTER BASE ADDRESS 77
QUEUE POINTER BASE ADDRESS 88
QUEUE POINTER BASE ADDRESS 99
QUEUE POINTER BASE ADDRESS 1010
QUEUE POINTER BASE ADDRESS 1212
QUEUE POINTER BASE ADDRESS 1313
QUEUE POINTER BASE ADDRESS 1414
QUEUE POINTER BASE ADDRESS 1515(MSB)
DESCRIPTIONBIT
11
TABLE 28. BC GENERAL PURPOSE QUEUE
POINTER REGISTER
RT, MT INTERRUPT STATUS QUEUE POINTER
REGISTER
(READ/WRITE1FH)
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COMMAND WORD CONTENTS ERROR0(LSB)
RT-to-RT 2ND COMMAND ERROR1
RT-to-RT GAP / SYNC / ADDRESS ERROR2
RT-to-RT FORMAT
INVALID WORD3
INCORRECT DATA SYNC4
WORD COUNT ERROR5
ILLEGAL COMMAND WORD6
DATA STACK ROLLOVER7
LOOP TEST FAIL8
NO RESPONSE TIMEOUT9
FORMAT ERROR 10
ERROR FLAG12
CHANNEL B/A13
SOM14
EOM
15(MSB)
DESCRIPTIONBIT
11
TABLE 30. RT MODE BLOCK STATUS WORD
GAP TIME (LSB)
MODE_CODE0(LSB)
CONTIGUOUS DATA / GAP1
CHANNEL B/A2
COMMAND / DATA3
ERROR4
BROADCAST5
THIS RT6
WORD FLAG7
• •
• •
• •
GAP TIME (MSB)15(MSB)
DESCRIPTIONBIT
8
TABLE 32. WORD MONITOR IDENTIFICATION WORD
DATA WORD COUNT / MODE CODE BIT 00(LSB)
DATA WORD COUNT / MODE CODE BIT 11
DATA WORD COUNT / MODE CODE BIT 22
REMOTE TERMINAL ADDRESS BIT 0
DATA WORD COUNT / MODE CODE BIT 33
DATA WORD COUNT / MODE CODE BIT 44
SUBADDRESS / MODE BIT 05
SUBADDRESS / MODE BIT 16
SUBADDRESS / MODE BIT 27
SUBADDRESS / MODE BIT 38
SUBADDRESS / MODE BIT 49
TRANSMIT / RECEIVE10
REMOTE TERMINAL ADDRESS BIT 1
12
REMOTE TERMINAL ADDRESS BIT 213
REMOTE TERMINAL ADDRESS BIT 314
REMOTE TERMINAL ADDRESS BIT 415(MSB)
DESCRIPTIONBIT
11
TABLE 31. 1553 COMMAND WORD
NOTE: TABLES 29 TO 35 ARE NOT REGISTERS, BUT THEY ARE WORDS STORED IN RAM.
INVALID WORD0(LSB)
INCORRECT SYNC TYPE1
WORD COUNT ERROR2
STATUS SET
WRONG STATUS ADDRESS / NO GAP3
GOOD DATA BLOCK TRANSFER4
RETRY COUNT 05
RETRY COUNT 16
MASKED STATUS SET7
LOOP TEST FAIL8
NO RESPONSE TIMEOUT9
FORMAT ERROR 10
ERROR FLAG12
CHANNEL B/A13
SOM14
EOM
15(MSB)
DESCRIPTIONBIT
11
TABLE 29. BC MODE BLOCK STATUS WORD
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COMMAND WORD CONTENTS ERROR0(LSB)
RT-to-RT 2ND COMMAND ERROR1
RT-to-RT GAP / SYNC / ADDRESS ERROR2
RT-to-RT TRANSFER
INVALID WORD3
INCORRECT SYNC4
WORD COUNT ERROR5
RESERVED6
DATA STACK ROLLOVER7
GOOD DATA BLOCK TRANSFER8
NO RESPONSE TIMEOUT9
FORMAT ERROR 10
ERROR FLAG12
CHANNEL B/A13
SOM14
EOM
15(MSB)
DESCRIPTIONBIT
11
TABLE 33. MESSAGE MONITOR MODE BLOCK
STATUS WORD
TERMINAL FLAG0(LSB)
DYNAMIC BUS CONTROL ACCEPTANCE1
SSFLAG2
REMOTE TERMINAL ADDRESS BIT 0
BUSY3
BROADCAST COMMAND RECEIVED4
RESERVED5
RESERVED6
RESERVED7
SERVICE REQUEST8
INSTRUMENTATION9
MESSAGE ERROR10
REMOTE TERMINAL ADDRESS BIT 112
REMOTE TERMINAL ADDRESS BIT 213
REMOTE TERMINAL ADDRESS BIT 314
REMOTE TERMINAL ADDRESS BIT 415(MSB)
DESCRIPTIONBIT
11
TABLE 35. 1553B STATUS WORD
NON-TEST REGISTER FUNCTION SUMMARY
A summary of the Mini-ACE Mark3 24 non-test registers fol-
lows.
INTERRUPT MASK REGISTERS #1 AND #2
Interrupt Mask Registers #1 and #2 are used to enable and dis-
able interrupt requests for various events and conditions.
NOTE: Please see Appendix “F” of the Enhanced Mini-ACE
Users Guide for important information applicable only to RT
MODE operation, enabling of the interrupt status queue and
use of specific non-message interrupts.
CONFIGURATION REGISTERS #1 AND #2
Configuration Registers #1 and #2 are used to select the Mini-
ACE Mark3’s mode of operation, and for software control of RT
Status Word bits, Active Memory Area, BC Stop-On-Error, RT
Memory Management mode selection, and control of the Time
Tag operation.
START/RESET REGISTER
The Start/Reset Register is used for "command" type functions
such as software reset, BC/MT Start, Interrupt reset, Time Tag
Reset, Time Tag Register Test, Initiate protocol self-test, Initiate
RAM self-test, Clear self-test register, and Clear RT Halt. The
Start/Reset Register also includes provisions for stopping the BC
in its auto-repeat mode, either at the end of the current message
or at the end of the current BC frame.
“1” FOR MESSAGE INTERRUPT EVENT
“0” FOR NON-MESSAGE INTERRUPT EVENT
0
END-OF-MESSAGE (EOM) RAM PARITY ERROR1
SUBADDRESS CONTROL
WORD EOM
PROTOCOL SELF-TEST
COMPLETE
2
RT CIRCULAR BUFFER 50%
ROLLOVER NOT USED
MODE CODE INTERRUPT RT ADDRESS PARITY
ERROR
3
FORMAT ERROR TIME TAG ROLLOVER4
HANDSHAKE FAIL NOT USED5
RT COMMAND (DESCRIPTOR)
STACK ROLLOVER NOT USED6
RT COMMAND (DESCRIPTOR)
STACK 50% ROLLOVER NOT USED7
MONITOR COMMAND
(DESCRIPTOR) STACK
ROLLOVER
NOT USED8
MONITOR COMMAND
(DESCRIPTOR) STACK 50%
ROLLOVER
NOT USED9
RT CIRCULAR BUFFER
ROLLOVER NOT USED10
MONITOR DATA STACK
ROLLOVER NOT USED12
MONITOR DATA STACK 50%
ROLLOVER NOT USED13
ILLEGAL COMMAND NOT USED14
TRANSMITTER TIMEOUT NOT USED15
DEFINITION FOR MESSAGE
INTERRUPT EVENT
DEFINITION FOR
NON-MESSAGE
INTERRUPT EVENT
BIT
11
TABLE 34. RT/MONITOR INTERRUPT STATUS WORD
(FOR INTERRUPT STATUS QUEUE)
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vidual receive (broadcast) subaddresses, and the alternate (fully
software programmable) RT Status Word. For MT mode, use of
the Enhanced Mode enables the Selective Message Monitor, the
combined RT/Selective Monitor modes, and the monitor trigger-
ing capability.
RT/MONITOR DATA STACK ADDRESS REGISTER
The RT/Monitor Data Stack Address Register provides a read/
writable indication of the last data word stored for RT or Monitor
modes.
BC FRAME TIME REMAINING REGISTER
The BC Frame Time Remaining Register provides a read-only
indication of the time remaining in the current BC frame. In the
enhanced BC mode, this timer may be used for minor or major
frame control, or as a watchdog timer for the BC message
sequence control processor. The resolution of this register is
100 µs/LSB.
BC TIME REMAINING TO NEXT MESSAGE REGISTER
The BC Time Remaining to Next Message Register provides a
read-only indication of the time remaining before the start of the
next message in a BC frame. In the enhanced BC mode, this
timer may also be used for the BC message sequence control
processor's Delay (DLY) instruction, or for minor or major frame
control. The resolution of this register is 1 µs/LSB.
BC FRAME TIME/ RT LAST COMMAND /MT TRIGGER
WORD REGISTER
In BC mode, this register is used to program the BC frame time,
for use in the frame auto-repeat mode. The resolution of this
register is 100 µs/LSB, with a range up to 6.55 seconds. In RT
mode, this register stores the current (or most previous) 1553
Command Word processed by the Mini-ACE Mark3 RT. In the
Word Monitor mode, this register is used to specify a 16-bit
Trigger (Command) Word. The Trigger Word may be used to start
or stop the monitor, or to generate interrupts.
BC INITIAL INSTRUCTION LIST POINTER REGISTER
The BC Initial Instruction List Pointer Register enables the host
to assign the starting address for the enhanced BC Instruction
List.
RT STATUS WORD REGISTER AND BIT WORD
REGISTERS
The RT Status Word Register and BIT Word Registers provide
read-only indications of the RT Status and BIT Words.
CONFIGURATION REGISTERS #6 AND #7:
Configuration Registers #6 and #7 are used to enable the Mini-
ACE Mark3 features that extend beyond the architecture of the
ACE/Mini-ACE (Plus). These include the Enhanced BC mode;
RT Global Circular Buffer (including buffer size); the RT/MT
Interrupt Status Queue, including valid/invalid message filtering;
enabling a software-assigned RT address; clock frequency
selection; a base address for the "non-data" portion of Mini-ACE
BC/RT COMMAND STACK REGISTER
The BC/RT Command Stack Register allows the host CPU to
determine the pointer location for the current or most recent
message.
BC INSTRUCTION LIST POINTER REGISTER
The BC Instruction List Pointer Register may be read to deter-
mine the current location of the Instruction List Pointer for the
Enhanced BC mode.
BC CONTROL WORD/RT SUBADDRESS CONTROL
WORD REGISTER
In BC mode, the BC Control Word/RT Subaddress Control Word
Register allows host access to the current word or most recent
BC Control Word. The BC Control Word contains bits that select
the active bus and message format, enable off-line self-test,
masking of Status Word bits, enable retries and interrupts, and
specify MIL-STD-1553A or -1553B error handling. In RT mode,
this register allows host access to the current or most recent
Subaddress Control Word. The Subaddress Control Word is
used to select the memory management scheme and enable
interrupts for the current message.
TIME TAG REGISTER
The Time Tag Register maintains the value of a real-time clock.
The resolution of this register is programmable from among 2, 4,
8, 16, 32, and 64 µs/LSB. The Start-of-Message (SOM) and End-
of-Message (EOM) sequences in BC, RT, and Message Monitor
modes cause a write of the current value of the Time Tag
Register to the stack area of the RAM.
INTERRUPT STATUS REGISTERS #1 AND #2
Interrupt Status Registers #1 and #2 allow the host processor to
determine the cause of an interrupt request by means of one or
two read accesses. The interrupt events of the two Interrupt
Status Registers are mapped to correspond to the respective bit
positions in the two Interrupt Mask Registers. Interrupt Status
Register #2 contains an INTERRUPT CHAIN bit, used to indi-
cate an interrupt event from Interrupt Status Register #1.
CONFIGURATION REGISTERS #3, #4, AND #5
Configuration Registers #3, #4, and #5 are used to enable many
of the Mini-ACE Mark3’s advanced features that were imple-
mented by the prior generation products, the ACE and Mini-ACE
(Plus). For BC, RT, and MT modes, use of the Enhanced Mode
enables the various read-only bits in Configuration Register #1.
For BC mode, Enhanced Mode features include the expanded
BC Control Word and BC Block Status Word, additional Stop-On-
Error and Stop-On-Status Set functions, frame auto-repeat,
programmable intermessage gap times, automatic retries,
expanded Status Word Masking, and the capability to generate
interrupts following the completion of any selected message. For
RT mode, the Enhanced Mode features include the expanded
RT Block Status Word, combined RT/Selective Message Monitor
mode, automatic setting of the TERMINAL FLAG Status Word bit
following a loop test failure; the double buffering scheme for indi-
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BC GENERAL PURPOSE QUEUE POINTER
The BC General Purpose Queue Pointer provides a means for
initializing the pointer for the General Purpose Queue, for the
Enhanced BC mode. In addition, this register enables the host to
determine the current location of the General Purpose Queue
pointer, which is incremented internally by the Enhanced BC
message sequence control engine.
RT/MT INTERRUPT STATUS QUEUE POINTER
The RT/MT Interrupt Status Queue Pointer provides a means for
initializing the pointer for the Interrupt Status Queue, for RT, MT,
and RT/MT modes. In addition, this register enables the host to
determine the current location of the Interrupt Status Queue
pointer, which is incremented by the RT/MT message proces-
sor.
BUS CONTROLLER (BC) ARCHITECTURE
The BC functionality for the Mini-ACE Mark3 includes two sepa-
rate architectures: (1) the older, non-Enhanced Mode, which
provides complete compatibility with the previous ACE and Mini-
ACE (Plus) generation products; and (2) the newer, Enhanced
BC mode. The Enhanced BC mode offers several new powerful
architectural features. These include the incorporation of a
highly autonomous BC message sequence control engine,
which greatly serves to offload the operation of the host CPU.
FIGURE 2. BC MESSAGE SEQUENCE CONTROL
OP CODE
DATA BLOCK
MESSAGE
CONTROL/STATUS
PARAMETER
(POINTER)
BLOCK
BC INSTRUCTION
LIST
BC INSTRUCTION
LIST POINTER REGISTER
BC CONTROL
WORD
COMMAND WORD
(Rx Command for
RT-to-RT transfer)
DATA BLOCK POINTER
TIME-TO-NEXT MESSAGE
TIME TAG WORD
BLOCK STATUS WORD
LOOPBACK WORD
RT STATUS WORD
2nd (Tx) COMMAND WORD
(for RT-to-RT transfer)
2nd RT STATUS WORD
(for RT-to-RT transfer)
INITIALIZE BY REGISTER
0D (RD/WR); READ CURRENT
VALUE VIA REGISTER 03
(RD ONLY)
Mark3 memory; LSB filtering for the Synchronize (with data) time
tag operations; and enabling a watchdog timer for the Enhanced
BC message sequence control engine.
NOTE: Please see Appendix “F” of the Enhanced Mini-ACE
User’s Guide for important information applicable only to RT
MODE operation, enabling of the interrupt status queue and
use of specific non-message interrupts.
BC CONDITION CODE REGISTER
The BC Condition Code Register is used to enable the host pro-
cessor to read the current value of the Enhanced BC Message
Sequence Control Engine's condition flags.
BC GENERAL PURPOSE FLAG REGISTER
The BC General Purpose Flag Register allows the host proces-
sor to be able to set, clear, or toggle any of the Enhanced BC
Message Sequence Control Engine's General Purpose condition
flags.
BIT TEST STATUS REGISTER
The BIT Test Status Register is used to provide read-only access
to the status of the protocol and RAM built-in self-tests (BIT).
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The Enhanced BC's message sequence control engine provides
a high degree of flexibility for implementing major and minor
frame scheduling; capabilities for inserting asynchronous mes-
sages in the middle of a frame; to separate 1553 message data
from control/status data for the purpose of implementing double
buffering and performing bulk data transfers; for implementing
message retry schemes, including the capability for automatic
bus channel switchover for failed messages; and for reporting
various conditions to the host processor by means of four user-
defined interrupts and a general purpose queue.
In both the non-Enhanced and Enhanced BC modes, the Mini-
ACE Mark3 BC implements all MIL-STD-1553B message for-
mats. Message format is programmable on a message-by-mes-
sage basis by means of the BC Control Word and the T/R bit of
the Command Word for the respective message. The BC Control
Word allows 1553 message format, 1553A/B type RT, bus chan-
nel, self-test, and Status Word masking to be specified on an
individual message basis. In addition, automatic retries and/or
interrupt requests may be enabled or disabled for individual mes-
sages. The BC performs all error checking required by MIL-STD-
1553B. This includes validation of response time, sync type and
sync encoding, Manchester II encoding, parity, bit count, word
count, Status Word RT Address field, and various RT-to-RT
transfer errors. The Mini-ACE Mark3 BC response timeout value
is programmable with choices of 18, 22, 50, and 130 µs. The
longer response timeout values allow for operation over long
buses and/or the use of repeaters.
In its non-Enhanced Mode, the Mini-ACE Mark3 may be pro-
grammed to process BC frames of up to 512 messages with no
processor intervention. In the Enhanced BC mode, there is no
explicit limit to the number of messages that may be processed
in a frame. In both modes, it is possible to program for either
single frame or frame auto-repeat operation. In the auto-repeat
mode, the frame repetition rate may be controlled either inter-
nally, using a programmable BC frame timer, or from an external
trigger input.
ENHANCED BC MODE: MESSAGE SEQUENCE CONTROL
One of the major new architectural features of the Mini-ACE
Mark3 series is its advanced capability for BC message
sequence control. The Mini-ACE Mark3 supports highly autono-
mous BC operation, which greatly offloads the operation of the
host processor.
The operation of the Mini-ACE Mark3’s message sequence
control engine is illustrated in FIGURE 2. The BC message
sequence control involves an instruction list pointer register;
an instruction list which contains multiple 2-word entries; a
message control/status stack, which contains multiple 8-word
or 10-word descriptors; and data blocks for individual mes-
sages.
The initial value of the instruction list pointer register is initialized
by the host processor (via Register 0D), and is incremented by
the BC message sequence processor (host readable via Register
03). During operation, the message sequence control processor
fetches the operation referenced by the instruction list pointer
register from the instruction list.
Note that the pointer parameter referencing the first word of a
message's control/status block (the BC Control Word) must con-
tain an address value that is modulo 8. Also, note that if the
message is an RT-to-RT transfer, the pointer parameter must
contain an address value that is modulo 16.
OP CODES
The instruction list pointer register references a pair of words in
the BC instruction list: an op code word, followed by a parameter
word. The format of the op code word, which is illustrated in
FIGURE 3, includes a 5-bit op code field and a 5-bit condition
code field. The op code identifies the instruction to be executed
by the BC message sequence controller.
Most of the operations are conditional, with execution dependent
on the contents of the condition code field. Bits 3-0 of the condi-
tion code field identifies a particular condition. Bit 4 of the condi-
tion code field identifies the logic sense ("1" or "0") of the
selected condition code on which the conditional execution is
dependent. TABLE 36 lists all the op codes, along with their
respective mnemonic, code value, parameter, and description.
TABLE 37 defines all the condition codes.
FIGURE 3. BC OP CODE FORMAT
15 1011121314 56789 01234
Odd
Parity 00OpCode Field 11 0 Condition Code Field
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Eight of the condition codes (8 through F) are set or cleared as
the result of the most recent message. The other eight are
defined as "General Purpose" condition codes GP0 through
GP7. There are three mechanisms for programming the values
of the General Purpose Condition Code bits: (1) They may be
set, cleared, or toggled by the host processor, by means of the
BC GENERAL PURPOSE FLAG REGISTER; (2) they may be
set, cleared, or toggled by the BC message sequence control
processor, by means of the GP Flag Bits (FLG) instruction; and
(3) GP0 and GP1 only (but none of the others) may be set or
cleared by means of the BC message sequence control proces-
sor's Compare Frame Timer (CFT) or Compare Message Timer
(CMT) instructions.
The host processor also has read-only access to the BC condi-
tion codes by means of the BC CONDITION CODE
REGISTER.
Note that four (4) instructions are unconditional. These are
Compare to Frame Timer (CFT), Compare to Message Timer
(CMT), GP Flag Bits (FLG), and Execute and Flip (XQF). For
these instructions, the Condition Code Field is "don't care". That
is, these instructions are always executed, regardless of the
result of the condition code test.
All of the other instructions are conditional. That is, they will only be
executed if the condition code specified by the condition code field
in the op code word tests true. If the condition code field tests false,
the instruction list pointer will skip down to the next instruction.
As shown in TABLE 36, many of the operations include a single-
word parameter. For an XEQ (execute message) operation, the
parameter is a pointer to the start of the message’s Control /
Status block. For other operations, the parameter may be an
address, a time value, an interrupt pattern, a mechanism to set
or clear general purpose flag bits, or an immediate value. For
several op codes, the parameter is "don't care" (not used).
As described above, some of the op codes will cause the mes-
sage sequence control processor to execute messages. In this
case, the parameter references the first word of a message
Control/Status block. With the exception of RT-to-RT transfer
messages, all message status/control blocks are eight words
long: a block control word, time-to-next-message parameter,
data block pointer, command word, status word, loopback word,
block status word, and time tag word.
In the case of an RT-to-RT transfer message, the size of the
message control/status block increases to 16 words. However, in
this case, the last six words are not used; the ninth and tenth
words are for the second command word and second status
word.
The third word in the message control/status block is a pointer
that references the first word of the message's data word block.
Note that the data word block stores only data words, which are
to be either transmitted or received by the BC. By segregating
data words from command words, status words, and other con-
trol and "housekeeping" functions, this architecture enables the
use of convenient, usable data structures, such as circular buf-
fers and double buffers.
Other operations support program flow control; i.e., jump and call
capability. The call capability includes maintenance of a call
stack which supports a maximum of four (4) entries; there is also
a return instruction. In the case of a call stack overrun or under-
run, the BC will issue a CALL STACK POINTER REGISTER
ERROR interrupt, if enabled.
Other op codes may be used to delay for a specified time; start a
new BC frame; wait for an external trigger to start a new frame;
perform comparisons based on frame time and time-to-next mes-
sage; load the time tag or frame time registers; halt; and issue host
interrupts. In the case of host interrupts, the message control pro-
cessor passes a 4-bit user-defined interrupt vector to the host, by
means of the Mini-ACE Mark3's Interrupt Status Register.
The purpose of the FLG instruction is to enable the message
sequence controller to set, clear, or toggle the value(s) of any or
all of the eight general purpose condition flags.
The op code parity bit encompasses all sixteen bits of the op
code word. This bit must be programmed for odd parity. If the
message sequence control processor fetches an undefined op
code word, an op code word with even parity, or bits 9-5 of an op
code word do not have a binary pattern of 01010, the message
sequence control processor will immediately halt the BC's
operation. In addition, if enabled, a BC TRAP OP CODE interrupt
will be issued. Also, if enabled, a parity error will result in an OP
CODE PARITY ERROR interrupt. TABLE 37 describes the
Condition Codes.
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TABLE 36. BC OPERATIONS FOR MESSAGE SEQUENCE CONTROL
INSTRUCTION MNEMONIC OP CODE
(HEX) PARAMETER
CONDITIONAL
OR
UNCONDITIONAL
DESCRIPTION
Interrupt
Request
Execute
Message
IRQ
XEQ
0006
0001
Interrupt
Bit Pattern
in 4 LS bits
Message Control /
Status Block
Address
Conditional
Conditional
(See Note)
Generate an interrupt if the condition flag tests TRUE, otherwise
continue execution at the next OpCode in the instruction list.
The passed parameter (Interrupt Bit Pattern) specifies which of
the ENHANCED BC IRQ bit(s) (bits 5-2) will be set in Interrupt
Status Register #2. Only the four LSBs of the passed parameter
are used. A parameter where the four LSBs are logic "0" will
not generate an interrupt.
Executes the message at the specified Message Control/Status
Block Address if the condition flag tests TRUE, otherwise con-
tinue execution at the next OpCode in the instruction list.
Compare to
Frame Timer
Halt
Jump
CFT
HLT
JMP
000A
0007
0002
Delay Time Value
(Resolution
= 100µS / LSB)
Not Used
(Don’t Care)
Instruction List
Address
Unconditional
Conditional
Conditional
Compare Time Value to Frame Time Counter. The LT/GP0 and
EQ/GP1 flag bits are set or cleared based on the results of the
compare. If the value of the CFT's parameter is less than the
value of the frame time counter, then the LT/GP0 and NE/GP1
flags will be set, while the GT-EQ/GP0 and EQ/GP1 flags will
be cleared. If the value of the CFT's parameter is equal to the
value of the frame time counter, then the GT-EQ/GP0 and EQ/
GP1 flags will be set, while the LT/GP0 and NE/GP1 flags will
be cleared. If the value of the CFT's parameter is greater than
the current value of the frame time counter, then the GT-EQ/
GP0 and NE/GP1 flags will be set, while the LT/GP0 and EQ/
GP1 flags will be cleared.
Stop execution of the Message Sequence Control Program until
a new BC Start is issued by the host if the condition flag tests
TRUE, otherwise continue execution at the next OpCode in the
instruction list.
Jump to the OpCode specified in the Instruction List if the con-
dition flag tests TRUE, otherwise continue execution at the next
OpCode in the instruction list.
Compare to
Message
Timer
Delay
Subroutine
Call
CMT
DLY
CAL
000B
0008
0003
Delay Time Value
(Resolution
= 1µS / LSB)
Delay Time Value
(Resolution = 1µS
/ LSB)
Instruction List
Address
Unconditional
Conditional
Conditional
Compare Time Value to Message Time Counter. The LT/GP0 and
EQ/GP1 flag bits are set or cleared based on the results of the
compare. If the value of the CMT's parameter is less than the value
of the message time counter, then the LT/GP0 and NE/GP1 flags
will be set, while the GT-EQ/GP0 and EQ/GP1 flags will be cleared.
If the value of the CMT's parameter is equal to the value of the
message time counter, then the GT-EQ/GP0 and EQ/GP1 flags will
be set, while the LT/GP0 and NE/GP1 flags will be cleared. If the
value of the CMT's parameter is greater than the current value of
the message time counter, then the GT-EQ/GP0 and NE/GP1 flags
will be set, while the LT/GP0 and EQ/GP1 flags will be cleared.
Delay the time specified by the Time parameter before execut-
ing the next OpCode if the condition flag tests TRUE, otherwise
continue execution at the next OpCode without delay. The delay
generated will use the Time to Next Message Timer.
Jump to the OpCode specified by the Instruction List Address
and push the Address of the Next OpCode on the Call Stack if
the condition flag tests TRUE, otherwise continue execution at
the next OpCode in the instruction list. Note that the maximum
depth of the subroutine call stack is four.
Wait Until
Frame Timer
= 0
Subroutine
Return
WFT
RTN
0009
0004
Not Used
(Don’t Care)
Not Used
(Don’t Care)
Conditional
Conditional
Wait until Frame Time counter is equal to Zero before continu-
ing execution of the Message Sequence Control Program if the
condition flag tests TRUE, otherwise continue execution at the
next OpCode without delay.
Return to the OpCode popped off the Call Stack if the condition
flag tests TRUE, otherwise continue execution at the next
OpCode in the instruction list.
NOTE: While the XEQ (Execute Message) instruction is conditional, not all condition codes may be used to enable its use. The ALWAYS and NEVER condition codes
may be used. The eight general purpose flag bits, GP0 through GP7, may also be used. However, if GP0 through GP7 are used, it is imperative that the host processor
not modify the value of the specific general purpose flag bit that enabled a particular message while that message is being processed. Similarly, the LT, GT-EQ, EQ, and
NE flags, which the BC only updates by means of the CFT and CMT instructions, may also be used. However, these two flags are dual use. Therefore, if these are used, it
is imperative that the host processor not modify the value of the specific flag (GP0 or GP1) that enabled a particular message while that message is being processed. The
NORESP, FMT ERR, GD BLK XFER, MASKED STATUS SET, BAD MESSAGE, RETRY0, and RETRY1 condition codes are not available for use with the XEQ instruction
and should not be used to enable its execution.
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Push Block
Status Word
PBS 0011 Not Used
(Don't Care)
Conditional Push the Block Status Word for the most recent message on
the General Purpose Queue if the condition flag tests TRUE,
otherwise continue execution at the next OpCode in the
instruction list.
TABLE 36. BC OPERATIONS FOR MESSAGE SEQUENCE CONTROL (CONT.)
INSTRUCTION MNEMONIC OP CODE
(HEX) PARAMETER DESCRIPTION
Load Time Tag
Counter
LTT 000D Time Value.
Resolution (µs/
LSB) is defined
by bits 9, 8, and 7
of Configuration
Register #2.
Conditional Load Time Tag Counter with Time Value if the condition flag
tests TRUE, otherwise continue execution at the next
OpCode in the instruction list.
Load Frame
Timer
LFT 000E Time Value
(resolution =
100 µs/LSB)
Conditional Load Frame Timer Register with the Time Value parameter
if the condition flag tests TRUE, otherwise continue execu-
tion at the next OpCode in the instruction list.
Start Frame
Timer
SFT 000F Not Used
(Don't Care)
Conditional Start Frame Time Counter with Time Value in Time Frame
register if the condition flag tests TRUE, otherwise continue
execution at the next OpCode in the instruction list.
Push Time Tag
Register
PTT 0010 Not Used
(Don't Care)
Conditional Push the value of the Time Tag Register on the General
Purpose Queue if the condition flag tests TRUE, otherwise
continue execution at the next OpCode in the instruction list.
Push Immediate
Value
PSI 0012 Immediate Value Conditional Push Immediate data on the General Purpose Queue if the
condition flag tests TRUE, otherwise continue execution at
the next OpCode in the instruction list.
Push Indirect PSM 0013 Memory
Address
Conditional Push the data stored at the specified memory location on
the General Purpose Queue if the condition flag tests TRUE,
otherwise continue execution at the next OpCode in the
instruction list.
Wait for
External
Trigger
WTG 0014 Not Used
(Don't Care)
Conditional Wait for a logic "0"-to-logic "1" transition on the EXT_TRIG
input signal before proceeding to the next OpCode in the
instruction list if the condition flag tests TRUE, otherwise
continue execution at the next OpCode without delay.
Execute and
Flip
XQF 0015 Message
Control /
Status Block
Address
Unconditional Execute (unconditionally) the message referenced by the
Message Control/Status Block Address. Following the pro-
cessing of this message, if the condition flag tests TRUE,
the BC will toggle bit 4 in the Message Control/Status Block
Address, and store the new Message Block Address as the
updated value of the parameter following the XQF instruc-
tion code. As a result, the next time that this line in the
instruction list is executed, the Message Control/Status
Block at the updated address (old address XOR 0010h),
rather than the old address, will be processed. If the condi-
tion flag tests FALSE, the value of the Message Control/
Status Block Address parameter will not change.
CONDITIONAL
OR
UNCONDITIONAL
GP Flag Bits FLG 000C Used to set,
clear, or toggle
GP
(General
Purpose)
Flag bits
(See description)
Unconditional Used to set, toggle, or clear any or all of the eight general
purpose flags. The table below illustrates the use of the GP
Flag Bits instruction for the case of GP0 (General Purpose
Flag 0). Bits 1 and 9 of the parameter byte affect flag GP1,
bits 2 and 10 effect GP2, etc., according to the following
rules:
Bit 8
0
0
1
0
1
0
1
1
Bit 0 Effect on GP0
No Change
Set Flag
Clear Flag
Toggle Flag
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8
TABLE 37. BC CONDITION CODES
BIT
CODE
LT/GP0
EQ/GP1
RETRY0
RETRY1
RETRY0
RETRY1
D
E
GP2
GP3
GP4
GP5
GP6
GP7
NORESP
GD BLK
XFER
NAME
(BIT 4 = 0)
These two bits reflect the retry status of the most recent message. The number of times that the mes-
sage was retried is delineated by these two bits as shown below:
RETRY COUNT 1 RETRY COUNT 0 Number of
(bit 14) (bit 13) Message Retries
0 0 0
0 1 1
1 0 N/A
1 1 2
FUNCTIONAL DESCRIPTION
INVERSE
(BIT 4 = 1)
GT-EQ/
GP0
NE/GP1
0
ALWAYS
Less than or GP0 flag. This bit is set or cleared based on the results of the compare. If the value of the
CMT's parameter is less than the value of the message time counter, then the LT/GP0 and NE/GP1
flags will be set, while the GT-EQ/GP0 and EQ/GP1 flags will be cleared. If the value of the CMT's
parameter is equal to the value of the message time counter, then the GT-EQ/GP0 and EQ/GP1 flags
will be set, while the LT/GP0 and NE/GP1 flags will be cleared. If the value of the CMT's parameter is
greater than the current value of the message time counter, then the GT-EQ/GP0 and NE/GP1 flags
will be set, while the LT/GP0 and EQ/GP1 flags will be cleared. Also, General Purpose Flag 1 may be
also be set or cleared by a FLG operation.
NEVERF
GP2
GP3
GP4
GP5
GP6
GP7
1
RESP
Equal Flag. This bit is set or cleared after CFT or CMT operation. If the value of the CMT's parameter is
equal to the value of the message time counter, then the EQ/GP1 flag will be set and the NE/GP1 bit
will be cleared. If the value of the CMT's parameter is not equal to the value of the message time coun-
ter, then the NE/GP1 flag will be set and the EQ/GP1bit will be cleared. Also, General Purpose Flag 1
may be also be set or cleared by a FLG operation.
GD BLK
XFER
BAD
MESSAGE
GOOD
MESSAGE
The ALWAYS flag should be set (bit 4 = 0) to designate an instruction as unconditional. The NEVER bit
(bit 4 = 1) can be used to implement a NOP or "skip" instruction.
C BAD MESSAGE indicates either a format error, loop test fail, or no response error for the most recent
message. Note that a "Status Set" condition has no effect on the "BAD MESSAGE/GOOD MESSAGE"
condition code.
FMT ERR FMT ERR9 FMT ERR indicates that the received portion of the most recent message contained one or more viola-
tions of the 1553 message validation criteria (sync, encoding, parity, bit count, word count, etc.), or the
RT's status word received from a responding RT contained an incorrect RT address field.
MASKED
STATUS
BIT
MASKED
STATUS
BIT
B
General Purpose Flags may be set, cleared, or toggled by a FLG operation. The host processor can
set, clear, or toggle these flags in the same way as the FLG instruction by means of the BC GENERAL
PURPOSE FLAG REGISTER.
Indicates that one or both of the following conditions have occurred for the most recent message: (1) If
one (or more) of the Status Mask bits (14 through 9) in the BC Control Word is logic "0" and the corre-
sponding bit(s) is (are) set (logic "1") in the received RT Status Word. In the case of the RESERVED
BITS MASK (bit 9) set to logic "0," any or all of the 3 Reserved Status Word bits being set will result in
a MASKED STATUS SET condition; and/or (2) If BROADCAST MASK ENABLED/XOR (bit 11 of
Configuration Register #4) is logic "1" and the MASK BROADCAST bit of the message's BC Control
Word is logic "0" and the BROADCAST COMMAND RECEIVED bit in the received RT Status Word is
logic "1."
2
3
4
5
6
7
NORESP indicates that an RT has either not responded or has responded later than the BC No
Response Timeout time. The Mini-ACE Mark3's No Response Timeout Time is defined per
MIL-STD-1553B as the time from the mid-bit crossing of the parity bit of the last word transmitted by
the BC to the mid-sync crossing of the RT Status Word. The value of the No Response Timeout value
is programmable from among the nominal values 18.5, 22.5, 50.5, and 130 µs (±1 µs) by means of bits
10 and 9 of Configuration Register #5.
A For the most recent message, GD BLK XFER will be set to logic "1" following completion of a valid
(error-free) RT-to-BC transfer, RT-to-RT transfer, or transmit mode code with data message. This bit is
set to logic "0" following an invalid message. GOOD DATA BLOCK TRANSFER is always logic "0" fol-
lowing a BC-to-RT transfer, a mode code with data, or a mode code without data. The Loop Test has
no effect on GOOD DATA BLOCK TRANSFER. GOOD DATA BLOCK TRANSFER may be used to
determine if the transmitting portion of an RT-to-RT transfer was error free.
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BC MESSAGE SEQUENCE CONTROL
The Mini-ACE Mark3 BC message sequence control capability
enables a high degree of offloading of the host processor. This
includes using the various timing functions to enable autono-
mous structuring of major and minor frames. In addition, by
implementing conditional jumps and subroutine calls, the mes-
sage sequence control processor greatly simplifies the insertion
of asynchronous, or "out-of-band" messages.
EXECUTE AND FLIP OPERATION
The Mini-ACE Mark3 BC's XQF, or "Execute and Flip" operation,
provides some unique capabilities. Following execution of this
unconditional instruction, if the condition code tests TRUE, the
BC will modify the value of the current XQF instruction's pointer
parameter by toggling bit 4 of the pointer. That is, if the selected
condition flag tests true, the value of the parameter will be
updated to the value = old address XOR 0010h. As a result, the
next time that this line in the instruction list is executed, the
Message Control/Status Block at the updated address (old
address XOR 0010h) will be processed, rather than the one at
the old address. The operation of the XQF instruction is illus-
trated in FIGURE 4.
There are multiple ways of utilizing the "execute and flip" instruc-
tion. One is to facilitate the implementation of a double buffering
data scheme for individual messages. This allows the message
sequence control processor to "ping-pong" between a pair of
data buffers for a particular message. By doing so, the host pro-
cessor can access one of the two Data Word blocks, while the
BC reads or writes the alternate Data Word block.
A second application of the "execute and flip" capability is in
conjunction with message retries. This allows the BC to not only
switch buses when retrying a failed message, but to automati-
cally switch buses permanently for all future times that the same
message is to be processed. This not only provides a high
degree of autonomy from the host CPU, but saves BC band-
width, by eliminating the need for future attempts to process
messages on an RT's failed channel.
XQF
POINTER XX00h
(part of) BC INSTRUCTION LIST MESSAGE
CONTROL/STATUS
BLOCK 0
DATA BLOCK 0
XX00h
MESSAGE
CONTROL/STATUS
BLOCK 1
DATA BLOCK 1
POINTER
POINTER
FIGURE 4. EXECUTE and FLIP (XQF) OPERATION
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GENERAL PURPOSE QUEUE
The Mini-ACE Mark3 BC allows for the creation of a general
purpose queue. This data structure provides a means for the
message sequence processor to convey information to the BC
host. The BC op code repertoire provides mechanisms to push
various items on this queue. These include the contents of the
Time Tag Register, the Block Status Word for the most recent
message, an immediate data value, or the contents of a speci-
fied memory address.
FIGURE 5 illustrates the operation of the BC General Purpose
Queue. Note that the BC General Purpose Queue Pointer
Register will always point to the next address location (modulo
64); that is, the location following the last location written by the
BC message sequence control engine.
If enabled, a BC GENERAL PURPOSE QUEUE ROLLOVER
interrupt will be issued when the value of the queue pointer
address rolls over at a 64-word boundary. The rollover will always
occur at a modulo 64 address.
LAST LOCATION
BC GENERAL
PURPOSE QUEUE
(64 Locations)
BC GENERAL
PURPOSE QUEUE
POINTER
REGISTER
NEXT LOCATION
FIGURE 5. BC GENERAL PURPOSE QUEUE
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REMOTE TERMINAL (RT) ARCHITECTURE
The Mini-ACE Mark3's RT architecture builds upon that of the
ACE and Mini-ACE. The Mini-ACE Mark3 provides multiprotocol
support, with full compliance to all of the commonly used data bus
standards, including MIL-STD-1553A, MIL-STD-1553B Notice 2,
STANAG 3838, General Dynamics 16PP303, and McAir A3818,
A5232, and A5690. For the Mini-ACE Mark3 RT mode, there is
programmable flexibility enabling the RT to be configured to fulfill
any set of system requirements. This includes the capability to
meet the MIL-STD-1553A response time requirement of 2 to 5 µs,
and multiple options for mode code subaddresses, mode codes,
RT status word, and RT BIT word.
The Mini-ACE Mark3 RT protocol design implements all of the
MIL-STD-1553B message formats and dual redundant mode
codes. The design has passed validation testing for MIL-STD-
1553B compliance. The Mini-ACE Mark3 RT performs compre-
hensive error checking including word and format validation, and
checks for various RT-to-RT transfer errors. One of the main fea-
tures of the Mini-ACE Mark3 RT is its choice of memory manage-
ment options. These include single buffering by subaddress,
double buffering for individual receive subaddresses, circular
buffering by individual subaddresses, and global circular buffering
for multiple (or all) subaddresses.
Other features of the Mini-ACE Mark3 RT include a set of inter-
rupt conditions, a flexible status queue with filtering based on
valid and/or invalid messages, flexible command illegalization,
programmable busy by subaddress, multiple options on time tag-
ging, and an "auto-boot" feature which allows the RT to initialize
as an online RT with the busy bit set following power turn-on.
RT MEMORY ORGANIZATION
TABLE 38 illustrates a typical memory map for an Mini-ACE
Mark3 RT with 4K RAM. The two Stack Pointers reside in fixed
locations in the shared RAM address space: address 0100 (hex)
for the Area A Stack Pointer and address 0104 for the Area B
Stack Pointer. In addition to the Stack Pointer, there are several
other areas of the shared RAM address space that are desig-
nated as fixed locations (all shown in bold). These are for the
Area A and Area B lookup tables, the illegalization lookup table,
the busy lookup table, and the mode code data tables.
The RT lookup tables (reference TABLE 39) provide a mecha-
nism for allocating data blocks for individual transmit, receive, or
broadcast subaddresses. The RT lookup tables include subad-
dress control words as well as the individual data block pointers.
If command illegalization is used, address range 0300-03FF is
used for command illegalizing. The descriptor stack RAM area, as
well as the individual data blocks, may be located in any of the
non-fixed areas in the shared RAM address space.
Note that in TABLE 38, there is no area allocated for "Stack B".
This is shown for purpose of simplicity of illustration. Also, note
that in TABLE 38, the allocated area for the RT command stack
is 256 words. However, larger stack sizes are possible. That is,
the RT command stack size may be programmed for 256 words
(64 messages), 512, 1024, or 2048 words (512 messages) by
means of bits 14 and 13 of Configuration Register 3.
Data Block 1000FE0-0FFF
••
••
••
Data Block 60420-043F
Data Block 50400-041F
Command Illegalizing Table
0300-03FF
RESERVED
Data Block 1-40280-02FF
Data Block 00260-027F
(not used)0248-025F
Busy Bit Lookup Table
0240-0247
Lookup Table B
01C0-023F
Lookup Table A
0140-01BF
Mode Code Data
0110-013F
Mode Code Selective Interrupt Table
0108-010F
Global Circular Buffer B Pointer
Stack Pointer B
0105
0104
RESERVED0102-0103
Global Circular Buffer A Pointer
Stack Pointer A
0101
0100
Stack A0000-00FF
DESCRIPTION
ADDRESS
(HEX)
0106-0107
TABLE 38. TYPICAL RT MEMORY MAP (SHOWN
FOR 4K RAM)
Subaddress
Control Word
Lookup Table
(Optional)
SACW SA0
•
•
•
SACW SA31
0220
•
•
•
023F
01A0
•
•
•
01BF
Broadcast
Lookup Pointer
Table
(Optional)
Bcst SA0
•
•
•
Bcst SA31
0200
•
•
•
021F
0180
•
•
•
019F
Transmit
Lookup Pointer
Table
Tx SA0
•
•
•
Tx SA31
01E0
•
•
•
01FF
0160
•
•
•
017F
Receive
(/Broadcast)
Lookup Pointer
Table
Rx(/Bcst) SA0
•
•
•
Rx(/Bcst) SA31
01C0
•
•
•
01DF
0140
•
•
•
015F
COMMENTDESCRIPTIONAREA BAREA A
TABLE 39. RT LOOK-UP TABLES
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RT MEMORY MANAGEMENT
The Mini-ACE Mark3 provides a variety of RT memory manage-
ment capabilities. As with the ACE and Mini-ACE, the choice of
memory management scheme is fully programmable on a trans-
mit/receive/broadcast subaddress basis.
In compliance with MIL-STD-1553B Notice 2, received data from
broadcast messages may be optionally separated from non-
broadcast received data. For each transmit, receive or broadcast
subaddress, either a single-message data block, a double buff-
ered configuration (two alternating Data Word blocks), or a vari-
able-sized (128 to 8192 words) subaddress circular buffer may
be allocated for data storage. The memory management scheme
for individual subaddresses is designated by means of the sub-
address control word (reference TABLE 40).
For received data, there is also a global circular buffer mode. In
this configuration, the data words received from multiple (or all)
subaddresses are stored in a common circular buffer structure.
Like the subaddress circular buffer, the size of the global circular
buffer is programmable, with a range of 128 to 8192 data
words.
The double buffering feature provides a means for the host pro-
cessor to easily access the most recent, complete received block
of valid Data Words for any given subaddress. In addition to help-
ing ensure data sample consistency, the circular buffer options
provide a means for greatly reducing host processor overhead
for multi-message bulk data transfer applications.
End-of-message interrupts may be enabled either globally (fol-
lowing all messages), following error messages, on a transmit/
receive/broadcast subaddress or mode code basis, or when a
circular buffer reaches its midpoint (50% boundary) or lower
(100%) boundary. A pair of interrupt status registers allow the
host processor to determine the cause of all interrupts by means
of a single read operation.
Subaddress -
specific circular buffer
of specified size.
8192-Word
1
(for receive and / or broadcast subaddresses only)
Global Circular Buffer: The buffer size is specified by
Configuration Register #6, bits 11-9. The pointer to the global
circular buffer is stored at address 0101 (for Area A) or
address 0105 (for Area B)
1
1
1
1
0
1
1
4096-Word010 1
1024-Word000 1
512-Word110 0
256-Word010 0
128-Word100 0
For Receive or Broadcast:
Double Buffered
For Transmit: Single Message
Single Message
0
0
0
0
1
0
0
0
SUBADDRESS CONTROL WORD BITS
MM0
MEMORY MANAGEMENT SUBADDRESS
BUFFER SCHEME DESCRIPTION
MM1
DOUBLE-BUFFERED OR
GLOBAL CIRCULAR BUFFER
(bit 15) MM2
TABLE 40. RT SUBADDRESS CONTROL WORD - MEMORY MANAGEMENT OPTIONS
2048-Word100 1
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SINGLE BUFFERED MODE
The operation of the single buffered RT mode is illustrated in
FIGURE 6. In the single buffered mode, the respective lookup
table entry must be written by the host processor. Received data
words are written to, or transmitted data words are read from the
data word block with starting address referenced by the lookup
table pointer. In the single buffered mode, the current lookup
table pointer is not updated by the Mini-ACE Mark3 memory
management logic. Therefore, if a subsequent message is
received for the same subaddress, the same Data Word block
will be overwritten or overread.
SUBADDRESS DOUBLE BUFFERING MODE
The Mini-ACE Mark3 provides a double buffering mechanism for
received data, that may be selected on an individual subaddress
basis for any or all receive (and/or broadcast) subaddresses. This
is illustrated in FIGURE 7. It should be noted that the Subaddress
Double Buffering mode is applicable for receive data only, not for
transmit data. Double buffering of transmit messages may be
easily implemented by software techniques.
The purpose of the subaddress double buffering mode is to pro-
vide data sample consistency to the host processor. This is
accomplished by allocating two 32-word data word blocks for
each individual receive (and/or broadcast receive) subaddress. At
any given time, one of the blocks will be designated as the "active"
1553 block while the other will be considered as "inactive". The
data words for the next receive command to that subaddress will
be stored in the active block. Following receipt of a valid message,
the Mini-ACE Mark3 will automatically switch the active and inac-
tive blocks for that subaddress. As a result, the latest, valid, com-
plete data block is always accessible to the host processor.
CIRCULAR BUFFER MODE
The operation of the Mini-ACE Mark3's circular buffer RT mem-
ory management mode is illustrated in FIGURE 8. As in the
single buffered and double buffered modes, the individual lookup
table entries are initially loaded by the host processor. At the
start of each message, the lookup table entry is stored in the
third position of the respective message block descriptor in the
descriptor stack area of RAM. Receive or transmit data words
are transferred to (from) the circular buffer, starting at the loca-
tion referenced by the lookup table pointer.
In general, the location after the last data word written or read
(modulo the circular buffer size) during the message is written to
the respective lookup table location during the end-of-message
sequence. By so doing, data for the next message for the respec-
tive transmit, receive(/broadcast), or broadcast subaddress will
be accessed from the next lower contiguous block of locations in
the circular buffer.
For the case of a receive (or broadcast receive) message with a
data word error, there is an option such that the lookup table
pointer will only be updated following receipt of a valid message.
That is, the pointer will not be updated following receipt of a
message with an error in a data word. This allows failed mes-
sages in a bulk data transfer to be retried without disrupting the
circular buffer data structure, and without intervention by the
RT's host processor.
GLOBAL CIRCULAR BUFFER
Beyond the programmable choice of single buffer mode, double
buffer mode, or circular buffer mode, programmable on an indi-
vidual subaddress basis, the Mini-ACE Mark3 RT architecture
provides an additional option, a variable sized global circular
FIGURE 6. RT SINGLE BUFFERED MODE
DATA
BLOCKS
DATA BLOCK
DATA BLOCK
BLOCK STATUS WORD
TIME TAG WORD
DATA BLOCK POINTER
RECEIVED COMMAND
WORD
DESCRIPTOR
STACKS
LOOK-UP
TABLE ADDR
LOOK-UP TABLE
(DATA BLOCK ADDR)
15 13 0
CURRENT
AREA B/A
CONFIGURATION
REGISTER
STACK
POINTERS
(See note)
Note: Lookup table is not used for mode commands when enhanced mode codes are enabled.
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FIGURE 7. RT DOUBLE BUFFERED MODE
15 13 0
BLOCK STATUS WORD
TIME TAG WORD
DATA BLOCK POINTER
RECEIVED COMMAND
WORD
CONFIGURATION
REGISTER
STACK
POINTERS
DESCRIPTOR
STACK
CURRENT
AREA B/A
DATA
BLOCKS
DATA
BLOCK 1
DATA
BLOCK 0
X..X 0 YYYYY
X..X 1 YYYYY
RECEIVE DOUBLE
BUFFER ENABLE
SUBADDRESS
CONTROL WORD
MSB
DATA BLOCK POINTER
LOOK-UP
TABLES
FIGURE 8. RT CIRCULAR BUFFERED MODE
CIRCULAR
BUFFER
ROLLOVER
15 13 0
RECEIVED
(TRANSMITTED)
MESSAGE
DATA
(NEXT LOCATION)
128,
256
8192
WORDS
POINTER TO
CURRENT
DATA BLOCK
POINTER TO
NEXT DATA
BLOCK
LOOK-UP TABLE
ENTRY
CIRCULAR
DATA
BUFFER
LOOK-UP TABLES
LOOK-UP
TABLE
ADDRESS
BLOCK STATUS WORD
TIME TAG WORD
DATA BLOCK POINTER
RECEIVED COMMAND
WORD
CONFIGURATION
REGISTER
STACK
POINTERS
DESCRIPTOR
STACK
CURRENT
AREA B/A
1. TX/RS/BCST_SA look-up table entry is updated following valid receive (broadcast) message
or following completion of transmit message
Notes:
*
2. For the Global Circular Buffer Mode, the pointer is read from and re-written to Address 0101 (for Area A)
or Address 0105 (for Area B).
buffer. The Mini-ACE Mark3 RT allows for a mix of single buff-
ered, double buffered, and individually circular buffered subad-
dresses, along with the use of the global double buffer for any
arbitrary group of receive(/broadcast) or broadcast subad-
dresses.
In the global circular buffer mode, the data for multiple receive
subaddresses is stored in the same circular buffer data structure.
The size of the global circular buffer may be programmed for 128,
256, 512, 1024, 2048, 4096, or 8192 words, by means of bits 11,
10, and 9 of Configuration Register #6. As shown in TABLE 40,
individual subaddresses may be mapped to the global circular
buffer by means of their respective subaddress control words.
The pointer to the Global Circular Buffer will be stored in location
0101 (for Area A), or location 0105 (for Area B).
The global circular buffer option provides a highly efficient meth-
od for storing received message data. It allows for frequently
used subaddresses to be mapped to individual data blocks, while
also providing a method for asynchronously received messages
to infrequently used subaddresses to be logged to a common
area. Alternatively, the global circular buffer provides an efficient
means for storing the received data words for all subaddresses.
Under this method, all received data words are stored chrono-
logically, regardless of subaddress.
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RT DESCRIPTOR STACK
The descriptor stack provides a chronology of all messages pro-
cessed by the Mini-ACE Mark3 RT. Reference FIGURES 6, 7,
and 8. Similar to BC mode, there is a four-word block descriptor
in the Stack for each message processed. The four entries to
each block descriptor are the Block Status Word, Time Tag Word,
the pointer to the start of the message's data block, and the
16-bit received Command Word.
The RT Block Status Word includes indications of whether a
particular message is ongoing or has been completed, what bus
channel it was received on, indications of illegal commands, and
flags denoting various message error conditions. For the double
buffering, subaddress circular buffering, and global circular buff-
ering modes, the data block pointer may be used for locating the
data blocks for specific messages. Note that for mode code com-
mands, there is an option to store the transmitted or received
data word as the third word of the descriptor, in place of the data
block pointer.
The Time Tag Word provides a 16-bit indication of relative time
for individual messages. The resolution of the Mini-ACE Mark3's
time tag is programmable from among 2, 4, 8, 16, 32, or 64 µs/
LSB. There is also a provision for using an external clock input
for the time tag. If enabled, there is a time tag rollover interrupt,
which is issued when the value of the time tag rolls over from
FFFF(hex) to 0. Other time tag options include the capabilities to
clear the time tag register following receipt of a Synchronize
(without data) mode command and/or to set the time tag follow-
ing receipt of a Synchronize (with data) mode command. For the
latter, there is an added option to filter the "set" capability based
on the LSB of the received data word being equal to logic "0".
RT INTERRUPTS
The Mini-ACE Mark3 offers a great deal of flexibility in terms of
RT interrupt processing. By means of the Mini-ACE Mark3’s two
Interrupt Mask Registers, the RT may be programmed to issue
interrupt requests for the following events/conditions: End-of-
(every)Message, Message Error, Selected (transmit or receive)
Subaddress, 100% Circular Buffer Rollover, 50% Circular Buffer
Rollover, 100% Descriptor Stack Rollover, 50% Descriptor Stack
Rollover, Selected Mode Code, Transmitter Timeout, Illegal
Command, and Interrupt Status Queue Rollover.
Interrupts for 50% Rollovers of Stacks and Circular Buffers.
The Mini-ACE Mark3 RT and Monitor are capable of issuing host
interrupts when a subaddress circular buffer pointer or stack
pointer crosses its mid-point boundary. For RT circular buffers,
this is applicable for both transmit and receive subaddresses.
Reference FIGURE 9. There are four interrupt mask and inter-
rupt status register bits associated with the 50% rollover
function:
(1) RT circular buffer;
(2) RT command (descriptor) stack;
(3) Monitor command (descriptor) stack; and
(4) Monitor data stack.
The 50% rollover interrupt is beneficial for performing bulk data
transfers. For example, when using circular buffering for a par-
ticular receive subaddress, the 50% rollover interrupt will inform
the host processor when the circular buffer is half full. At that
time, the host may proceed to read the received data words in
the upper half of the buffer, while the Mini-ACE Mark3 RT writes
received data words to the lower half of the circular buffer. Later,
when the RT issues a 100% circular buffer rollover interrupt, the
host can proceed to read the received data from the lower half of
the buffer, while the Mini-ACE Mark3 RT continues to write
received data words to the upper half of the buffer.
Interrupt status queue. The Mini-ACE Mark3 RT, Monitor, and
combined RT/Monitor modes include the capability for generat-
ing an interrupt status queue. As illustrated in FIGURE 10, this
provides a chronological history of interrupt generating events
and conditions. In addition to the Interrupt Mask Register, the
Interrupt Status Queue provides additional filtering capability,
such that only valid messages and/or only invalid messages may
result in the creation of an entry to the Interrupt Status Queue.
Queue entries for invalid and/or valid messages may be disabled
by means of bits 8 and 7 of configuration register #6.
The interrupt status queue is 64 words deep, providing the capa-
bility to store entries for up to 32 messages. These events and
conditions include both message-related and non-message
related events. Note that the Interrupt Vector Queue Pointer
Register will always point to the next location (modulo 64) follow-
ing the last vector/pointer pair written by the Mini-ACE Mark3
RT.
The pointer to the Interrupt Status Queue is stored in the
INTERRUPT VECTOR QUEUE POINTER REGISTER (register
address 1F). This register must be initialized by the host, and is
subsequently incremented by the RT message processor. The
interrupt status queue is 64 words deep, providing the capability
to store entries for up to 32 messages.
The queue rolls over at addresses of modulo 64. The events that
result in queue entries include both message-related and non-
message-related events. Note that the Interrupt Vector Queue
Pointer Register will always point to the next location (modulo 64)
following the last vector/pointer pair written by the Mini-ACE
Mark3 RT, Monitor, or RT/Monitor.
Each event that causes an interrupt results in a two-word entry
to be written to the queue. The first word of the entry is the inter-
rupt vector. The vector indicates which interrupt event(s)/
condition(s) caused the interrupt.
The interrupt events are classified into two categories: message
interrupt events and non-message interrupt events. Message-
based interrupt events include End-of-Message, Selected mode
code, Format error, Subaddress control word interrupt, RT
Circular buffer Rollover, Handshake failure, RT Command stack
rollover, transmitter timeout, MT Data Stack rollover,
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FIGURE 10. RT (and MONITOR) INTERRUPT STATUS QUEUE
(shown for message Interrupt event)
INTERRUPT
VECTOR
DATA WORD
BLOCK
DESCRIPTOR
STACK
PARAMETER
(POINTER)
INTERRUPT STATUS QUEUE
(64 Locations)
INTERRUPT VECTOR
QUEUE POINTER
REGISTER (IF)
BLOCK STATUS WORD
TIME TAG
DATA BLOCK POINTER
RECEIVED COMMAND
NEXT
VECTOR
FIGURE 9. 50% and 100% ROLLOVER INTERRUPTS
DATA POINTER
CIRCULAR
BUFFER*
(128,256,...8192 WORDS)
LOOK-UP TABLE
RECEIVED
(TRANSMITTED)
MESSAGE DATA
BLOCK STATUS WORD
TIME TAG WORD
DATA BLOCK POINTER
RECEIVED COMMAND WORD
DESCRIPTOR STACK
50%
ROLLOVER
INTERRUPT
50%
The example shown is for an RT Subaddress Circular Buffer.
The 50% and 100% Rollover Interrupts are also applicable to
the RT Global Circular Buffer, RT Command Stack,
Monitor Command Stack, and Monitor Data Stack.
Note
100%
ROLLOVER
INTERRUPT
100%
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TABLE 41. ILLEGALIZATION TABLE MEMORY MAP
3FC
3BE
37D
3C2
381
33F
300
ADDRESS
Own Addr / Tx, SA 30. WC15-0
Own Addr / Rx, SA 31. MC15-0
Brdcst / Tx, SA 30. WC31-16
Own Addr / Tx, SA 1. WC15-0
Own Addr / Rx, SA 0. MC31-16
Brdcst / Rx, SA 31. MC31-16
Brdcst / Rx, SA 0. MC15-0
DESCRIPTION
3FD
3BF
37E
3C3
382
340
301
Own Addr / Tx, SA 30. WC31-16
Own Addr / Rx, SA 31. MC31-16
Brdcst / Tx, SA 31. MC15-0
Own Addr / Tx, SA 1. WC31-16
Own Addr / Rx, SA 1. WC15-0
Brdcst / Tx, SA 0. MC15-0
Brdcst / Rx, SA 0. MC31-16
3FE
3C0
37F
383
341
302
Own Addr / Tx, SA 31. MC15-0
Own Addr / Tx, SA 0. MC15-0
Brdcst / Tx, SA 31. MC31-16
Own Addr / Rx, SA 1. WC31-16
Brdcst / Tx, SA 0. MC31-16
Brdcst / Rx, SA 1. WC15-0
•
•
•
•
•
•
•
•
•
•
•
•
3FF
3C1
380
342
303
•
•
•
•
•
•
•
•
•
•
•
•
Own Addr / Tx, SA 31. MC31-16
Own Addr / Tx, SA 0. MC31-16
Own Addr / Rx, SA 0. MC15-0
Brdcst / Tx, SA 1. WC15-0
Brdcst / Rx, SA 1. WC31-16
MT Command Stack rollover, RT Command Stack 50% rollover,
MT Data Stack 50% rollover, MT Command Stack 50% rollover,
and RT Circular buffer 50% rollover. Non-message interrupt
events/conditions include time tag rollover, RT address parity
error, RAM parity error, and BIT completed.
Bit 0 of the interrupt vector (interrupt status) word indicates
whether the entry is for a message interrupt event (if bit 0 is logic
"1") or a non-message interrupt event (if bit 0 is logic "0"). It is
not possible for one entry on the queue to indicate both a mes-
sage interrupt and a non-message interrupt.
As illustrated in FIGURE 10, for a message interrupt event, the
parameter word is a pointer. The pointer will reference the first
word of the RT or MT command stack descriptor (i.e., the Block
Status Word).
For a RAM Parity Error non-message interrupt, the parameter
will be the RAM address where the parity check failed. For the
RT address Parity Error, Protocol Self-test Complete, and Time
Tag rollover non-message interrupts, the parameter is not used;
it will have a value of 0000.
If enabled, an INTERRUPT STATUS QUEUE ROLLOVER inter-
rupt will be issued when the value of the queue pointer address
rolls over at a 64-word address boundary.
NOTE: Please see Appendix “F” of the Enhanced Mini-ACE
User’s Guide for important information applicable only to RT
MODE operation, enabling of the interrupt status queue and
use of specific non-message interrupts.
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RT COMMAND ILLEGALIZATION
The Mini-ACE Mark3 provides an internal mechanism for RT
Command Word illegalizing. By means of a 256-word area in
shared RAM, the host processor may designate that any mes-
sage be illegalized, based on the command word T/R bit, subad-
dress, and word count/mode code fields. The Mini-ACE Mark3
illegalization scheme provides the maximum in flexibility, allow-
ing any subset of the 4096 possible combinations of broadcast/
own address, T/R bit, subaddress, and word count/mode code to
be illegalized.
The address map of the Mini-ACE Mark3's illegalizing table is
illustrated in TABLE 41.
BUSY BIT
The Mini-ACE Mark3 RT provides two different methods for set-
ting the Busy status word bit: (1) globally, by means of
Configuration Register #1; or (2) on a T/R-bit/subaddress basis,
by means of a RAM lookup table. If the host CPU asserts the
BUSY bit to logic “0” in Configuration Register #1, the Mini-ACE
Mark3 RT will respond to all non-broadcast commands with the
Busy bit set in its RT Status Word.
Alternatively, there is a Busy lookup table in the Mini-ACE Mark3
shared RAM. By means of this table, it is possible for the host
processor to set the busy bit for any selectable subset of the 128
combinations of broadcast/own address, T/R bit, and subad-
dress.
If the busy bit is set for a transmit command, the Mini-ACE Mark3
RT will respond with the busy bit set in the status word, but will
not transmit any data words. If the busy bit is set for a receive
command, the RT will also respond with the busy status bit set.
There are two programmable options regarding the reception of
data words for a non-mode code receive command for which the
RT is busy: (1) to transfer the received data words to shared
RAM; or (2) to not transfer the data words to shared RAM.
RT ADDRESS
The Mini-ACE Mark3 offers several different options for designat-
ing the Remote Terminal address. These include the following:
(1) hardwired, by means of the 5 RT ADDRESS inputs, and the
RT ADDRESS PARITY input; (2) by means of the RT ADDRESS
(and PARITY) inputs, but latched via hardware, on the rising
edge of the RT_AD_LAT input signal; (3) input by means of the
RT ADDRESS (and PARITY) inputs, but latched via host soft-
ware; and (4) software programmable, by means of an internal
register. In all four configurations, the RT address is readable by
the host processor.
RT BUILT-IN-TEST (BIT) WORD
The bit map for the Mini-ACE Mark3's internal RT Built-in-Test
(BIT) Word is indicated in TABLE 42.
COMMAND WORD CONTENTS ERROR0 (LSB)
RT-to-RT 2ND COMMAND WORD ERROR1
RT-to-RT NO RESPONSE ERROR2
TRANSMITTER SHUTDOWN B
RT-to-RT GAP / SYNC ADDRESS ERROR3
PARITY / MANCHESTER ERROR RECEIVED4
INCORRECT SYNC RECEIVED5
LOW WORD COUNT6
HIGH WORD COUNT7
BIT TEST FAILURE8
TERMINAL FLAG INHIBITED9
TRANSMITTER SHUTDOWN A10
HANDSHAKE FAILURE12
LOOP TEST FAILURE A13
LOOP TEST FAILURE B14
TRANSMITTER TIMEOUT15(MSB)
DESCRIPTIONBIT
11
TABLE 42. RT BIT WORD
RT AUTO-BOOT OPTION
If utilized, the RT pin-programmable auto-boot option allows the
Mini-ACE Mark3 RT to automatically initialize as an active
remote terminal with the Busy status word bit set to logic "1"
immediately following power turn-on. This is a useful feature for
MIL-STD-1760 applications, in which the RT is required to be
responding within 150 ms after power-up. This feature is avail-
able for versions of the Mini-ACE Mark3 with 4K words of RAM.
OTHER RT FEATURES
The Mini-ACE Mark3 includes options for the Terminal flag status
word bit to be set either under software control and/or automati-
cally following a failure of the loopback self-test. Other software
programmable RT options include software programmable RT
status and RT BIT words, automatic clearing of the Service
Request bit following receipt of a Transmit vector word mode
command, options regarding Data Word transfers for the Busy
and Message error (illegal) Status word bits, and options for the
handling of 1553A and reserved mode codes.
MONITOR ARCHITECTURE
The Mini-ACE Mark3 includes three monitor modes:
(1) A Word Monitor mode
(2) A selective message monitor mode
(3) A combined RT/message monitor mode
For new applications, it is recommended that the selective mes-
sage monitor mode be used, rather than the word monitor mode.
Besides providing monitor filtering based on RT address, T/R bit,
and subaddress, the message monitor eliminates the need to
determine the start and end of messages by software.
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WORD MONITOR MODE
In the Word Monitor Terminal mode, the Mini-ACE Mark3 moni-
tors both 1553 buses. After the software initialization and Monitor
Start sequences, the Mini-ACE Mark3 stores all Command,
Status, and Data Words received from both buses. For each
word received from either bus, a pair of words is stored to the
Mini-ACE Mark3's shared RAM. The first word is the word
received from the 1553 bus. The second word is the Monitor
Identification (ID), or "Tag" word. The ID word contains informa-
tion relating to bus channel, word validity, and inter-word time
gaps. The data and ID words are stored in a circular buffer in the
shared RAM address space.
WORD MONITOR MEMORY MAP
A typical word monitor memory map is illustrated in TABLE 43.
TABLE 43 assumes a 64K address space for the Mini-ACE
Mark3's monitor. The Active Area Stack pointer provides the
address where the first monitored word is stored. In the example,
it is assumed that the Active Area Stack Pointer for Area A (loca-
tion 0100) is initialized to 0000. The first received data word is
stored in location 0000, the ID word for the first word is stored in
location 0001, etc.
The current Monitor address is maintained by means of a coun-
ter register. This value may be read by the CPU by means of the
Data Stack Address Register. It is important to note that when
the counter reaches the Stack Pointer address of 0100 or 0104,
the initial pointer value stored in this shared RAM location will be
overwritten by the monitored data and ID Words. When the
internal counter reaches an address of FFFF (or 0FFF, for an
Mini-ACE Mark3 with 4K RAM), the counter rolls over to 0000.
WORD MONITOR TRIGGER
In the Word Monitor mode, there is a pattern recognition trigger
and a pattern recognition interrupt. The 16-bit compare word for
Third Received 1553 Word
•
•
•
Received 1553 Words and Identification Word
•
•
•
FFFF
Stack Pointer
(Fixed Location - gets overwritten)
0100
•
•
•
•
•
•
Third Identification Word005
Second Identification Word0003
Second Received 1553 Word0002
First Identification Word0001
First Received 1553 Word0000
FUNCTION
HEX
ADDRESS
0004
TABLE 43. TYPICAL WORD MONITOR MEMORY
MAP
both the trigger and the interrupt is stored in the Monitor Trigger
Word Register. The pattern recognition interrupt is enabled by
setting the MT Pattern Trigger bit in Interrupt Mask Register #1.
The pattern recognition trigger is enabled by setting the Trigger
Enable bit in Configuration Register #1 and selecting either the
Start-on-trigger or the Stop-on-trigger bit in Configuration
Register #1.
The Word Monitor may also be started by means of a low-to-high
transition on the EXT_TRIG input signal.
SELECTIVE MESSAGE MONITOR MODE
The Mini-ACE Mark3 Selective Message Monitor provides
monitoring of 1553 messages with filtering based on RT
address, T/R bit, and subaddress with no host processor inter-
vention. By autonomously distinguishing between 1553 com-
mand and status words, the Message Monitor determines when
messages begin and end, and stores the messages into RAM,
based on a programmable filter of RT address, T/R bit, and
subaddress.
The selective monitor may be configured as just a monitor, or as a
combined RT/Monitor. In the combined RT/Monitor mode, the
Mini-ACE Mark3 functions as an RT for one RT address (including
broadcast messages), and as a selective message monitor for the
other 30 RT addresses. The Mini-ACE Mark3 Message Monitor
contains two stacks, a command stack and a data stack, that are
independent from the RT command stack. The pointers for these
stacks are located at fixed locations in RAM.
MONITOR SELECTION FUNCTION
Following receipt of a valid command word in Selective Monitor
mode, the Mini-ACE Mark3 will reference the selective monitor
lookup table to determine if the particular command is enabled.
The address for this location in the table is determined by means
of an offset based on the RT Address, T/R bit, and Subaddress
bit 4 of the current command word, and concatenating it to the
monitor lookup table base address of 0280 (hex). The bit location
within this word is determined by subaddress bits 3-0 of the cur-
rent command word.
If the specified bit in the lookup table is logic "0", the command
is not enabled, and the Mini-ACE Mark3 will ignore this com-
mand. If this bit is logic "1", the command is enabled and the
Mini-ACE Mark3 will create an entry in the monitor command
descriptor stack (based on the monitor command stack pointer),
and store the data and status words associated with the com-
mand into sequential locations in the monitor data stack. In addi-
tion, for an RT-to-RT transfer in which the receive command is
selected, the second command word (the transmit command) is
stored in the monitor data stack.
The address definition for the Selective Monitor Lookup Table is
illustrated in TABLE 44.
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SELECTIVE MESSAGE MONITOR MEMORY
ORGANIZATION
A typical memory map for the Mini-ACE Mark3 in the Selective
Message Monitor mode, assuming a 4K RAM space, is illustrat-
ed in TABLE 45. This mode of operation defines several fixed
locations in the RAM. These locations are allocated in a way in
which none of them overlap with the fixed RT locations. This
allows for the combined RT/Selective Message Monitor mode.
The fixed memory map consists of two Monitor Command Stack
Pointers (locations 102 and 106 hex), two Monitor Data Stack
Pointers (locations 103 and 107 hex), and a Selective Message
Monitor Lookup Table (locations 0280 through 02FF hex).
For this example, the Monitor Command Stack size is assumed
to be 1K words, and the Monitor Data Stack size is assumed to
be 2K words.
FIGURE 11 illustrates the Selective Message Monitor operation.
Upon receipt of a valid Command Word, the Mini-ACE Mark3 will
reference the Selective Monitor Lookup Table to determine if the
current command is enabled. If the current command is disabled,
the Mini-ACE Mark3 monitor will ignore (and not store) the cur-
rent message. If the command is enabled, the monitor will create
an entry in the Monitor Command Stack at the address location
referenced by the Monitor Command Stack Pointer, and an entry
in the monitor data stack starting at the location referenced by
the Monitor Data Stack Pointer.
The format of the information in the data stack depends on the
format of the message that was processed. For example, for a
BC-to-RT transfer (receive command), the monitor will store the
command word in the monitor command descriptor stack, with the
Monitor Command Stack Pointer B (fixed location)
Monitor Data Stack A0800-0FFF
Monitor Command Stack A0400-07FF
Not Used0300-03FF
Selective Monitor Lookup Table (fixed location)0280-02FF
Not Used0108-027F
Monitor Data Stack Pointer B (fixed location)0107
Not Used0104-0105
Monitor Data Stack Pointer A (fixed location)0103
Monitor Command Stack Pointer A (fixed location)0102
Not Used
0000-0101
DESCRIPTION
ADDRESS
(HEX)
0106
TABLE 45. TYPICAL SELECTIVE MESSAGE
MONITOR MEMORY MAP (shown for 4K RAM for
“Monitor only” mode)
data words and the receiving RT's status word stored in the moni-
tor data stack.
The size of the monitor command stack is programmable, with
choices of 256, 1K, 4K, or 16K words. The monitor data stack
size is programmable with choices of 512, 1K, 2K, 4K, 8K, 16K,
32K or 64K words.
MONITOR INTERRUPTS
Selective monitor interrupts may be issued for End-of-message
and for conditions relating to the monitor command stack pointer
and monitor data stack pointer. The latter, as shown in FIGURE
9, include Command Stack 50% Rollover, Command Stack
100% Rollover, Data Stack 50% Rollover, and Data Stack 100%
Rollover.
The 50% rollover interrupts may be used to inform the host proces-
sor when the command stack or data stack is half full. At that time,
the host may proceed to read the received messages in the upper
half of the respective stack, while the Mini-ACE Mark3 monitor
writes messages to the lower half of the stack. Later, when the
monitor issues a 100% stack rollover interrupt, the host can pro-
ceed to read the received data from the lower half of the stack,
while the Mini-ACE Mark3 monitor continues to write received data
words to the upper half of the stack.
INTERRUPT STATUS QUEUE
Like the Mini-ACE Mark3 RT, the Selective Monitor mode
includes the capability for generating an interrupt status queue.
As illustrated in FIGURE 10, this provides a chronological history
of interrupt generating events. Besides the two Interrupt Mask
Registers, the Interrupt Status Queue provides additional filter-
ing capability, such that only valid messages and/or only invalid
messages may result in entries to the Interrupt Status Queue.
The interrupt status queue is 64 words deep, providing the capa-
bility to store entries for up to 32 monitored messages.
SUBADDRESS 40(LSB)
TRANSMIT / RECEIVE1
RTAD_02
Logic “0”
RTAD_13
RTAD_24
RTAD_35
RTAD_46
Logic “1”7
Logic “0”8
Logic “1”9
Logic “0”10
Logic “0”12
Logic “0”13
Logic “0”14
Logic “0”15(MSB)
DESCRIPTIONBIT
11
TABLE 44. MONITOR SELECTION TABLE LOOKUP
ADDRESS
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15 13 0
BLOCK STATUS WORD
TIME TAG WORD
DATA BLOCK POINTER
RECEIVED COMMAND
WORD
CONFIGURATION
REGISTER #1
MONITOR COMMAND
STACK POINTERS
MONITOR
COMMAND STACKS
CURRENT
AREA B/A
MONITOR DATA
STACKS
MONITOR DATA
BLOCK #N + 1
MONITOR DATA
BLOCK #N
CURRENT
COMMAND WORD
MONITOR DATA
STACK POINTERS
IF THIS BIT IS "0" (NOT SELECTED)
NO WORDS ARE STORED IN EITHER
THE COMMAND STACK OR DATA STACK.
IN ADDITION, THE COMMAND AND DATA
STACK POINTERS WILL NOT BE UPDATED.
NOTE
SELECTIVE MONITOR
LOOKUP TABLES
SELECTIVE MONITOR
ENABLE
(SEE NOTE)
OFFSET BASED ON
RTA4-RTA0, T/R, SA4
FIGURE 11. SELECTIVE MESSAGE MONITOR MEMORY MANAGEMENT
MISCELLANEOUS
CLOCK INPUT
The Mini-ACE Mark3 decoder is capable of operating from a 10,
12, 16, or 20 MHz clock input. Depending on the configuration
of the specific model Mini-ACE Mark3 terminal, the selection of
the clock input frequency may be chosen by one of either two
methods. For all versions, the clock frequency may be specified
by means of the host processor writing to Configuration Register
#6. With the second method, which is applicable only for the
versions incorporating 4K (but not 64K) words of internal RAM,
the clock frequency may be specified by means of the input
signals that are otherwise used as the A15 and A14 address
lines.
ENCODER/DECODERS
For the selected clock frequency, there is internal logic to derive
the necessary clocks for the Manchester encoder and decoders.
For all clock frequencies, the decoders sample the receiver out-
puts on both edges of the input clock. By in effect doubling the
decoders' sampling frequency, this serves to widen the tolerance
to zero-crossing distortion, and reduce the bit error rate.
For interfacing to fiber optic transceivers (e.g., for MIL-STD-1773
applications), the decoders are capable of operating with single-
ended, rather than double-ended, input signals. The standard
transceiverless version (BU-64XXXX0) of the Mini-ACE Mark3 is
internally strapped for single-ended input signals. For applica-
tions involving the use of double-ended transceivers, it is sug-
gested that you contact the factory at DDC regarding a double-
ended transceiverless version of the Mini-ACE Mark3.
TIME TAG
The Mini-ACE Mark3 includes an internal read/writable Time Tag
Register. This register is a CPU read/writable 16-bit counter with
a programmable resolution of either 2, 4, 8, 16, 32, or 64 µs per
LSB. Another option allows software controlled incrementing of
the Time Tag Register. This supports self-test for the Time Tag
Register. For each message processed, the value of the Time
37
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Tag Register is loaded into the second location of the respective
descriptor stack entry ("TIME TAG WORD") for both the BC and
RT modes.
The functionality involving the Time Tag Register that's compati-
ble with ACE/Mini-ACE (Plus) includes: the capability to issue an
interrupt request and set a bit in the Interrupt Status Register
when the Time Tag Register rolls over FFFF to 0000; for RT
mode, the capability to automatically clear the Time Tag Register
following reception of a Synchronize (without data) mode com-
mand, or to load the Time Tag Register following a Synchronize
(with data) mode command.
Additional time tag features supported by the Mini-ACE Mark3
include the capability for the BC to transmit the contents of the
Time Tag Register as the data word for a Synchronize (with data)
mode command; the capability for the RT to "filter" the data word
for the Synchronize with data mode command, by only loading
the Time Tag Register if the LSB of the received data word is "0";
an instruction enabling the BC Message Sequence Control
engine to load the Time Tag Register with a specified value; and
an instruction enabling the BC Message Sequence Control
engine to write the value of the Time Tag Register to the General
Purpose Queue.
INTERRUPTS
The Mini-ACE Mark3 series terminals provide many program-
mable options for interrupt generation and handling. The inter-
rupt output pin (INT) has three software programmable modes of
operation: a pulse, a level output cleared under software control,
or a level output automatically cleared following a read of the
Interrupt Status Register (#1 or #2).
Individual interrupts are enabled by the two Interrupt Mask
Registers. The host processor may determine the cause of the
interrupt by reading the two Interrupt Status Registers, which
provide the current state of interrupt events and conditions. The
Interrupt Status Registers may be updated in two ways. In one
interrupt handling mode, a particular bit in Interrupt Status
Register #1 or #2 will be updated only if the event occurs and the
corresponding bit in Interrupt Mask Register #1 or #2 is enabled.
In the enhanced interrupt handling mode, a particular bit in one
of the Interrupt Status Registers will be updated if the event/
condition occurs regardless of the value of the corresponding
Interrupt Mask Register bit. In either case, the respective
Interrupt Mask Register (#1 or #2) bit is used to enable an inter-
rupt for a particular event/condition.
The Mini-ACE Mark3 supports all the interrupt events from ACE/
Mini-ACE (Plus), including RAM Parity Error, Transmitter Timeout,
BC/RT Command Stack Rollover, MT Command Stack and Data
Stack Rollover, Handshake Error, BC Retry, RT Address Parity
Error, Time Tag Rollover, RT Circular Buffer Rollover, BC Message,
RT Subaddress, BC End-of-Frame, Format Error, BC Status Set,
RT Mode Code, MT Trigger, and End-of-Message.
For the Mini-ACE Mark3's Enhanced BC mode, there are four
user-defined interrupt bits. The BC Message Sequence Control
Engine includes an instruction enabling it to issue these inter-
rupts at any time.
For RT and Monitor modes, the Mini-ACE Mark3 architecture
includes an Interrupt Status Queue. This provides a mechanism
for logging messages that result in interrupt requests. Entries to
the Interrupt Status Queue may be filtered such that only valid
and/or invalid messages will result in entries on the queue.
The Mini-ACE Mark3 incorporates additional interrupt conditions
beyond the ACE/Mini-ACE (Plus), based on the addition of
Interrupt Mask Register #2 and Interrupt Status Register #2. This
is accomplished by chaining the two Interrupt Status Registers
using the INTERRUPT CHAIN BIT (bit 0) in Interrupt Status
Register #2 to indicate that an interrupt has occurred in Interrupt
Status Register #1. Additional interrupts include "Self-Test
Completed", masking bits for the Enhanced BC Control Interrupts,
50% Rollover interrupts for RT Command Stack, RT Circular
Buffers, MT Command Stack, and MT Data Stack; BC Op Code
Parity Error, (RT) Illegal Command, (BC) General Purpose
Queue or (RT/MT) Interrupt Status Queue Rollover, Call Stack
Pointer Register Error, BC Trap Op Code, and the four User-
Defined interrupts for the Enhanced BC mode.
BUILT-IN TEST
A salient feature of the Mini-ACE Mark3 is its highly autonomous
self-test capability. This includes both protocol and RAM self-
tests. Either or both of these self-tests may be initiated by
command(s) from the host processor.
The protocol test consists of a comprehensive toggle test of the
terminal's logic. The test includes testing of all registers,
Manchester decoders, protocol logic, and memory management
logs. This test is completed in approximately 32,000 clock cycles.
That is, about 1.6 ms with a 20 MHz clock, 2.0 ms at 16 MHz,
2.7 ms at 12 MHz, and 3.2 ms at 10 MHz.
There is also a separate built-in test (BIT) for the Mini-ACE
Mark3's 4K X 16 or 64K X 16 shared RAM. This test consists of
writing and then reading/verifying the two walking patterns "data
= address" and "data = address inverted". This test takes 10
clock cycles per word. For a Mini-ACE Mark3 with 4K words of
RAM, this is about 2.0 ms with a 20 MHz clock, 2.6 ms at 16
MHz, 3.4 ms at 12 MHz, or 4.1 ms at 10 MHz. For an Mini-ACE
Mark3 with 64K words of RAM, this test takes about 32.8 ms with
a 20 MHz clock, 40.1 ms at 16 MHz, 54.6 ms at 12 MHz, or 65.6
ms at 10 MHz.
The Mini-ACE Mark3 built-in protocol test is performed automati-
cally at power-up. In addition, the protocol or RAM self-tests may
be initiated by a command from the host processor, via the
START/RESET REGISTER. For RT mode, this may include the
host processor invoking self-test following receipt of an Initiate
self-test mode command. The results of the self-test are host
38
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accessible by means of the BIT status register. For RT mode, the
result of the self-test may be communicated to the bus controller
via bit 8 of the RT BIT word ("0" = pass, "1" = fail).
Assuming that the protocol self-test passes, all of the register
and shared RAM locations will be restored to their state prior to
the self-test, with the exception of the 60 RAM address locations
0342-037D and the TIME TAG REGISTER. Note that for RT
mode, these locations map to the illegalization lookup table for
"broadcast transmit subaddresses 1 through 30" (non-mode
code subaddresses). Since MIL-STD-1553 does not define
these as valid command words, this section of the illegalization
lookup table is normally not used during RT operation. The TIME
TAG REGISTER will continue to increment during the self-test.
If there is a failure of the protocol self-test, it is possible to access
information about the first failed vector. This may be done by means
of the Mini-ACE Mark3's upper registers (register addresses 32
through 63). Through these registers, it is possible to determine the
self-test ROM address of the first failed vector, the expected
response data pattern (from the ROM), the register or memory
address, and the actual (incorrect) data value read from register or
memory. The on-chip self-test ROM is 4K X 24.
Note that the RAM self-test is destructive. That is, following the
RAM self-test, regardless of whether the test passes or fails, the
shared RAM is not restored to its state prior to this test. Following
a failed RAM self-test, the host may read the internal RAM to
determine which location(s) failed the walking pattern test.
RAM PARITY
The BC/RT/MT version of the Mini-ACE Mark3 is available with
options of 4K or 64K words of internal RAM. For the 64K option,
the RAM is 17 bits wide. The 64K X 17 internal RAM allows for
parity generation for RAM write accesses, and parity checking for
RAM read accesses. This includes host RAM accesses, as well as
accesses by the Mini-ACE Mark3’s internal logic. When the Mini-
ACE Mark3 detects a RAM parity error, it reports it to the host
processor by means of an interrupt and a register bit. Also, for the
RT and Selective Message Monitor modes, the RAM address
where a parity error was detected will be stored on the Interrupt
Status Queue (if enabled).
RELOCATABLE MEMORY MANAGEMENT LOCATIONS
In the Mini-ACE Mark3’s default configuration, there is a fixed
area of shared RAM addresses, 0000h-03FF, that is allocated for
storage of the BC's or RT's pointers, counters, tables, and other
"non-message" data structures. As a means of reducing the over-
all memory address space for using multiple Mini-ACE Mark3’s in
a given system (e.g., for use with the DMA interface configura-
tion), the Mini-ACE Mark3 allows this area of RAM to be relocated
by means of 6 configuration register bits. To provide backwards
compatibility to ACE and Mini-ACE, the default for this RAM area
is 0000h-03FFh.
HOST PROCESSOR INTERFACE
The Mini-ACE Mark3 supports a wide variety of processor inter-
face configurations. These include shared RAM and DMA con-
figurations, straightforward interfacing for 16-bit and 8-bit buses,
support for both non-multiplexed and multiplexed address/data
buses, non-zero wait mode for interfacing to a processor
address/data buses, and zero wait mode for interfacing (for
example) to microcontroller I/O ports. In addition, with respect to
the ACE/Mini-ACE, the Mini-ACE Mark3 provides two major
improvements: (1) reduced maximum host access time for
shared RAM mode; and (2) increased maximum DMA grant time
for the transparent/DMA mode.
The Mini-ACE Mark3's maximum host holdoff time (time prior to
the assertion of the READYD handshake signal) has been sig-
nificantly reduced. For ACE/Mini-ACE, this maximum holdoff
time is 17 internal word transfer cycles, resulting in an overall
holdoff time of approximately 4.6 µs, using a 16 MHz clock. By
comparison, using the Mini-ACE Mark3's ENHANCED CPU
ACCESS feature, this worst-case holdoff time is reduced signifi-
cantly, to a single internal transfer cycle. For example, when
operating the Mini-ACE Mark3 in its 16-bit buffered, non-zero
wait configuration with a 16 MHz clock input, this results in a
maximum overall host transfer cycle time of 632 ns for a read
cycle, or 570 ns for a write cycle.
In addition, when using the ACE or Mini-ACE in the transparent/
DMA configuration, the maximum request-to-grant time, which
occurs prior to an RT start-of-message sequence, is
4.0 µs with a 16 MHz clock, or 3.5 µs with a 12 MHz clock. For
the Mini-ACE Mark3 functioning as a MIL-STD-1553B RT, this
time has been increased to 8.5 µs at 10 MHz, 9 µs at 12 MHz,
10 µs at 16 MHz, and 10.5 µs at 20MHz. This provides greater
flexibility, particularly for systems in which a host has to arbitrate
among multiple DMA requestors.
By far, the most commonly used processor interface configura-
tion is the 16-bit buffered, non-zero wait mode. This configuration
may be used to interface between 16-bit or 32-bit microproces-
sors and an Mini-ACE Mark3. In this mode, only the Mini-ACE
Mark3's internal 4K or 64K words of internal RAM are used for
storing 1553 message data and associated "housekeeping"
functions. That is, in this configuration, the Mini-ACE Mark3 will
never attempt to access memory on the host bus.
FIGURE 12 illustrates a generic connection diagram between a
16-bit (or 32-bit) microprocessor and an Mini-ACE Mark3 for the
16-bit buffered configuration, while FIGURES 13 and 14, and asso-
ciated tables illustrate the processor read and write timing respec-
tively.
39
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HOST
CH. A
TX/RXA
TX/RXA
CH. B
TX/RXB
TX/RXB
RTAD4-RTAD0 RT
ADDRESS,
PARITY
RTADP
D15-D0
+3.3V
CLK IN
CLOCK
OSCILLATOR
N/C
N/C
POLARITY_SEL
(NOTE 2)
ZERO_WAIT
(NOTE 3)
ADDRESS
DECODER
SELECT
MEM/REG
RD/WR
STRBD
READYD
TAG_CLK
RD/WR
CPU STROBE
CPU ACKNOWLEDGE (NOTE 4)
RESET
+3.3 V
MSTCLR
SSFLAG/EXT_TRIG
INT
CPU INTERRUPT REQUEST
NOTES:
1. CPU ADDRESS LATCH SIGNAL PROVIDED BY PROCESSORS WITH MULTIPLEXED ADDRESS/DATA BUSES. FOR PROCESSORS WITH NON-MULTIPLEXED
ADDRESS AND DATA BUSES, ADDR_LAT SHOULD BE CONNECTED TO +3.3V.
2. IF POLARITY_SEL = "1", RD/WR IS HIGH TO READ, LOW TO WRITE. IF POLARITY_SEL = "0", RD/WR IS LOW TO READ, HIGH TO WRITE.
3. ZERO_WAIT SHOULD BE STRAPPED TO LOGIC "1" FOR NON-ZERO WAIT INTERFACE AND TO LOGIC "0" FOR ZERO WAIT INTERFACE.
4. CPU ACKNOWLEDGE PROCESSOR INPUT ONLY FOR NON-ZERO WAIT TYPE OF INTERFACE.
A15-A12
A11-A0
N/C
ADDR_LAT
TRANSPARENT/BUFFERED
CPU ADDRESS LATCH (NOTE 1)
+3.3V
16/8_BIT
TRIGGER_SEL
MSB/LSB
+3.3 V
Mini-ACE
Mark3
FIGURE 12. HOST PROCESSOR INTERFACE - 16-BIT BUFFERED CONFIGURATION
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CLOCK IN
VALID
t7
t3 t8
t11
t13 t15
VALID
t10
t4 t9 t12
t19
VALID
t16
t17
SELECT
(Note 2,7)
(Note 2)
(Note 3,4,7)
(Note 4,5)
STRBD
MEM/REG
RD/WR
IOEN
(Note 2,6)
(Note 6)
(Note 6)
(Note 7,8,9)
READYD
A15-A0
D15-D0
t5
t1
t2 t6 t14 t18
FIGURE 13. CPU READING RAM / REGISTER (16-BIT BUFFERED, NONZERO WAIT)
NOTES:
1. For the 16-bit buffered nonzero wait configuration, TRANSPARENT/BUFFERED must be connected to logic "0". ZERO_WAIT and DTREQ / 16/8
must be connected to logic "1". The inputs TRIGGER_SEL and MSB/LSB may be connected to either Vcc or ground.
2. SELECT and STRBD may be tied together. IOEN goes low on the first rising CLK edge when SELECT • STRBD is sampled low (satisfying t1)
and the Mark3’s protocol/memory management logic is not accessing the internal RAM. When this occurs, IOEN goes low, starting the transfer
cycle. After IOEN goes low, SELECT may be released high.
3. MEM/REG must be presented high for memory access, low for register access.
4. MEM/REG and RD/WR are buffered transparently until the first falling edge of CLK after IOEN goes low. After this CLK edge, MEM/REG and
RD/WR become latched internally.
5. The logic sense for RD/WR in the diagram assumes that POLARITY_SEL is connected to logic "1". If POLARITY_SEL is connected to logic "0",
RD/WR must be asserted low to read.
6. The timing for IOEN, READYD and D15-D0 assumes a 50 pf load. For loading above 50 pf, the validity of IOEN, READYD, and D15-D0 is
delayed by an additional 0.14 ns/pf typ, 0.28 ns/pf max.
7. The timing for A15-A0, MEM/REG and SELECT assumes that ADDR-LAT is connected to logic "1". Refer to Address Latch timing for additional
details.
8. The address bus A15-A0 is internally buffered transparently until the first rising edge of CLK after IOEN goes low. After this CLK edge, A15-A0
become latched internally.
9. Setup time given for use in worst case timing calculations. None of the Mark3’s input signals are required to be synchronized to the system
clock. When SELECT and STRBD do not meet the setup time of t1, but occur during the setup window of an internal flip-flop, an additional clock
cycle will be inserted between the falling clock edge that latches MEM/REG and RD/WR and the rising clock edge that latches the Address
(A15-A0). When this occurs, the delay from IOEN falling to READYD falling (t11) increases by one clock cycle and the address hold time (t10)
must be increased by one clock cycle.
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2, 6
2, 6
2, 6
2, 6
2, 6
2, 6
2, 6
2, 6
3, 4, 5, 7
3, 4, 5, 7
6
6
6
6
2
2, 6
7, 8
6, 9
6, 9
6, 9
3, 4, 5, 7
6
6
6, 9
7, 8, 9
3, 4, 5, 7
6
3, 4, 5, 7
3, 4, 5, 7
2, 6
2, 6
MAXTYP
MIN UNITS
MAX
TYP
MIN
DESCRIPTION
REF
7.2
155
820
970
138
635
4.6
6.0
35
27
62
45
61
44
40
0
40
0
40
∞
40
0
25
520
35
165150135
265250235
205187.5170
30
23
11
315300285
30
15
40
12
16
10
3.6
105
15
NOTES
2, 9
2, 6 117
µs7.2 (contended access, with ENHANCED CPU ACCESS = “0” @ 10 MHz)
ns150 (uncontended access @ 10 MHz)
ns815 (contended access, with ENHANCED CPU ACCESS = “1” @ 12 MHz)
ns965 (contended access, with ENHANCED CPU ACCESS = “1” @ 10 MHz)
ns133 (uncontended access @ 12 MHz)
ns630 (contended access, with ENHANCED CPU ACCESS = “1” s @ 16 MHz)
µs4.6 (contended access, with ENHANCED CPU ACCESS = “0” @ 16 MHz)
µs6.0 (contended access, with ENHANCED CPU ACCESS = “0” @ 12 MHz)
ns40 @ 10 MHz
t3
t4
ns32 @ 12 MHz
ns67 @ 10 MHz
ns50 @ 12 MHz
ns71 @ 10 MHz
ns54 @ 12 MHz
ns40CLOCK IN rising edge delay to output data validt19
ns0STRBD high hold time from READYD risingt18
ns40STRBD rising delay to output data tri-statet17
ns0Output Data hold time following STRBD rising edget16
ns30STRBD rising edge delay to IOEN rising edge and READYD rising edget15
ns∞READYD falling to STRBD rising release timet14
ns40CLOCK IN rising edge delay to READYD fallingt13
t12
ns0SELECT hold time following IOEN fallingt6
ns30 @ 16 MHz
ns515 (contended access, with ENHANCED CPU ACCESS = “1” @ 20 MHz)
ns30Address valid setup time prior to CLOCK IN rising edget9
ns165150135IOEN falling delay to READYD falling (@ 20 MHz)
ns265250235 @ 12 MHz
ns205187.5170 @ 16 MHz
ns30MEM/REG, RD/WR hold time following CLOCK IN falling edget8
ns33 @ 16 MHz
ns21Output Data valid prior to READYD falling (@ 20 MHz)
ns315300285 @ 10 MHz
ns30Address hold time following CLOCK IN rising edget10
t11
ns10MEM/REG, RD/WR setup time prior to CLOCK IN falling edget7
ns40CLOCK IN rising edge delay to IOEN falling edget5
ns17Time for Address to become valid following SELECT and STRBD low (@ 20MHz)
ns21 @ 16 MHz
ns15
Time for MEM/REG and RD/WR to become valid following SELECT and STRBD
low (@ 20 MHz)
µs3.6 (contended access, with ENHANCED CPU ACCESS = “0” @ 20 MHz)
ns100SELECT and STRBD low to IOEN low (uncontended access @ 20 MHz)
t2
ns10SELECT and STRBD low setup time prior to clock rising edget1
3.3V LOGIC
5V LOGIC
TABLE FOR FIGURE 13. CPU READING RAM OR REGISTERS
(SHOWN FOR 16-BIT, BUFFERED, NONZERO WAIT MODE)
ns112 (uncontended access @ 16 MHz)
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CLOCK IN
t1
t6
t7
t2
t3
t18
t16
VALID
t8 t9
t14
t15 t17
VALID
t12
t10
t4
t11
t5
VALID
t13
SELECT
(Note 2,7)
(Note 2)
(Note 3,4,7)
(Note 4,5)
STRBD
MEM/REG
RD/WR
IOEN
(Note 2,6)
(Note 6)
(Note 9,10)
(Note 7,8,9,10)
READYD
A15-A0
D15-D0
FIGURE 14. CPU WRITING RAM / REGISTER (16-BIT BUFFERED, NONZERO WAIT)
NOTES:
1. For the 16-bit buffered nonzero wait configuration TRANSPARENT/BUFFERED must be connected to logic "0", ZERO_WAIT and DTREG / 16/8
must be connected to logic "1". The inputs TRIGGER_SEL and MSB/LSB may be connected to either Vcc or ground.
2. SELECT and STRBD may be tied together. IOEN goes low on the first rising CLK edge when SELECT • STRBD is sampled low (satisfying t1)
and the Mark3’s protocol/memory management logic is not accessing the internal RAM. When this occurs, IOEN goes low, starting the transfer
cycle. After IOEN goes low, SELECT may be released high.
3. MEM/REG must be presented high for memory access, low for register access.
4. MEM/REG and RD/WR are buffered transparently until the first falling edge of CLK after IOEN goes low. After this CLK edge, MEM/REG and
RD/WR become latched internally.
5. The logic sense for RD/WR in the diagram assumes that POLARITY_SEL is connected to logic "1". If POLARITY_SEL is connected to logic "0",
RD/WR must be asserted high to write.
6. The timing for the IOEN and READYD outputs assume a 50 pf load. For loading above 50 pf, the validity of IOEN and READYD is delayed by an
additional 0.14 ns/pf typ, 0.28 ns/pf max.
7. The timing for A15-A0, MEM/REG, and SELECT assumes that ADDR-LAT is connected to logic "1". Refer to Address Latch timing for additional
details.
8. The address bus A15-A0 and data bus D15-D0 are internally buffered transparently until the first rising edge of CLK after IOEN goes low. After
this CLK edge, A15-A0 and D15-D0 become latched internally.
9. Setup time given for use in worst case timing calculations. None of the Mark3’s input signals are required to be synchronized to the system
clock. When SELECT and STRBD do not meet the setup time of t1, but occur during the setup time of an internal flip-flop, an additional clock
cycle may be inserted between the falling clock edge that latches MEM/REG and RD/WR and the rising clock edge that latches the address
(A15-A0) and data (D15-D0). When this occurs, the delay from IOEN falling to READYD falling (t14) increases by one clock cycle and the
address and data hold time (t12 and t13) must be increased by one clock.
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(uncontended access @ 16 MHz) 112 ns
TABLE FOR FIGURE 14. CPU WRITING RAM OR REGISTERS
(SHOWN FOR 16-BIT, BUFFERED, NONZERO WAIT MODE)
3.3V LOGIC5V LOGIC
@ 16 MHz
t1 SELECT and STRBD low setup time prior to clock rising edge 10 ns
50
t2 SELECT and STRBD low to IOEN low (uncontended access @ 20 MHz) 100 ns
ns
(contended access, with ENHANCED CPU ACCESS = “0” @ 20 MHz) 3.6 µs
Time for MEM/REG and RD/WR to become valid following SELECT and STRBD
low (@ 20 MHz) 15 ns
@ 16 MHz 21 ns
45
Time for Address to become valid following SELECT and STRBD low (@ 20MHz) 17 ns
Time for data to become valid following SELECT and STRBD low (@ 20 MHz) 37 ns
t7 SELECT hold time following IOEN falling 0 ns
@ 12 MHz
t10 Address valid setup time prior to CLOCK IN rising edge 30 ns
IOEN falling delay to READYD falling @ 20 MHz 85 100 115 ns
t12 Address valid hold time following CLOCK IN rising edge 30 ns
70
85 100 1156, 9
@ 16 MHz
ns
t8 MEM/REG, RD/WR setup time prior to CLOCK IN falling edge 10 ns
110 125 140 ns110 125 1406, 9
@ 12 MHz 152 167
65
t11 Data valid setup time prior to CLOCK IN rising edge 10 ns
t9 MEM/REG, RD/WR setup time following CLOCK IN falling edge 30 ns
t5
(contended access, with ENHANCED CPU ACCESS = “1” @ 20 MHz) 465 ns
@ 10 MHz
@ 16 MHz 30 ns
t6 CLOCK IN rising edge delay to IOEN falling edge 40 ns
87
t13 Data valid hold time following CLOCK IN rising edge 10 ns
ns
t15 CLOCK IN rising edge delay to READYD falling 40 ns
t16 READYD falling to STRBD rising release time ∞ns
82
t17 STRBD rising delay to IOEN rising edge and READYD rising edge 30 ns
t18 STRBD high hold time from . rising 10 ns
182 ns152 167 1826, 9
t14
@ 10 MHz 185 200 215 ns185 200 2156, 9
@ 12 MHz 50 ns
t4
@ 10 MHz 67 ns
@ 12 MHz 32 ns
t3
@ 10 MHz 40 ns
(contended access, with ENHANCED CPU ACCESS = “0” @ 12 MHz) 6.0 µs
(contended access, with ENHANCED CPU ACCESS = “0” @ 16 MHz) 4.6 µs
(contended access, with ENHANCED CPU ACCESS = “1” @ 16 MHz) 565 ns
(uncontended access @ 12 MHz) 133 ns
(contended access, with ENHANCED CPU ACCESS = “1” @ 10 MHz) 865 ns
(contended access, with ENHANCED CPU ACCESS = “1” @ 12 MHz) 732 ns
(uncontended access @ 10 MHz) 150 ns
(contended access, with ENHANCED CPU ACCESS = “0” @ 10 MHz) 7.2 µs
1172, 6
2, 10
NOTES
15
105
3.6
10
16
12
32
0
35
30
15
15
35
470
25
40
15
40
∞
40
10
45
62
27
35
6.0
4.6
570
138
870
737
155
7.2
REF DESCRIPTION MIN TYP MAX UNITS
MIN TYP MAX
2, 6
2, 6
3, 4, 5, 7
3, 4, 5, 7
2
7, 8
7, 8, 9
3, 4, 5, 7
3, 4, 5, 7
2, 6
6
9
6
6
3, 4, 5, 7
3, 4, 5, 7
2, 6
2, 6
2, 6
2, 6
2, 6
2, 6
2, 6
2, 6
44
Data Device Corporation
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BU-6474X/6484X/6486X
AJ-6/11-0
+3.3 VOLT INTERFACE TO MIL-STD-1553 BUS
(BU-64XXXX8/9)
The Mini-ACE Mark3 is the world's first MIL-STD-1553 terminal
powered entirely by 3.3 volts. Unique isolation transformer turns
ratios, single output winding transformers and new interconnec-
tion methods are required in order to meet mandated MIL-
STD-1553 differential voltage levels.
FIGURE 15 illustrates the two possible interface methods
between the Mini-ACE Mark3 series and a MIL-STD-1553 bus.
Connections for both direct (short stub, 1:3.75) and transformer
(long stub, 1:2.7) coupling, as well as nominal peak-to-peak volt-
age levels at various points (when transmitting), are indicated in
the diagram.
The center tap of the primary winding (the side of the trans-
former that connects to the Mark3) must be directly connected to
the +3.3 volt plane. Additionally, a 10µf, low inductance tantalum
capacitor and a 0.01µf ceramic capacitor must be mounted as
close as possible and with the shortest leads to the center tap of
the transformer(s) and ground plane.
Additionally, during transmission large currents flow from the
transformer center tap, through the primaries and the TX/RX pins,
and then out the transceiver grounds (pins 22 and 79) into the
ground plane. The traces in this path should be sized accordingly
and the connections to the ground plane should be as short as
possible.
FIGURE 15. BU-64XXXX8/9 (+3.3 VOLT) INTERFACE TO MIL-STD-1553 BUS
Mini-ACE Mark3/
Micro-ACE-TE
DATA
BUS
Z0
55 Ω
55 Ω
TX/RX
TX/RX
(1:3.75)
(7.4 Vpp) 28 Vpp
1 FT MAX
Z0
(1:2.7)
20 Vpp
(1:1.41)
COUPLING
TRANSFORMER
0.75 Z0
0.75 Z0
LONG STUB
(TRANSFORMER
COUPLED)
20 FT MAX
28 Vpp
SHORT STUB
(DIRECT COUPLED)
OR
DIRECT-COUPLED
ISOLATION TRANSFORMER
7 Vpp
7Vpp
Mini-ACE Mark3/
Micro-ACE-TE
(7.4 Vpp)
10µF
.01µF
3.3V
10µF
.01µF
3.3V
TRANSFORMER-COUPLED
ISOLATION TRANSFORMER
NOTES: 1. Transformer center tap capacitors: use a 10µF tantalum for low inductance, and a 0.01µF ceramic.
Both must be mounted as close as possible, and with the shortest leads to the center tap of the
transformer(s) and ground.
2. Connect the Mark3 hybrid grounds as directly as possible to the 3.3V ground plane.
3. Zo = 70 to 85 Ohms.
TX/RX
TX/RX
+
+
45
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+3.3 VOLT INTERFACE TO MIL-STD-1553 BUS
(BU-64XXXXC/D)
FIGURE 16 illustrates the two possible interface methods
between the Mini-ACE Mark3 series and a MIL-STD-1553 bus.
Connections for both direct (short stub, 1:2.65) and transformer
(long stub, 1:2.038) coupling, as well as nominal peak-to-peak
voltage levels at various points (when transmitting), are indicated
in the diagram.
The center tap of the primary winding (the side of the trans-
former that connects to the Mark3) must be directly connected to
ground.
Additionally, during transmission, large currents flow from the
transceiver power supply through the TX/RX pins into the trans-
former primaries and then out the center tap into the ground
plane. The traces in this path should be sized accordingly and the
connections to the ground plane should be as short as possible.
A 10µf, low inductance tantalum capacitor and a 0.01µf ceramic
capacitor must be mounted as close as possible and with the
shortest leads to the transceiver power input of the Mini-ACE
Mark 3.
FIGURE 16. BU-64XXXXC/D (+3.3 VOLT) INTERFACE TO MIL-STD-1553 BUS
Mini-ACE Mark3/
Micro-ACE-TE
DATA
BUS
Z0
55 Ω
55 Ω
TX/RX
TX/RX
(1:2.65)
28 Vpp
1 FT MAX
Z0
(1:2.038)
20 Vpp
(1:1.41)
COUPLING
TRANSFORMER
0.75 Z0
0.75 Z0
LONG STUB
(TRANSFORMER
COUPLED)
20 FT MAX
28 Vpp
SHORT STUB
(DIRECT COUPLED)
OR
DIRECT-COUPLED
ISOLATION TRANSFORMER
7 Vpp
7Vpp
Mini-ACE Mark3/
Micro-ACE-TE
TRANSFORMER-COUPLED
ISOLATION TRANSFORMER
NOTES: 1. Connect the Mark3 hybrid grounds as directly as possible to the 3.3V ground plane.
2. Zo = 70 to 85 Ohms.
TX/RX
TX/RX
3.3V
.01µF
10µF +
3.3V
.01µF
10µF +
46
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+3.3 VOLT ISOLATION TRANSFORMERS
In selecting isolation transformers to be used with the Mini-ACE
Mark3, there is a limitation on the maximum amount of leakage
inductance. If this limit is exceeded, the transmitter rise and fall
times may increase, possibly causing the bus amplitude to fall
below the minimum level required by MIL-STD-1553.
In addition, an excessive leakage imbalance may result in a
transformer dynamic offset that exceeds 1553 specifications. The
maximum allowable leakage inductance is a function of the cou-
pling method. For Transformer Coupled applications, it is a maxi-
mum of 5.0 µH . For Direct it is a maximum of 10.0 µH, and is
measured as follows:
The side of the transformer that connects to the Mark3 is defined
as the "primary" winding. If one side of the primary is shorted to
the primary center-tap, the inductance should be measured
across the "secondary" (stub side) winding. This inductance must
be less than 5.0 µH (Transformer Coupled) and 10.0 µH (Direct
Coupled). Similarly, if the other side of the primary is shorted to
the primary center-tap, the inductance measured across the
"secondary" (stub side) winding must also be less than 5.0 µH
(Transformer Coupled) and 10.0 µH (Direct Coupled).
The difference between these two measurements is the "differen-
tial" leakage inductance. This value must be less than 1.0 µH
(Transformer Coupled) and 2.0 µH (Direct Coupled).
Beta Transformer Technology Corporation (BTTC), a subsidiary
of DDC, manufactures transformers in a variety of mechanical
configurations with the required turns ratios of 1:3.75 direct cou-
pled, and 1:2.7 transformer coupled for BU-6XXXXX8/9 Models
and the required turns ratios of 1:2.65 direct coupled, and
1:2.038 transformer coupled for BU-6XXXXXC/D Models. TABLE
46 provides a listing of these transformers with the corresponding
model numbers.
For further information, contact BTTC at 631-244-7393 or at
www.bttc-beta.com.
TABLE 46. BTTC TRANSFORMERS FOR USE WITH +3.3 VOLT Mini-ACE Mark3
MODEL
NUMBER
BTTC PART
NUMBER
# OF CHANNELS,
CONFIGURATION
COUPLING
RATIO
DESCRIPTION
COUPLING
RATIO
(1:X)
MOUNTING MAX
HEIGHT
WIDTH
(INCLUDING
LEADS)
LENGTH
(INCLUDING
LEADS)
BU-6XXXXX8/9 MLP-2033 Single Direct (1:3.75) SMT 0.185" 0.4" 0.52"
BU-6XXXXXC/D MLP-2030 Single Direct (1:2.65) SMT 0.185" 0.4" 0.52"
BU-6XXXXX8/9 MLP-3033 Single Direct (1:3.75) Through Hole 0.185" 0.4" 0.4"
BU-6XXXXX8/9 MLP-2233 Single Transformer (1:2.7) SMT 0.185" 0.4" 0.52"
BU-6XXXXXC/D MLP-2230 Single Transformer (1:2.038) SMT 0.185" 0.4" 0.52"
BU-6XXXXX8/9 MLP-3233 Single Transformer (1:2.7) Through Hole 0.185" 0.4" 0.4"
BU-6XXXXX8/9 MLP-3333 Single Direct &
Transformer
(1:3.75) &
(1:2.7) Through Hole 0.185" 0.4" 0.4"
BU-6XXXXXC/D DSS-3330 Dual (Side-by-Side) Direct &
Transformer
(1:2.65) &
(1:2.038) SMT 0.185" 0.52" 0.675"
BU-6XXXXX8/9 DSS-2033 Dual (Side-by-Side) Direct (1:3.75) SMT 0.13" 0.72" 0.96"
BU-6XXXXX8/9 DSS-2233 Dual (Side-by-Side) Transformer (1:2.7) SMT 0.13" 0.72" 0.96"
BU-6XXXXX8/9 DSS-1003 Dual (Side-by-Side) Direct &
Transformer
(1:3.75) &
(1:2.7) SMT 0.165" 0.72" 0.96"
BU-6XXXXX8/9 TSM-2033 Dual (Stacked) Direct (1:3.75) SMT 0.32" 0.4" 0.52"
BU-6XXXXX8/9 TSM-2233 Dual (Stacked) Transformer (1:2.7) SMT 0.32" 0.4" 0.52"
BU-6XXXXXC/D TSM-2230 Dual (Stacked) Transformer (1:2.038) SMT 0.32" 0.4" 0.52"
47
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+5.0 VOLT INTERFACE TO MIL-STD-1553 BUS
FIGURE 17 illustrates the interface between the +5.0 volt ver-
sions of the Mini-ACE Mark3 series and a MIL-STD-1553 bus.
Connections for both direct (short stub) and transformer (long
stub) coupling, as well as the nominal peak-to-peak voltage lev-
els at various points (when transmitting), are indicated in the
diagram.
FIGURE 17. MINI-ACE MARK3 / MICRO-ACE-TE (+5.0 VOLT) INTERFACE TO MIL-STD-1553 BUS
Mini-ACE Mark3/
Micro-ACE-TE
DATA
BUS
Z0
55 Ω
55 Ω
TX/RX
TX/RX
(1:2.5)
11.2 Vpp 28 Vpp
1 FT MAX
Z0
(1:1.79)
11.2 Vpp 20 Vpp
(1:1.41)
COUPLING
TRANSFORMER
0.75 Z0
0.75 Z0
LONG STUB
(TRANSFORMER
COUPLED)
20 FT MAX
28 Vpp
SHORT STUB
(DIRECT COUPLED)
OR
NOTES: 1. Z 0= 70 TO 85 OHMS
ISOLATION
TRANSFORMER
ISOLATION
TRANSFORMER
7 Vpp
7 Vpp
2. NOMINAL VOLTAGE
LEVELS SHOWN
Mini-ACE Mark3/
Micro-ACE-TE
5V
.01µF
10µF +
5V
.01µF
10µF +
48
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+5.0 VOLT ISOLATION TRANSFORMERS
In selecting isolation transformers to be used with the Mini-ACE
Mark3 / Micro-ACE-TE, there is a limitation on the maximum
amount of leakage inductance. If this limit is exceeded, the trans-
mitter rise and fall times may increase, possibly causing the bus
amplitude to fall below the minimum level required by MIL-
STD-1553. In addition, an excessive leakage imbalance may
result in a transformer dynamic offset that exceeds 1553 specifi-
cations.
The maximum allowable leakage inductance is 6.0 µH, and
is measured as follows:
The side of the transformer that connects to the Mini-ACE Mark3
/ Micro-ACE-TE is defined as the “primary” winding. If one side
of the primary is shorted to the primary center-tap, the induc-
tance should be measured across the “secondary” (stub side)
winding. This inductance must be less than 6.0 µH. Similarly, if
the other side of the primary is shorted to the primary center-tap,
the inductance measured across the “secondary” (stub side)
winding must also be less than 6.0 µH.
The difference between these two measurements is the
“differential” leakage inductance. This value must be less than 1.0
µH.
Beta Transformer Technology Corporation (BTTC), a subsidiary
of DDC, manufactures transformers in a variety of mechanical
configurations with the required turns ratios of 1:2.5 direct cou-
pled, and 1:1.79 transformer coupled. TABLE 47 provides a list-
ing of many of these transformers.
For further information, contact BTTC at 631-244-7393 or at
www.bttc-beta.com.
Notes:
1. All Transformers in the table above can be used with BU-6XXXXX3/6 (1553B transceivers).
2. Transformers identified with "#" in the table above are not recommended for use with the BU-6XXXXX4 (McAir-Compatable transceivers)
TABLE 47. BTTC TRANSFORMERS FOR USE WITH 5.0 VOLT Mini-ACE Mark3 / MICRO-ACE-TE
BTTC PART
NUMBER
# OF CHANNELS,
CONFIGURATION
COUPLING RATIO
DESCRIPTION
COUPLING
RATIO (1:X) MOUNTING MAX HEIGHT
WIDTH
(INCLUDING
LEADS)
LENGTH
(INCLUDING
LEADS)
MLP-2005 Single Direct (1:2.5) SMT 0.185" 0.4" 0.52"
MLP-3005 Single Direct (1:2.5) Through Hole 0.185" 0.4" 0.4"
B-3230 (-30) # Single Direct (1:2.5) Through Hole 0.25" 0.35" 0.5"
MLP-2205 Single Transformer (1:1.79) SMT 0.185" 0.4" 0.52"
MLP-3205 Single Transformer (1:1.79) Through Hole 0.185" 0.4" 0.4"
B-3229 (-29) # Single Transformer (1:1.79) Through Hole 0.25" 0.35" 0.5"
HLP-6015 # Single Direct & Transformer (1:2.5) &
(1:1.79) SMT 0.19" 0.63" 1.13"
B-3227 (-27) # Single Direct & Transformer (1:2.5) &
(1:1.79) SMT 0.29" 0.63" 1.13"
MLP-3305 Single Direct & Transformer (1:2.5) &
(1:1.79) Through Hole 0.185" 0.4" 0.4"
B-3226 (-26) # Single Direct & Transformer (1:2.5) &
(1:1.79) Through Hole 0.25" 0.625" 0.625"
HLP-6014 # Single Direct & Transformer (1:2.5) &
(1:1.79) Flat Pack 0.19" 0.63" 1.13"
B-3231 (-31) # Single Direct & Transformer (1:2.5) &
(1:1.79) Flat Pack 0.29" 0.63" 1.13"
DSS-2005 Dual (Side-by-Side) Direct (1:2.5) SMT 0.13" 0.72" 0.96"
DSS-2205 Dual (Side-by-Side) Transformer (1:1.79) SMT 0.13" 0.72" 0.96"
DSS-1005 Dual (Side-by-Side) Direct & Transformer (1:2.5) &
(1:1.79) SMT 0.165" 0.72" 0.96"
TSM-2005 Dual (Stacked) Direct (1:2.5) SMT 0.32" 0.4" 0.52"
TSM-2205 Dual (Stacked) Transformer (1:1.79) SMT 0.32" 0.4" 0.52"
TST-9117 # Dual (Stacked) Direct & Transformer (1:2.5) &
(1:1.79) SMT 0.335" 1.125" 1.125"
TST-9107 # Dual (Stacked) Direct & Transformer (1:2.5) &
(1:1.79) Through Hole 0.335" 0.625" 0.625"
TST-9127 # Dual (Stacked) Direct & Transformer (1:2.5) &
(1:1.79) Flat Pack 0.335" 0.625" 0.625"
49
Data Device Corporation
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BU-6474X/6484X/6486X
AJ-6/11-0
THERMAL MANAGEMENT FOR MICRO-ACE-TE
(324-BALL BGA PACKAGE)
Ball Grid Array (BGA) components necessitate that thermal
management issues be considered early in the design stage for
MIL-STD-1553 terminals. This is especially true if high transmit-
ter duty cycles are expected. The temperature range specified for
DDC's Micro-ACE-TE device refers to the temperature at the
ball, not the case.
All Micro-ACE-TE devices incorporate multiple package connec-
tions which perform the dual function of transceiver circuit
ground and thermal heat sink. Refer to the pinout tables for ther-
mal ball connection locations. It is mandatory that these thermal
FIGURE 18. BALL LOCATIONS FOR MICRO-ACE-TE (324-BALL BGA PACKAGE)
balls be directly soldered to a circuit ground/thermal plane (a
circuit trace is insufficient). Operation without an adequate
ground/thermal plane is not recommended and extended expo-
sure to these conditions may affect device reliability.
The purpose of this ground/thermal plane is to conduct the heat
being generated by the transceivers within the package and
conduct this heat away from the Micro-ACE-TE. In general, the
circuit ground and thermal (chassis) ground are not the same
ground plane. It is acceptable for these balls to be directly sol-
dered to a ground plane but it must be located in close physical
and thermal proximity ("0.003" pre-preg layer recommended) to
the thermal plane.
V U T R P N M L K J H G F E D C B A
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
BOTTOM VIEW
S/N
D/C
TOP VIEW
ESD and Pin 1 Identifier
50
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FLAT PACK AND GULL WING PACKAGES - SIGNAL DESCRIPTIONS BY FUNCTIONAL GROUPS
+ 3.3V_Xcvr -
+ 3.3V_Logic 10, 30, 51, 69
Gnd_Xcvr -
Gnd_Logic 22, 79, 31, 50, 70
TABLE 48. POWER AND GROUND
SIGNAL NAME
BU-64743F/G0
BU-64843F/G0
BU-64863F/G0
PIN
-
-
22, 79
31, 50, 70
BU-64745F/G3/4
BU-64845F/G3/4
PIN
BU-64743F/G3/4
BU-64843F/G3/4
BU-64863F/G3/4
PIN
+ 3.3 Volt Transceiver Power
+ 5.0V_Xcvr -
-
30, 51, 69
22, 79
31, 50, 70
10 10 + 5.0 Volt Transceiver Power
+3.3 Volt Logic Power
+ 5.0V_Logic -30, 51, 69
10
30, 51, 69
22, 79
31, 50, 70
BU-64743F/G8/9
BU-64843F/G8/9
BU-64863F/G8/9
PIN
-
-
-+5.0 Volt Logic Power
Transceiver Ground
Logic Ground
DESCRIPTION
TXDATA_A (O) 3
TXDATA_A (O) 5
RXDATA_A (I) 8
RXDATA_A
(I, not enabled)* 4
TABLE 50. INTERFACE TO EXTERNAL TRANSCEIVER (BU-64XX3F/G0 TRANSCEIVERLESS VERSION)
SIGNAL NAME
BU-64743F/G0
BU-64843F/G0
BU-64863F/G0
PIN
Digital Manchester biphase transmit outputs, A bus
Digital Manchester biphase receive inputs, A bus
TXINH_A_OUT (O) 11
TXDATA_B (O) 15
TXDATA_B (O) 17
RXDATA_B (I) 21
Digital output to inhibit external transmitter, A bus
Digital Manchester biphase transmit outputs, B bus
Digital Manchester biphase receive inputs, B bus
RXDATA_B
(I, not enabled)* 16
TXINH_B_OUT (O) 9Digital output to inhibit external transmitter, B bus
UPADDREN / NC 14
4K versions: UPADDREN / 64K versions: NC
For 4K RAM versions, this signal is always configured as UPADDREN.
This signal is used to control the function of the upper 4 address inputs (A15-A12). For these versions
of Mark3 if UPADDREN is connected to logic "1", then these four signals operate as address lines
A15-A12. If UPADDREN is connected to logic "0", then A15 and A14 function as CLK_SEL_1 and
CLK_SEL_0 respectively; A13 MUST be connected to +3.3V-LOGIC; and A12 functions as RTBOOT.
DESCRIPTION
TX/RX-A (I/O) 3
Analog Transmit/Receive Input/Outputs. Connect directly to 1553 isolation transformers.
TX/RX-A (I/O) 5
TX/RX-B (I/O) 15
TX/RX-B (I/O) 17
TABLE 49. 1553 ISOLATION TRANSFORMER (BU-64XXXF/G3/4/8/9 VERSIONS)
SIGNAL NAME DESCRIPTION
BU-6474XF/G3/4/8/9
BU-6484XF/G3/4/8/9
BU-64863F/G3/4/8/9
PIN
*NOTE: Standard transceiverless parts have their receiver inputs internally strapped for single-ended operation. The
RXDATAx pins are connected to inputs that are not enabled. Contact the factory for a non-standard part that
enables differential receive inputs.
NOTE: Logic ground and transceiver ground are not tied together inside the package.
51
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A15 / CLK_
SEL_1
A15 (MSB) 73 16-bit bi-directional address bus.
For 64K RAM versions, this signal is always configured as address line A15 (MSB).
Refer to the description for A11-A0 below.
For 4K RAM versions, if UPADDREN is connected to logic "1", this signal operates as
address line A15.
For 4K RAM versions, if UPADDREN is connected to logic "0", this signal operates as
CLK_SEL_1. In this case, A15/CLK_SEL_1 and A14/CLK_SEL_0 are used to select
the Mark3 clock frequency, as follows:
CLK_SEL_1 CLK_SEL_0 Clock Frequency
0 0 10 MHz
0 1 20 MHz
1 0 12 MHz
1 1 16 MHz
A14 / CLK_
SEL_0
A14 80 For 64K RAM versions, this signal is always configured as address line A14. Refer to
the description of A11-A0 below.
For 4K RAM versions, if UPADDREN is connected to logic "1", this signal operates as
A14.
For 4K RAM versions, if UPADDREN is connected to logic "0", then this signal oper-
ates as CLK_SEL_0. In this case, CLK_SEL_1 and CLK_SEL_0 are used to select the
Mark3 clock frequency, as defined in the description for A15/CLK_SEL1 above.
TABLE 52. PROCESSOR ADDRESS BUS
SIGNAL NAME
DESCRIPTION
BU-6474XF/GX
BU-6484XF/GX
BU-64863F/GX
PIN
4K RAM
(BU-6474XF/GX
BU-6484XF/GX)
64K RAM
(BU-64863F/GX)
16-bit bi-directional data bus.This bus interfaces the host processor to the Mini-ACE Mark3's internal regis-
ters and internal RAM. In addition, in transparent mode, this bus allows data transfers to take place between
the internal protocol/memory management logic and up to 64K x 16 of external RAM. Most of the time, the
outputs for D15 through D0 are in the high impedance state. They drive outward in the buffered or transpar-
ent mode when the host CPU reads the internal RAM or registers.
Also, in the transparent mode, D15-D0 will drive outward (towards the host) when the protocol/management
logic is accessing (either reading or writing) internal RAM, or writing to external RAM. In the transparent
mode, D15-D0 drives inward when the CPU writes internal registers or RAM, or when the protocol/memory
management logic reads external RAM.
D10 60
D9 57
D8 52
D7 53
D6 41
D5 49
D4 43
D3 48
D2 47
D1 42
D0 (LSB) 46
D15 (MSB) 59
D14 56
D13 54
D12 55
D11 58
TABLE 51. DATA BUS
SIGNAL NAME DESCRIPTION
BU-6474XF/GX
BU-6484XF/GX
BU-64863F/GX
PIN
FLAT PACK AND GULL WING PACKAGES - SIGNAL DESCRIPTIONS BY FUNCTIONAL GROUPS (CONT.)
52
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A11 1
Lower 12 bits of 16-bit bi-directional address bus.
In both the buffered and transparent modes, the host CPU accesses Mark3 registers and internal RAM by
means of A11 - A0 (4K versions). For 64K versions, A15-A12 are also used for this purpose.
In buffered mode, A12-A0 (or A15-A0) are inputs only. In the transparent mode, A12-A0 (or A15-A0) are
inputs during CPU accesses and become outputs, driving outward (towards the CPU) when the 1553 pro-
tocol/memory management logic accesses up to 64K words of external RAM.
In transparent mode, the address bus is driven outward only when the signal DTACK is low (indicating that
the Mark3 has control of the RAM interface bus) and IOEN is high, indicating a non-host access. Most of
the time, including immediately after power turn-on, A12-A0 (or A15-A0) will be in high impedance (input)
state.
A10 2
A09 75
A08 7
A07 12
A06 27
A05 74
A04 78
A03 13
A02 19
A01 33
A00 (LSB) 18
SIGNAL NAME DESCRIPTION
BU-6474XF/GX
BU-6484XF/GX
BU-64863F/GX
PIN
A13 /
+3.3V/+5.0V
LOGIC
77 For 64K RAM versions, this signal is always configured as address line A13. Refer to
the description for A11-A0 below.
For 4K RAM versions, if UPADDREN is connected to logic "1", this signal operates as A13.
For 4K RAM versions, if UPADDREN is connected to logic "0", then this signal MUST
be connected to +3.3V-LOGIC (logic "1") for the BU-64XX3 or +5.0V (logic "1") for the
BU-64XX5.
A13
A12 / RTBOOT 76 For 64K RAM versions, this signal is always configured as address line A12. Refer to
the description for A11-A0 below.
For 4K RAM versions, if UPADDREN is connected to logic "1", this signal operates as
A12.
For 4K RAM versions, if UPADDREN is connected to logic "0", then this signal func-
tions as RTBOOT. If RTBOOT is connected to logic "0", the Mark3 will initialize in RT
mode with the Busy status word bit set following power turn-on. If RTBOOT is hard-
wired to logic "1", the Mark3 will initialize in either Idle mode (for an RT-only part), or in
BC mode (for a BC/RT/MT part).
A12
TABLE 52. PROCESSOR ADDRESS BUS (CONT.)
SIGNAL NAME
DESCRIPTION
BU-6474XF/GX
BU-6484XF/GX
BU-64863F/GX
PIN
4K RAM
(BU-6474XF/GX
BU-6484XF/GX)
64K RAM
(BU-64863F/GX)
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SELECT (I) 66 Device Select.
Generally connected to a CPU address decoder output to select the Mark3 for a transfer to/from either
RAM or register.
STRBD (I) 68 Strobe Data.
Used in conjunction with SELECT to initiate and control the data transfer cycle between the host processor
and the Mark3. STRBD must be asserted low through the full duration of the transfer cycle.
RD / WR (I) 71 Read/Write.
For host processor access, RD/WR selects between reading and writing. In the 16-bit buffered mode, if
POL_SEL is logic "0”, then RD/WR should be low (logic "0") for read accesses and high (logic "1") for write
accesses. If POL_SEL is logic "1", or the interface is configured for a mode other than 16-bit buffered
mode, then RD/WR is high (logic "1") for read accesses and low (logic "0") for write accesses.
ADDR_LAT(I) /
MEMOE (O)
20 Memory Output Enable or Address Latch.
In buffered mode, the ADDR_LAT input is used to configure the buffers for A15-A0, SELECT, MEM/REG,
and MSB/LSB (for 8-bit mode only) in latched mode (when low) or transparent mode (when high). That is,
the Mark3's internal transparent latches will track the values on A15-A0, SELECT, MEM/REG, and MSB/
LSB when ADDR_LAT is high, and latch the values when ADDR_LAT goes low.
In general, for interfacing to processors with a non-multiplexed address/data bus, ADDR_LAT should be
hardwired to logic "1". For interfacing to processors with a multiplexed address/data bus, ADDR_LAT
should be connected to a signal that indicates a valid address when ADDR_LAT is logic "1".
In transparent mode, MEMOE output signal is used to enable data outputs for external RAM read cycles
(normally connected to the OE input signal on external RAM chips).
ZEROWAIT (I) /
MEMWR (O)
28 Memory Write or Zero Wait.
In buffered mode, input signal (ZEROWAIT) used to select between the zero wait mode (ZEROWAIT = "0")
and the non-zero wait mode (ZEROWAIT = "1").
In transparent mode, active low output signal (MEMWR) asserted low during memory write transfers to
strobe data into external RAM (normally connected to the WR input signal on external RAM chips).
16 / 8 (I) /
DTREQ (O)
29 Data Transfer Request or Data Bus Select.
In buffered mode, input signal 16/8 used to select between the 16 bit data transfer mode (16/8= "1") and
the 8-bit data transfer mode (16/8 = "0").
In transparent mode (16-bit only), active low level output signal DTREQ used to request access to the pro-
cessor/RAM interface bus (address and data buses).
MSB / LSB (I) /
DTGRT (I)
72 Data Transfer Grant or Most Significant Byte/Least Significant Byte.
In 8-bit buffered mode, input signal (MSB/LSB) used to indicate which byte is currently being transferred
(MSB or LSB). The logic sense of MSB/LSB is controlled by the POL_SEL input. MSB/LSB is not used in
the 16-bit buffered mode.
In transparent mode, active low input signal (DTGRT) asserted in response to the DTREQ output to indi-
cate that control of the external processor/RAM bus has been transferred from the host processor to the
Mark3.
TABLE 53. PROCESSOR INTERFACE CONTROL
SIGNAL NAME DESCRIPTION
BU-6474XF/GX
BU-6484XF/GX
BU-64863F/GX
PIN
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POL_SEL (I) /
DTACK (O)
35 Data Transfer Acknowledge or Polarity Select.
In 16-bit buffered mode, if POL_SEL is connected to logic "1", RD/WR should be asserted high (logic "1")
for a read operation and low (logic "0") for a write operation. In 16-bit buffered mode, if POL_SEL is con-
nected to logic "0", RD/WR should be asserted low (logic "0") for a read operation and high (logic "1") for a
write operation.
In 8-bit buffered mode (TRANSPARENT/ BUFFERED = "0" and 16/8 = "0"), POL_SEL input signal used to
control the logic sense of the MSB/LSB signal. If POL_SEL is connected to logic "0", MSB/LSB should be
asserted low (logic "0") to indicate the transfer of the least significant byte and high (logic "1") to indicate
the transfer of the most significant byte. If POL_SEL is connected to logic "1", MSB/LSB should be asserted
high (logic "1") to indicate the transfer of the least significant byte and low (logic "0") to indicate the transfer
of the most significant byte.
In transparent mode, active low output signal (DTACK) used to indicate acceptance of the processor/RAM
interface bus in response to a data transfer grant (DTGRT). Mark3 RAM transfers over A15-A0 and D15-D0
will be framed by the time that DTACK is asserted low.
TRIG_SEL (I) /
MEMENA_IN (I)
34 Memory Enable or Trigger Select input.
In 8-bit buffered mode, input signal (TRIG-SEL) used to select the order in which byte pairs are transferred
to or from the Mark3 by the host processor. In the 8-bit buffered mode, TRIG_SEL should be asserted high
(logic 1) if the byte order for both read operations and write operations is MSB followed by LSB. TRIG_SEL
should be asserted low (logic 0) if the byte order for both read operations and write operations is LSB fol-
lowed by MSB.
This signal has no operation in the 16-bit buffered mode (it does not need to be connected).
In transparent mode, active low input MEMENA_IN, used as a Chip Select (CS) input to the Mark3's inter-
nal shared RAM. If only internal RAM is used, should be connected directly to the output of a gate that is
OR'ing the DTACK and IOEN output signals.
MEM / REG(I) 6Memory/Register.
Generally connected to either a CPU address line or address decoder output. Selects between memory
access (MEM/REG = "1") or register access (MEM/REG = "0").
TRANSPARENT/
BUFFERED (I)
61 Used to select between the buffered mode (when strapped to logic "0") and transparent/DMA mode (when
strapped to logic "1") for the host processor interface.
SSFLAG (I) /
EXT_TRIG(I)
37 Subsystem Flag (RT) or External Trigger (BC/Word Monitor) input.
In RT mode, if this input is asserted low, the Subsystem Flag bit will be set in the Mark3's RT Status Word.
If the SSFLAG input is logic "0" while bit 8 of Configuration Register #1 has been programmed to logic "1"
(cleared), the Subsystem Flag RT Status Word bit will become logic "1," but bit 8 of Configuration Register
#1, SUBSYSTEM FLAG, will return logic "1" when read. That is, the sense on the SSFLAG input has no
effect on the SUBSYSTEM FLAG register bit.
In the non-enhanced BC mode, this signal operates as an External Trigger input. In BC mode, if the exter-
nal BC Start option is enabled (bit 7 of Configuration Register #1), a low to high transition on this input will
issue a BC Start command, starting execution of the current BC frame.
In the enhanced BC mode, during the execution of a Wait for External Trigger (WTG) instruction, the Mark3
BC will wait for a low-to-high transition on EXT_TRIG before proceeding to the next instruction.
In the Word Monitor mode, if the external trigger is enabled (bit 7 of Configuration Register #1), a low to
high transition on this input will initiate a monitor start.
This input has no effect in Message Monitor mode.
TABLE 53. PROCESSOR INTERFACE CONTROL (CONT.)
SIGNAL NAME DESCRIPTION
BU-6474XF/GX
BU-6484XF/GX
BU-64863F/GX
PIN
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IOEN(O) 64 I/O Enable.
Tri-state control for external address and data buffers. Generally not used in buffered mode. When low, indi-
cates that the Mark3 is currently performing a host access to an internal register, or internal (for transparent
mode) external RAM. In transparent mode, IOEN (low) should be used to enable external address and data
bus tri-state buffers.
READYD (O) 62 Handshake output to host processor.
For a nonzero wait state read access, READYD is asserted at the end of a host transfer cycle to indicate that
data is available to be read on D15 through D0 when asserted (low). For a nonzero wait state write cycle,
READYD is asserted at the end of the cycle to indicate that data has been transferred to a register or RAM
location. For both nonzero wait reads and writes, the host must assert STRBD low until READYD is asserted
low.
In the (buffered) zero wait state mode, this output is normally logic "1", indicating that the Mark3 is in a state
ready to accept a subsequent host transfer cycle. In zero wait mode, READYD will transition from high to low
during (or just after) a host transfer cycle, when the Mark3 initiates its internal transfer to or from registers or
internal RAM. When the Mark3 completes its internal transfer, READYD returns to logic "1", indicating it is
ready for the host to initiate a subsequent transfer cycle.
TABLE 53. PROCESSOR INTERFACE CONTROL (CONT.)
SIGNAL NAME DESCRIPTION
BU-6474XF/GX
BU-6484XF/GX
BU-64863F/GX
PIN
RTAD4 (MSB) (I) 40 RT Address input.
If bit 5 of Configuration Register #6, RT ADDRESS SOURCE, is programmed to logic "0" (default), then the
Mark3's RT address is provided by means of these 5 input signals. In addition, if RT ADDRESS SOURCE is
logic "0", the source of RT address parity is RTADP.
There are many methods for using these input signals for designating the Mark3's RT address. For details,
refer to the description of RT_AD_LAT.
If RT ADDRESS SOURCE is programmed to logic "1", then the Mark3's source for its RT address and parity is
under software control, via data lines D5-D0. In this case, the RTAD4-RTAD0 and RTADP signals are not used.
RTAD3 (I) 39
RTAD2 (I) 24
RTAD1 (I) 45
RTAD0 (LSB) (I) 38
RT_AD_LAT (I) 36 RT Address Latch.
Input signal used to control the Mark3's internal RT address latch. If RT_AD_LAT is connected to logic "0", then
the Mark3 RT is configured to accept a hardwired (transparent) RT address from RTAD4-RTAD0 and RTADP.
If RT_AD_LAT is initially logic "0", and then transitions to logic "1", the values presented on RTAD4-RTAD0
and RTADP will be latched internally on the rising edge of RT_AD_LAT.
If RT_AD_LAT is connected to logic "1", then the Mark3's RT address is latchable under host processor con-
trol. In this case, there are two possibilities: (1) If bit 5 of Configuration Register #6, RT ADDRESS SOURCE,
is programmed to logic "0" (default), then the source of the RT Address is the RTAD4-RTAD0 and RTADP
input signals. (2) If RT ADDRESS SOURCE is programmed to logic "1", then the source of the RT Address is
the lower 6 bits of the processor data bus, D5-D1 (for RTAD4-0) and D0 (for RTADP).
In either of these two cases (with RT_AD_LAT = "1"), the processor will cause the RT address to be latched
by: (1) Writing bit 15 of Configuration Register #3, ENHANCED MODE ENABLE, to logic "1". (2) Writing bit 3
of Configuration Register #4, LATCH RT ADDRESS WITH CONFIGURATION REGISTER #5, to logic "1". (3)
Writing to Configuration Register #5. In the case of RT ADDRESS SOURCE = "1", then the values of RT
address and RT address parity must be written to the lower 6 bits of Configuration Register #5, via D5-D0. In
the case where RT ADDRESS SOURCE = "0", the bit values presented on D5-D0 become "don't care".
RTADP (I) 44 Remote Terminal Address Parity.
This input signal must provide an odd parity sum with RTAD4-RTAD0 in order for the RT to respond to non-broad-
cast commands. That is, there must be an odd number of logic "1"s from among RTAD-4-RTAD0 and RTADP.
TABLE 54. RT ADDRESS
SIGNAL NAME DESCRIPTION
BU-6474XF/GX
BU-6484XF/GX
BU-64863F/GX
PIN
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SLEEPIN (I) UPADDREN
(I)
For 64K RAM versions with internal transceivers, this signal is always configured as
SLEEPIN.
This signal is used to control the transceiver sleep (power-down) circuitry. For these
versions of Mark3 if SLEEPIN is connected to logic "0", the transceivers are fully pow-
ered and operate normally. If SLEEPIN is connected to logic "1", the transceivers are in
sleep mode (dormant, low-power mode) of operation and are NOT operational.
For 4K RAM versions, this signal is always configured as UPADDREN.
This signal is used to control the function of the upper 4 address inputs (A15-A12). For
these versions of Mark3 if UPADDREN is connected to logic "1", then these four signals
operate as address lines A15-A12. If UPADDREN is connected to logic "0", then A15
and A14 function as CLK_SEL_1 and CLK_SEL_0 respectively; A13 MUST be con-
nected to +3.3V-LOGIC; and A12 functions as RTBOOT.
For 64K RAM transceiverless versions, this signal is always a No Connect (NC).
14
INT (O) Interrupt Request output.
If the LEVEL/PULSE interrupt bit (bit 3) of Configuration Register #2 is logic "0", a neg-
ative pulse of approximately 500ns in width is output on INT to signal an interrupt
request.
If LEVEL/PULSE is high, a low level interrupt request output will be asserted on INT.
The level interrupt will be cleared (high) after either: (1) The processor writes a value of
logic "1" to INTERRUPT RESET, bit 2 of the Start/Reset Register; or (2) If bit 4 of
Configuration Register #2, INTERRUPT STATUS AUTO-CLEAR is logic "1" then it will
only be necessary to read the Interrupt Status Register (#1 and/or #2) that is request-
ing an interrupt enabled by the corresponding Interrupt Mask Register. However, for the
case where both Interrupt Status Register #1 and Interrupt Status Register #2 have bits
set reflecting interrupt events, it will be necessary to read both interrupt status registers
in order to clear INT.
63
CLOCK_IN (I) 20 MHz, 16 MHz, 12 MHz, or 10 MHz clock input.26
TX_INH_A (I) Transmitter inhibit inputs for Channel A and Channel B, MIL-STD-1553 transmitters.
For normal operation, these inputs should be connected to logic "0". To force a shut-
down of Channel A and/or Channel B, a value of logic "1" should be applied to the
respective TX_INH input.
65
TX_INH_B (I) 67
Master Clear. Negative true Reset input, normally asserted low following power turn-on.MSTCLR(I) 25
Time Tag Clock. External clock that may be used to increment the Time Tag Register. This
option is selected by setting Bits 7, 8 and 9 of Configuration Register # 2 to Logic "1".
TAG_CLK (I) 23
INCMD (O) /
MCRST (O)
In-command or Mode Code Reset.
The function of this pin is controlled by bit 0 of Configuration Register #7, MODE CODE
RESET/INCMD SELECT.
If this register bit is logic "0" (default), INCMD will be active on this pin. For BC, RT, or
Selective Message Monitor modes, INCMD is asserted low whenever a message is
being processed by the Mark3. In Word Monitor mode, INCMD will be asserted low for
as long as the monitor is online.
For RT mode, if MODE CODE RESET/INCMD SELECT is programmed to logic "1",
MCRST will be active. In this case, MCRST will be asserted low for two clock cycles fol-
lowing receipt of a Reset remote terminal mode command.
In BC or Monitor modes, if MODE CODE RESET/INCMD SELECT is logic "1", this sig-
nal is inoperative; i.e., in this case, it will always output a value of logic "1".
32
TABLE 55. MISCELLANEOUS
SIGNAL NAME
DESCRIPTION
BU-6474XF/GX
BU-6484XF/GX
BU-64863F/GX
PIN
4K RAM
(BU-6474XF/GX
BU-6484XF/GX)
NC
64K RAM
(BU-64863F/
G0)
64K RAM
(BU-64863F/G8
BU-64863F/G9)
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NC
4
No User Connections to these pins allowed.
8
9
11
16
21
TABLE 56. NO USER CONNECTIONS
SIGNAL NAME DESCRIPTION
BU-6474XF/GX
BU-6484XF/GX
BU-64863F/GX
PIN
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BALL GRID ARRAY PACKAGE - SIGNAL DESCRIPTIONS BY FUNCTIONAL GROUPS
+ 3.3V_Xcvr -
+ 3.3V_Logic -
Gnd_Logic
E12, E13, E14, F12,
F13, F14, G12, G13,
G14, H12, H13, H14
VDD_Low (I) A13
TABLE 57. POWER AND GROUND
SIGNAL NAME
BU-64840B3
BU-64860B(R)3
BALL
BU-64743B8
BU-64843B(R)8
BU-64863B(R)8
BALL
+ 3.3 Volt Transceiver Power
+ 5.0V_Xcvr F1, F2, U13,V13
A4, A5, B4, B5, J1,
J2, J3, J4, J5, K1,
K2, K3, K4, K5, U4,
U5, V4, V5
A8, A9, B8, B9,
L16, L17, M16,
M17, N12, N13,
P12, P13, R6, R7,
T6, T7, U6, U7, V6,
V7
E10, E11, E12,
F10, F11, F12,
G10, G11, G12,
H10, H11, H12,
R11, R12, R13,
T11, T12, T13, U11,
U12, U13
-
- + 5.0 Volt Transceiver Power
+3.3 V Logic Power
+ 5.0V/
+ 3.3V_Logic
A7, L1, L2, L15, L16,
M3, P7, P9, R9, V8 -+5.0V/+3.3V Logic Power. These balls may connect to either +5.0V or +3.3V. Refer
to input signal VDD_Low (ball A13) to determine voltage selection options.
+ 5.0V_RAM P4, R4,
(BU-64860B(R)3 only) - For BU-64860B3 this ball must be connected to +5.0V
Gnd_Xcvr/
Thermal
D3, D4, D5, E2, E3, E4,
E5, F3, F4, F5, G2, G3,
G4, G5, H3, H4, H5, P11,
P12, P13, P14, P15, R11,
R12, R13, R14, R15, T11,
T12, T13, T14, T15, U12,
U14
D3, D4, D5, E3, E4,
E5, F1, F2, F3, F4,
F5, G3, G4, G5, L3,
L4, L5, M3, M4, M5,
N1, N2, N3, N4, N5,
P3, P4, P5
Transceiver Ground/Thermal connections. See Thermal Management Section for
important user information.
Logic Ground.
Input that selects logic threshold voltage. Set to logic "0" for 3.3V threshold and to
+5V(logic "1") for 5V threshold. Must match "+5.0V/+3V Logic" input voltage.
DESCRIPTION
NOTE: Logic ground and transceiver ground are not tied together inside the package.
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TX/RX-A (I/O) D1, D2, E1
Analog Transmit/Receive Input/Outputs. Connect directly to 1553 isolation trans-
formers.
TX/RX-A (I/O) G1, H1, H2
TX/RX-B (I/O) U11, V11, V12
TX/RX-B (I/O) U15, V14, V15
TABLE 58. 1553 ISOLATION TRANSFORMER
SIGNAL NAME DESCRIPTION
BU-64840B3
BU-64860B(R)3
BALL
D1, D2, E1, E2
G1, G2, H1, H2
L1, L2, M1, M2
P1, P2, R1, R2
BU-64743B8
BU-64843B(R)8
BU-64863B(R)8
BALL
SNGL_END (I)
No Connect "NC" if
utilizing "Built-In"
Transceivers
If SNGL_END is connected to logic "0" the Manchester decoder inputs
will be configured to accept single-ended input signals
(e.g.,MIL-STD-1773 fiber optic receiver outputs). If SNGL_END is con-
nected to logic "1," the decoder inputs will be configured to accept
standard double-ended Manchester bi-phase input signals (i.e., MIL-
STD-1553 receiver outputs).
These two signals MUST be separated for "Transceiverless" operation.
Transmitter inhibit inputs for Channel A of external MIL-STD-1553
transmitters. To enable transmitter this input should be connected to
logic "0". To force a shutdown of Channel A, a value of logic "1" should
be applied to the respective TXINH input.
Digital transmit inhibit outputs. Connect to TX_INH_OUT inputs of
external MIL-STD-1553 transceiver. Asserted high to inhibit when not
transmitting on the respective bus.
These two signals MUST be separated for "Transceiverless" operation.
Digital manchester biphase transmit data outputs. Connect directly to
corresponding inputs of a MIL-STD-1553 or MIL-STD-1773 (fiber
optic) transceiver.
TXINH_IN_A
These two signals
MUST be directly
connected for normal
"Built-In" transceiver
operation.
TXINH_OUT_A
TXDATA_IN_A These two signals
MUST be directly
connected for normal
"Built-In" transceiver
operation.
TABLE 59. MANDATORY ADDITIONAL CONNECTIONS & INTERFACE TO EXTERNAL TRANSCEIVER
SIGNAL NAME FOR USE WITH EXTERNAL TRANSCEIVERS
"TRANSCEIVERLESS"
USING INTERNAL
"BUILT-IN"
TRANSCEIVERS
A15
A4
A5
C8
D14
E7
E8
C7
TXDATA_OUT_A B8 C8
These two signals MUST be separated for "Transceiverless" operation.
Digital manchester biphase transmit data outputs. Connect directly to
corresponding inputs of a MIL-STD-1553 or MIL-STD-1773 (fiber
optic) transceiver.
TXDATA_IN_A These two signals
MUST be directly
connected for normal
"Built-In" transceiver
operation.
C4 D7
TXDATA_OUT_A C5 D8
These two signals MUST be separated for "Transceiverless" operation.
Digital manchester biphase receive data inputs. Connect directly to
corresponding outputs of a MIL-STD-1553 or MIL-STD-1773 (fiber
optic) transceiver.
RXDATA_IN_A These two signals
MUST be directly
connected for normal
"Built-In" transceiver
operation.
D10 G8
RXDATA_OUT_A E10 G7
These two signals MUST be separated for "Transceiverless" operation.
Digital manchester biphase receive data inputs. Connect directly to
corresponding outputs of a MIL-STD-1553 or MIL-STD-1773 (fiber
optic) transceiver.
RXDATA_IN_A These two signals
MUST be directly
connected for normal
"Built-In" transceiver
operation.
E9 H8
RXDATA_OUT_A F9 H7
These two signals MUST be separated for "Transceiverless" operation.
Transmitter inhibit inputs for Channel B of external MIL-STD-1553
transmitters. To enable transmitter this input should be connected to
logic "0". To force a shutdown of Channel B, a value of logic "1" should
be applied to the respective TXINH input.
Digital transmit inhibit outputs. Connect to TX_INH_OUT inputs of
external MIL-STD-1553 transceiver. Asserted high to inhibit when not
transmitting on the respective bus.
TXINH_IN_B These two signals
MUST be directly
connected for normal
"Built-In" transceiver
operation.
T8 N7
TXINH_OUT_B R8 N8
BU-64840B3
BU-64860B(R)3
BU-64743B8
BU-64843B(R)8
BU-64863B(R)8
BALL BALL
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These two signals MUST be separated for "Transceiverless" operation.
Digital manchester biphase transmit data outputs. Connect directly to
corresponding inputs of a MIL-STD-1553 or MIL-STD-1773 (fiber
optic) transceiver.
TXDATA_IN_B These two signals
MUST be directly
connected for normal
"Built-In" transceiver
operation.
R10 L7
TXDATA_OUT_B P10 L8
These two signals MUST be separated for "Transceiverless" operation.
Digital manchester biphase transmit data outputs. Connect directly to
corresponding inputs of a MIL-STD-1553 or MIL-STD-1773 (fiber
optic) transceiver.
TXDATA_IN_B These two signals
MUST be directly
connected for normal
"Built-In" transceiver
operation.
N12 M7
TXDATA_OUT_B M12 M8
These two signals MUST be separated for "Transceiverless" operation.
Digital manchester biphase receive data inputs. Connect directly to
corresponding outputs of a MIL-STD-1553 or MIL-STD-1773 (fiber
optic) transceiver.
RXDATA_IN_B These two signals
MUST be directly
connected for normal
"Built-In" transceiver
operation.
M13 P10
RXDATA_OUT_B M14 P9
These two signals MUST be separated for "Transceiverless" operation.
Digital manchester biphase receive data inputs. Connect directly to
corresponding outputs of a MIL-STD-1553 or MIL-STD-1773 (fiber
optic) transceiver.
RXDATA_IN_B These two signals
MUST be directly
connected for normal
"Built-In" transceiver
operation.
N13 R10
RXDATA_OUT_B N14 R9
TABLE 59. MANDATORY ADDITIONAL CONNECTIONS & INTERFACE TO EXTERNAL TRANSCEIVER (CONT.)
SIGNAL NAME FOR USE WITH EXTERNAL TRANSCEIVERS
"TRANSCEIVERLESS"
UTILIZING INTERNAL
"BUILT-IN"
TRANSCEIVERS
BU-64840B3
BU-64860B(R)3
BU-64743B8
BU-64843B(R)8
BU-64863B(R)8
BALL BALL
D15 (MSB) D15
16-bit bi-directional data bus. This bus interfaces the host processor to the Mini-
ACE Mark3's internal registers and internal RAM. In addition, in transparent mode,
this bus allows data transfers to take place between the internal protocol/memory
management logic and up to 64K x 16 of external RAM. Most of the time, the out-
puts for D15 through D0 are in the high impedance state. They drive outward in
the buffered or transparent mode when the host CPU reads the internal RAM or
registers.
Also, in the transparent mode, D15-D0 will drive outward (towards the host) when
the protocol/management logic is accessing (either reading or writing) internal
RAM, or writing to external RAM. In the transparent mode, D15-D0 drives inward
when the CPU writes internal registers or RAM, or when the protocol/memory
management logic reads external RAM.
D14 E17
D13 E16
D12 E18
TABLE 60. DATA BUS
SIGNAL NAME DESCRIPTION
BU-64840B3
BU-64860B(R)3
BALL
D16
F15
E16
F18
D11 E15
D10 F16
D09 F15
D08 F18
E17
E18
F16
G18
D07 F17
D06 G18
D05 G16
D04 G17
F17
J18
H17
H18
D03 G15
D02 H18
D01 J17
D00 (LSB) H17
G17
J17
K16
K17
BU-64743B8
BU-64843B(R)8
BU-64863B(R)8
BALL
BALL GRID ARRAY PACKAGE - SIGNAL DESCRIPTIONS BY FUNCTIONAL GROUPS (CONT.)
61
Data Device Corporation
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A15 / CLK_
SEL_1
A15 (MSB) C10 16-bit bi-directional address bus.
For 64K RAM versions, this signal is always configured as address
line A15 (MSB). Refer to the description for A11-A0 below.
For 4K RAM versions, if UPADDREN is connected to logic "1", this
signal operates as address line A15.
For 4K RAM versions, if UPADDREN is connected to logic "0", this signal
operates as CLK_SEL_1. In this case, A15/CLK_SEL_1 and A14/CLK_
SEL_0 are used to select the Mark3 clock frequency, as follows:
CLK_SEL_1 CLK_SEL_0 Clock Frequency
0 0 10 MHz
0 1 20 MHz
1 0 12 MHz
1 1 16 MHz
TABLE 61. PROCESSOR ADDRESS BUS
SIGNAL NAME
DESCRIPTION
BU-64840B3
BU-64860B(R)3
BALL
A11
A14 / CLK_
SEL_0
A14 A10 For 64K RAM versions, this signal is always configured as address
line A14. Refer to the description of A11-A0 below.
For 4K RAM versions, if UPADDREN is connected to logic "1", this
signal operates as A14.
For 4K RAM versions, if UPADDREN is connected to logic "0", then
this signal operates as CLK_SEL_0. In this case, CLK_SEL_1 and
CLK_SEL_0 are used to select the Mark3 clock frequency, as defined
in the description for A15/CLK_SEL1 above.
A7
A13 /
LOGIC “1”
A13 B10 For 64K RAM versions, this signal is always configured as address
line A13. Refer to the description for A11-A0 below.
For 4K RAM versions, if UPADDREN is connected to logic "1", this
signal operates as A13.
For 4K RAM versions, if UPADDREN is connected to logic "0", then
this signal MUST be connected to +3.3V-LOGIC (logic "1").
B10
A12 /
RTBOOT
A12 A9 For 64K RAM versions, this signal is always configured as address
line A12. Refer to the description for A11-A0 below.
For 4K RAM versions, if UPADDREN is connected to logic "1", this
signal operates as A12.
For 4K RAM versions, if UPADDREN is connected to logic "0", then
this signal functions as RTBOOT. If RTBOOT is connected to logic "0",
the Mark3 will initialize in RT mode with the Busy status word bit set
following power turn-on. If RTBOOT is hardwired to logic "1", the
Mark3 will initialize in either Idle mode (for an RT-only part), or in BC
mode (for a BC/RT/MT part).
A10
BU-64743B8
BU-64843B(R)8
BU-64863B(R)8
BALL
4K RAM
(BU-64743B8
BU-6484XBX)
64K RAM
(BU-6486XBX)
BALL GRID ARRAY PACKAGE - SIGNAL DESCRIPTIONS BY FUNCTIONAL GROUPS (CONT.)
62
Data Device Corporation
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A11A11 B9 Lower 12 bits of 16-bit bi-directional address bus.
In both the buffered and transparent modes, the host CPU accesses
Mark3 registers and internal RAM by means of A11 - A0 (4K ver-
sions). For 64K versions, A15-A12 are also used for this purpose.
In buffered mode, A12-A0 (or A15-A0) are inputs only. In the transpar-
ent mode, A12-A0 (or A15-A0) are inputs during CPU accesses and
become outputs, driving outward (towards the CPU) when the 1553
protocol/memory management logic accesses up to 64K words of
external RAM.
In transparent mode, the address bus is driven outward only when the
signal DTACK is low (indicating that the Mark3 has control of the RAM
interface bus) and IOEN is high, indicating a non-host access. Most of
the time, including immediately after power turn-on, A12-A0 (or
A15-A0) will be in high impedance (input) state.
E6
A10A10 A8 C15
A09A09 B7 C10
A08A08 C9 D10
A07A07 C7 D9
A06A06 D7 V9
A05A05 C6 C12
A04A04 D8 B7
A03A03 D6 E9
A02A02 E8 C9
A01A01 E7 U8
A00A00 F10 F8
TABLE 61. PROCESSOR ADDRESS BUS (CONT.)
SIGNAL NAME
DESCRIPTION
BU-64840B3
BU-64860B(R)3
BALL
BU-64743B8
BU-64843B(R)8
BU-64863B(R)8
BALL
4K RAM
(BU-64743B8
BU-6484XBX)
64K RAM
(BU-6486XBX)
BALL GRID ARRAY PACKAGE - SIGNAL DESCRIPTIONS BY FUNCTIONAL GROUPS (CONT.)
63
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SELECT (I) B12
Device Select.
Generally connected to a CPU address decoder output to select the Mark3 for a
transfer to/from either RAM or register.
TABLE 62. PROCESSOR INTERFACE CONTROL
SIGNAL NAME DESCRIPTION
BU-64840B3
BU-64860B(R)3
BALL
B12
STRBD (I) A12
Strobe Data.
Used in conjunction with SELECT to initiate and control the data transfer cycle
between the host processor and the Mark3. STRBD must be asserted low through
the full duration of the transfer cycle.
A12
ADDR_LAT(I) /
MEMOE (O) L9
Memory Output Enable or Address Latch.
In buffered mode, the ADDR_LAT input is used to configure the buffers for
A15-A0, SELECT, MEM/REG, and MSB/LSB (for 8-bit mode only) in latched mode
(when low) or transparent mode (when high). That is, the Mark3's internal trans-
parent latches will track the values on A15-A0, SELECT, MEM/REG, and MSB/
LSB when ADDR_LAT is high, and latch the values when ADDR_LAT goes low.
In general, for interfacing to processors with a non-multiplexed address/data bus,
ADDR_LAT should be hardwired to logic "1". For interfacing to processors with a
multiplexed address/data bus, ADDR_LAT should be connected to a signal that
indicates a valid address when ADDR_LAT is logic "1".
In transparent mode, MEMOE output signal is used to enable data outputs for
external RAM read cycles (normally connected to the OE input signal on external
RAM chips).
U10
ZEROWAIT (I) /
MEMWR (O) M10
Memory Write or Zero Wait.
In buffered mode, input signal (ZEROWAIT) used to select between the zero wait
mode (ZEROWAIT = "0") and the non-zero wait mode (ZEROWAIT = "1").
In transparent mode, active low output signal (MEMWR) asserted low during
memory write transfers to strobe data into external RAM (normally connected to
the WR input signal on external RAM chips).
T8
16 / 8 (I) /
DTREQ (O) L10
Data Transfer Request or Data Bus Select.
In buffered mode, input signal 16/8 used to select between the 16 bit data transfer
mode (16/8 = "1") and the 8-bit data transfer mode (16/8 = "0").
In transparent mode (16-bit only), active low level output signal DTREQ used to
request access to the processor/RAM interface bus (address and data buses).
R17
MSB / LSB (I) /
DTGRT (I) J7
Data Transfer Grant or Most Significant Byte/Least Significant Byte.
In 8-bit buffered mode, input signal (MSB/LSB) used to indicate which byte is cur-
rently being transferred (MSB or LSB). The logic sense of MSB/LSB is controlled
by the POL_SEL input. MSB/LSB is not used in the 16-bit buffered mode.
In transparent mode, active low input signal (DTGRT) asserted in response to the
DTREQ output to indicate that control of the external processor/RAM bus has
been transferred from the host processor to the Mark3.
B6
RD / WR (I) A11
Read/Write.
For host processor access, RD/WR selects between reading and writing. In the
16-bit buffered mode, if POL_SEL is logic "0”, then RD/WR should be low (logic
"0") for read accesses and high (logic "1") for write accesses. If POL_SEL is logic
"1", or the interface is configured for a mode other than 16-bit buffered mode, then
RD/WR is high (logic "1") for read accesses and low (logic "0") for write accesses.
B11
BU-64743B8
BU-64843B(R)8
BU-64863B(R)8
BALL
BALL GRID ARRAY PACKAGE - SIGNAL DESCRIPTIONS BY FUNCTIONAL GROUPS (CONT.)
64
Data Device Corporation
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BU-6474X/6484X/6486X
AJ-6/11-0
TABLE 62. PROCESSOR INTERFACE CONTROL (CONT.)
SIGNAL NAME DESCRIPTION
BU-64840B3
BU-64860B(R)3
BALL
BU-64743B8
BU-64843B(R)8
BU-64863B(R)8
BALL
POL_SEL (I) /
DTACK (O) N9
Data Transfer Acknowledge or Polarity Select.
In 16-bit buffered mode, if POL_SEL is connected to logic "1", RD/WR should be
asserted high (logic "1") for a read operation and low (logic "0") for a write opera-
tion. In 16-bit buffered mode, if POL_SEL is connected to logic "0", RD/WR should
be asserted low (logic "0") for a read operation and high (logic "1") for a write
operation.
In 8-bit buffered mode (TRANSPARENT/ BUFFERED = "0" and 16/8 = "0"), POL_
SEL input signal used to control the logic sense of the MSB/LSB signal. If POL_
SEL is connected to logic "0", MSB/LSB should be asserted low (logic "0") to indi-
cate the transfer of the least significant byte and high (logic "1") to indicate the
transfer of the most significant byte. If POL_SEL is connected to logic "1", MSB/
LSB should be asserted high (logic "1") to indicate the transfer of the least signifi-
cant byte and low (logic "0") to indicate the transfer of the most significant byte.
In transparent mode, active low output signal (DTACK) used to indicate accep-
tance of the processor/RAM interface bus in response to a data transfer grant
(DTGRT). Mark3 RAM transfers over A15-A0 and D15-D0 will be framed by the
time that DTACK is asserted low.
V8
TRIG_SEL (I) /
MEMENA_IN (I) L11
Memory Enable or Trigger Select input.
In 8-bit buffered mode, input signal (TRIG-SEL) used to select the order in which
byte pairs are transferred to or from the Mark3 by the host processor. In the 8-bit
buffered mode, TRIG_SEL should be asserted high (logic 1) if the byte order for
both read operations and write operations is MSB followed by LSB. TRIG_SEL
should be asserted low (logic 0) if the byte order for both read operations and
write operations is LSB followed by MSB.
This signal has no operation in the 16-bit buffered mode (it does not need to be
connected).
In transparent mode, active low input MEMENA_IN, used as a Chip Select (CS)
input to the Mark3's internal shared RAM. If only internal RAM is used, should be
connected directly to the output of a gate that is OR'ing the DTACK and IOEN out-
put signals.
N17
MEM / REG(I) C11
Memory/Register.
Generally connected to either a CPU address line or address decoder output.
Selects between memory access (MEM/REG = "1") or register access (MEM/REG
= "0").
A6
BALL GRID ARRAY PACKAGE - SIGNAL DESCRIPTIONS BY FUNCTIONAL GROUPS (CONT.)
65
Data Device Corporation
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AJ-6/11-0
TABLE 62 . PROCESSOR INTERFACE CONTROL (CONT.)
SIGNAL NAME DESCRIPTION
BU-64840B3
BU-64860B(R)3
BALL
BU-64743B8
BU-64843B(R)8
BU-64863B(R)8
BALL
SSFLAG (I) /
EXT_TRIG(I) J8
Subsystem Flag (RT) or External Trigger (BC/Word Monitor) input.
In RT mode, if this input is asserted low, the Subsystem Flag bit will be set in the
Mark3's RT Status Word. If the SSFLAG input is logic "0" while bit 8 of
Configuration Register #1 has been programmed to logic "1" (cleared), the
Subsystem Flag RT Status Word bit will become logic "1," but bit 8 of
Configuration Register #1, SUBSYSTEM FLAG, will return logic "1" when read.
That is, the sense on the SSFLAG input has no effect on the SUBSYSTEM FLAG
register bit.
In the non-enhanced BC mode, this signal operates as an External Trigger input.
In BC mode, if the external BC Start option is enabled (bit 7 of Configuration
Register #1), a low to high transition on this input will issue a BC Start command,
starting execution of the current BC frame.
In the enhanced BC mode, during the execution of a Wait for External Trigger
(WTG) instruction, the Mark3 BC will wait for a low-to-high transition on EXT_
TRIG before proceeding to the next instruction.
In the Word Monitor mode, if the external trigger is enabled (bit 7 of Configuration
Register #1), a low to high transition on this input will initiate a monitor start.
This input has no effect in Message Monitor mode.
R8
TRANSPARENT/
BUFFERED (I) D16 Used to select between the buffered mode (when strapped to logic "0") and trans-
parent/DMA mode (when strapped to logic "1") for the host processor interface.
D17
READYD (O) C15
Handshake output to host processor.
For a nonzero wait state read access, READYD is asserted at the end of a host
transfer cycle to indicate that data is available to be read on D15 through D0 when
asserted (low). For a nonzero wait state write cycle, READYD is asserted at the
end of the cycle to indicate that data has been transferred to a register or RAM
location. For both nonzero wait reads and writes, the host must assert STRBD low
until READYD is asserted low.
In the (buffered) zero wait state mode, this output is normally logic "1", indicating
that the Mark3 is in a state ready to accept a subsequent host transfer cycle. In
zero wait mode, READYD will transition from high to low during (or just after) a
host transfer cycle, when the Mark3 initiates its internal transfer to or from regis-
ters or internal RAM. When the Mark3 completes its internal transfer, READYD
returns to logic "1", indicating it is ready for the host to initiate a subsequent trans-
fer cycle.
B15
IOEN(O) C14
I/O Enable.
Tri-state control for external address and data buffers. Generally not used in buff-
ered mode. When low, indicates that the Mark3 is currently performing a host
access to an internal register, or internal (for transparent mode) external RAM. In
transparent mode, IOEN (low) should be used to enable external address and
data bus tri-state buffers.
A15
BALL GRID ARRAY PACKAGE - SIGNAL DESCRIPTIONS BY FUNCTIONAL GROUPS (CONT.)
66
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TABLE 63. RT ADDRESS
SIGNAL NAME DESCRIPTION
BU-64840B3
BU-64860B(R)3
BALL
BU-64743B8
BU-64843B(R)8
BU-64863B(R)8
BALL
RTAD4 (MSB) (I) J16 RT Address input.
If bit 5 of Configuration Register #6, RT ADDRESS SOURCE, is programmed to
logic "0" (default), then the Mark3's RT address is provided by means of these 5
input signals. In addition, if RT ADDRESS SOURCE is logic "0", the source of RT
address parity is RTADP.
There are many methods for using these input signals for designating the Mark3's
RT address. For details, refer to the description of RT_AD_LAT.
If RT ADDRESS SOURCE is programmed to logic "1", then the Mark3's source for
its RT address and parity is under software control, via data lines D5-D0. In this
case, the RTAD4-RTAD0 and RTADP signals are not used.
J15
RTAD3 (I) K17 M18
RTAD2 (I) L17 J16
RTAD1 (I) K18 L18
RTAD0 (LSB) (I) K16 N18
RT_AD_LAT (I) L18
RT Address Latch.
Input signal used to control the Mark3's internal RT address latch. If RT_AD_LAT is
connected to logic "0", then the Mark3 RT is configured to accept a hardwired (trans-
parent) RT address from RTAD4-RTAD0 and RTADP.
If RT_AD_LAT is initially logic "0", and then transitions to logic "1", the values pre-
sented on RTAD4-RTAD0 and RTADP will be latched internally on the rising edge
of RT_AD_LAT.
If RT_AD_LAT is connected to logic "1", then the Mark3's RT address is latchable
under host processor control. In this case, there are two possibilities: (1) If bit 5 of
Configuration Register #6, RT ADDRESS SOURCE, is programmed to logic "0"
(default), then the source of the RT Address is the RTAD4-RTAD0 and RTADP
input signals. (2) If RT ADDRESS SOURCE is programmed to logic "1", then the
source of the RT Address is the lower 6 bits of the processor data bus, D5-D1 (for
RTAD4-0) and D0 (for RTADP).
In either of these two cases (with RT_AD_LAT = "1"), the processor will cause the
RT address to be latched by: (1) Writing bit 15 of Configuration Register #3,
ENHANCED MODE ENABLE, to logic "1". (2) Writing bit 3 of Configuration
Register #4, LATCH RT ADDRESS WITH CONFIGURATION REGISTER #5, to
logic "1". (3) Writing to Configuration Register #5. In the case of RT ADDRESS
SOURCE = "1", then the values of RT address and RT address parity must be
written to the lower 6 bits of Configuration Register #5, via D5-D0. In the case
where RT ADDRESS SOURCE = "0", the bit values presented on D5-D0 become
"don't care".
P18
RTADP (I) J18
Remote Terminal Address Parity.
This input signal must provide an odd parity sum with RTAD4-RTAD0 in order for the
RT to respond to non-broadcast commands. That is, there must be an odd number of
logic "1"s from among RTAD-4-RTAD0 and RTADP.
K18
BALL GRID ARRAY PACKAGE - SIGNAL DESCRIPTIONS BY FUNCTIONAL GROUPS (CONT.)
67
Data Device Corporation
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UPADDREN (I)Logic "1" C12
This signal is used to control the function of the upper 4 address
inputs (A15-A12). If UPADDREN is connected to logic "1", then these
four signals operate as address lines A15-A12. If UPADDREN is con-
nected to logic "0", then A15 and A14 function as CLK_SEL_1 and
CLK_SEL_0 respectively; A13 MUST be connected to LOGIC "1"; and
A12 functions as RTBOOT.
TABLE 64. MISCELLANEOUS
SIGNAL NAME
DESCRIPTION
BU-64840B3
BU-64860B(R)3
BALL
F7
SLEEPIN (I) -
This signal is used to control the transceiver sleep (power-down) cir-
cuitry. If SLEEPIN is connected to logic "0", the transceivers are fully
powered and operate normally. If SLEEPIN is connected to logic "1",
the transceivers are in sleep mode (dormant, low-power mode) of
operation and are NOT operational.
R4
INCMD (O) H16
For BC, RT, or Selective Message Monitor modes, INCMD is asserted
low whenever a message is being processed by the Micro-ACE-TE. In
Word Monitor mode, INCMD will be asserted low for as long as the
monitor is online.
P17
MCRST (O) B13 For RT mode MCRST will be asserted low for two clock cycles follow-
ing receipt of a Reset remote terminal mode command.
D11
RSTBITEN (I) M18
If this input is set to logic "1", the Built-In-Self-Test (BIST) will be
enabled after hardware reset (for example, following power-up). A logic
"0" input disables both the power-up and user-initiated automatic BIST.
L14
INT (O) D17
Interrupt Request output. If the LEVEL/PULSE interrupt bit (bit 3) of
Configuration Register #2 is logic "0", a negative pulse of approxi-
mately 500 ns in width is output on INT to signal an interrupt request.
If LEVEL/PULSE is high, a low level interrupt request output will be
asserted on INT. The level interrupt will be cleared (high) after either:
(1) The processor writes a value of logic "1" to INTERRUPT RESET,
bit 2 of the Start/Reset Register; or (2) If bit 4 of Configuration
Register #2, INTERRUPT STATUS AUTO-CLEAR is logic "1" then it
will only be necessary to read the Interrupt Status Register (#1 and/or
#2) that is requesting an interrupt enabled by the corresponding
Interrupt Mask Register. However, for the case where both Interrupt
Status Register #1 and Interrupt Status Register #2 have bits set
reflecting interrupt events, it will be necessary to read both interrupt
status registers in order to clear INT.
D18
CLOCK_IN (I) M9 20 MHz, 16 MHz, 12 MHz, or 10 MHz clock input.T10
MSTCLR (I) B11 Master Clear. Negative true Reset input, normally asserted low follow-
ing power turn-on.
R18
TAG_CLK (I) D18
Time Tag Clock. External clock that may be used to increment the
Time Tag Register. This option is selected by setting Bits 7, 8 and 9 of
Configuration Register # 2 to Logic "1".
F14
TX_INH_A (I)
TX_INH_B (I)
A14 Transmitter inhibit inputs for Channel A and Channel B, MIL-
STD-1553 transmitters. For normal operation, these inputs should be
connected to logic "0". To force a shutdown of Channel A and/or
Channel B, a value of logic "1" should be applied to the respective
TX_INH input.
A14
C13 B14
BU-64743B8
BU-64843B(R)8
BU-64863B(R)8
BALL
4K RAM
(BU-64743B8
BU-6484XB(R)X)
64K RAM
(BU-6486XB(R)X)
BALL GRID ARRAY PACKAGE - SIGNAL DESCRIPTIONS BY FUNCTIONAL GROUPS (CONT.)
68
Data Device Corporation
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BU-6474X/6484X/6486X
AJ-6/11-0
TABLE 65. NO USER CONNECTIONS
SIGNAL NAME DESCRIPTION
BU-64840B3
BU-64860B(R)3
BALL
BU-64743B8
BU-64843B(R)8
BU-64863B(R)8
BALL
NC
A1, A2, A3, A6, A16,
A17, A18, B1, B2,
B3, B4, B5, B6, B14,
B15, B16, B17, B18,
C1, C2, C3, C16,
C17, C18, D9, D11,
D12, D13, D14, E6,
E11, F6, F7, F8,
F11, G6, G7, G8,
G9, G10, G11, H6,
H7, H8, H9, H10,
H11, H15, J1, J2, J3,
J4, J5, J6, J9, J10,
J11, J12, J13, J14,
J15, K1, K2, K3, K4,
K5, K6, K7, K8, K9,
K10, K11, K12, K13,
K14, K15, L3, L4,
L5, L6, L7, L8, L12,
L13, L14, M1, M2,
M4, M5, M6, M7,
M8, M11, M15, M16,
M17, N1, N2, N3,
N4, N5, N6, N7, N8,
N10, N11, N15, N16,
N17, N18, P1, P2,
P3, P5, P6, P8, P16,
P17, P18, R1, R2,
R3, R5, R6, R7,
R16, R17, R18, T1,
T2, T3, T4, T5, T6,
T7, T9, T10, T16,
T17, T18, U1, U2,
U3, U4, U5, U6, U7,
U8, U9, U10, U16,
U17, U18, V1, V2,
V3, V4, V5, V6, V7,
V9, V10, V16, V17,
V18
No User Connections to these balls allowed.
A1, A2, A3, A13,
A16, A17, A18, B1,
B2, B3, B13, B16,
B17, B18, C1, C2,
C3, C4, C5, C6,
C11, C13, C14, C16,
C17, C18, D6, D12,
D13, D15, E13, E14,
E15, F6, F9, F13,
G6, G9, G13, G14,
G15, G16, H3, H4,
H5, H6, H9, H13,
H14, H15, H16, J6,
J7, J8, J9, J10, J11,
J12, J13, J14, K6,
K7, K8, K9, K10,
K11, K12, K13, K14,
K15, L6, L9, L10,
L11, L12, L13, L15,
M6, M9, M10, M11,
M12, M13, M14,
M15, N6, N9, N10,
N11, N14, N15, N16,
P6, P7, P8, P11,
P14, P15, P16, R3,
R5, R14, R15, R16,
T1, T2, T3, T4, T5,
T9, T14, T15, T16,
T17, T18, U1, U2,
U3, U9, U14, U15,
U16, U17, U18, V1,
V2, V3, V10, V11,
V12, V13, V14, V15,
V16, V17, V18
BALL GRID ARRAY PACKAGE - SIGNAL DESCRIPTIONS BY FUNCTIONAL GROUPS (CONT.)
69
Data Device Corporation
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AJ-6/11-0
41
PIN
DB06
42
DB08
43
+3.3V_LOGIC for BU-64XX3 or +5.0V_LOGIC for BU-64XX5
GND_LOGIC
44
DB05
45
DB03
46
47 DB02
48
DB00
49
RTAD1
50
RTADP
51
FUNCTION
DB04
52
DB01
DB09
53
DB14
54
55 DB12
56
DB13
57
DB07
TX_INH_A
IOEN
INT
61 TRANS/BUFF
63
64
65
GND_LOGIC
+3.3V_LOGIC for BU-64XX3 or +5.0V_LOGIC for BU-64XX569
70
RD/WR71
A09
75
A12* or A12/RTBOOT**76
A05
DB10
DB15
DB11
58
59
60
SELECT
READYD62
66
STRBD
TX_INH_B67
68
A15* or A15/CLK_SEL_1**
MSB/LSB/DTGRT72
73
74
A111
A10
TX/RX_A
PIN
DO NOT CONNECT - FACTORY TEST POINT
2
FUNCTION
3
4
TX/RX_A5
MEM/REG6
A087
DO NOT CONNECT - FACTORY TEST POINT
DO NOT CONNECT - FACTORY TEST POINT
+3.3V_XCVR for BU-64XXXF/G8/9 or
+5.0_XCVR for BU-64XXXF/G3/4
8
9
10
DO NOT CONNECT - FACTORY TEST POINT11
TABLE 66. MINI-ACE MARK3 BU-64XXXF/G3/4/8/9 VERSIONS PINOUTS
A0712
A0313
SLEEPIN* or UPADDREN**14
TX/RX_B15
DO NOT CONNECT - FACTORY TEST POINT
TX/RX_B
A00
16
17
18
A0219
ADDR_LAT/MEMOE20
DO NOT CONNECT - FACTORY TEST POINT21
GND _XCVR
TAG_CLK
RTAD2
22
23
24
MSTCLR25
CLOCK_IN26
A06
ZEROWAIT/MEMWR
27
28
16/8/DTREQ29
+3.3V_LOGIC for BU-64XX3 or +5.0V_LOGIC for BU-64XX530
GND_LOGIC
INCMD/MCRST
31
32
A0133
TRIG_SEL/MEMENA_IN34
POL_SEL/DTACK
RT_AD_LAT
35
36
SSFLAG/EXT_TRIG37
A13* or A13/+3.3V_LOGIC** for BU-64XX3
or +5.0V_LOGIC** for BU-64XX5
77
A04
78
RTAD038
RTAD3
39 GND_XCVR
79
A14* or A14/CLK_SEL_0**80
RTAD440
* Applicable for 64K RAM option.
** Applicable for 4K RAM option.
70
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AJ-6/11-0
41
PIN
DB06
42
DB08
43
3.3V_LOGIC
GND_LOGIC
44
DB05
45
DB03
46
47 DB02
48
DB00
49
RTAD1
50
RTADP
51
FUNCTION
DB04
52
DB01
DB09
53
DB14
54
55 DB12
56
DB13
57
DB07
TX_INH_A
IOEN
INT
61 TRANS/BUFF
63
64
65
GND_LOGIC
3.3V_LOGIC69
70
RD/WR71
A0975
A12* or A12/RTBOOT**76
A05
DB10
DB15
DB11
58
59
60
SELECT
READYD62
66
STRBD
TX_INH_B
67
68
A15* or A15/CLK_SEL_1**
MSB/LSB/DTGRT72
73
74
A111
A10
TXDATA_A
PIN
RXDATA_A ***
2
FUNCTION
3
4
TXDATA_A5
MEM/REG6
A087
RXDATA_A
TXINH_B_OUT
+3.3V_LOGIC
8
9
10
TXINH_A_OUT11
TABLE 67. MINI-ACE MARK3 BU-64XX3F/G0 (TRANSCEIVERLESS) VERSION PINOUTS
A0712
A0313
UPADDREN** or NC*14
TXDATA_B15
RXDATA_B ***
TXDATA_B
A00
16
17
18
A0219
ADDR_LAT/MEMOE20
RXDATA_B21
GND_LOGIC
TAG_CLK
RTAD2
22
23
24
MSTCLR25
CLOCK_IN26
A06
ZEROWAIT/MEMWR
27
28
16/8/DTREQ29
3.3V_LOGIC30
GND_LOGIC
INCMD/MCRST
31
32
A0133
TRIG_SEL/MEMENA_IN34
POL_SEL/DTACK
RT_AD_LAT
35
36
SSFLAG/EXT_TRIG37 A13* or A13/+3.3V_LOGIC**77
A0478RTAD038
RTAD339 GND_LOGIC79
A14* or A14/CLK_SEL_0**80
RTAD440
* Applicable for 64K RAM option.
** Applicable for 4K RAM option.
*** Standard transceiverless parts have their receiver inputs internally strapped for single-ended operation. The RXDATAx pins are connected to inputs
that are not enabled.
71
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AJ-6/11-0
TABLE 68. MICRO-ACE-TE BU-64743B8/BU-648X3B(R)8 (+3.3V BGA PACKAGE) PINOUTS
SIGNAL
BALL
NC
SIGNAL
BALL
A1
NCA2
NCA3
+3.3V_XCVRA4
+3.3V_XCVRA5
MEM/REG
A6
A14* or A14/CLK_SEL_0**A7
+3.3V LOGICA8
+3.3V LOGICA9
A12* or A12/RTBOOT**A10
A15* or A15/CLK_SEL_1**A11
STRBDA12
NCA13
TX_INH_AA14
IOENA15
NCA16
NCA17
NCA18
NCB1
NCB3
NCB2
+3.3V_XCVR
B4
+3.3V_XCVRB5
MSB/LSB / DTGRT
B6
A4B7
+3.3V LOGIC
B8
+3.3V LOGIC B9
A13* or LOGIC “1”**B10
RD/WRB11
SELECTB12
NCB13
TX_INH_BB14
READYB15
NCB16
NCB17
NCB18
NCC1
NC
C2
NCC3
NC
C4
NCC5
NC
C6
TXDATA_IN_AC7
TXDATA_OUT_A
C8
A2C9
A9
C10
NCC11
A5
C12
NCC13
NC
C14
A10C15
NC
C16
NCC17
NC
C18
TX/RX-AD1
GND_XCVR/THERMAL***D3
TX/RX-A
D2
GND_XCVR/THERMAL***
D4
GND_XCVR/THERMAL***D5
NC
D6
TXDATA_IN_AD7
TXDATA_OUT_A
D8
A7D9
A8
D10
MCRSTD11
NC
D12
NCD13
SNGL_END / NC
D14
NCD15
D15
D16
TRANS/BUFFD17
INT
D18
* Applicable for 64K RAM option.
** Applicable for 4K RAM option.
*** See Thermal Management Section for important user information.
NOTES NOTES
connect to ball C8
connect to ball C7
connect to ball D8
connect to ball D7
72
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TABLE 68. MICRO-ACE-TE BU-64743B8/BU-648X3B(R)8 (+3.3V BGA PACKAGE) PINOUTS (CONT.)
SIGNAL
connect to ball E8
connect to ball E7
NOTES
BALL
TX/RX-AG1
TX/RX-A
G2
GND_XCVR/THERMAL***G3
GND_XCVR/THERMAL***
G4
GND_XCVR/THERMAL***G5
NC
G6
RXDATA_OUT_AG7
RXDATA_IN_A
G8
NCG9
GND_LOGIC
G10
GND_LOGICG11
GND_LOGIC
G12
NCG13
NC
G14
NCG15
NC
G16
D3G17
D8
G18
TX/RX-AH1
NCH3
TX/RX-A
H2
NC
H4
NCH5
NC
H6
RXDATA_OUT_AH7
RXDATA_IN_A
H8
NCH9
GND_LOGIC
H10
GND_LOGICH11
GND_LOGIC
H12
NCH13
NC
H14
NCH15
NC
H16
D5H17
D4
H18
SIGNAL
connect to ball G8
connect to ball G7
connect to ball H8
connect to ball H7
NOTES
BALL
* Applicable for 64K RAM option.
** Applicable for 4K RAM option.
*** See Thermal Management Section for important user information.
SIGNAL
BALL
TX/RX-AE1
TX/RX-A
E2
GND_XCVR/THERMAL***E3
GND_XCVR/THERMAL***
E4
GND_XCVR/THERMAL***E5
A11
E6
TXINH_IN_AE7
TXINH_OUT_A
E8
A3E9
GND_LOGIC
E10
GND_LOGICE11
GND_LOGIC
E12
NCE13
NC
E14
NCE15
D13
E16
D11E17
D10
E18
GND_XCVR/THERMAL***F1
GND_XCVR/THERMAL***
F3
GND_XCVR/THERMAL***
F2
GND_XCVR/THERMAL***
F4
GND_XCVR/THERMAL***F5
NC
F6
LOGIC 1* or UPADDREN**F7
A0
F8
NCF9
GND_LOGIC
F10
GND_LOGICF11
GND_LOGIC
F12
NCF13
TAG_CLK
F14
D14F15
D9
F16
D7F17
D12
F18
73
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AJ-6/11-0
* Applicable for 64K RAM option.
** Applicable for 4K RAM option.
*** See Thermal Management Section for important user information.
+3.3V_XCVRJ1
+3.3V_XCVR
J2
+3.3V_XCVRJ3
+3.3V_XCVR
J4
+3.3V_XCVRJ5
NC
J6
NCJ7
NC
J8
NCJ9
NC
J10
NCJ11
NC
J12
NCJ13
NC
J14
RTAD4J15
RTAD2
J16
D2J17
D6
J18
+3.3V_XCVRK1
+3.3V_XCVR
K3
+3.3V_XCVR
K2
+3.3V_XCVR
K4
+3.3V_XCVR
K5
NC
K6
NCK7
NC
K8
NCK9
NC
K10
NCK11
NC
K12
NCK13
NC
K14
NCK15
D1
K16
D0K17
RTADP
K18
TX/RX-BL1
TX/RX-B
L2
GND_XCVR/THERMAL***L3
GND_XCVR/THERMAL***
L4
GND_XCVR/THERMAL***L5
NC
L6
TXDATA_IN_BL7
TXDATA_OUT_B
L8
NCL9
NC
L10
NCL11
NC
L12
NCL13
RSTBITEN
L14
NCL15
+3.3V_LOGIC
L16
+3.3V_LOGICL17
RTAD1
L18
TX/RX-BM1
GND_XCVR/THERMAL***M3
TX/RX-B
M2
GND_XCVR/THERMAL***
M4
GND_XCVR/THERMAL***M5
NC
M6
TXDATA_IN_BM7
TXDATA_OUT_B
M8
NCM9
NC
M10
NCM11
NC
M12
NCM13
NC
M14
NCM15
+3.3V_LOGIC
M16
+3.3V_LOGICM17
RTAD3
M18
TABLE 68. MICRO-ACE-TE BU-64743B8/BU-648X3B(R)8 (+3.3V BGA PACKAGE) PINOUTS (CONT.)
SIGNAL NOTES
BALL SIGNAL
connect to ball L8
connect to ball L7
connect to ball M8
connect to ball M7
NOTES
BALL
SIGNAL
BALL
74
Data Device Corporation
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AJ-6/11-0
GND_XCVR/THERMAL***N1
GND_XCVR/THERMAL***N2
GND_XCVR/THERMAL***N3
GND_XCVR/THERMAL***N4
GND_XCVR/THERMAL***N5
NCN6
TXINH_IN_BN7
TXINH_OUT_BN8
NCN9
NCN10
NCN11
+3.3V_LOGICN12
+3.3V_LOGICN13
NCN14
NCN15
NCN16
TRIG_SEL/MEMENA_INN17
RTAD0N18
TX/RX-BP1
GND_XCVR/THERMAL***P3
TX/RX-BP2
GND_XCVR/THERMAL***P4
GND_XCVR/THERMAL***P5
NCP6
NCP7
NCP8
RXDATA_OUT_BP9
RXDATA_IN_BP10
NCP11
+3.3V_LOGICP12
+3.3V_LOGICP13
NCP14
NCP15
NCP16
INCMDP17
RT_AD_LATP18
TX/RX-BR1
TX/RX-BR2
NCR3
SLEEPINR4
NCR5
+3.3V_LOGICR6
+3.3V_LOGICR7
SSFLAG/EXT_TRIGR8
RXDATA_OUT_BR9
RXDATA_IN_BR10
GND_LOGICR11
GND_LOGICR12
GND_LOGICR13
NCR14
NCR15
NCR16
16/8 / DTREQR17
MSTCLRR18
NCT1
NCT3
NCT2
NCT4
NCT5
+3.3V_LOGICT6
+3.3V_LOGICT7
ZEROWAIT/MEMWRT8
NCT9
CLOCK_INT10
GND_LOGICT11
GND_LOGICT12
GND_LOGICT13
NCT14
NCT15
NCT16
NCT17
NCT18
* Applicable for 64K RAM option.
** Applicable for 4K RAM option.
*** See Thermal Management Section for important user information.
TABLE 68. MICRO-ACE-TE BU-64743B8/BU-648X3B(R)8 (+3.3V BGA PACKAGE) PINOUTS (CONT.)
SIGNAL
connect to ball N8
connect to ball N7
connect to ball P10
connect to ball P9
NOTES
BALL SIGNAL
connect to ball R10
connect to ball R9
NOTES
BALL
SIGNAL
BALL
75
Data Device Corporation
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TABLE 68. MICRO-ACE-TE BU-64743B8/BU-648X3B(R)8 (+3.3V BGA PACKAGE) PINOUTS (CONT.)
NOTES NOTES
NCU1
NCU2
NCU3
+3.3V_XCVRU4
+3.3V_XCVRU5
+3.3V_LOGICU6
+3.3V_LOGICU7
A1
U8
NCU9
ADDR_LAT/MEMOEU10
GND_LOGICU11
GND_LOGICU12
GND_LOGICU13
NCU14
NCU15
NC
U16
NCU17
NCU18
NCV1
NCV3
NCV2
+3.3V_XCVRV4
+3.3V_XCVRV5
+3.3V_LOGICV6
+3.3V_LOGICV7
POL_SEL/DTACKV8
A6V9
NCV10
NCV11
NCV12
NCV13
NCV14
NCV15
NCV16
NCV17
NCV18
SIGNAL
BALL SIGNAL
BALL
* Applicable for 64K RAM option.
** Applicable for 4K RAM option.
*** See Thermal Management Section for important user information.
76
Data Device Corporation
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AJ-6/11-0
BALL
TABLE 69. MICRO-ACE-TE BU-648X0B(R)3 (+5.0V BGA PACKAGE) PINOUTS
SIGNAL NOTES BALL SIGNAL NOTES
A1 NC C1 NC
A2 NC C2 NC
A3 NC C3 NC
A4 TXINH_IN_A connect to ball A5 C4 TXDATA_IN_A connect to ball C5
A5 TXINH_OUT_A connect to ball A4 C5 TXDATA_OUT_A connect to ball C4
A6 NC C6 A05
A7 +5.0V/+3.3V_LOGIC C7 A07
A8 A10 C8 TXDATA_IN_A connect to ball B8
A9 A12* or A12/RTBOOT** C9 A08
A10 A14* or A14/CLK_SEL_0** C10 A15* or A15/CLK_SEL_1**
A11 RD/WR C11 MEM/REG
A12 STRBD C12 LOGIC “1”* or UPADDREN**
A13 VDD_LOW C13 TX_INH_B
A14 TX_INH_A C14 IOEN
A15 SNGL_END C15 READYD
A16 NC C16 NC
A17 NC C17 NC
A18 NC C18 NC
B1 NC D1 TX/RX-A
B2 NC D2 TX/RX-A
B3 NC D3 GND_XCVR/THERMAL***
B4 NC D4 GND_XCVR/THERMAL***
B5 NC D5 GND_XCVR/THERMAL***
B6 NC D6 A03
B7 A09 D7 A06
B8 TXDATA_OUT_A connect to ball C8 D8 A04
B9 A11 D9 NC
B10 A13* or A13 / LOGIC “1”** D10 RXDATA_IN_A connect to ball E10
B11 MSTCLR D11 NC
B12 SELECT D12 NC
B13 MCRST D13 NC
B14 NC D14 NC
B15 NC D15 D15
B16 NC D16 TRANS/BUFF
B17 NC D17 INT
B18 NC D18 TAG_CLK
* Applicable for 64K RAM option.
** Applicable for 4K RAM option.
*** See Thermal Management Section for important user information.
77
Data Device Corporation
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BU-6474X/6484X/6486X
AJ-6/11-0
BALL
TABLE 69. MICRO-ACE-TE BU-648X0B(R)3 (+5.0V BGA PACKAGE) PINOUTS (CONT.)
SIGNAL NOTES BALL SIGNAL NOTES
E1 TX/RX-A G1 TX/RX-A
E2 GND_XCVR/THERMAL*** G2 GND_XCVR/THERMAL***
E3 GND_XCVR/THERMAL*** G3 GND_XCVR/THERMAL***
E4 GND_XCVR/THERMAL*** G4 GND_XCVR/THERMAL***
E5 GND_XCVR/THERMAL*** G5 GND_XCVR/THERMAL***
E6 NC G6 NC
E7 A01 G7 NC
E8 A02 G8 NC
E9 RXDATA_IN_A connect to ball F9 G9 NC
E10 RXDATA_OUT_A connect to ball D10 G10 NC
E11 NC G11 NC
E12 GND_LOGIC G12 GND_LOGIC
E13 GND_LOGIC G13 GND_LOGIC
E14 GND_LOGIC G14 GND_LOGIC
E15 D11 G15 D03
E16 D13 G16 D05
E17 D14 G17 D04
E18 D12 G18 D06
F1 +5.0V_XCVR H1 TX/RX-A
F2 +5.0V_XCVR H2 TX/RX-A
F3 GND_XCVR/THERMAL*** H3 GND_XCVR/THERMAL***
F4 GND_XCVR/THERMAL*** H4 GND_XCVR/THERMAL***
F5 GND_XCVR/THERMAL*** H5 GND_XCVR/THERMAL***
F6 NC H6 NC
F7 NC H7 NC
F8 NC H8 NC
F9 RXDATA_OUT_A connect to ball E9 H9 NC
F10 A00 H10 NC
F11 NC H11 NC
F12 GND_LOGIC H12 GND_LOGIC
F13 GND_LOGIC H13 GND_LOGIC
F14 GND_LOGIC H14 GND_LOGIC
F15 D09 H15 NC
F16 D10 H16 INCMD
F17 D07 H17 D00
F18 D08 H18 D02
* Applicable for 64K RAM option.
** Applicable for 4K RAM option.
*** See Thermal Management Section for important user information.
78
Data Device Corporation
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AJ-6/11-0
BALL
TABLE 69. MICRO-ACE-TE BU-648X0B(R)3 (+5.0V BGA PACKAGE) PINOUTS (CONT.)
SIGNAL NOTES BALL SIGNAL NOTES
J1 NC L1 +5.0V/+3.3V_LOGIC
J2 NC L2 +5.0V/+3.3V_LOGIC
J3 NC L3 NC
J4 NC L4 NC
J5 NC L5 NC
J6 NC L6 NC
J7 MSB/LSB / DTGRT L7 NC
J8 SSFLAG/EXT_TRIG L8 NC
J9 NC L9 ADDR_LAT/MEMOE
J10 NC L10 16/8 / DTREQ
J11 NC L11 TRIG_SEL/MEMENA_IN
J12 NC L12 NC
J13 NC L13 NC
J14 NC L14 NC
J15 NC L15 +5.0V/+3.3V_LOGIC
J16 RTAD4 L16 +5.0V/+3.3V_LOGIC
J17 D01 L17 RTAD2
J18 RTADP L18 RT_AD_LAT
K1 NC M1 NC
K2 NC M2 NC
K3 NC M3 +5.0V/+3.3V_LOGIC
K4 NC M4 NC
K5 NC M5 NC
K6 NC M6 NC
K7 NC M7 NC
K8 NC M8 NC
K9 NC M9 CLOCK_IN
K10 NC M10 ZEROWAIT/MEMWR
K11 NC M11 NC
K12 NC M12 TXDATA_OUT_B connect to ball N12
K13 NC M13 RXDATA_IN_B connect to ball M14
K14 NC M14 RXDATA_OUT_B connect to ball M13
K15 NC M15 NC
K16 RTAD0 M16 NC
K17 RTAD3 M17 NC
K18 RTAD1 M18 RSTBITEN
* Applicable for 64K RAM option.
** Applicable for 4K RAM option.
*** See Thermal Management Section for important user information.
79
Data Device Corporation
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BALL
TABLE 69. MICRO-ACE-TE BU-648X0B(R)3 (+5.0V BGA PACKAGE) PINOUTS (CONT.)
SIGNAL NOTES BALL SIGNAL NOTES
N1 NC R1 NC
N2 NC R2 NC
N3 NC R3 NC
N4 NC R4 +5.0V_RAM* or NC**
N5 NC R5 NC
N6 NC R6 NC
N7 NC R7 NC
N8 NC R8 TXINH_OUT_B connect to ball T8
N9 POL_SEL/DTACK R9 +5.0V/+3.3V_LOGIC
N10 NC R10 TXDATA_IN_B connect to ball P10
N11 NC R11 GND_XCVR/THERMAL***
N12 TXDATA_IN_B connect to ball M12 R12 GND_XCVR/THERMAL***
N13 RXDATA_IN_B connect to ball N14 R13 GND_XCVR/THERMAL***
N14 RXDATA_OUT_B connect to ball N13 R14 GND_XCVR/THERMAL***
N15 NC R15 GND_XCVR/THERMAL***
N16 NC R16 NC
N17 NC R17 NC
N18 NC R18 NC
P1 NC T1 NC
P2 NC T2 NC
P3 NC T3 NC
P4 +5.0V_RAM* or NC** T4 NC
P5 NC T5 NC
P6 NC T6 NC
P7 +5.0V/+3.3V_LOGIC T7 NC
P8 NC T8 TXINH_IN_B connect to ball R8
P9 +5.0V/+3.3V_LOGIC T9 NC
P10 TXDATA_OUT_B connect to ball R10 T10 NC
P11 GND_XCVR/THERMAL*** T11 GND_XCVR/THERMAL***
P12 GND_XCVR/THERMAL*** T12 GND_XCVR/THERMAL***
P13 GND_XCVR/THERMAL*** T13 GND_XCVR/THERMAL***
P14 GND_XCVR/THERMAL*** T14 GND_XCVR/THERMAL***
P15 GND_XCVR/THERMAL*** T15 GND_XCVR/THERMAL***
P16 NC T16 NC
P17 NC T17 NC
P18 NC T18 NC
* Applicable for 64K RAM option.
** Applicable for 4K RAM option.
*** See Thermal Management Section for important user information.
80
Data Device Corporation
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AJ-6/11-0
BALL
TABLE 69. MICRO-ACE-TE BU-648X0B(R)3 (+5.0V BGA
PACKAGE) PINOUTS (CONT.)
SIGNAL NOTES
U1 NC
U2 NC
U3 NC
U4 NC
U5 NC
U6 NC
U7 NC
U8 NC
U9 NC
U10 NC
U11 TX/RX-B
U12 GND_XCVR/THERMAL***
U13 +5.0V_XCVR
U14 GND_XCVR/THERMAL***
U15 TX/RX-B
U16 NC
U17 NC
U18 NC
V1 NC
V2 NC
V3 NC
V4 NC
V5 NC
V6 NC
V7 NC
V8 +5.0V/+3.3V_LOGIC
V9 NC
V10 NC
V11 TX/RX-B
V12 TX/RX-B
V13 +5.0V_XCVR
V14 TX/RX-B
V15 TX/RX-B
V16 NC
V17 NC
V18 NC
* Applicable for 64K RAM option.
** Applicable for 4K RAM option.
*** See Thermal Management Section for important user information.
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BALL PAIRS WIRED
TOGETHER
BALL PAIRS WIRED
TOGETHER
(R)TABLE 70. MICRO-ACE-TE BU-64863B8-600 (BGA PACKAGE) “DAISY CHAIN”
MECHANICAL SAMPLE CONNECTIONS
A1-A2
A3-A4
A5-A6
A7-A8
A9-A10
A11-A12
A13-A14
A15-A16
A17-A18
B1-B2
B3-B4
B5-B6
B7-B8
B9-B10
B11-B12
B13-B14
E1-E2
E3-E4
E5-E6
E7-E8
E9-E10
E11-E12
E13-E14
E15-E16
E17-E18
F1-F2
F3-F4
F5-F6
F7-F8
F9-F10
F11-F12
F13-F14
F15-F16
F17-F18
G1-G2
G3-G4
G5-G6
G7-G8
G9-G10
G11-G12
G13-G14
G15-G16
G17-G18
H1-H2
H3-H4
H5-H6
H7-H8
H9-H10
H11-H12
H13-H14
H15-H16
H17-H18
J1-J2
J3-J4
J5-J6
J7-J8
J9-J10
J11-J12
J13-J14
J15-J16
J17-J18
K1-K2
K3-K4
K5-K6
K7-K8
K9-K10
K11-K12
K13-K14
K15-K16
K17-K18
L1-L2
L3-L4
L5-L6
L7-L8
L9-L10
L11-L12
L13-L14
L15-L16
L17-L18
M1-M2
M3-M4
M5-M6
M7-M8
M9-M10
M11-M12
M13-M14
M15-M16
M17-M18
N1-N2
N3-N4
N5-N6
N7-N8
N9-N10
N11-N12
N13-N14
N15-N16
N17-N18
P1-P2
P3-P4
P5-P6
P7-P8
P9-P10
P11-P12
P13-P14
P15-P16
P17-P18
R1-R2
R3-R4
R5-R6
R7-R8
R9-R10
R11-R12
R13-R14
R15-R16
R17-R18
T1-T2
T3-T4
T5-T6
T7-T8
T9-T10
T11-T12
T13-T14
T15-T16
T17-T18
U1-U2
U3-U4
U5-U6
U7-U8
U9-U10
U11-U12
U13-U14
U15-U16
U17-U18
V1-V2
V3-V4
V5-V6
V7-V8
V9-V10
V11-V12
V13-V14
V15-V16
V17-V18
BALL PAIRS WIRED
TOGETHER
BALL PAIRS WIRED
TOGETHER
BALL PAIRS WIRED
TOGETHER
B15-B16
B17-B18
C1-C2
C3-C4
C5-C6
C7-C8
C9-C10
C11-C12
C13-C14
C15-C16
C17-C18
D1-D2
D3-D4
D5-D6
D7-D8
D9-D10
D11-D12
D13-D14
D15-D16
D17-D18
82
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P1 PIN #
TABLE 71. BU-64863E8 EVALUATION BOARD PINOUTS
MADE FROM 80-PIN MINI-ACE MARK3 BU-64863G8 BC/RT/MT 64K RAM
DEVICE PIN # FUNCTION P2 PIN # DEVICE PIN # FUNCTION
12A10 1 -NC
21A11 2 -NC
36MEM/REG 3 -STUB_TX/RX_B
47A08 4 -STUB_TX/RX_B
518 A00 5 22, 31, 50, 70, 79 GND
613 A03 6 22, 31, 50, 70, 79 GND
719 A02 7 -STUB_TX/RX_B
812 A07 8 -STUB_TX/RX_B
980 A14 9 -NC
10 22, 31, 50, 70, 79 GND 10 -NC
11 22, 31, 50, 70, 79 GND 11 -+3.3V_XFMR_CT
12 22, 31, 50, 70, 79 GND 12 -+3.3V_XFMR_CT
13 77 A13 13 10 +3.3V_XCVR
14 78 A04 14 10 +3.3V_XCVR
15 75 A09 15 -NC
16 76 A12 16 -NC
17 73 A15 17 -STUB_TX/RX_A
18 74 A05 18 -STUB_TX/RX_A
19 71 RD/WR 19 22, 31, 50, 70, 79 GND
20 72 MSB/LSB / DTGRT 20 22, 31, 50, 70, 79 GND
21 30, 51, 69 +3.3V_LOGIC 21 -STUB_TX/RX_A
22 30, 51, 69 +3.3V_LOGIC 22 -STUB_TX/RX_A
23 68 STRBD 23 -NC
24 -NC 24 -NC
25 66 SELECT
26 67 TX_INH_B
27 64 IOEN
28 65 TX_INH_A
29 62 READYD
30 63 INT
31 -NC
32 61 TRANS/BUFF
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P3 PIN #
TABLE 71. BU-64863E8 EVALUATION BOARD PINOUTS (CONT.)
MADE FROM 80-PIN MINI-ACE MARK3 BU-64863G8 BC/RT/MT 64K RAM
DEVICE PIN # FUNCTION P4 PIN # DEVICE PIN # FUNCTION
114 SLEEPIN 1 41 D06
220 ADDR_LAT/MEMOE 2 -NC
322, 31, 50, 70, 79 GND 3 43 D04
4-NC 4 42 D01
530, 51, 69 +3.3V_LOGIC 5 45 RTAD1
630, 51, 69 +3.3V_LOGIC 6 44 RTADP
722, 31, 50, 70, 79 GND 7 47 D02
822, 31, 50, 70, 79 GND 8 46 D00
922, 31, 50, 70, 79 GND 9 49 D05
10 23 TAG_CLK 10 48 D03
11 24 RTAD2 11 22, 31, 50, 70, 79 GND
12 22, 31, 50, 70, 79 GND 12 22, 31, 50, 70, 79 GND
13 25 MSTCLR 13 30, 51, 69 +3.3V_LOGIC
14 26 CLOCK_IN 14 30, 51, 69 +3.3V_LOGIC
15 22, 31, 50, 70, 79 GND 15 52 D08
16 27 A06 16 53 D07
17 28 ZEROWAIT/MEMWR 17 54 D13
18 29 16/8 / DTREQ 18 55 D12
19 30, 51, 69 +3.3V_LOGIC 19 56 D14
20 30, 51, 69 +3.3V_LOGIC 20 57 D09
21 -NC 21 58 D11
22 -NC 22 59 D15
23 32 INCMD/MCRST 23 60 D10
24 33 A01 24 -NC
25 34 TRIG_SEL/MEMENA_IN
26 35 POL_SEL/DTACK
27 36 RT_AD_LAT
28 37 SSFLAG/EXT_TRIG
29 38 RTAD0
30 39 RTAD3
31 -NC
32 40 RTAD4
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P1 PIN #
TABLE 72. BU-61860E3 EVALUATION BOARD PINOUTS
MADE FROM 128-BALL µ-ACE (MICRO-ACE) BU-61860B3 BC/RT/MT 64K RAM
DEVICE PIN # FUNCTION P2 PIN # DEVICE PIN # FUNCTION
1A6 A10 1 -DIR_TX/RX_B
2B7 A11 2 -DIR_TX/RX_B
3B13 MEM/REG 3 -STUB_TX/RX_B
4B5 A08 4 -STUB_TX/RX_B
5A1 A00 5A9,B9,C17,C18,E2,F2,G2,K17,
K18,U4,U9,U13,U14,U15,V1,V4 GND
6B3 A03
6A9,B9,C17,C18,E2,F2,G2,K17,
K18,U4,U9,U13,U14,U15,V1,V4 GND
7A2 A02
7-STUB_TX/RX_B
8A5 A07
8-STUB_TX/RX_B
9B10 A14
9-DIR_TX/RX_B
10 A9,B9,C17,C18,E2,F2,G2,K17,
K18,U4,U9,U13,U14,U15,V1,V4 GND
10 -DIR_TX/RX_B
11 A9,B9,C17,C18,E2,F2,G2,K17,
K18,U4,U9,U13,U14,U15,V1,V4 GND 11 -NC
12 A9,B9,C17,C18,E2,F2,G2,K17,
K18,U4,U9,U13,U14,U15,V1,V4 GND 12 -NC
13 A10 A13
13 E1,F1,G1 +5.0V Vcc CH A
14 A3 A04
14 E1,F1,G1 +5.0V Vcc CH A
15 B6 A09
15 -DIR_TX/RX_A
16 A7 A12
16 -DIR_TX/RX_A
17 A11 A15
17 -STUB_TX/RX_A
18 B4 A05
18 STUB_TX/RX_A
19 A12 RD/WR 19 A9,B9,C17,C18,E2,F2,G2,K17,
K18,U4,U9,U13,U14,U15,V1,V4 GND
20 U6 MSB/LSB / DTGRT 20 A9,B9,C17,C18,E2,F2,G2,K17,
K18,U4,U9,U13,U14,U15,V1,V4 GND
21 A8,A16,B8,B16,L1,L2,L17,L18,
U3,V3 +5.0V_LOGIC 21 -STUB_TX/RX_A
22 A8,A16,B8,B16,L1,L2,L17,L18,
U3,V3 +5.0V_LOGIC 22 -STUB_TX/RX_A
23 B14 STRBD
23 -DIR_TX/RX_A
24 -NC
24 -DIR_TX/RX_A
25 B12 SELECT
26 A15 TX_INH_B
27 A17 IOEN
28 A14 TX_INH_A
29 B15 READYD
30 A18 INT
31 B18 TAG_CLK
32 B17 TRANS/BUFF
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P3 PIN #
TABLE 72. BU-61860E3 EVALUATION BOARD PINOUTS (CONT.)
MADE FROM 128-BALL µ-ACE (MICRO-ACE) BU-61860B3 BC/RT/MT 64K RAM
DEVICE PIN # FUNCTION P4 PIN # DEVICE PIN # FUNCTION
1N2 UPADDREN 1 J18 D06
2V8 ADDR_LAT/MEMOE 2 P17 RSTBITEN
3A9,B9,C17,C18,E2,F2,G2,K17,
K18,U4,U9,U13,U14,U15,V1,V4 GND 3M18 D04
4V2 VDD_LOW
4M17 D01
5A8,A16,B8,B16,L1,L2,L17,L18,
U3,V3 +5.0V_LOGIC
5V18 RTAD1
6A8,A16,B8,B16,L1,L2,L17,L18,
U3,V3 +5.0V_LOGIC
6T18 RTADP
7A9,B9,C17,C18,E2,F2,G2,K17,
K18,U4,U9,U13,U14,U15,V1,V4 GND
7G18 D02
8A9,B9,C17,C18,E2,F2,G2,K17,
K18,U4,U9,U13,U14,U15,V1,V4 GND
8H18 D00
9A9,B9,C17,C18,E2,F2,G2,K17,
K18,U4,U9,U13,U14,U15,V1,V4 GND
9H17 D05
10 -NC
10 G17 D03
11 U17 RTAD2
11 A9,B9,C17,C18,E2,F2,G2,K17,
K18,U4,U9,U13,U14,U15,V1,V4 GND
12 A9,B9,C17,C18,E2,F2,G2,K17,
K18,U4,U9,U13,U14,U15,V1,V4 GND
12 A9,B9,C17,C18,E2,F2,G2,K17,
K18,U4,U9,U13,U14,U15,V1,V4 GND
13 B11 MSTCLR
13 A8,A16,B8,B16,L1,L2,L17,L18,
U3,V3 +5.0V_LOGIC
14 V9 CLOCK_IN
14 A8,A16,B8,B16,L1,L2,L17,L18,
U3,V3 +5.0V_LOGIC
15 A9,B9,C17,C18,E2,F2,G2,K17,
K18,U4,U9,U13,U14,U15,V1,V4 GND
15 F18 D08
16 A4 A06
16 F17 D07
17 U8 ZEROWAIT/MEMWR
17 J17 D13
18 V7 16/8 / DTREQ
18 E18 D12
19 A8,A16,B8,B16,L1,L2,L17,L18,
U3,V3 +5.0V_LOGIC
19 D18 D14
20 A8,A16,B8,B16,L1,L2,L17,L18,
U3,V3 +5.0V_LOGIC
20 N18 D09
21 V13,V14,V15 +5.0V Vcc CH B
21 E17 D11
22 V13,V14,V15 +5.0V Vcc CH B
22 D17 D15
23 M1 INCMD
23 N17 D10
24 B1 A01
24 A13 MCRST
25 V6 TRIG_SEL/MEMENA_IN
26 U7 POL_SEL/DTACK
27 P18 RT_AD_LAT
28 T2 SSFLAG/EXT_TRIG
29 V17 RTAD0
30 U18 RTAD3
31 -NC
32 T17 RTAD4
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U2
T2 T1
P1 P3
P4
P2
0.100 [2.54]
1.600 [40.64]
0.100
[2.54]
2.200 [55.88]
2.300 [58.42]
2.515 [63.88]
(MAX)
0.062 (1.57)
4X 0.230
[5.84]
0.350 [8.89]
(MAX)
31
32
29
30
27
28
25
26
23
24
21
22
19
20
17
18
15
16
13
14
11
12
9
10
7
8
5
6
3
4
1
2
31
32
29
30
27
28
25
26
23
24
21
22
19
20
17
18
15
16
13
14
11
12
9
10
7
8
5
6
3
4
1
2
23
24
21
22
19
20
17
18
15
16
13
14
11
12
9
10
7
8
5
6
3
4
1
2
23
24
21
22
19
20
17
18
15
16
13
14
11
12
9
10
7
8
5
6
3
4
1
2
U2
S/N
DC
0.100
[2.54]
2.015 [51.18]
(MAX)
1.700 [43.18]
2 X 11 EQUAL SPACES @
0.100 [2.54] = 1.100 [27.94]
(TOL NON-CUM)
0.150 [3.81]
2 X 0.300 [7.62]
2X 15 EQUAL SP @
0.100 [2.54]=
1.500 [38.10]
(TOL-NONCUM)
2X 0.600 [15.24]
0.350 [8.89]
(MAX)
112 X 0.025 ±.001
[0.64]
112 X 0.025 ±.001
[0.64]
112 X 0.025 ±.001
[0.64]
FIGURE 19. BU-61860E3 +5.0V µ-ACE (MICRO-ACE) & TRANSFORMER EVALUATION BOARD
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T2 T1
P1 P3
P4
P2
112 X 0.025 ±.001
[0.64]
0.100 [2.54]
1.600 [40.64]
0.100
[2.54]
2.200 [55.88]
2.300 [58.42]
2.515 [63.88]
(MAX)
0.062 (1.57)
4X 0.230
[5.84]
0.350 [8.89]
(MAX)
31
32
29
30
27
28
25
26
23
24
21
22
19
20
17
18
15
16
13
14
11
12
9
10
7
8
5
6
3
4
1
2
31
32
29
30
27
28
25
26
23
24
21
22
19
20
17
18
15
16
13
14
11
12
9
10
7
8
5
6
3
4
1
2
23
24
21
22
19
20
17
18
15
16
13
14
11
12
9
10
7
8
5
6
3
4
1
2
23
24
21
22
19
20
17
18
15
16
13
14
11
12
9
10
7
8
5
6
3
4
1
2
S/N
DC
0.100
[2.54]
2.015 [51.18]
(MAX)
1.700 [43.18]
2 X 11 EQUAL SPACES @
0.100 [2.54] = 1.100 [27.94]
(TOL NON-CUM)
0.150 [3.81]
2 X 0.300 [7.62]
2X 15 EQUAL SP @
0.100 [2.54]=
1.500 [38.10]
(TOL-NONCUM)
2X 0.600 [15.24]
U1
0.350 [8.89]
(MAX)
FIGURE 20. BU-64863E8 MINI-ACE MARK3 (+3.3 VOLT) & TRANSFORMER EVALUATION BOARD
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#1
4 X 0.880 (22.35)
REF
PIN #1 DENOTED
BY INDEX MARK
#20
#21
#41
#60
#61
#80
PIN #1 DENOTED
BY INDEX MARK
PIN NUMBERS FOR
REFERENCE ONLY
4 X 19 EQUAL SP @
0.040 (1.016) = 0.760 (19.304)
(TOL. NON-CUM.)
0.015 (0.381)
TYP.
#40
0.006 (0.152)
+0.010
- 0.004
(+0.254)
(- 0.102)
1.110 (28.194)
0.010 (0.254)
MAX.
0.130 (3.302)
MAX.
0.060 (1.524)
MAX.
4 X 0.060 (1.524)
0.004 (0.102)
± 0.015
SIDE VIEW
TOP VIEW
Notes:
1) Dimensions are in inches (mm).
2) Tolerances = ±0.005 inches unless otherwise specified.
3) Package Material: Alumina (AL203)
4) Lead Material: Kovar, Plated by 50µ in. minimum nickel under 60µ in. minimum gold.
FIGURE 21. MECHANICAL OUTLINE DRAWING FOR MINI-ACE MARK3 80-PIN GULL WING PACKAGE
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FIGURE 22. MECHANICAL OUTLINE DRAWING FOR MINI-ACE MARK3 80-PIN FLAT PACKAGE
#1
Notes:
1) Dimensions are in inches (mm).
2) Tolerances = ±0.005 inches unless otherwise specified.
3) Package Material: Alumina (AL203)
4) Lead Material: Kovar, Plated by 50µ in. minimum nickle under 60µ in. minimum gold.
4 X 19 EQUAL SP @
0.040 (1.016) = 0.760 (19.304)
(TOL. NON-CUM.)
TOP VIEW
SIDE VIEW
#20
#21
#41
#60
#61
#80
PIN NUMBERS FOR
REFERENCE ONLY
4 X 0.890 (22.606)
MAX.
0.015 (0.381)
TYP.
#40
2 X 1.88 (47.75)
4 X 0.200 (5.08)
2 X 2.36 (59.94)
REF.
0.500 (12.7)
REF
0.050 (1.27)
0.008 (0.2032)
0.025 (0.635)
0.130 (3.302)
MAX.
±0.02
±0.002
4 X 0.060 (1.524)
0.910 (23.114)
MAX.
PIN #1 DENOTED
BY INDEX MARK
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.0394 [1.00]
(TYP)
.815 [20.70]
(MAX)
SQUARE
.670 [17.02]
(TYP)
17 EQ. SP. @
.0394 [1.00] = .670 [17.02]
(TOL NONCUM)
(TYP)
.065 [1.65]
(TYP)
.065 [1.65]
(TYP)
Triangle denotes
Ball A1
V U T R P N M L K J H G F E D C B A
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
.022 [0.56] DIA
B = Sn/Pb (63/37) BALL
R = Sn/Ag/Cu (96.5/3.0/0.5) BALL
0.120 [3.05]
(MAX)
BOTTOM VIEW
SIDE VIEW
Notes:
1) Dimensions are in inches (mm).
2) Cover material: Diallyl Phthalate (DAP).
3) Base material: FR4 PC board.
4) Solder Ball Cluster to be centralized within ±.010 of outline dimensions.
5) The copper pads (324 places) on the bottom of the BGA package are .025” (0.635 mm)
in diameter prior to processing. Final ball size is .022” (0.56 mm) after processing (typical).
0.015 [0.38]
(REF)
Cover Material
Diallyl Phthalate (DAP)
FR4 P.C. Board
FIGURE 23. MECHANICAL OUTLINE DRAWING FOR MICRO-ACE-TE BGA PACKAGE
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ORDERING INFORMATION FOR MINI-ACE MARK3
BU-64XXXXX-XXXX
Supplemental Process Requirements:
S = Pre-Cap Source Inspection
L = 100% Pull Test
Q = 100% Pull Test and Pre-Cap Source Inspection
K = One Lot Date Code
W = One Lot Date Code and Pre-Cap Source Inspection
Y = One Lot Date Code and 100% Pull Test
Z = One Lot Date Code, Pre-Cap Source Inspection and 100% Pull Test
Blank = None of the Above
Test Criteria:
0 = Standard Testing
1 = X-Ray
2 = MIL-STD-1760 Amplitude Compliant (not available with Voltage/Transceiver Options 0 “Transceiverless”
or 4/9/D “McAir compatible”)
3 = MIL-STD-1760 and X-Ray
Process Requirements:
0 = Standard DDC practices, no Burn-In
1 = MIL-PRF-38534 Compliant (note 3)
2 = B (note 1)
3 = MIL-PRF-38534 Compliant (note 3) with PIND Testing
4 = MIL-PRF-38534 Compliant (note 3) with Solder Dip
5 = MIL-PRF-38534 Compliant (note 3) with PIND Testing and Solder Dip
6 = B (note 1) with PIND Testing
7 = B (note 1) with Solder Dip
8 = B (note 1) with PIND Testing and Solder Dip
9 = Standard DDC Processing with Solder Dip, no Burn-In (see table on next page)
Temperature Range (note 2)/Data Requirements:
1 = -55°C to +125°C
2 = -40°C to +85°C
3 = 0°C to +70°C
4 = -55°C to +125°C with Variables Test Data
5 = -40°C to +85°C with Variables Test Data
6 = Custom Part (Reserved)
7 = Custom Part (Reserved)
8 = 0°C to +70°C with Variables Test Data
Voltage/Transceiver Option:
0 = Transceiverless (contact factory for availability)
3 = +5.0 Volts rise/fall times = 100 to 300 ns (-1553B)
4 = +5.0 Volts rise/fall times = 200 to 300 ns (-1553B and McAir compatible. Not available with
Test Criteria option 2 “MIL-STD-1760 Amplitude Compliant”)
8 = +3.3 Volts rise/fall times = 100 to 300 ns (-1553B) (note 5)
(Not available with Logic/RAM Voltage option 5 “+5.0 Volt”.)
9 = +3.3 Volts rise/fall times = 200 to 300 ns (-1553B and McAir compatible. Not available with
Test Criteria option 2 “MIL-STD-1760 Amplitude Compliant” or with Logic/RAM Voltage
option 5 “+5.0 Volt”.) (note 5)
C = +3.3 Volts rise/fall times = 100 to 300 ns (-1553B) (note 6)
(Not available with Logic/RAM Voltage option 5 “+5.0 Volt”.)
D = +3.3 Volts rise/fall times = 200 to 300 ns (-1553B and McAir compatible. Not available with Test Criteria
option 2 “MIL-STD-1760 Amplitude Compliant” or with Logic/RAM Voltage option 5 “+5.0 Volt”.) (note 6)
Package Type:
F = 80-Lead Flat Pack
G = 80-Lead “Gull Wing” (Formed Lead)
Logic / RAM Voltage:
3 = 3.3 Volt
5 = 5.0 Volt (applicable only for BU-64745 and BU-64845)
Product Type (see next page for Product Matrix):
BU-6474 = RT only with 4K RAM
BU-6484 = BC /RT / MT with 4K x 16 RAM
BU-6486 = BC /RT / MT with 64K x 17 RAM
Notes:
1. Standard DDC processing with burn-in and full temp test. See table on next page.
2. Temperature Range applies to case temperature.
3. MIL-PRF-38534 product grading is designated with the following dash numbers:
Class H is a -11X, 13X, 14X, 15X, 41X, 43X, 44X, 45X
Class G is a -21X, 23X, 24X, 25X, 51X, 53X, 54X, 55X
Class D is a -31X, 33X, 34X, 35X, 81X, 83X, 84X, 85X
4. The above products contain tin-lead solder finish as applicable to solder dip
requirements.
5. Transformer center-tap connected to +3.3V_XCVR, see FIGURE 15 (Obsolete)
6. Transformer center-tap connected to GND, see FIGURE 16
92
Data Device Corporation
www.ddc-web.com
BU-6474X/6484X/6486X
AJ-6/11-0
4K x 16 3.3 V 5.0 V3.3 VBU-64743X3
4K x 16 3.3 V 5.0 V3.3 VBU-64743X4
4K x 16 3.3 V 3.3 V3.3 VBU-64743X8
4K x 16 3.3 V 3.3 V3.3 VBU-64743X9
4K x 16 5.0 V 5.0 V5.0 VBU-64745X3
4K x 16 5.0 V 5.0 V5.0 VBU-64745X4
4K x 16 3.3 V 5.0 V3.3 VBU-64843X3
4K x 16 3.3 V 5.0 V3.3 VBU-64843X4
4K x 16 3.3 V 3.3 V3.3 VBU-64843X8
4K x 16 3.3 V 3.3 V3.3 VBU-64843X9
4K x 16 5.0 V 5.0 V5.0 VBU-64845X3
4K x 16 5.0 V 5.0 V5.0 VBU-64845X4
64K x 17 3.3 V 5.0 V3.3 VBU-64863X3
64K x 17 3.3 V 5.0 V3.3 VBU-64863X4
64K x 17 3.3 V 3.3 V3.3 VBU-64863X8
64K x 17 3.3 V 3.3 V3.3 VBU-64863X9
MEMORY TRANSCEIVER
VOLTAGE
RAM VOLTAGELOGIC VOLTAGEPART NUMBER
MINI-ACE MARK3 PRODUCT MATRIX
TABLE 11015 (note 1), 1030 (note 2)
BURN-IN
Notes:
1. For Process Requirement "B" (refer to ordering information), devices may be non-compliant with MIL-
STD-883, Test Method 1015, Paragraph 3.2. Contact factory for details.
2. When applicable.
3000g2001CONSTANT ACCELERATION
C1010TEMPERATURE CYCLE
A and C1014SEAL
—2009, 2010, 2017, and 2032INSPECTION
CONDITION(S)METHOD(S)
MIL-STD-883
TEST
STANDARD DDC PROCESSING
FOR HYBRID AND MONOLITHIC HERMETIC PRODUCTS
4K x 16 3.3 V 3.3 V3.3 VBU-64743XC
4K x 16 3.3 V 3.3 V3.3 VBU-64743XD
4K x 16 3.3 V 3.3 V3.3 VBU-64843XC
4K x 16 3.3 V 3.3 V3.3 VBU-64843XD
64K x 17 3.3 V 3.3 V3.3 VBU-64863XC
64K x 17 3.3 V 3.3 V3.3 VBU-64863XD
93
Data Device Corporation
www.ddc-web.com
BU-6474X/6484X/6486X
AJ-6/11-0
ORDERING INFORMATION FOR MICRO-ACE-TE (NOTE 3)
BU-6XXXXBX-E0X
Test Criteria:
0 = 18V Amplitude, only available with “Voltage transceiver option = 4”
2 = MIL-STD-1760 Amplitude Compliant, Standard
Process Requirements:
0 = Standard DDC practices, no Burn-In
Temperature Range (note 2) /Data Requirements:
E = -40°C to +100°C
Voltage/Transceiver Option:
3 = +5.0 Volts rise/fall times = 100 to 300 ns (1553B)
4 = +5.0 Volts 200 to 300 ns rise/fall times, 1553 and McAir compatible
(not available with “Test Criteria option = 2”)
8 = +3.3 Volts rise/fall times = 100 to 300 ns (1553B) (note 5)
C = +3.3 Volts rise/fall times = 100 to 300 ns (1553B) (note 6)
Package Type:
B = 324-ball BGA Package
R = RoHS Compliant 324-ball BGA Package
Logic / RAM Voltage:
0 = 3.3 Volt or +5.0 Volt logic
(For BU-64860, 64K x 17 RAM voltage is always +5.0V)
3 = 3.3 Volt
Product Type (see Product Matrix):
BU-6474 = RT only with 4K x 16 RAM
BU-6484 = BC /RT / MT with 4K x 16 RAM
BU-6486 = BC /RT / MT with 64K x 17 RAM
Notes:
1. See Application Note AN/B-37 for SSRT implementation. option if using BU-6484x (BC/RT/MT) with 4K x 16 RAM
2. Temperature range applies to ball temperature.
3. See Micro-ACE TE Product Matrix below for valid ordering options.
4. Unless otherwise specified these products contain tin lead solder
5. Transformer center-tap connected to +3.3V_XCVR, see FIGURE 15 (Obsolete)
6. Transformer center-tap connected to GND, see FIGURE 16
B1010TEMPERATURE CYCLE
—
2010, 2017, and 2032
INSPECTION
CONDITION(S)METHOD(S)
MIL-STD-883
TEST
STANDARD DDC PROCESSING
FOR BGA PRODUCTS
BU-64743B8-E02 3.3V
BU-64843B(R)8-E02 3.3V
BU-64860B(R)3-E02 3.3V or 5.0V
MICRO-ACE TE PRODUCT MATRIX
PART NUMBER LOGIC
VOLTAGE
3.3V
3.3V
5.0V
RAM
VOLTAGE
MEMORY
BU-64840B3-E02 3.3V or 5.0V
4K x 16
4K x 16
64K x 17
4K x 16 Same as Logic
3.3V
3.3V
5.0V
TRANSCEIVER
VOLTAGE
5.0V
SPECIAL ORDER
MIN QTY
MAY APPLY
X
X
BU-64863B(R)8-E02 3.3V 64K x 17 3.3V 3.3V
BU-64860B(R)4-E00 3.3V or 5.0V 64K x 17 5.0V 5.0V
BU-64843B(R)C-E02 3.3V 3.3V
4K x 16 3.3V
BU-64863B(R)C-E02 3.3V 64K x 17 3.3V 3.3V
94
AJ-6/11-0 PRINTED IN THE U.S.A.
DATA DEVICE CORPORATION
REGISTERED TO ISO 9001:2000
FILE NO. A5976
R
E
G
I
S
T
E
R
E
D
F
I
R
M
®
U
105 Wilbur Place, Bohemia, New York, U.S.A. 11716-2426
For Technical Support - 1-800-DDC-5757 ext. 7771
Headquarters, N.Y., U.S.A. - Tel: (631) 567-5600, Fax: (631) 567-7358
United Kingdom - Tel: +44-(0)1635-811140, Fax: +44-(0)1635-32264
France - Tel: +33-(0)1-41-16-3424, Fax: +33-(0)1-41-16-3425
Germany - Tel: +49-(0)89-15 00 12-11, Fax: +49-(0)89-15 00 12-22
Japan - Tel: +81-(0)3-3814-7688, Fax: +81-(0)3-3814-7689
Asia -Tel: +65-6489-4801
World Wide Web - http://www.ddc-web.com
The information in this data sheet is believed to be accurate; however, no responsibility is
assumed by Data Device Corporation for its use, and no license or rights are
granted by implication or otherwise in connection therewith.
Specifications are subject to change without notice.
Please visit our Web site at www.ddc-web.com for the latest information.
ORDERING INFORMATION FOR MICRO-ACE-TE MECHANICAL SAMPLE
BU-64863B8-600
MICRO-ACE-TE (324 Ball BGA) Mechanical Sample, with "daisy chain" connections of alternating balls,
for use in environmental (mechanical / thermal) integrity testing.
ORDERING INFORMATION FOR +5.0V TRANSCEIVER EVALUATION BOARD
BU-61860E3-300
Evaluation board intended to support customers who are interested in electrically connecting and
evaluating the performance of +5.0V Enhanced Mini-ACE and/or +5.0V µ-ACE (MICRO-ACE)
series of products.
ORDERING INFORMATION FOR +3.3V TRANSCEIVER EVALUATION BOARD
BU-64863E8-300
Evaluation board intended to support customers who are interested in electrically connecting and
evaluating the performance of the +3.3V Mini-ACE Mark3 and/or +3.3V MICRO-ACE-TE series of
products.
RECORD OF CHANGE
For BU-64743 Data Sheet
Revision
Date
Pages
Description
AD
3/2009
87, 88
Added notes 3 & 4 on figures 20 & 21
AE
6/2009
45, 47
Replaced Tables 46 and 47
AF
10/2009
92
Changed to "Package Type" ordering description.
FROM:
R = Lead Free 324-ball BGA Package
TO:
R = RoHS Compliant 324-ball BGA Package
AG
4/2010
5, 44, 45,
Table 46 (MLP-3233 & MLP-3333 - From:
"SMT" To: "Through Hole"
Figure 15 ( Deleted "BETA LVB-4103" &
"BETA LVB-4203")
Added NOT Bar to all occurren ces of "R TBOO T"
Table 1 (Therm al - 324 BALL BGA PACKAGE)
From: Maximum peak temperature of Solder
Reflow Profile +260°C
To: The reflow profile detailed in IPC/JEDEC
J-STD-020 is applicable for both leaded and lead-
free products +245°C
(PHYSICAL CHARACTERISTICS - Micro-
ACE-TE)
Added: Electrostatic Discharge Sensitivity
ESD Class 0
AJ
6/2011
2, 39, 44, 45, 47,
90, 91, 92
Updated Figures 1 and 12.
Added Figure 16 (BU-64XXXX8/9). Incremented
all following Figure numbers. Update to Figure
17.
Replaced Table 46 and corresponding description.
Added Options “C” and “D”, and notes 5 and 6 to
Ordering Information for Mini-ACE Mark3.
Added Option “C” and notes to Ordering
Information for Micro-ACE-TE
