PD97401 IR3640MPBF HIGH FREQUENCY SYNCHRONOUS PWM BUCK CONTROLLER Features Description * * * * * * The IR3640M is a synchronous Buck PWM controller * * * * * * * * * * * * * 4.5V to 5.5V external supply Wide Input voltage from 1.5V to 24V Output voltage range: 0.7V to 0.9*Vin Programmable switching frequency up to 1.5MHz Programmable Soft-start Hiccup mode over current protection using Rds(on) sensing Programmable OCP Reference voltage 0.7V (+/-1%, 0oC <Tj<125oC) Enhanced Pre-bias start up Output voltage tracking Integrated MOSFET drivers and bootstrap diode Operating temp: -40oC <Tj<125oC External synchronization Power Good output Thermal shut down Over voltage protection Enable Input with voltage monitoring capability Pb-Free & Halogen-Free (RoHS Compliant) 20 -Lead MLPQ package (3mmx4mm) Applications * * * * Point of Load Power Architectures Server & Netcom Applications Game Consoles General DC/DC Converters designed for applications. performance The single demanding loop DC/DC voltage mode architecture simplifies design while delivery precise output voltage regulation and fast transient response. Because of its wide input and output voltage range it can be used in a large variety of point of load applications within a system and across different markets. The part is designed to drive a pair of N-Channel MOSFETs from 250kHz to 1.5Mhz switching frequency giving designers the flexibility to optimize the solution for best efficiency or smallest footprint. The output voltage can be precisely regulated from as low as 0.7V within a tolerance of +/-1% over temperature, line and load variations. The device also integrates a diversity of features including; programmable soft start, pre-bias start up, voltage tracking, external synchronization, enable input and Power Good output. Fault protection features include thermal shutdown, over voltage and over current shutdown and under voltage lock out. Typical Application 06/15/2009 1 IR3640MPBF ABSOLUTE MAXIMUM RATINGS (Voltages referenced to GND unless otherwise specified) * Vcc and PVcc ...................................................... -0.3V to 8V (Note2) * Boot ................................................................ -0.3V to 40V * SW ................................................................ -4V (100ns), -0.3V(DC) to 31V * Boot to SW * LDrv to PGND ...................................................... -0.3V to Vcc+0.3V (Note1) * HDrv to SW ......................................................... -0.3V to BOOT+0.3V (Note1) * OCSet * Input / output Pins * PGND to GND ..................................................... -0.3V to +0.3V * Storage Temperature Range .......................................... -55C To 150C * Junction Temperature Range ......................................... -40C To 150C (Note2) * ESD Classification ................................................ JEDEC Class 1C * Moisture sensitivity level.......................................... JEDEC Level 2@260 C ........................................................ -0.3V to Vcc+0.3V (Note1) ............................................................ -0.3V to 30V, 30mA ................................................ -0.3V to Vcc+0.3V (Note1) Note1: Must not exceed 8V Note2: Vcc must not exceed 7.5V for Junction Temperature between -10oC and -40oC Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications are not implied. Package Information JA = 36o C/W * JC = 4o C/W 20-Lead MLPQ (3x4)mm *Exposed pad on underside is connected to a copper pad through vias for 4-layer PCB board design Ordering Information 06/15/2009 PKG DESIG PACKAGE DESCRIPTION PIN COUNT PARTS PER REEL M IR3640MTRPbF 20 3000 2 IR3640MPBF Fig. 2. Simplified block diagram of the IR3640 06/15/2009 3 IR3640MPBF Pin Description Pin Number Pin Name Description 1 NC No Connect 2 LDrv Output driver for Low-side MOSFET 3 PGnd Power Ground 4 SW Switch Node 5 HDrv Output driver for High-side MOSFET 6 NC No Connect 7 Boot Supply Voltage for High-side Driver 8 Enable User programmable Enable 9 Seq Sequence. If it is not used connect to Vcc 10 Fb Inverting Pin of E/A 11 Vsns OVP / PGood Sense 12 Comp Output of Error Amplifier 13 Gnd IC Ground 14 Rt Set the Switching Frequency 15 SS/SD Soft Start/Shutdown 16 OCset External Resistor connection to set the Over Current Limit 17 PGood Power Good Output. Open Drain 18 Sync External Synchronization 19 Vcc Supply Voltage for IC Bias 20 PVcc Supply Voltage for Driver section 06/15/2009 4 IR3640MPBF Recommended Operating Conditions Symbol Definition Min Max Vcc and PVcc Fs Tj Supply voltages Operating frequency Junction temperature 4.5 225 -40 5.5 1650 125 Units V kHz o C Electrical Specifications Unless otherwise specified, these specification apply over 4.5V<Vcc<5.5V, 0oC<Tj<125oC Typical values are specified at 25oC Parameter SYM Test Condition Min TYP MAX Units Voltage Accuracy Regulated voltage at Fb VFb 0.7 o Accuracy o 0 C<Tj<125 C o o -40 C<Tj<125 C, Note3 V -1.0 +1.0 -2 +2 % Supply Current Vcc Supply Current (Standby) Icc (Standby) No Switching, Enable low 500 Vcc Supply Current (Dyn) Icc (Dynamic) 40 Vcc Supply current Ibias Vcc=5V, Freq=600kHz, Enable high, CLOAD_H=2.2nF CLOAD_L=4.4nF Vcc=5V, Freq=600kHz, Enable high, Cload=Open A mA 6 Under Voltage Lockout / Enable Vcc-Threshold-Start Vcc_UVLO_Start Vcc Rising Trip Level 4.06 4.26 4.46 Vcc-Threshold-Stop Vcc_UVLO_Stop Vcc Falling Trip Level 3.76 3.96 4.16 0.25 0.3 0.38 Vcc-Hysteresis Vcc-Hys V Enable Threshold-Start En_UVLO_Start Enable Rising Trip Level 1.14 1.2 1.36 Enable Threshold-Stop En_UVLO_Stop Enable Falling Trip Level 0.9 1.0 1.06 0.16 0.20 0.25 Enable-Hysteresis Enable Current Leakage En_Hys Ien Enable=3.3V 18 A V Oscillator Rt Voltage Frequency FS Ramp Amplitude Ramp Offset 06/15/2009 0.665 0.7 0.735 Rt=59K 225 250 275 Rt=28.7K 450 500 550 Rt=9.31K 1350 1500 1650 kHz Vramp Note4 1.8 Vp-p Ramp (os) Note4 0.6 V 5 IR3640MPBF Electrical Specifications Parameter SYM Test Condition Min TYP MAX Units Oscillator (cont.) Min Pulse Width Dmin(ctrl) Max Duty Cycle Dmax Fixed Off Time Hdrv(off) Sync Frequency Range Note4 Fs=250kHz 50 92 Note4 20% above free running frequency Sync Pulse Duration High % 130 225 100 Sync Level Threshold ns 200 ns 1650 kHz 200 ns 2 V Low 0.6 Error Amplifier Input Offset Voltage Vos Vfb-Vseq Vseq=0.8V -10 0 +10 Input Bias Current IFb(E/A) -1 +1 Input Bias Current IVp(E/A) -1 +1 Sink Current Isink(E/A) 0.40 0.85 1.2 Isource(E/A) 8 10 13 mV A mA Source Current Slew Rate Gain-Bandwidth Product DC Gain SR Note4 7 12 20 V/s GBWP Note4 20 30 40 MHz Gain Note4 100 110 120 dB Vcc=4.5V 3.4 3.5 3.7 V 120 220 mV 1 V A Maximum Voltage Vmax(E/A) Minimum Voltage Vmin(E/A) Seq Common Mode Voltage Seq Note4 0 Soft Start Current ISS Source 14 20 26 Soft Start Clamp Voltage Shutdown Output Threshold Vss(clamp) 2.7 3.0 3.3 Soft Start/SD V SD 0.3 Over Current Protection OCSET Current OC Comp Offset Voltage SS off time 06/15/2009 IOCSET VOFFSET SS_Hiccup Fs=250kHz 20.8 23.6 26.4 Fs=500kHz 43 48.8 54.6 Fs=1500kHz 136 154 172 Note4 -10 0 +10 4096 A mV Cycles 6 IR3640MPBF Electrical Specifications Parameter SYM Test Condition Min TYP MAX Units Thermal Shutdown Thermal Shutdown 140 Note4 Hysteresis o C 20 Power Good Power Good Threshold Delay Comparator Threshold Delay Comparator Hysteresis PGood Voltage Low PGood Comparator Delay Leakage Current VPG SS(Delay) Delay(SShys) PG(voltage) Vsns Rising 83 88 93 %Vref Relative to charge voltage, SS rising Note4 2.0 2.1 2.2 V 260 300 340 mV 0.5 V IPGood=-5mA PG(Delay) 256/Fs s Ileakage 0 10 uA High Side Driver Source Impedance Sink Impedance Rsource(Hdrv) VBoot-VSW =5V, Note4 2.0 5.0 Rsink(Hdrv) VBoot-VSW =5V , Note4 1.0 2.5 Rise Time THdrv(Rise) Fall Time THdrv(Fall) Deadband Time Tdead(L to H) SW Bias Current Isw VBoot-VSW =5V, Cload=2.2nF 1V to 4V VBoot-VSW =5V, Cload=2.2nF 4V to 1V Ldrv going Low to Hdrv going High, 1V to 1V SW=0V, Enable=0V 40 27 10 20 ns 45 6 A Low Side Driver Source Impedance Rsource(Ldrv) Vcc=5V, Note4 1.0 2.5 Sink Impedance Rsource(Ldrv) Vcc=5V, Note4 0.4 1.0 Rise Time TLdrv(Rise) Fall Time TLdrv(Fall) Vcc=5V Cload=4.4nF 1V to 4V Vcc=5V Cload=4.4nF 4V to 1V Deadband Time Tdead(H to L) Hdrv going Low to Ldrv going High, 1V to 1V 40 40 ns 10 20 45 110 115 120 %Vref 150 ns 470 mV Over Voltage Protection OVP Trip Threshold OVP Fault Prop Delay OVP(trip)_Vref OVP(delay) Bootstrap Diode Forward Voltage I(Boot)=30mA 180 260 Note3: Cold temperature performance is guaranteed via correlation using statistical quality control. Not tested in production Note4: Guaranteed by Design, but not tested in production 06/15/2009 7 IR3640MPBF TYPICAL OPERATING CHARACTERISTICS: (-40oC - 125oC) Fs= 500 kHz Ic(Dyn) Icc(Standby) 300 280 [mA] [uA] 260 240 220 200 -20 0 20 40 60 80 100 120 24 706 22 701 18 691 16 40 60 80 100 -40 -20 0 20 20 40 40 60 80 100 120 [kHz] 50.6 50.4 50.2 50.0 49.8 49.6 49.4 49.2 49.0 48.8 48.6 -40 -20 0 20 Tem p[oC] [V] 0 20 40 -20 0 60 60 80 100 120 4.10 4.05 4.00 3.95 3.90 3.85 3.80 3.75 3.70 -40 -20 0 20 40 60 Tem p[oC] Enable(UVLO) Start Enable(UVLO) Stop 40 60 Tem p[oC] 06/15/2009 40 Tem p[oC] 20 80 100 120 80 100 120 80 100 120 80 100 120 Vcc(UVLO) Stop [V] [V] [V] 1.36 1.34 1.32 1.30 1.28 1.26 1.24 1.22 1.20 1.18 1.16 1.14 -40 -20 60 Tem p[oC] Vcc(UVLO) Start 4.40 4.35 4.30 4.25 4.20 4.15 4.10 4.05 4.00 -40 120 IOCSET(500kHz) [uA] 0 100 Tem p[oC] FREQUENCY -20 80 14 120 Tem p[oC] 510 508 506 504 502 500 498 496 494 492 490 -40 60 20 696 20 40 ISS 26 0 20 Vfb 711 -20 0 Tem p[oC] 716 686 -40 -20 Tem p[oC] [uA] [mV] 180 -40 25 24 23 22 21 20 19 18 17 16 15 -40 80 100 120 1.06 1.04 1.02 1.00 0.98 0.96 0.94 0.92 0.90 -40 -20 0 20 40 60 Tem p[oC] 8 IR3640MPBF Circuit Description THEORY OF OPERATION Introduction The IR3640 uses a PWM voltage mode control scheme with external compensation to provide good noise immunity and maximum flexibility in selecting inductor values and capacitor types. The switching frequency is programmable from 250kHz to 1.5MHz and provides the capability of optimizing the design in terms of size and performance. IR3640 provides precisely regulated output voltage programmed via two external resistors from 0.7V to 0.9*Vin. If the input to the Enable pin is derived from the bus voltage by a suitably programmed resistive divider, it can be ensured that the IR3640 does not turn on until the bus voltage reaches the desired level. Only after the bus voltage reaches or exceeds this level will the voltage at Enable pin exceed its threshold, thus enabling the IR3640. Therefore, in addition to being a logic input pin to enable the IR3640, the Enable feature, with its precise threshold, also allows the user to implement an Under-Voltage Lockout for the bus voltage Vin. This is desirable particularly for high output voltage applications, where we might want the IR3640 to be disabled at least until Vin exceeds the desired output voltage level. The IR3640 operates with an external bias supply from 4.5V to 5.5V, allowing an extended operating input voltage range from 1.5V to 24V. The device utilizes the on-resistance of the low side MOSFET as current sense element, this method enhances the converter's efficiency and reduces cost by eliminating the need for external current sense resistor. Under-Voltage Lockout and POR The under-voltage lockout circuit monitors the input supply Vcc and the Enable input. It assures that the MOSFET driver outputs remain in the off state whenever either of these two signals drop below the set thresholds. Normal operation resumes once Vcc and Enable rise above their thresholds. Fig. 3a: Normal Start up, Device turns on when the Bus voltage reaches 10.2V Figure 3b shows the recommended start-up sequence for the non-sequenced operation of IR3640, when Enable is used as a logic input. The POR (Power On Ready) signal is generated when all these signals reach the valid logic level (see system block diagram). When the POR is asserted the soft start sequence starts (see soft start section). Enable The Enable features another level of flexibility for start up. The Enable has precise threshold which is internally monitored by Under-Voltage Lockout (UVLO) circuit. Therefore, the IR3640 will turn on only when the voltage at the Enable pin exceeds this threshold, typically, 1.2V. 06/15/2009 Fig. 3b: Recommended startup sequence, Non-Sequenced operation 9 IR3640MPBF Figure 3c shows the recommended startup sequence for sequenced operation of IR3640 with Enable used as logic input. Fig. 5. Pre-Bias startup pulses Soft-Start Fig. 3c. Recommended startup sequence, Sequenced operation Pre-Bias Startup IR3640 is able to start up into pre-charged output, which prevents oscillation and disturbances of the output voltage. The output starts in asynchronous fashion and keeps the synchronous MOSFET off until the first gate signal for control MOSFET is generated. Figure 4 shows a typical Pre-Bias condition at start up. The synchronous MOSFET always starts with a narrow pulse width and gradually increases its duty cycle with a step of 25%, 50%, 75% and 100% until it reaches the steady state value. The number of these startup pulses for the synchronous MOSFET is internally programmed. Figure 5 shows a series of 32, 16, 8 startup pulses. Fig. 4. Pre-Bias startup 06/15/2009 The IR3640 has a programmable soft-start to control the output voltage rise and limit the current surge at the start-up. To ensure correct start-up, the soft-start sequence initiates when the Enable and Vcc rise above their UVLO thresholds and generate the Power On Ready (POR) signal. The internal current source (typically 20uA) charges the external capacitor Css linearly from 0V to 3V. Figure 6 shows the waveforms during the soft start. The start up time can be estimated by: Tstart = (1.4 - 0.7)* CSS 20A - - (1) During the soft start the OCP is enabled to protect the device for any short circuit and over current condition. The SS pin can be used as shutdown signal, pulling low this pin will result to turning off the high side driver and turning on the low side driver. Fig. 6. Theoretical operation waveforms during soft-start 10 IR3640MPBF Operating Frequency The switching frequency can be programmed between 250kHz - 1500kHz by using an external resistor from Rt to Gnd. Table 1 tabulates the oscillator frequency versus Rt. Trailing edge modulation is used for generating PWM signal(Fig.7) . Table 1. Switching Frequency and IOCSet vs. External Resistor (Rt) Rt (k) 47.5 35.7 28.7 23.7 20.5 17.8 15.8 14.3 12.7 11.5 10.7 9.76 9.31 Fs (kHz) 300 400 500 600 700 800 900 1000 1100 1200 1300 1400 1500 Iocset (A) 29.4 39.2 48.7 59.07 68.2 78.6 88.6 97.9 110.2 121.7 130.8 143.4 150.3 Over-Current Protection The over current protection is performed by sensing current through the RDS(on) of low side MOSFET. This method enhances the converter's efficiency and reduce cost by eliminating a current sense resistor. As shown in Fig. 8, an external resistor (ROCset is connected between OCSet pin and the drain of low side MOSFET (Q2) which sets the current limit set point. The internal current source develops a voltage across RSET. An internal current source sources current (IOCSet ) out of the OCSet pin. This current is a function of the switching frequency and hence, of Rt. Table 1. shows IOCSet at different switching frequencies. I OCSet (A) = 1400 Rt (k) - -(2) I OCSET IR3640 Q1 OCSet RSET L1 VOUT Q2 Hiccup Control Ramp VC Fig. 8: Connection of over current sensing resistor Clock Cntl gate Sync gate Fig. 7: Trailing-edge Modulation Frequency Synchronization The IR3640 is capable of accepting an external digital synchronization signal. Synchronization will be enabled by the rising edge at an external clock. The switching frequency is set by external resistor (Rt). During synchronization, Rt is selected such that the free running frequency is 20% below the synchronization frequency. When unused, the sync pin will remain floating and is noise immune. 06/15/2009 When the low side MOSFET is turned on, the inductor current flows through the Q2 and results a voltage which is given by: VOCSet = ( IOCSet ROCSet ) - ( R ) DS (on IL ) - -(3) An over current is detected if the OCSet pin goes below ground. Hence, at the current limit threshold, VOCset=0. Then, for a current limit setting ILimit, ROCSet is calculated as follows: ROCSet = R DS (on) * I Limit IOCSet - -(4) 11 IR3640MPBF An over-current detection trips the OCP comparator, latches OCP signal and cycles the soft start function in hiccup mode. Vo1 Vo2 The hiccup is performed by shorting the softstart capacitor to ground and counting the number of switching cycles. The soft start pin is held low until 4096 cycles have been completed. The OCP signal resets and the converter recovers. After every soft start cycle, the converter stays in this mode until the overload or short circuit is removed. Simultaneous Powerup Fig. 9a: Simultaneous Power-up of the slave with respect to the master. Through these pins, voltage sequencing such as simultaneous, sequential, etc. can be implemented. Figure 9b shows simultaneous sequencing configurations. In simultaneous powerup, the voltage at the Seq pin of the slave reaches 0.7V before the Fb pin of the master. For RE/RF =RC/RD, therefore, the output voltage of the slave follows that of the master until the voltage at the Seq pin of the slave reaches 0.7 V. After the voltage at the Seq pin of the slave exceeds 0.85V, the internal 0.7V reference of the slave dictates its output voltage. The OCP circuit starts sampling current typically 160 ns after the low gate drive rises to about 3V. This delay functions to filter out switching noise. The value of ROCSet should be checked in an actual circuit to ensure that the over current protection circuit activates as expected. Vin1 Shutdown The IR3640 can be shutdown by pulling the Enable pin below its 1 V threshold. This will tristate both, the high side driver as well as the low side driver. Alternatively, the output can be shutdown by pulling the soft-start pin below 0.3V. In shutdown by this method, the high side driver is turned off, and the low side driver is turned on. Thus, in this method, the output voltage can be actively discharged through the synchronous FET. Normal operation is resumed by cycling the voltage at the Soft Start pin. Vcc Enable Vcc Boot HDrv Vo (Master) SW PGood1 PGood OCSet Seq LDrv PGnd Rt RA Vsns SS/ SD Gnd Sync Comp Fb RB Vin2 Vo (Master) Vcc Enable Vcc Boot HDrv Vo (Salve) SW PGood2 PGood Output Voltage Sequencing RE Seq>0.85V (steady state) OCSet LDrv Seq PGnd The IR3640 can accommodate a full spectrum of user programmable sequencing option using Seq, Enable and Power Good pins. RF Rt RC Vsns SS/ SD Gnd Sync Comp Fb RD Note: Vo (Master) > Vo (Salve) Fig. 9b: Application Circuit for Simultaneous Sequencing 06/15/2009 12 IR3640MPBF Thermal Shutdown Temperature sensing is provided inside IR3640. The trip threshold is typically set to 140oC. When trip threshold is exceeded, thermal shutdown turns off both MOSFETs and discharges the soft start capacitor. Automatic restart is initiated when the sensed temperature drops within the operating range. There is a 20oC hysteresis in the thermal shutdown threshold. Power Good and Over-voltage Protection The IC continually monitors the output voltage via sense pin. The Vsns voltage compares to a fixed voltage. As soon as the sensed voltage reaches 0.88*Vref, the Power Good signal flags. Power Good pin needs to be externally pulled high. High state indicates that output is in regulation. Figure 10a and 10b shows the timing diagrams of Power Good function. If the output voltage exceeds the over voltage threshold, an over voltage trip signal asserts, this will result to turn off the high side driver and turn on the low side driver until the Vsns voltage drops below 1.15*Vref threshold. Both drivers are latched off until a reset performed by cycling either Vcc or Enable. Fig.10b: IR3640 Sequencing Power Up The OVP threshold can be externally programmed to user defined value. Figure 10c shows the response in over-voltage condition. Fig.10c: IR3640 Timing Diagram of Overvoltage Protection Fig.10a: IR3640 Non-Sequencing Power Up (Seq=Vcc) 06/15/2009 13 IR3640MPBF Minimum on time Considerations Maximum Duty Ratio Considerations The minimum ON time is the shortest amount of time for which the Control FET may be reliably turned on, and this depends on the internal timing delays. For the IR3640, the typical minimum on-time is specified as 50 ns. Any design or application using the IR3640 must ensure operation with a pulse width that is higher than this minimum on-time and preferably higher than 100 ns. This is necessary for the circuit to operate without jitter and pulse-skipping, which can cause high inductor current ripple and high output voltage ripple. A fixed off-time of 200 ns maximum is specified for the IR3640. This provides an upper limit on the operating duty ratio at any given switching frequency. It is clear, that higher the switching frequency, the lower is the maximum duty ratio at which the IR3640 can operate. To allow some margin, the maximum operating duty ratio in any application using the IR3640 should still accommodate about 250 ns off-time. Figure 11 shows a plot of the maximum duty ratio vs. the switching frequency, with 250 ns off-time. = D Fs M a x Duty Cycle Vout Vin x Fs In any application that uses the IR3640, the following condition must be satisfied: t on (min) t on t on (min) Vout Vin x Fs Vin x Fs Vout t on(min) Max D uty C ycle (% ) t on = 95 90 85 80 75 70 65 60 55 250 450 650 850 1050 1250 1450 1650 S w itching Frequency (kH z ) Fig. 11: Maximum duty cycle vs. switching frequency The minimum output voltage is limited by the reference voltage and hence Vout(min) = 0.7 V. Therefore, for Vout(min) = 0.7 V, Vin x Fs Vout (min) Vin x Fs t on(min) 0.7 V = 7 x 10 6 V/s 100 ns Therefore, at the maximum recommended input voltage 24V and minimum output voltage, the converter should be designed at a switching frequency that does not exceed 292 kHz. Conversely, for operation at the maximum recommended operating frequency 1.65 MHz and minimum output voltage, any voltage above 4.2 V may not be stepped down without pulseskipping. 06/15/2009 14 IR3640MPBF Application Information Output Voltage Programming Design Example: The following example is a typical application for IR3640. The application circuit is shown on page 23. Vin=12V,( 13.2V, max ) Vo=1.8V I o=25 A R Vo = Vref 1 + 8 R9 Vo 54mV Fs=600kHz As explained earlier, the precise threshold of the Enable lends itself well to implementation of a UVLO for the Bus Voltage. V in R2 Fig. 12: Typical application of the IR3640 for programming the Enable threshold For a typical Enable threshold of VEN = 1.2 V R2 = VEN = 1.2 R1 + R2 - -(5) - -(6) For a Vin (min)=10.1V, R1=4.99K and R2=681 ohm is a good choice. Programming the frequency For Fs = 600 kHz, select Rt = 23.7 k, using Table. 1. 06/15/2009 IR3640 IR3624 R8 Fb R1 Enable VEN Vin( min ) - VEN VOUT R9 IR3640 IR3640 R2 = R1 - -(7) When an external resistor divider is connected to the output as shown in figure 11. Enabling the IR3640 Vin (min) * Output voltage is programmed by reference voltage and external voltage divider. The Fb pin is the inverting input of the error amplifier, which is internally referenced to 0.7V. The divider is ratioed to provide 0.7V at the Fb pin when the output is at its desired value. The output voltage is defined by using the following equation: Fig. 13: Typical application of the IR3640 for programming the output voltage Equation (7) can be rewritten as: Vref - -(8) R9 = R8 V -V O ref For the calculated values of R8 and R9 see feedback compensation section. Soft-Start Programming The soft-start timing can be programmed by selecting the soft-start capacitance value. The start-up time of the converter can be calculated by using: Tstart * 20uA CSS = - -(9) (1.4 - 0.7)V Where Tstart is the desired start-up time (ms). For a start-up time of 3.5ms, the soft-start capacitor will be 0.099uF. Choose a ceramic capacitor at 0.1uF. 15 IR3640MPBF Bootstrap Capacitor Selection Input Capacitor Selection To drive the high side switch, it is necessary to supply a gate voltage at least 4V greater than the bus voltage. This is achieved by using a bootstrap configuration, which comprises the internal bootstrap diode and an external capacitor (C6). The operation of the circuit is as follows: When the lower MOSFET is turned on, the capacitor node connected to SW is pulled down to ground. The capacitor charges towards PVcc through the internal bootstrap diode, which has a forward voltage drop VD. The voltage VC across the bootstrap capacitor C6 is approximately given as The ripple current generated during the on time of upper the MOSFET should be provided by the input capacitor. The RMS value of this ripple is expressed by: VC PVCC -VD --( 10) When the upper MOSFET turns on in the next cycle, the capacitor node connected to SW rises to the bus voltage Vin. However, if the value of C6 is appropriately chosen, the voltage VC across C6 remains approximately unchanged and the voltage at the Boot pin becomes VBoot Vin + PVcc - VD - -(11) I RMS = I o D (1 - D ) D= Where: --(12) Vo - -(13) Vin D is the Duty Cycle IRMS is the RMS value of the input capacitor current. Io is the output current. For Io=25A and D=0.15, the IRMS=8.9A. Ceramic capacitors are recommended due to their peak current capabilities, they also feature low ESR and ESL at higher frequency which enables better efficiency. For this application, it is advisable to have 4x10uF 25V ceramic capacitors GRM31CR61E106KA12L from Murata Electronics. In addition to these, although not mandatory, a 2X330uF, 25V SMD capacitor EEV-FK1E331P may also be used as a bulk capacitor. Inductor Selection Fig. 14: Bootstrap circuit to generate Vc voltage A capacitor in the range of 0.1uF is generally adequate for most applications. 06/15/2009 The inductor is selected based on output power, operating frequency and efficiency requirements. A low inductor value causes large ripple current, resulting in the smaller size, faster response to a load transient but poor efficiency and high output noise. Generally, the selection of the inductor value can be reduced to the desired maximum ripple current in the inductor (i ) . The optimum point is usually found between 20% and 50% ripple of the output current. For the buck converter, the inductor value for the desired operating ripple current can be determined using the following relation: 16 IR3640MPBF i 1 ; t = D t Fs Vo L = (Vin - Vo ) Vin i * Fs Vin - Vo = L - -(14) Where: Vin = Maximum input voltage Vo = Output Voltage i = Inductor ripple current F s= Switching frequency t = Turn on time D = Duty cycle i 35%(I o ) , then the output inductor is If calculated to be 0.29uH. Select L=0.33uH The MPL104-R33 from Delta provides a compact, low profile inductor suitable for this application. Output Capacitor Selection The voltage ripple and transient requirements determine the output capacitors type and values. The criteria is normally based on the value of the Effective Series Resistance (ESR). However the actual capacitance value and the Equivalent Series Inductance (ESL) are other contributing components. These components can be described as: Vo = Vo( ESR) + Vo( ESL) + Vo(C ) Vo( ESR) = I L * ESR V Vo( ESL) = in * ESL L Vo(C ) = I L 8 *Co * Fs Vo = Output voltage ripple IL = Inductor ripple current 06/15/2009 Since the output capacitor has a major role in the overall performance of the converter and determines the result of transient response, selection of the capacitor is critical. The IR3840 can perform well with all types of capacitors. As a rule, the capacitor must have low enough ESR to meet output ripple and load transient requirements. The goal for this design is to meet the voltage ripple requirement in the smallest possible capacitor size. Therefore it is advisable to select ceramic capacitors due to their low ESR and ESL and small size. Ten of the Murata GRM21BR60G476ME15L (47uF/4V) capacitors is a good choice. Power MOSFET Selection The IR3640 uses two N-Channel MOSFETs per channel. The selection criteria to meet power transfer requirements are based on maximum drain-source voltage (VDSS), gate-source drive voltage (Vgs), maximum output current, Onresistance RDS(on), and thermal management. The MOSFET must have a maximum operating voltage (VDSS) exceeding the maximum input voltage (Vin). The gate drive requirement is almost the same for both MOSFETs. A logic-level transistor can be used and caution should be taken with devices at very low gate threshold voltage (Vgs) to prevent undesired turn-on of the complementary MOSFET, which results in a shoot-through current. The total power dissipation for MOSFETs includes conduction and switching losses. For the Buck converter the average inductor current is equal to the DC load current. The conduction loss is defined as: 2 Pcond (upperswitch)= Iload R ds(on) D 2 Pcond (lowerswitch)= Iload Rds(on) (1- D) = R ds(on) temperat ure dependency 17 IR3640MPBF The RDS(on) temperature dependency should be considered for the worst case operation. This is typically given in the MOSFET datasheet. Ensure that the conduction losses and switching losses do not exceed the package ratings or violate the overall thermal budget. For this design, the IRF6710 is selected for control FET and IRF6795 is selected for the synchronous FET. These devices provide low on resistance in a DirectFET package. The MOSFETs have the following data: ControlFET(IRF6710): Vds = 25V,Qg = 8.8nC SyncFET(IRF6795): Vds = 25V,Qg = 35nC Rds(on) = 9.0m @Vgs = 4.5V Rds(on) = 2.4m @Vgs = 4.5V The conduction losses will be: Pcond=2.12W at Io=25A. The switching loss is more difficult to calculate, even though the switching transition is well understood. The reason is the effect of the parasitic components and switching times, such as turn-on / turn-off delays and rise and fall times. The control MOSFET contributes to the majority of the switching losses in a synchronous Buck converter. The synchronous MOSFET turns on under zero voltage conditions, therefore, the turn on losses for synchronous MOSFET can be neglected. With a linear approximation, the total switching loss can be expressed as: Psw = Where: Vds(off ) tr + t f * * Iload 2 T - -(15) V ds(off) = Drain to source voltage at the off time tr = Rise time tf = Fall time VDS 90% 10% VGS td(ON) tr td(OFF) tf Fig. 15: Switching time waveforms By using equation (15), we can calculate the switching losses. Psw=2.34W at Io=25A. The reverse recovery loss is also another contributing factor in control FET switching losses. This is equivalent to extra current required to remove the minority charges from the synchronous FET. The reverse recovery loss can be expressed as: PQrr = Qrr*Vin*Fs Qrr:Reverse Recovery Charge Vin: Input Bus Voltage Fs: Switching Frequency The gate driving loss is the power consumption to drive both the control and synchronous FETs. The gate driving loss can be estimated as: PDriver = Qg*Vg*Fs Qg:TotalGateCharge Vg: GateDrivingVoltage Fs: Switching Frequency T = Switching period Feedback Compensation Iload = Load current The IR3640 is a voltage mode controller. The control loop is a single voltage feedback path including error amplifier and error comparator. To achieve fast transient response and accurate output regulation, a compensation circuit is necessary. The goal of the compensation network is to provide a closed-loop transfer function with the highest 0dB crossing frequency and adequate phase margin (greater than 45o). The switching time waveforms is shown in Fig. 15. From IRF6710 data sheet: tr = 20ns tf = 6ns These values are taken under a certain test condition. For more details please refer to the IRF6710 data sheet. 06/15/2009 18 IR3640MPBF The output LC filter introduces a double pole, -40dB/decade gain slope above its corner resonant frequency, and a total phase lag of 180o (see Fig. 16). The resonant frequency of the LC filter is expressed as follows: FLC = 1 2 Lo Co C4 R8 Zf Fb R9 Gain(dB) E/A Comp Ve VREF H(s) dB FZ Phase 0dB C POLE R3 - -(16) Figure 16 shows gain and phase of the LC filter. Since we already have 180o phase shift from the output filter alone , the system risks being unstable. Gain VOUT Z IN F POLE Frequency Fig. 17: TypeII compensation network and its asymptotic gain plot 0 -40dB/decade The transfer function (Ve/Vo) is given by: -180o FLC Frequency FLC Frequency Fig. 16: Gain and Phase of LC filter The IR3640 uses a voltage-type error amplifier with high-gain (110dB) and wide-bandwidth. The output of it is available for DC gain control or AC phase compensation. The error amplifier can be compensated either in type II or type III compensation. When it is used in type II compensation, a series RC circuit from Comp pin to ground as shown in figure 16 is used. This method requires the output capacitor should have enough ESR to satisfy stability requirements. In general the output capacitor's ESR generates a zero typically at 5kHz to 50kHz which is essential for an acceptable phase margin. The ESR zero of the output capacitor expressed as follows: FESR = 06/15/2009 1 2 * ESR*Co - -(17) Zf 1+ sR3C4 Ve = H(s) = - =- - -(18) Vo ZIN sR8C4 The (s) indicates that the transfer function varies as a function of frequency. This configuration introduces a gain and zero, expressed by: R H (s ) = 3 - -(19) R8 1 - -(20) 2*R3*C4 First select the desired zero-crossover frequency (Fo): Fo > FESR and Fo (1/5 ~ 1/10) * Fs Fz = Use the following equation to calculate R3: R3 = Vosc * Fo * FESR * R8 2 Vin * FLC - -(21) Where: Vin = Maximum Input Voltage Vosc = Oscillator Ramp Voltage Fo = Crossover Frequency FESR = Zero Frequency of the Output Capacitor FLC = Resonant Frequency of the Output Filter R8 = Feedback Resistor 19 IR3640MPBF To cancel one of the LC filter poles, place the zero before the LC filter resonant frequency pole: VOUT ZIN C7 Fz = 75%FLC 1 Fz = 0.75* 2 Lo *Co 1 FP = C *C 2 * R3 * 4 POLE C4 + CPOLE The pole sets to one half of the switching frequency which results in the capacitor CPOLE: 1 1 * R3 * Fs - C4 1 * R 3 * Fs For a general solution for unconditional stability for any type of output capacitors, in a wide range of ESR values we should implement local feedback with a compensation network (type III). The typically used compensation network for voltage-mode controller is shown in Fig. 17. In such configuration, the transfer function is given by: Zf Ve =- Vo Z IN By replacing Zin and Zf according to Fig. 17, the transfer function can be expressed as: H (s) = (1 + sR3C4 ) * [1 + sC7 (R8 + R10 )] -1 * sR8 (C4 + C3 ) C 4 * C3 * (1 + sR10C7 ) 1 + sR3 C4 + C3 06/15/2009 R3 R10 - -(22) Using equations (15) and (16) to calculate C4. One more capacitor is sometimes added in parallel with C4 and R3. This introduces one more pole which is mainly used to suppress the switching noise. The additional pole is given by: CPOLE = C3 C4 R8 Zf Fb R9 E/A Comp Ve VREF Gain(dB) H(s) dB FZ1 FZ2 FP2 FP3 Frequency Fig.18: Compensation network with local feedback and its asymptotic gain plot The compensation network has three poles and two zeros and they are expressed as follows: FP1 = 0 FP 2 = 1 2 * R10 * C7 FP 3 = 1 1 C4 * C3 2 * R3 * C3 2 * R3 C4 + C3 Fz1 = 1 2 * R3 * C4 Fz 2 = 1 1 2 * C7 * (R8 + R10 ) 2 * C7 * R8 Cross over frequency is expressed as: Fo = R3 * C7 * Vin 1 * Vosc 2 * Lo * Co Based on the frequency of the zero generated by the output capacitor and its ESR versus crossover frequency, the compensation type can be different. Table 2 below shows the compensation types and location of the crossover frequency. 20 IR3640MPBF Table 2 The compensation type and location of FESR versus Fo Compensator Type FESR vs Fo Type II FLC<FESR<Fo<Fs/2 Electrolytic Tantalum Type III FLC<Fo<FESR Tantalum Ceramic Output Capacitor The higher the crossover frequency, the potentially faster the load transient response. However, the crossover frequency should be low enough to allow attenuation of switching noise. Typically, the control loop bandwidth or crossover frequency is selected such that Fo (1/5~1/10)* Fs The DC gain should be large enough to provide high DC-regulation accuracy. The phase margin should be greater than 45o for overall stability. For this design we have: Vin=12V Vo=1.8V Vosc=1.8V Vref=0.7V Lo=0.33uH Co=10x47uF(ceramic) It must be noted here that the value of the capacitance used in the compensator design must be the small signal value. For instance, the small signal capacitance of the 47uF capacitor used in this design is 23uF at 1.8 V DC bias and 600 kHz frequency. It is this value that must be used for all computations related to the compensation. The small signal value may be obtained from the manufacturer's datasheets, design tools or SPICE models. Alternatively, they may also be inferred from measuring the power stage transfer function of the converter and measuring the double pole frequency FLC and using equation (16) to compute the small signal Co. 06/15/2009 These result to: FLC=18.3kHz FESR=2306kHz Fs/2=300kHz Select crossover frequency: Fo=100kHz Since: FLC<Fo<FS/2<FESR, TypeIII is selected to place the pole and zeros. Detailed calculation of compensation TypeIII: Desired Phase Margin = 70o FZ 2 = Fo 1-sin =17.63kHz 1+ sin FP2 = Fo 1+ sin = 567.1kHz 1-sin Select: FZ1 = 0.5* FZ 2 = 8.82 kHz and FP3 = 0.5* Fs = 300 kHz Select: C7 = 2.2nF Calculate R3, C3 and C4 : R3 = 2 * Fo * Lo *Co *Vosc ; R3 = 3.25 k C7 *Vin Select: R3 = 3.24 k C4 = 1 ; C4 = 5.57 nF, Select: C4 = 5.6 nF 2 * FZ1 * R3 C3 = 1 ; C3 =163.74 pF, Select: C3 =160 pF 2 * FP3 * R3 Calculate R10, R8 and R9 : R10 = 1 ; R10 =130 , Select: R10 =130 2 *C7 * FP2 21 IR3640MPBF R8 = Select R7=2.55KOhm 1 - R10; R8 = 3.98 k, 2 *C7 * FZ 2 Using (24): R6=4.16KOhm Select R6=4.12KOhm Select: R8 = 4.02 k R9 = Vref Vo -Vref * R8; R9 = 2.56 k Select: R9 = 2.55 k Use a pull up resistor (4.99K) from PGood pin to Vcc. Layout Consideration Programming the Current-Limit The Current-Limit threshold can be set by connecting a resistor (ROCSET) from the drain of the low-side MOSFET to the OCSet pin. The resistor can be calculated by using equation (3). The RDS(on) has a positive temperature coefficient and it should be considered for the worst case operation. This resistor must be placed close to the IC. This IC doesn't require a small ceramic capacitor from OCset pin to ground. I SET = I L(critical) = ROCSet IOCSet RDS(on) - - (23) RDS ( on) = 2.4m *1.5 = 3.6m I SET I o( LIM ) = 25 A *1.5 = 37.5 A (50% over nominal output current) I OCSet = 59.1uA (at Fs = 600kHz) R OCSet = 2.29K Select R7 = 2.26K Setting the Power Good Threshold Power Good threshold can be programmed by using two external resistors (R6, R7 in Page 23). The following formula can be used to set the threshold: R6 = ( 0.9 *Vout -1) * R7 0.88*Vref - - (24) Where: 0.88*Vref is reference of the internal comparator, for IR3640, it is 0.62V 0.9*Vout is selectable threshold for power good, for this design it is 1.62V. 06/15/2009 The layout is very important when designing high frequency switching converters. Poor layout will affect noise pickup and can cause a good design to perform with less than expected results. Start to place the power components, making all the connection in the top layer with wide, copper filled areas. The inductor, output capacitors and the MOSFETS should be as close to each other as possible. This helps to reduce the EMI radiated by the power traces due to the high switching currents through them. Place input capacitor very close to the drain of the high-side MOSFET. The feedback part of the system should be kept away from the inductor and other noise sources. The critical bypass components such as capacitors for Vcc and PVcc should be close to the respective pins. It is important to place the feedback components including feedback resistors and compensation components close to Fb and Comp pins. Place the Rocset resistor close to Ocset pin and connect this with a short trace to SW pin. In a multilayer PCB use one layer as a power ground plane and have a control circuit ground (analog ground), to which all signals are referenced. The goal is to localize the high current path to a separate loop that does not interfere with the more sensitive analog control function. These two grounds must be connected together on the PC board layout at a single point. The MLPQ is a thermally enhanced package. Based on thermal performance it is recommended to use 4-layers PCB. To effectively remove heat from the device the exposed pad should be connected to ground plane using vias. 22 IR3640MPBF Application Diagram: Fig. 19: Typical Application Circuit for Non-Sequencing 12V to 1.8V, 25A Point of Load Converter Suggested Bill of Materials for the application circuit: Reference Cin Cin Co C1 C2 C6 C8 C3 C4 C7 L1 Q1 Q2 R1 R11 R2 R3 R4 R5 R6 R7 R9 R8 R10 06/15/2009 Value 330uF 10uF 47uF 1.0uF 0.1uF 160pF 5.6nF 2200pF 0.33uH IRF6710S2TRPbF IRF6795MPbF 4.99K 681 3.24K 23.7K 2.26K 4.12K 2.55K 4.02K 130 Description SMD Elecrolytic, 25V,F-size,20% Ceramic,25V,1210,X5R,10% Ceramic,4V,0805,X5R,10% Ceramic,25V,0603,X5R,10% Ceramic,50V,0603,X7R,10% Ceramic,50V,0603,C0G,5% Ceramic,25V,0603,C0G,5% Ceramic,50V,0603,C0G,5% SMT-Inductor,1.5mOhms,10x11mm,20% IRF6710 SQ 25V IRF6795 MX 25V Thick-film,0603,1/10W,1% Thick-film,0603,1/10 W,1% Thick-film,0603,1/10W,1% Thick-film,0603,1/10W,1% Thick-film,0603,1/10W,1% Thick-film,0603,1/10 W,1% Thick-film,0603,1/10 W,1% Thick-film,0603,1/10 W,1% Thick-film,0603,1/10 W,1% Manufacturer Panasonic Taiyo-Yuden Murata Electronics Murata Electronics Panasonic Murata Electronics Panasonic-ECG TDK Corporation Delta International Rectifier International Rectifier Rohm Vishey/Dale Rohm Rohm Rohm Rohm Rohm Rohm Rohm Part Number EEE-FK1E331P TMK325BJ106MN-T GRM21BR60G476ME15L GRM188R61E105KA12D ECJ-1VB1H104K GRM1885C1H161JA01D C1608C0G1E562J C1608C0G1H222J MPL104-R33IR IRF6710S2TRPbF IRF6795MPbF MCR03EZPFX4991 CRCW0603681RFKEA MCR03EZPFX3241 MCR03EZPFX2372 MCR03EZPFX2261 MCR03EZPFX4121 MCR03EZPFX2551 MCR03EZPFX4021 MCR03EZPFX1300 23 IR3640MPBF Application Diagram: IR3640 Fig. 20: Typical Circuit for Sequencing Application 06/15/2009 24 IR3640MPBF TYPICAL OPERATING WAVEFORMS (Vin=12.0V, Vcc=5V, Vo=1.8V, Io=0- 25A, Room Temperature, No Air Flow, Fig.19) Fig. 21: Start up at 0A Load Ch1:Vo, Ch2:PGood Ch3:VSS Ch4: Vin Fig. 23: Start up with 1.5V Prebias, 0A Load, Ch2:Vout Ch3:VSS Ch4: PGood Fig. 25: Inductor node at 25A load Ch2:SW 06/15/2009 Fig. 22: Start up at 25A Load Ch1:Vo, Ch2:PGood Ch3:VSS Ch4: Vin Fig. 24: Output Voltage Ripple, 25A load Ch3: Vout Fig. 26: Short (Hiccup) Recovery Ch2:Vout, Ch3:VSS , Ch4:Io 25 IR3640MPBF TYPICAL OPERATING WAVEFORMS (Vin=12V, Vcc=5V, Vo=1.8V, Room Temperature, No Air Flow, Fig.19) Fig. 27: Transient Response 0A-12.5A load Ch2:Vout, Ch4:Io 06/15/2009 26 IR3640MPBF TYPICAL OPERATING WAVEFORMS (Vin=12V, Vcc=5V, Vo=1.8V, Io=0-25A, Room Temperature, No Air Flow, Fig.19) Fig.28: Bode Plot at 25A load shows a bandwidth of 113.6kHz and phase margin of 50.4 degrees 06/15/2009 27 IR3640MPBF TYPICAL OPERATING WAVEFORMS (Vin=12V, Vo=1.8V, Io=0-25A, Room Temperature, No Air Flow, Fig.19) IR3640_IRF6710_IRF6795_0.33uH Efficiency vs. Io 95 Efficiency(%) 90 85 80 75 70 1 3 5 7 9 11 13 15 17 19 21 23 25 21 23 25 Io(A) IR3640_IRF6710_IRF6795_0.33uH Power Loss vs. Io 7 6 Ploss(W) 5 4 3 2 1 0 1 3 5 7 9 11 13 15 17 19 Io(A) Fig.29: Efficiency and power loss vs. load current 06/15/2009 28 IR3640MPBF PCB Metal and Components Placement * Lead land width should be equal to nominal part lead width. The minimum lead to lead spacing should be 0.2mm to minimize shorting. * Lead land length should be equal to maximum part lead length + 0.3 mm outboard extension +0.05mm inboard extension. The outboard extension ensures a large and inspectable toe fillet, and the inboard extension will accommodate any part misalignment and ensure a fillet. * Center pad land length and width should be equal to maximum part pad length and width. However, the minimum metal to metal spacing should be 0.17mm for 2 oz. Copper ( 0.1mm for 1 oz. Copper and 0.23mm for 3 oz. Copper). * Four 0.30mm diameter via shall be placed in the center of the pad land and connected to ground to minimize the noise effect on the IC. 06/15/2009 29 IR3640MPBF Solder Resist * The solder resist should be pulled away from the metal lead lands by a minimum of 0.06mm. The solder resist mis-alignment is a maximum of 0.05mm and it is recommended that the lead lands are all Non Solder Mask Defined (NSMD). Therefore pulling the S/R 0.06mm will always ensure NSMD pads. * The minimum solder resist width is 0.13mm. At the inside corner of the solder resist where the lead land groups meet, it is recommended to provide a fillet so a solder resist width of 0.17mm remains. * The land pad should be Non Solder Mask Defined (NSMD), with a minimum pullback of the solder resist off the copper of 0.06mm to accommodate solder resist mis-alignment. * Ensure that the solder resist in-between the lead lands and the pad land is 0.15mm due to the high aspect ratio of the solder resist strip separating the lead lands from the pad land. * Each via in the land pad should be tented or plugged from bottom boardside with solder resist. 06/15/2009 30 IR3640MPBF Stencil Design * * * * The stencil apertures for the lead lands should be approximately 80% of the area of the lead lands. Reducing the amount of solder deposited will minimize the occurrence of lead shorts. Since for 0.5mmpitch devices the leads are only 0.25mm wide, the stencil apertures should not be made narrower; openings in stencils < 0.25mm wide are difficult to maintain repeatable solder release. The stencil lead land apertures should therefore be shortened in length by 80% and centered on the lead land. The land pad aperture should deposit approximately 50% area of solder on the center pad. If too much solder is deposited on the center pad the part will float and the lead lands will be open. The maximum length and width of the land pad stencil aperture should be equal to the solder resist opening minus an annular 0.2mm pull back to decrease the incidence of shorting the center land to the lead lands when the part is pushed into the solder paste. 06/15/2009 31 IR3640MPBF IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 This product has been designed and qualified for the Industrial market. Visit us at www.irf.com for sales contact information Data and specifications subject to change without notice. 11/07 06/15/2009 32