LTC4218CDHC-12#PBF - Linear Technology Corporation

LTC4218

4218ff

FEATURES

APPLICATIONS

DESCRIPTION

Hot Swap Controller

The LTC

4218 is a Hot Swap™ controller that allows a board

to be safely inserted and removed from a live backplane.

An internal high side switch driver controls the gate of an

external N-channel MOSFET for supply voltages from 2.9V

to 26.5V. A dedicated 12V version (LTC4218-12) contains

preset 12V speciﬁ c thresholds, while the standard LTC4218

allows adjustable thresholds.

The LTC4218 provides an accurate (5%) current limit with

current foldback limiting. The current limit threshold can

be adjusted dynamically using an external pin. Additional

features include a current monitor output that ampliﬁ es

the sense voltage for ground referenced current sensing.

Overvoltage, undervoltage and power good monitoring

are also provided.

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and

Hot Swap is a trademark of Linear Technology Corporation. All other trademarks are the

property of their respective owners.

12V, 6A Card Resident Application

n Wide Operating Voltage Range: 2.9V to 26.5V

n Adjustable, 5% Accurate (15mV) Current Limit

n Current Monitor Output

n Adjustable Current Limit Timer Before Fault

n Power Good and Fault Outputs

n Adjustable Inrush Current Control

n 2% Accurate Undervoltage and Overvoltage

Protection

n Available in 16-Lead SSOP and 16-Pin 5mm × 3mm

DFN Packages

n RAID Systems

n ATCA, AMC, μTCA Systems

n Server I/O Cards

n Industrial

Power-Up Waveform

TYPICAL APPLICATION

ADC

0.1μF

12V

20k

4218 TA01a

10k

AUTO

RETRY

0.1μF

0.01μF

330μF

SENSE–GATE

SENSE+

VDD

SOURCE

GND

IMON

ISET

LTC4218DHC-12

INTVCC

TIMER

FLT

10Ω

2mΩ Si7108DN VOUT

12V

25ms/DIV 4218 TA01b

VIN

10V/DIV

IIN

1A/DIV

VOUT

10V/DIV

CONTACT BOUNCE

LTC4218

4218ff

SENSE+

SENSE–

ISET

IMON

FLT

GATE

VDD

TIMER

INTVCC

GND

SOURCE

TOP VIEW

DHC PACKAGE

16-LEAD

(

5mm s 3mm

)

PLASTIC DFN

TJMAX = 125°C, θJA = 43°C/W

EXPOSED PAD (PIN 17) IS SUBSTRATE GND

GN PACKAGE

16-LEAD PLASTIC SSOP

TOP VIEW

VDD

TIMER

INTVCC

GND

SOURCE

SENSE+

SENSE–

ISET

IMON

FLT

GATE

TJMAX = 150°C, θJA = 135°C/W

PIN CONFIGURATION

ABSOLUTE MAXIMUM RATINGS

Supply Voltage (VDD) ................................. –0.3V to 35V

Input Voltages

FB, OV, UV ............................................. –0.3V to 12V

TIMER ................................................... –0.3V to 3.5V

SENSE– .............................VDD – 10V or –0.3V to VDD

SENSE+ .............................VDD – 10V or –0.3V to VDD

SOURCE ........................................ – 5V to VDD + 0.3V

Output Voltages

ISET, IMON ................................................. –0.3V to 3V

PG, FLT .................................................. –0.3V to 35V

INTVCC .................................................. –0.3V to 3.5V

GATE (Note 3) ........................................ –0.3V to 35V

(Notes 1, 2)

Operating Temperature Range

LTC4218C ................................................ 0°C to 70°C

LTC4218I .............................................–40°C to 85°C

Storage Temperature Range .................. –65°C to 150°C

Lead Temperature (Soldering, 10 sec)

GN Package Only ..............................................300°C

ORDER INFORMATION

LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE

LTC4218CDHC-12#PBF LTC4218CDHC-12#TRPBF 421812 16-Lead (5mm × 3mm) Plastic DFN 0°C to 70°C

LTC4218IDHC-12#PBF LTC4218IDHC-12#TRPBF 421812 16-Lead (5mm × 3mm) Plastic DFN –40°C to 85°C

LTC4218CGN#PBF LTC4218CGN#TRPBF 4218 16-Lead Plastic SSOP 0°C to 70°C

LTC4218IGN#PBF LTC4218IGN#TRPBF 4218I 16-Lead Plastic SSOP –40°C to 85°C

Consult LTC Marketing for parts speciﬁ ed with wider operating temperature ranges. *The temperature grade is identiﬁ ed by a label on the shipping container.

Consult LTC Marketing for information on non-standard lead based ﬁ nish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel speciﬁ

cations, go to: http://www.linear.com/tapeandreel/

LTC4218

4218ff

ELECTRICAL CHARACTERISTICS

The l denotes the speciﬁ cations which apply over the full operating

temperature range, otherwise speciﬁ cations are at TA = 25°C. VDD = 12V unless otherwise noted.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

DC Characteristics

VDD Input Supply Range l2.9 26.5 V

IDD Input Supply Current FET On l1.6 5 mA

VDD(UVL) Input Supply Undervoltage Lockout VDD Rising l2.65 2.73 2.85 V

VDD(UVTH) Input Supply Undervoltage Threshold LTC4218-12 Only VDD Rising l9.6 9.88 10.2 V

ΔVDD(UVHYST) Input Supply Undervoltage Hysteresis LTC4218-12 Only l520 640 760 mV

VDD(OVTH) Input Supply Overvoltage Threshold LTC4218-12 Only VDD Rising l14.7 15.05 15.4 V

ΔVDD(OVHYST) Input Supply Overvoltage Hysteresis LTC4218-12 Only l183 244 305 mV

VSOURCE(PGTH) SOURCE Power Good Threshold LTC4218-12 Only VSOURCE Rising l10.2 10.5 10.8 V

ΔVSOURCE(PGHYST) SOURCE Power Good Hysteresis LTC4218-12 Only l127 170 213 mV

ΔVSNS(TH) Current Limit Sense Voltage Threshold

(VSENSE+ – VSENSE–)

VFB = 1.23V

VFB = 0V

VFB = 1.23V, RSET = 20kΩ

14.25

2.8

6.7

3.75

7.5

15.75

4.7

8.325

ISENSE–(IN) SENSE– Pin Input Current VSENSE– = 12V l4 ±10 μA

ISENSE+(IN) SENSE+ Pin Input Current VSENSE+ = 12V l5.5 ±20 μA

ΔVGATE External N-Channel Gate Drive

(VGATE – VSOURCE)

VDD = 2.9V to 26.5V (Note 3)

IGATE = 0, –1μA

l5 6.15 6.5 V

ΔVGATE-HIGH(TH) Gate High Threshold (VGATE – VSOURCE) l3.5 4.2 4.8 V

IGATE(UP) External N-Channel Gate Pull-Up Current Gate Drive On, VGATE = VSOURCE = 12V l–19 –24 –29 μA

IGATE(FST) External N-Channel Gate Fast Pull-Down

Current

Fast Turn Off, VGATE = 18V,

VSOURCE =12V

l100 170 220 mA

IGATE(DN) External N-Channel Gate Pull-Down Current Gate Drive Off, VGATE = 18V,

VSOURCE =12V

l200 250 340 μA

Inputs

IIN OV, UV, FB Pin Input Current VIN = 1.2V, LTC4218 Only l0±1 μA

RIN OV, UV, FB Pin Input Resistance LTC4218-12 Only l13 18 23 kΩ

V(TH) OV, UV, FB Pin Threshold Voltage VIN Rising l1.21 1.235 1.26 V

ΔVOV(HYST) OV Pin Hysteresis l10 20 30 mV

ΔVUV(HYST) UV Pin Hysteresis l50 80 110 mV

VUV(RTH) UV Pin Reset Threshold Voltage VUV Falling l0.55 0.62 0.7 V

ΔVFB(HYST) FB Pin Power Good Hysteresis l10 20 30 mV

RISET ISET Pin Output Resistor l19.5 20 20.5 kΩ

ISOURCE SOURCE Pin Input Current VSOURCE = VGATE = 12V, LTC4218-12 Only

VSOURCE = VGATE = 12V, LTC4218 Only

VSOURCE = VGATE = 0V

±1

μA

Outputs

VINTVCC INTVCC Output Voltage I = 0mA, 10mA 3.1 V

VOL PG, FLT Pin Output Low Voltage IOUT = 2mA l0.4 0.8 V

IOH PG, FLT Pin Input Leakage Current VOUT = 30V l0 ±10 μA

VTIMER(H) TIMER Pin High Threshold VTIMER Rising l1.2 1.235 1.28 V

VTIMER(L) TIMER Pin Low Threshold VTIMER Falling l0.1 0.21 0.3 V

ITIMER(UP) TIMER Pin Pull Up Current VTIMER = 0V l–80 –100 –120 μA

ITIMER(DN) TIMER Pin Pull-Down Current VTIMER = 1.2V l1.4 2 2.6 μA

LTC4218

4218ff

ELECTRICAL CHARACTERISTICS

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: All currents into pins are positive, all voltages are referenced to

GND unless otherwise speciﬁ ed.

The l denotes the speciﬁ cations which apply over the full operating

temperature range, otherwise speciﬁ cations are at TA = 25°C. VDD = 12V unless otherwise noted.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

ITIMER(RATIO) TIMER Pin Current Ratio ITIMER(DN)/

ITIMER(UP)

l1.6 2 2.7 %

IMON(FS) IMON Full-Scale Output Current VSENSE+ – VSENSE– = 15mV l94 100 106 μA

IMON(OFF) IMON Pin Offset Current VSENSE+ – VSENSE– = 1mV l±0 ±6 μA

GIMON IMON Pin Gain VSENSE+ – VSENSE– = 15mV and 1mV l6.47 6.67 6.87 μA/mV

AC Characteristics

tPHL(GATE) Input High (OV), Input Low (UV) to GATE

Low Propagation Delay

VGATE < 16.5V Falling l35 μs

tPHL(SENSE) VSENSE+ – VSENSE– High to GATE Low

Propagation Delay

VFB = 0, Step (VSENSE+ – VSENSE–) to

60mV, CGATE = 1.5nF, VGATE < 16.5V

Falling

l0.2 1 μs

tD(ON) Turn-On Delay Step VUV to 2V, VGATE > 13V l50 100 150 ms

Note 3: An internal clamp limits the GATE pin to a maximum of 6.5V above

the SOURCE pin. Driving either GATE or SOURCE pin to voltages beyond

the clamp may damage the device.

LTC4218

4218ff

TYPICAL PERFORMANCE CHARACTERISTICS

IDD vs VDD INTVCC Load Regulation

UV Low-High Threshold

vs Temperature

UV Hysteresis vs Temperature

Timer Pull-Up Current

vs Temperature Current Limit Delay

Current Limit Threshold Foldback Current Limit Adjustment ISET Resistor vs Temperature

TA = 25°C, VDD = 12V unless otherwise noted.

VDD (V)

1.0

IDD (mA)

1.2

1.4

1.6

1.8

2.0

5 101520

4218 G01

25 30

–40°C

25°C

85°C

ILOAD (mA)

0.5

1.5

1.0

INTVCC (V)

3.5

2.0

2.5

3.0

4218 G02

–14–12–10–8–6–4–2

VDD = 5V

VDD = 3.3V

TEMPERATURE (°C)

–50

UV LOW-HIGH HRESHOLD (V)

1.234

1.232

1.230

1.228

1.226

–25 0 25

4218 G03

50 75 100

TEMPERATURE (°C)

–50

UV HYSTERESIS (V)

0.10

0.08

0.06

0.04

–25 0 25

4218 G04

50 75 100

TEMPERATURE (°C)

–50

TIMER PULL-UP CURRENT (μA)

–110

–105

–100

–95

–90

–25 0 25

4218 G05

50 75 100

CURRENT LIMIT SENSE VOLTAGE

(VSENSE+ – VSENSE–) (mV)

CURRENT LIMIT PROPAGATION DELAY (μs)

1000

100

0.1

075

4218 G06

15 30 45 60

CGATE = 10nF

FB VOLTAGE (V)

CURRENT LIMIT SENSE VOLTAGE

(VSENSE+ – VSENSE–) (mV)

0.2 0.4 0.6 0.8

4218 G07

1.0 1.2

RSET (Ω)

CURRENT LIMIT SENSE VOLTAGE

(VDD – VSENSE) (mV)

10k 100k 1M

4218 G08

10M

TEMPERATURE (°C)

–50

RISET (kΩ)

–25 0 25

4218 G09

50 75 100

LTC4218

4218ff

TYPICAL PERFORMANCE CHARACTERISTICS

Gate Drive vs Temperature PG, FLT VOUT Low vs ILOAD

GATE Pull-Up Current

vs Temperature

Gate Pull-Up Current

vs Gate Drive Gate Drive vs VDD

TA = 25°C, VDD = 12V unless otherwise noted.

IMON vs Temperature and VDD

IMON vs Sense VIMON vs Sense

TEMPERATURE (°C)

–50

IGATE PULL-UP (μA)

–26.0

–25.5

–25.0

–24.5

–24.0

–25 0 25

4218 G10

50 75 100

IGATE (μA)

GATE DRIVE (VGATE – VSOURCE) (V)

–5 –10 –15 –20

4218 G11

–25 –30

VDD = 12V

VDD = 3.3V

VDD (V)

6.2

6.0

5.8

5.6

5.4

5.2

51015

4218 G12

20 25 30

GATE DRIVE (VGATE – VSOURCE) (V)

TEMPERATURE (°C)

–50

6.15

6.14

6.13

6.12

6.11

6.10

–25 0 25

4218 G13

50 75 100

GATE DRIVE (VGATE – VSOURCE) (V)

ILOAD (mA)

PG, FLT VOUT LOW (V)

2468

4218 G14

10 12

FLT

TEMPERATURE (°C)

–50

105

100

–25 0 25

4218 G15

50 75 100

IMON (μA)

VDD = 3.3V, 12V, 24V

VSENSE+ – VSENSE– = 15mV

SENSE VOLTAGE (mV)

IMON (μA)

100

510

4218 G16

SENSE VOLTAGE (mV)

VIMON (V)

510

4218 G17

RIMON = 100k

RIMON = 40k

RIMON = 20k

RIMON = 10k

LTC4218

4218ff

PIN FUNCTIONS

Exposed Pad: Exposed pad may be left open or connected

to device ground.

FB: Foldback and Power Good Comparator Input. Connect

this pin to an external resistive divider from SOURCE for

the LTC4218 (adjustable version). The LTC4218-12 version

uses a ﬁ xed internal divider with optional external adjust-

ment. Open the pin if the LTC4218-12 thresholds for 12V

operation are desired. If the voltage falls below 0.6V, the

output power is considered bad and the current limit is

reduced. If the voltage falls below 1.21V the PG pin will

pull low to indicate the power is bad.

FLT: Overcurrent Fault Indicator. Open drain output pulls

low when an overcurrent fault has occurred and the circuit

breaker trips. For overcurrent auto-retry tie to UV pin (see

Applications Information for details).

GATE: Gate Drive for External N-Channel FET. An internal

24μA current source charges the gate of the external

N-channel MOSFET. A resistor and capacitor network

from this pin to ground sets the turn-on rate. During an

undervoltage or overvoltage generated turn-off a 250μA

pull-down current turns the MOSFET off. During a short

circuit or undervoltage lockout, a 170mA pull-down current

source between GATE and SOURCE is activated.

GND: Device Ground.

IMON: Current Monitor Output. The current sourced from

this pin is deﬁ ned as the current sense voltage (between

the SENSE+ and SENSE– pins) multiplied by 6.67μA/mV.

Placing a 20k resistor from this pin to GND creates a 0V to

2V voltage swing when the current sense voltage ranges

from 0mV to 15mV.

INTVCC: Internal 3.1V Supply Decoupling Output. This pin

must have a 0.1μF or larger capacitor.

ISET: Current Limit Adjustment Pin. For 15mV current limit

threshold, open this pin. This pin is driven by a 20k resis-

tor in series with a voltage source. The pin voltage is used

to generate the current limit threshold. The internal 20k

resistor and an external resistor between ISET and ground

create an attenuator that lowers the current limit value.

NC: No Connection

OV: Overvoltage Comparator Input. Connect this pin to

an external resistive divider from VDD for the LTC4218

(adjustable version). The LTC4218-12 version uses a ﬁ xed

internal divider with optional external adjustment for 12V

operation. Open the pin if the LTC4218-12 thresholds are

desired. If the voltage at this pin rises above 1.235V, an

overvoltage is detected and the switch turns off. Tie to

GND if unused.

PG: Power Good Indicator. Open drain output pulls low

when the FB pin drops below 1.21V indicating the power is

bad. If the FB pin rises above 1.23V and the GATE to OUT

voltage exceeds 4.2V, the open-drain pull-down releases

the PG pin to go high.

SENSE–: Current Sense Minus Input. Connect this pin to

the opposite of VDD current sense resistor side. The cur-

rent limit circuit controls the GATE pin to limit the sense

voltage between the SENSE+ and SENSE– pins to 15mV

or less depending on the voltage at the FB pin.

SENSE+: Current Sense Plus Input. Connect this pin to

the VDD side of the current sense resistor.

SOURCE: N-Channel MOSFET Source Connection. Connect

this pin to the source of the external N-channel MOSFET

switch. This pin provides a return for the gate pull-down

circuit. In the LTC4218-12 version, the power good com-

parator monitors an internal resistive divider between the

SOURCE pin and GND.

TIMER: Timer Input. Connect a capacitor between this pin

and ground to set a 12ms/μF duration for current limit

before the switch is turned off. If the UV pin is toggled

low while the MOSFET switch is off, the switch will turn on

again following a cool down time of 518ms/μF duration.

UV: Undervoltage Comparator Input. Tie high if unused.

Connect this pin to an external resistive divider from VDD for

the LTC4218 (adjustable version). The LTC4218-12 version

drives the UV pin with an internal resistive divider from

VDD. Open the pin if the preset LTC4218-12 thresholds for

12V operation are desired. If the UV pin voltage falls below

1.15V, an undervoltage is detected and the switch turns

off. Pulling this pin below 0.62V resets the overcurrent

fault and allows the switch to turn back on (see Applica-

tions Information for details). If overcurrent auto-retry is

desired then tie this pin to the FLT

pin.

VDD: Supply Voltage. This pin has an undervoltage lockout

threshold of 2.73V.

LTC4218

4218ff

FUNCTIONAL DIAGRAM

4218 BD

20k

VDD

* DFN ONLY

EXPOSED PAD*

IMON

INTVCC

100μA

TIMER

FLT

–

ISET

GATE SOURCE

GND

CLAMP

0.6V

REFERENCE

CHARGE

PUMP

AND GATE

DRIVER

3.1V

GEN

LOGIC

FOLDBACK

0.6V

2.65V

1.235V

+–

–

1.235V

–

0.2V

–

TM1

1.235V –

TM2

0.62V

–

RST

VDD

2.73V +

–

UVLO1

1.235V –

2μA

–

UVLO2

SENSE–

SENSE+

SOURCE

150k

20k

140k

20k

224k

20k

LTC4218

4218ff

OPERATION

The Functional Diagram displays the main circuits of the

device. The LTC4218 is designed to turn a board’s sup-

ply voltage on and off in a controlled manner, allowing

the board to be safely inserted and removed from a live

backplane. During normal operation, the charge pump

and gate driver turn on the external N-channel pass FET’s

gate to provide power to the load.

The current sense (CS) ampliﬁ er monitors the load current

using the voltage sensed across the current sense resistor.

The CS ampliﬁ er limits the current in the load by reducing

the GATE-to-SOURCE voltage in an active control loop. It

is simple to adjust the current limit threshold using the

current setting (ISET) pin. This allows a different threshold

during other times such as startup.

A short circuit on the output to ground causes signiﬁ cant

power dissipation during active current limiting. To limit

this power, the foldback ampliﬁ er reduces the current limit

value from 15mV to 3.75mV (referred to the SENSE+ minus

SENSE– voltage) in a linear manner as the FB pin drops

below 0.6V (see Typical Performance Characteristics).

If an overcurrent condition persists, the TIMER pin ramps

up with a 100μA current source until the pin voltage exceeds

1.2V (comparator TM2). This indicates to the logic that it

is time to turn off the MOSFET to prevent overheating. At

this point the TIMER pin ramps down using the 2μA current

source until the voltage drops below 0.2V (Comparator

TM1) which tells the logic to start an internal 100ms timer.

At this point, the pass transistor has cooled and it is safe

to turn it on again.

The ﬁ xed 12V version, LTC4218-12, uses two separate

internal dividers from VDD to drive the UV and OV pins.

This version also features a divider from the SOURCE pin

to drive the FB pin. The LTC4218-12 is available in a DFN

package while the LTC4218 (adjustable version) is in a

SSOP package.

The output voltage is monitored using the FB pin and the

PG comparator to determine if the power is available for

the load. The power good condition is signaled by the PG

pin using an open-drain pull-down transistor.

The Functional Diagram shows the monitoring blocks of

the LTC4218. The comparators on the left side include

the UV and OV comparators. These comparators are used

to determine if the external conditions are valid prior to

turning on the MOSFET. But ﬁ rst, the undervoltage lockout

circuits (UVLO1 and UVLO2) must validate the input supply

and internally generated 3.1V supply (INTVCC) and gener-

ate the power up initialization to the logic circuits. If the

external conditions remain valid for 100ms the MOSFET

is allowed to turn on.

Other monitoring features include the IMON current monitor.

The current monitor (CM) outputs a current proportional

to the sense resistor current. This current can drive an

external resistor or other circuits for monitoring purposes.

LTC4218

4218ff

APPLICATIONS INFORMATION

The typical LTC4218 application is in a high availability

system that uses a positive voltage supply to distribute

power to individual cards. The basic application circuit

is shown in Figure 1. External component selection is

discussed in detail in the following sections.

Figure 2. Supply Turn-On

Figure 1. 3A, 12V Card Resident Application

Turn-On Sequence

The power supply on a board is controlled by placing

an external N-channel pass transistor (Q1) in the power

path. Note the sense resistor (RS) detects current and

the capacitor (CGATE) controls gate slew rate. Resistor R1

prevents high frequency oscillations in Q1 and resistor

RGATE isolates CGATE during fast turn-off.

Several conditions must be present before the external

pass transistor can be turned on. First, the supply VDD

must exceed its undervoltage lockout level. Next, the

internally generated supply INTVCC must cross its 2.65V

undervoltage threshold. This generates a 25μs power-

on-reset pulse which clears the logic’s fault register and

initializes internal latches.

After the power-on-reset pulse, the LTC4218 will go through

the following sequence. First, the UV and OV pins must

indicate that the input power is within the acceptable range.

All of these conditions must be satisﬁ ed for a duration

of 100ms to ensure that any contact bounce during the

insertion has ended.

The pass transistor is turned on by charging up the GATE

with a 24μA charge pump generated current source

(Figure 2).

The voltage at the GATE pin rises with a slope equal to

24μA/CGATE and the supply inrush current is set at:

IINRUSH =CL

CGATE

•24μA

When the GATE voltage reaches the MOSFET threshold

voltage, the switch begins to turn on and the SOURCE

voltage follows the GATE voltage as it increases. Once

SOURCE reaches VDD, the GATE will ramp up until clamped

by the 6.15V zener between GATE and SOURCE.

As the SOURCE pin voltage rises, so will the FB pin which

is monitoring it. If the voltage across the current sense

resistor (RS) gets too high, the inrush current will be limited

by the internal current limiting circuitry. Once the FB pin

crosses its 1.235V threshold and the GATE to SOURCE

voltage exceeds 4.2V, the PG pin will cease to pull low and

indicate that the power is good.

Turn-Off Sequence

The switch can be turned off by a variety of conditions. A

normal turn-off is initiated by the UV pin going below its

1.235V threshold. Additionally, several fault conditions will

turn off the switch. These include an input overvoltage (OV

pin) and overcurrent circuit breaker (SENSE pin). Normally,

the switch is turned off with a 250μA current pulling down

the GATE pin to ground. With the switch turned off, the

SOURCE pin voltage drops which pulls the FB pin below

its threshold. The PG then pulls low to indicate output

power is no longer good.

150k

20k

ADC

226k

0.1μF

20k

12V

4218 F01

10k

10Ω

0.1μF

330μF

VOUT

12V

VDD

GND

IMON

RSET

20k

2mΩ

Si7108DN

RMON

20k

ISET

CGATE

0.01μF

RGATE

GATE SOURCESENSE–

SENSE+

LTC4218GN

INTVCC

TIMER

FLT

140k

20k

t1 t2

SLOPE = 24μA/CGATE

GATE

SOURCE

VDD + 6.15

VDD

4218 F02

LTC4218

4218ff

APPLICATIONS INFORMATION

If VDD drops below 2.65V for greater than 5μs or INTVCC

drops below 2.5V for greater than 1μs, a fast shutdown

of the switch is initiated. The GATE is pulled down with a

170mA current to the SOURCE pin.

Overcurrent Fault

The LTC4218 features an adjustable current limit with

foldback that protects the MOSFET when excessive load

current happens. To protect the switch during active cur-

rent limit, the available current is reduced as a function

of the output voltage sensed by the FB pin. A graph in the

Typical Performance Characteristics shows the current

limit versus FB voltage.

An overcurrent fault occurs when the current limit circuitry

has been engaged for longer than the time-out delay set by

the TIMER. Current limiting begins when the current sense

voltage between the SENSE+ and SENSE– pins reaches

3.75mV to 15mV (depending on the foldback). The GATE

pin is then brought down with a 170mA GATE-to-SOURCE

current. The voltage on the GATE is regulated in order to

limit the current sense voltage to less than 15mV. At this

point, a circuit breaker time delay starts by charging the

external timing capacitor from the TIMER pin with a 100μA

pull-up current. If the TIMER pin reaches its 1.2V thresh-

old, the external switch turns off (with a 250μA current

from GATE to ground). Next, the FLT pin is pulled low to

indicate an overcurrent fault has turned off the MOSFET.

For a given circuit breaker time delay, the equation for

setting the timing capacitor’s value is as follows:

T = TCB • 0.083[μF/ms]

After the switch is turned off, the TIMER pin begins

discharging the timing capacitor with a 2μA pull-down

current. When the TIMER pin reaches its 0.2V threshold,

the switch is allowed to turn on again if the overcurrent

fault has been cleared. Bringing the UV pin below 0.6V

and then high will clear the fault.

Tying the FLT pin to the UV pin allows the part to self-clear

the fault and turn the MOSFET on as soon as TIMER pin has

ramped below 0.2V. In this auto retry mode, the LTC4218

repeatedly tries to turn on after an overcurrent at a period

determined by the capacitor on the TIMER pin.

The waveform in Figure 3 shows how the output latches

off following a short circuit. The drop across the sense

resistor is 3.75mV as the timer ramps up.

Figure 3. Short-Circuit Waveform

Current Limit Adjustment

The default value of the active current limiting signal

threshold is 15mV. The current limit threshold can be

adjusted lower by placing a resistor on the ISET pin. As

shown in the Functional Diagram the voltage at the ISET

pin (via the clamp circuit) sets the CS ampliﬁ er’s built-in

offset voltage. This offset voltage directly determines the

active current limit value. With the ISET pin open, the volt-

age at the ISET pin is determined by the buffered reference

voltage. This voltage is set to 0.618V which corresponds

to a 15mV current limit threshold.

An external resistor placed between the ISET pin and ground

forms a resistive divider with the internal 20k sourcing

resistor. The divider acts to lower the voltage at the ISET

pin and therefore lower the current limit threshold. The

overall current limit threshold precision is reduced to ±11%

when using a 20k resistor to half the threshold.

Using a switch (connected to ground) in series with the

external resistor allows the active current limit to change

only when the switch is closed. This feature can be used

when the startup current exceeds the typical maximum

load current.

1ms/DIV 4218 F03

$VGATE

10V/DIV

IOUT

2A/DIV

VOUT

10V/DIV

TIMER

2V/DIV

LTC4218

4218ff

APPLICATIONS INFORMATION

Monitor MOSFET Current

The current in the MOSFET passes through the sense

resistor. The voltage on the sense resistor is converted to

a current that is sourced out of the IMON pin. The gain of

the ISENSE ampliﬁ er is 100μA from IMON for 15mV on the

sense resistor. This output current can be converted to a

voltage using an external resistor to drive a comparator

or ADC. The voltage compliance for the IMON pin is from

0V to INTVCC – 0.7V.

A microcontroller with a built-in comparator can build a

simple integrating single-slope ADC by resetting a capaci-

tor that is charged with this current. When the capacitor

voltage trips the comparator and the capacitor is reset, a

timer is started. The time between resets will indicate the

MOSFET current.

Monitor OV and UV Faults

Protecting the load from an overvoltage condition is the

main function of the OV pin. In the LTC4218-12 an internal

resistive divider (driving the OV pin) connects to a compara-

tor to turn off the MOSFET when the VDD voltage exceeds

15.05V. If the VDD pin subsequently falls back below 14.8V,

the switch will be allowed to turn on immediately. In the

LTC4218, the OV pin threshold is 1.235V when rising and

1.215V when falling out of overvoltage.

The UV pin functions as an undervoltage protection pin or

as an “on” pin. In the LTC4218-12 the MOSFET turns off

when VDD falls below 9.23V. If the VDD pin subsequently

rises above 9.88V for 100ms, the switch will be allowed

to turn on again. The LTC4218 UV turn on/off threshold

is 1.235V (rising) and 1.155V (falling).

In the case of an undervoltage or overvoltage, the MOSFET

turns off and there is indication on the PG status pin. When

the overvoltage is removed, the MOSFET’s gate ramps up

immediately.

Power Good Indication

In addition to setting the foldback current limit threshold,

the FB pin is used to determine a power good condition.

The LTC4218-12 uses an internal resistive divider on the

SOURCE pin to drive the FB pin. The PG comparator in-

dicates logic high when SOURCE pin rises above 10.5V. If

the SOURCE pin subsequently falls below 10.3V, the com-

parator toggles low. On the LTC4218, the PG comparator

drives high when the FB pin rises above 1.23V and low

when falls below 1.215V.

Once the PG comparator is high, the GATE pin voltage

is monitored with respect to the SOURCE pin. Once the

GATE minus SOURCE voltage exceeds 4.2V, the PG pin

goes high. This indicates to the system that it is safe to

load the Output while the MOSFET is completely turned

“on”. The PG pin goes low when the GATE is commanded

off (using the UV, OV or SENSE+/SENSE– pins) or when

the PG comparator drives low.

12V Fixed Version

In the LTC4218-12, the UV, OV and FB pins are driven by

internal dividers which may need to be ﬁ ltered to prevent

false faults. By placing a bypass capacitor on these pins

the faults are delayed by the RC time constant. Use the RIN

value from the electrical table for this calculation.

In cases where the ﬁ xed thresholds need a slight adjust-

ment, placing a resistor from the UV or OV pins to VDD

or GND will adjust the threshold up or down. Likewise,

placing a resistor between FB pin to OUT or GND adjusts

the threshold. Again, use the RIN value from the electrical

table for this calculation.

An example in Figure 4 raises the UV turn-on voltage from

9.88V to 10.5V. Increasing the UV level requires adding a

resistor between UV and ground. The resistor, (RSHUNT1),

can be calculated using electrical table parameters as

follows:

RSHUNT1 =RIN

()

•V

OLD

NEW –V

OLD

()

=18k • 9.88

10.5 – 9.88

()

=287k

Figure 4. Adjusting LTC4218-12 Thresholds

4218 F04

LTC4218-12

RSHUNT1

RSHUNT2

VDD

LTC4218

4218ff

APPLICATIONS INFORMATION

In this same ﬁ gure the OV threshold is lowered from

15.05V to 13.5V. Decreasing the OV threshold requires

adding a resistor between VDD and OV. This resistor can

be calculated as follows:

RSHUNT2 =RIN

()

•V

OLD

VTH

()

VNEW –V

OV TH

()

VOLD –V

NEW

()

⎛

⎝

⎜

⎞

⎠

⎟

⎟=

18k •15.05

1.235

13.5–1.235

()

15.05–13.5

()

⎛

⎝

⎜

⎞

⎠

⎟

⎟=1.736M

Use the equation for RSHUNT1 for increasing the OV and

FB thresholds. Likewise, use the equation for RSHUNT2 for

decreasing the UV and FB thresholds.

Design Example

Consider the following design example (Figure 5): VIN =

12V, IMAX = 7.5A. IINRUSH = 1A, CL = 330μF, VUVON = 9.88V,

VOVOFF = 15.05V, VPWRGD = 10.5V. A current limit fault trig-

gers an automatic restart of the power up sequence.

The selection of the sense resistor, (RS), is set by the

overcurrent threshold of 15mV:

S = 15mV/IMAX = 15mV/7.5A = 0.002Ω

The MOSFET should be sized to handle the power dissi-

pation during the inrush charging of the output capacitor

COUT. The method used to determine the power in Q1 is

the principal:

C = Energy in CL = Energy in Q1

Thus:

C = ½ CV2 = ½ (330μF)(12)2 = 0.024J

Calculate the time it takes to charge up COUT:

tCHARGUP =CL•V

IINRUSH

=330μF • 12V

1A =4ms

The inrush current is set to 1A using CGATE:

CGATE =CL

IGATE(UP)

IINRUSH

=330μF 24μA

1A ≅0.01μF

The average power dissipated in the MOSFET:

DISS = EC/tCHARGUP = 0.024J/4ms = 6W

The SOA (safe operating area) curves of candidate MOS-

FETs must be evaluated to ensure that the heat capacity

of the package can stand 6W for 4ms. The SOA curves of

the Vishay Siliconix Si7108DN provide 1.5A at 10V (15W)

for 100ms, satisfying the requirement.

Figure 5. 6A, 12V Card Resident Application

12V

0.1μF ADC

0.1μF

20k

4218 F05

10k

330μF

SENSE–GATE

SENSE+

VDD

SOURCE

GND

IMON

LTC4218DHC-12

INTVCC

TIMER

FLT

10Ω

2mΩ

Si7108DN

12V

VOUT

12V

RGATE

CGATE

0.01μF

LTC4218

4218ff

APPLICATIONS INFORMATION

Next, the power dissipated in the MOSFET during overcur-

rent must be limited. The active current limit uses a timer

to prevent excessive energy dissipation in the MOSFET. The

worst-case power occurs when the voltage versus current

proﬁ le of the foldback current limit is at the maximum.

This occurs when the current is 6A and the voltage is one

half of 12V or (6V). See the Current Limit Sense Voltage vs

FB Voltage in the Typical Performance curves to view this

proﬁ le. In order to survive 36W, the MOSFET SOA dictates

a maximum time at this power level. The Si7108DN allows

60W for 10ms or less. Therefore, it is acceptable to set

the current limit timeout using CT to be 1.2ms:

T = 1.2ms/12[ms/μF] = 0.1μF

After the 1.2ms timeout the FLT pin needs to pull down on

the UV pin to restart the power-up sequence.

Since the default values for overvoltage, undervoltage and

power good thresholds for the 12V ﬁ xed version match

the requirements, no external components are required

for the UV, OV and FB pins.

The ﬁ nal schematic results in very few external com-

ponents. Resistor R1 (10Ω) prevents high frequency

oscillations in Q1 while RGATE of 1k isolates CGATE during

fast turn-off. The pull-up resistor, (R2), connects to the

PG pin while the 20k (R3) converts the IMON current to a

voltage at a ratio:

IMON =6.67 μA

⎡

⎣

⎢⎤

⎦

⎥•2 mV

⎡

⎣

⎢⎤

⎦

⎥•20k•I

OUT =0.267 V

⎡

⎣

⎢⎤

⎦

⎥•I

OUT

In addition, there is a 0.1μF bypass (C1) on the INTVCC pin.

Layout Considerations

To achieve accurate current sensing, a Kelvin connection

for the sense resistor is recommended. The PCB layout

should be balanced and symmetrical to minimize wiring

errors. In addition, the PCB layout for the sense resistors

and the power MOSFETs should include good thermal

management techniques for optimal device power dissipa-

tion. A recommended PCB layout for the sense resistor

and power MOSFET is illustrated in Figure 6.

In Hot Swap applications where load currents can be 6A,

narrow PCB tracks exhibit more resistances than wider

tracks and operate at elevated temperatures. The minimum

trace width for 1oz copper foil is 0.02” per amp to make sure

the trace stays at a reasonable temperature. Using 0.03”

per amp or wider is recommended. Note that 1oz copper

exhibits a sheet resistance of about 0.5mΩ/square. Small

resistances add up quickly in high current applications.

Figure 6. Recommended Layout

4218 F06

LTC4218

4218ff

Figure 7. 3.3V, 6A Card Resident Application

APPLICATIONS INFORMATION

It is also important to put C1, the bypass capacitor for the

INTVCC pin, as close as possible between the INTVCC and

GND. Place the 10Ω resistor as close as possible to Q1.

This will limit the parasitic trace capacitance that leads to

Q1 self-oscillation.

Additional Applications

The LTC4218 has a wide operating range from 2.9V to

26.5V. The UV, OV and PG thresholds are set with a few

0.1μF

14.7k

10k

17.4k

ADC

3.16k

10k

3.3V

RMON

20k

4218 F07

10k

330μF

SENSE–GATE

SENSE+

VDD

SOURCE

GND

IOUT

LTC4218GN

INTVCC

TIMER

FLT

10Ω

2mΩ

Si7102DN

3.3V

RGATE

CGATE

0.01μF

VOUT

3.3V

resistors. All other functions are independent of supply

voltage.

The last page includes a 24V application with a UV

threshold of 19.8V, an OV threshold of 28.3V and a PG

threshold of 20.75V. Figure 7 shows a 3.3V applica-

tion with a UV threshold of 2.87V, an OV threshold of

3.77V and a PG threshold of 3.05V. Figure 8 shows a

backplane resident application, where load insertion

activates turn-on.

Figure 8. 12V, 6A Backplane Resident Application with Insertion Activiated Turn -On

0.1μF

20k

140k

150k

ADC

12V

LOAD

RMON

20k

4218 F08

10k

SENSE–GATE

SENSE+

VDD

SOURCE

GND

IMON

LTC4218GN

INTVCC

TIMER

FLT

10Ω

2mΩ

Si7108DN

RGATE

1kCGATE

0.01μF

VOUT

12V

20k

LTC4218

4218ff

PACKAGE DESCRIPTION

GN Package

16-Lead Plastic SSOP (Narrow .150 Inch)

(Reference LTC DWG # 05-08-1641)

DHC Package

16-Lead Plastic DFN (5mm × 3mm)

(Reference LTC DWG # 05-08-1706)

3.00 ±0.10

(2 SIDES)

5.00 ±0.10

(2 SIDES)

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE

TOP AND BOTTOM OF PACKAGE

NOTE:

1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WJED-1)

IN JEDEC PACKAGE OUTLINE MO-229

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

0.40 ± 0.10

BOTTOM VIEW—EXPOSED PAD

1.65 ± 0.10

(2 SIDES)

0.75 ±0.05

R = 0.115

TYP

R = 0.20

TYP

4.40 ±0.10

(2 SIDES)

169

PIN 1

TOP MARK

(SEE NOTE 6)

0.200 REF

0.00 – 0.05

(DHC16) DFN 1103

0.25 ± 0.05

PIN 1

NOTCH

0.50 BSC

4.40 ±0.05

(2 SIDES)

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

1.65 ±0.05

(2 SIDES)2.20 ±0.05

0.50 BSC

0.65 ±0.05

3.50 ±0.05

PACKAGE

OUTLINE

0.25 ± 0.05

GN16 (SSOP) 0204

345678

.229 – .244

(5.817 – 6.198)

.150 – .157**

(3.810 – 3.988)

16 15 14 13

.189 – .196*

(4.801 – 4.978)

12 11 10 9

.016 – .050

(0.406 – 1.270)

.015 ± .004

(0.38 ± 0.10) × 45°

0° – 8° TYP

.007 – .0098

(0.178 – 0.249)

.0532 – .0688

(1.35 – 1.75)

.008 – .012

(0.203 – 0.305)

TYP

.004 – .0098

(0.102 – 0.249)

.0250

(0.635)

BSC

.009

(0.229)

REF

.254 MIN

RECOMMENDED SOLDER PAD LAYOUT

.150 – .165

.0250 BSC.0165 ±.0015

.045 ±.005

* DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD

FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

INCHES

(MILLIMETERS)

NOTE:

1. CONTROLLING DIMENSION: INCHES

2. DIMENSIONS ARE IN

3. DRAWING NOT TO SCALE

Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

LTC4218

4218ff

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

REVISION HISTORY

REV DATE DESCRIPTION PAGE NUMBER

D 12/09 Revised Order Information.

Revised Equation in Applications Information.

E 04/10 Revised Storage Temperature Range in Absolute Maximum Ratings section.

Revised Additional Applications section and inserted Figure 8 in Applications Information.

F 1/12 Updated Typical Applications.

Revised Inputs and Outputs sections of Electrical Characteristics.

Updated INTVCC and PG pin descriptions.

Changed value of R2 in Figure 1.

Deleted text from Overcurrent & Fault section and updated values in Monitor OV and UV Faults section.

Revised Typical Application and Related Parts list.

11, 12

(Revision history begins at Rev D)

LTC4218

4218ff

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com

LT 0112 REV F • PRINTED IN USA

TYPICAL APPLICATION

24V, 6A Card Resident Application with Auto-Retry

RELATED PARTS

PART NUMBER DESCRIPTION COMMENTS

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158k

10k

215k

ADC

4.32k

0.1μF

10k

24V

20k

4218 TA02

*DIODES INC., SMAJ24A

10k

0.1μF

330μF

SENSE–GATE

SENSE+

VDD

SOURCE

GND

IMON

ISET

LTC4218GN

INTVCC

TIMER

FLT

10Ω

Si7788DP

24V

2mΩ

0.01μF

VOUT

24V