Rev.5.00, Nov. 17.2003, page 1 of 22
HN58V256A Series
HN58V257A Series
256k EEPROM (32-kword × 8-bit)
Ready/Busy and RES function (HN58V257A)
REJ03C0147-0500Z
(Previous ADE-203-357D (Z) Rev.4.0)
Rev. 5.00
Nov. 17. 2003
Description
Renesas Technology's HN58V256A and HN58V257A are electrically erasable and programmable ROMs
organized as 32768-word × 8-bit. They have r ealized high speed, low power con sum ption and h ig h reliability
by employing advanced MNOS memory technology and CMOS process and circuitry technology. They also
have a 64-byte page programming function to make their write operations faster.
Features
• Single 3 V supply: 2.7 to 5.5 V
• Access time: 120 ns max
• Power dissipation:
Active: 20 mW/MHz, (typ)
Standby: 110 µW (max)
• On-chip latches: address, data, CE, OE, WE
• Automatic by te wr ite: 10 ms max
• Automatic page write (64 bytes): 10 ms max
• Ready/Busy (only the HN58V257A series)
• Data polling and Toggle bit
• Data protection circuit on power on/off
• Conforms to JEDEC byte-wide standard
• Reliable CMOS with MNOS cell technology
• 105 erase/write cycles (in page mode)
• 10 years data retention
• Software data protection
• Write protection by RES pin (only the HN58V257A series)
• Industrial versions (Temperature range: −20 to 85°C and −40 to 85°C) are also available.
• There are free also lead free products.
HN58V256A Series, HN58V257A Series
Rev.5.00, Nov. 17.2003, page 2 of 22
Ordering Information
Type No. Access time Package
HN58V256AFP-12 120 ns 400 mil 28-pin plastic SOP (FP-28D)
HN58V256AT-12 120 ns 28-pin plastic TSOP (TFP-28DB)
HN58V257AT-12 120 ns 32-pin plastic TSOP (TFP-32DA)
HN58V256AFP-12E 120 ns 400 mil 28-pin plastic SOP (FP-28DV)
Lead Free
HN58V256AT-12E 120 ns 28-pin plastic TSOP (TFP-28DBV)
Lead Free
HN58V257AT-12E 120 ns 32-pin plastic TSOP (TFP-32DAV)
Lead Free
Pin Arrangement
HN58V256AFP Series HN58V256AT Series
HN58V257AT Series
(Top view)
(Top view)
(Top view)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
V
SS
V
CC
WE
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
A2
A1
A0
I/O0
I/O1
I/O2
V
SS
I/O3
I/O4
I/O5
I/O6
I/O7
CE
A10
A3
A4
A5
A6
A7
A12
A14
V
CC
WE
A13
A8
A9
A11
OE
15
16
17
18
19
20
21
22
23
24
25
26
27
28
14
13
12
11
10
9
8
7
6
5
4
3
2
1
A2
A1
A0
I/O0
I/O1
I/O2
V
SS
I/O3
I/O4
I/O5
I/O6
I/O7
CE
A10
A3
A4
A5
A6
A7
A12
A14
V
CC
WE
A13
A8
A9
A11
OE
17
18
19
20
21
22
23
24
25
26
27
28
29
30
16
15
14
13
12
11
10
9
8
7
6
5
4
3
31
32 2
1
NC
NC
RES
RDY/
Busy
HN58V256A Series, HN58V257A Series
Rev.5.00, Nov. 17.2003, page 3 of 22
Pin Description
Pin name Function
A0 to A14 Address input
I/O0 to I/O7 Data input/output
OE Output enable
CE Chip enable
WE Write enable
VCC Power supply
VSS Ground
RDY/Busy*1 Ready busy
RES*1 Reset
NC No connection
Note: 1. This function is supported by only the HN58V257A series.
Block Diagram
Note: 1. This function is supported by only the HN58V257A series.
V
V
OE
CE
A5
A0
A6
A14
WE
CC
SS
I/O0 I/O7
High voltage generator
Control logic and timing
Y decoder
X decoder
Address
buffer and
latch
I/O buffer
and
input latch
Y gating
Memory array
Data latch
RES
RDY/
Busy
RES
*
1
*
1
*
1
to
to
to
HN58V256A Series, HN58V257A Series
Rev.5.00, Nov. 17.2003, page 4 of 22
Operation Table
Operation CE
CECE
CE
OE
OE OE
OE
WE
WEWE
WE RES
RESRES
RES*3 RDY/Busy
BusyBusy
Busy*3 I/O
Read VIL V
IL V
IH V
H*1 High-Z Dout
Standby VIH ×*2 × × High-Z High-Z
Write VIL V
IH V
IL V
H High-Z to VOL Din
Deselect VIL V
IH V
IH V
H High-Z High-Z
Write inhibit × × V
IH ×
× V
IL × ×
Data polling VIL V
IL V
IH V
H V
OL Data out (I/O7)
Program reset × × × V
IL High-Z High-Z
Notes: 1. Refer to the recommended DC operating condition.
2. ×: Don’t care
3. This function is supported by only the HN58V267A series.
Absolute Maximum Ratings
Parameter Symbol Value Unit
Supply voltage relative to VSS V
CC −0.6 to +7.0 V
Input voltage relative to VSS Vin −0.5*1 to +7.0*3 V
Operating temperature range*2 Topr 0 to +70 °C
Storage temperature range Tstg −55 to +125 °C
Notes: 1. Vin min = −3.0 V for pulse width ≤ 50 ns
2. Including electrical characteristics and data retention
3. Should not exceed VCC + 1.0 V.
Recommended DC Operating Conditions
Parameter Symbol Min Typ Max Unit
Supply voltage VCC 2.7 3.0 5.5 V
V
SS 0 0 0 V
Input voltage VIL −0.3*1 0.6 V
V
IH 1.9*2 V
CC + 0.3*3 V
V
H*4 V
CC −0.5 V
CC + 1.0 V
Operating temperature Topr 0 +70 °C
Notes: 1. VIL min: −1.0 V for pulse width ≤ 50 ns.
2. VIH min for VCC = 3.6 to 5.5 V is 2.4 V.
3. VIH max: VCC + 1.0 V for pulse width ≤ 50 ns.
4. This function is supported by only the HN58V257A series.
HN58V256A Series, HN58V257A Series
Rev.5.00, Nov. 17.2003, page 5 of 22
DC Characteristics (Ta = 0 to +70°C, VCC = 2.7 to 5.5 V)
Parameter Symbol Min Typ Max Unit Test conditions
Input leakage current ILI 2*1 µA VCC = 5.5 V, Vin = 5.5 V
Output leakage current ILO 2 µA VCC = 5.5 V, Vout = 5.5/0.4 V
Standby VCC current ICC1 20 µA CE = VCC
I
CC2 1 mA CE = VIH
Operating VCC current ICC3 8 mA Iout = 0 mA, Duty = 100%,
Cycle = 1 µs, VCC = 3.6 V
12 mA Iout = 0 mA, Duty = 100%,
Cycle = 1 ns, VCC = 5.5 V
12 mA Iout = 0 mA, Duty = 100%,
Cycle = 120 µs, VCC = 3.6 V
30 mA Iout = 0 mA, Duty = 100%,
Cycle = 120 ns, VCC = 5.5 V
Output low voltage VOL 0.4 V IOL = 2.1 mA
Output high voltage VOH V
CC × 0.8 V IOH = −400 µA
Note: 1. ILI on RES = 100 µA max (only the HN58V257A series)
Capacitance (Ta = +25°C, f = 1 MHz)
Parameter Symbol Min Typ Max Unit Test conditions
Input capacitance*1 Cin 6 pF Vin = 0 V
Output capacitance*1 Cout 12 pF Vout = 0 V
Note: 1. This parameter is periodically sampled and not 100% tested.
HN58V256A Series, HN58V257A Series
Rev.5.00, Nov. 17.2003, page 6 of 22
AC Characteristics (Ta = 0 to +70°C, VCC = 2.7 to 5.5 V)
Test Condit ions
• Input pulse levels: 0.4 V to 2.4 V (VCC ≤ 3.6V), 0.4V to 3.0 V (VCC > 3.6 V), 0 V to VCC (RES pin*2)
• Input rise and fall time: ≤ 5 ns
• Input timing reference levels: 0.8, 1.8 V
• Output load: 1TTL Gate +100 pF
• Output reference levels: 1.5 V, 1.5 V
Read Cycle
HN58V256A/HN58V257A
-12
Parameter Symbol Min Max Unit Test conditions
Address to output delay tACC 120 ns CE = OE = VIL, WE = VIH
CE to output delay tCE 120 ns OE = VIL, WE = VIH
OE to output delay tOE 10 60 ns CE = VIL, WE = VIH
Address to output hold tOH 0 ns CE = OE = VIL, WE = VIH
OE (CE) high to output float*1 t
DF 0 40 ns CE = VIL, WE = VIH
RES low to output float*1, 2 t
DFR 0 350 ns CE = OE = VIL, WE = VIH
RES to output delay*2 t
RR 0 600 ns CE = OE = VIL, WE = VIH
HN58V256A Series, HN58V257A Series
Rev.5.00, Nov. 17.2003, page 7 of 22
Write Cycle
Parameter Symbol Min*3 Typ Max Unit Test conditions
Address setup time tAS 0 ns
Address hold time tAH 50 ns
CE to write setup time (WE controlled) tCS 0 ns
CE hold time (WE controlled) tCH 0 ns
WE to write setup time (CE controlled) tWS 0 ns
WE hold time (CE controlled) tWH 0 ns
OE to write setup time tOES 0 ns
OE hold time tOEH 0 ns
Data setup time tDS 70 ns
Data hold time tDH 0 — ns
WE pulse width (WE controlled) tWP 200 ns
CE pulse width (CE controlled) tCW 200 ns
Data latch time tDL 100 ns
Byte load cycle tBLC 0.3 30 µs
Byte load window tBL 100 µs
Write cycle time tWC 10*4 ms
Time to device busy tDB 120 ns
Write start time tDW 0*5 ns
Reset protect time*2 t
RP 100 µs
Reset high time*2, 6 t
RES 1 µs
Notes: 1. tDF and tDFR are defined as the time at which the outputs achieve the open circuit conditions and are
no longer driven.
2. This function is supported by only the HN58V257A series.
3. Use this device in longer cycle than this value.
4. tWC must be longer than this value unless polling techniques or RDY/Busy (only the HN58V257A
series) are used. This device automatically completes the internal write operation within this value.
5. Next read or write operation can be initiated after tDW if polling techniques or RDY/Busy (only the
HN58V257A series) are used.
6. This parameter is sampled and not 100% tested.
7. A6 through A14 are page addresses and these addresses are latched at the first falling edge of
WE.
8. A6 through A14 are page addresses and these addresses are latched at the first falling edge of
CE.
9. See AC read characteristics.
HN58V256A Series, HN58V257A Series
Rev.5.00, Nov. 17.2003, page 8 of 22
Timing Waveforms
Read Timing Waveform
Address
CE
OE
WE
Data Out
High
Data out valid
tACC
tCE
tOE
tOH
tDF
tRR
tDFR
RES
*2
HN58V256A Series, HN58V257A Series
Rev.5.00, Nov. 17.2003, page 9 of 22
Byte Writ e Timing Waveform (1 ) (WE Controlled)
Address
CE
WE
OE
Din
RDY/
Busy
*2
tWC
tCH
tAH
tCS
tAS tWP
tOEH
tBL
tOES
tDS tDH
tDB
tRP
RES
*2
VCC
tRES
High-Z High-Z
tDW
HN58V256A Series, HN58V257A Series
Rev.5.00, Nov. 17.2003, page 10 of 22
Byte Writ e Timing Waveform (2 ) (CE Controlled)
Address
CE
WE
OE
Din
RDY/
Busy
*
2
t
WC
t
AH
t
WS
t
AS
t
OEH
t
WH
t
OES
t
DS
t
DH
t
DB
t
RP
RES
*
2
V
CC
t
CW
t
BL
t
DW
t
RES
High-Z High-Z
HN58V256A Series, HN58V257A Series
Rev.5.00, Nov. 17.2003, page 11 of 22
Page Write Timing Waveform (1) (WE Controlled)
Address
A0 to A14
WE
CE
OE
Din
RDY/
Busy
*2
tAS tAH tBL
tWC
tOEH
tDH
tDB
tOES
tRP
tRES
RES
*2
VCC
tCH
tCS
tWP tDL tBLC
tDS
tDW
High-Z High-Z
*7
HN58V256A Series, HN58V257A Series
Rev.5.00, Nov. 17.2003, page 12 of 22
Page Write Timing Waveform (2) (CE Controlled)
Address
A0 to A14
WE
CE
OE
Din
RDY/
Busy
*2
tAS tAH tBL
tWC
tOEH
tDH
tDB
tOES
tRP
tRES
RES
*2
VCC
tWH
tWS
tCW
tDL tBLC
tDS
tDW
High-Z High-Z
*8
HN58V256A Series, HN58V257A Series
Rev.5.00, Nov. 17.2003, page 13 of 22
Data
DataData
Data Polling Timing Wa veform
tCE
tOEH
tWC
tDW
tOES
Address
CE
WE
OE
I/O7
tOE
Din X
An An
Dout
X
Dout X
*9
*9
An
HN58V256A Series, HN58V257A Series
Rev.5.00, Nov. 17.2003, page 14 of 22
Toggle bit
This device provide another function to determine the internal programming cycle. If the EEPROM is set to
read mode during the internal programming cycle, I/O6 will charge from “1” to “0” (toggling) for each read.
When the intern al programming cycle is finished, to g gling of I/O6 will stop and the d e v ice can be accessible
for next read or program.
Toggle bit Waveform
Notes: 1. I/O6 beginning state is “1”.
2. I/O6 ending state will var y.
3. See AC read characteristics.
4. Any address location can be used, but the address must be fixed.
WE
t
OES
OE
CE
Dout
I/O6 Dout Dout Dout
Next mode
t
OE
t
CE
t
DW
t
WC
t
OEH
*1 *2 *2
Address
*3
*3
*4
Din
HN58V256A Series, HN58V257A Series
Rev.5.00, Nov. 17.2003, page 15 of 22
Software Data Protection Timing Waveform (1) (in protection mode)
V
CE
WE
Address
Data 5555
AA 2AAA
55 5555
A0
tBLC tWC
CC
Write address
Write data
Software Data Protection Timing Waveform (2) (in non-protection mode)
V
CE
WE
Address
Data
t
WC
CC
Normal active
mode
5555
AA 2AAA
55 5555
80 5555
AA 2AAA
55 5555
20
HN58V256A Series, HN58V257A Series
Rev.5.00, Nov. 17.2003, page 16 of 22
Functional Description
Automatic Page Write
Page-mode wr ite f eature allows 1 to 6 4 bytes of da ta to be written into the EEPROM in a single write cy cle.
Following th e initial byte cycle, an ad ditional 1 to 63 bytes can be written in the sam e manner. Each
additional b y te lo ad cycle must be started within 30 µs from th e preceding fallin g edge of WE or CE. When
CE or WE is high for 100 µs after data input, the EEPROM enters write mode automatically and the input
data are written into the EEPROM.
Data
DataData
Data Polling
Data polling indicates the status that the EEPROM is in a write cycle or not. If EEPROM is set to read mode
during a write cycle, an inversion of the last byte of data outputs from I/O7 to indicate that the EEPROM is
performing a write operation.
RDY/Busy
BusyBusy
Busy Signal (only the HN58V257A series)
RDY/Busy signal also allows the status of the EEPROM to be determined. The RDY/Busy signal has high
impedance except in write cycle and is lowered to VOL after the first write sign a l. At th e end of a write cycle,
the RDY/Busy signal changes state to high impedance.
RES
RESRES
RES Signal (only the HN58V257A series)
When RES is low, the EEPROM cannot be read or programmed. Therefore, data can be protected by keeping
RES low when VCC is switched. RES should be high during read and programming because it doesn't provide
a latch function.
V
Program inhibit
CC
RES
Program inhibit
Read inhibit Read inhibit
HN58V256A Series, HN58V257A Series
Rev.5.00, Nov. 17.2003, page 17 of 22
WE
WEWE
WE, CE
CECE
CE Pin Operation
During a write cycle, addresses are latched by the falling edge of WE or CE, and data is latched by the rising
edge of WE or CE.
Write/Erase Endurance and Data Retentio n Time
The endurance is 105 cycles in case of the page programming and 104 cycles in case of the byte programming
(1% cumulative failure rate). The data retention time is more th an 10 years when a device is page-
programmed less than 104 cycles.
Data Protection
To prevent this phenomenon, this device has a noise cancellation function that cuts noise if its width is 20 ns
or less.
1. Data Protection against Noise on Control Pins (CE, OE, WE) during Operation
During readout or standby, noise on the control pins may act as a trigger and turn the EEPROM to
programming mode by mistake. Be careful not to allow noise of a width of more than 20 ns on the
control pins.
WE
CE
OE
V
0 V
V
0 V
20 ns max
IH
IH
HN58V256A Series, HN58V257A Series
Rev.5.00, Nov. 17.2003, page 18 of 22
2. Data Protection at VCC On/Off
When VCC is turned on or off, noise on the control pins generated by external circuits (CPU, etc) may act
as a trigger and turn the EEPROM to program mode by mistake. To prevent this unintentional
programming, the EEPROM must be kept in an unprogrammable state while the CPU is in an unstable
state.
Note: The EPROM should be kept in unprogrammable state during VCC on/off by using CPU RESET signal.
VCC
CPU
RESET
Unprogrammable Unprogrammable
**
2.1 Protection by CE, OE, WE
To realize the unprogrammable state, the input level of control pins must be held as shown in the
table below.
CE VCC × ×
OE × V
SS ×
WE × × V
CC
×: Don’t care.
VCC: Pull-up to VCC level.
VSS: Pull-down to VSS level.
2.2 Protection by RES (only the HN58V257A series)
The unprogrammable state can be realized by that the CPU’s reset signal inputs directly to the
EEPROM’s RES pin. RES should be kept VSS level during VCC on/off.
The EEPROM breaks off programming operation when RES becomes low, programming
operation doesn’t finish correctly in case that RES falls low during programming operation. RES
should be kept high for 10 ms after the last data input.
V
CC
RES
WE
or
CE
100 µs min 10 ms min
1 µs min
Program inhibit Program inhibit
HN58V256A Series, HN58V257A Series
Rev.5.00, Nov. 17.2003, page 19 of 22
3. Software data protection
To prevent unintentional programming, this device has the software data protection (SDP) mode. The
SDP is enabled by inputting the following 3 bytes code and write data. SDP is not enabled if only the 3
bytes code is input. To program data in the SDP enable mode, 3 bytes code must be input before write
data.
Data
AA
↓
55
↓
A0
↓
Write data }
Address
5555
↓
2AAA
↓
5555
↓
Write address Normal data input
The SDP mode is disabled by inputting the following 6 bytes code. Note that, if data is input in the SDP
disable cycle, data can not be written.
Data
AA
↓
55
↓
80
↓
AA
↓
55
↓
20
Address
5555
↓
2AAA
↓
5555
↓
5555
↓
2AAA
↓
5555
The software data protection is not enabled at the shipment.
Note: There are some differences between Renesas Technology’s and other company’s for enable/disable
sequence of software data protection. If there are any questions , please contact with Renesas
Technology’s sales offices.
HN58V256A Series, HN58V257A Series
Rev.5.00, Nov. 17.2003, page 20 of 22
Package Dimensions
HN58V256AFP Series (FP-28D, FP-28DV)
Package Code
JEDEC
JEITA
Mass
(reference value)
FP-28D, FP-28DV
Conforms
—
0.7 g
*Dimension including the plating thickness
Base material dimension
0˚ – 8˚
*0.17 ± 0.05
1.0 ± 0.2
0.20 ± 0.10
2.50 Max
8.4
18.3
18.8 Max
1.12 Max
28 15
114 11.8 ± 0.3
1.7
0.20
0.15
M
1.27
*0.40 ± 0.08
0.38 ± 0.06
0.15 ± 0.04
Unit: mm
HN58V256A Series, HN58V257A Series
Rev.5.00, Nov. 17.2003, page 21 of 22
Package Dimensions (cont.)
HN58V256AT Series (TFP-28DB, TFP-28DBV)
Package Code
JEDEC
JEITA
Mass
(reference value)
TFP-28DB, TFP-28DBV
—
—
0.23 g
*Dimension including the plating thickness
Base material dimension
0.10
M
0.55
8.00
*0.22 ± 0.08
13.40 ± 0.30
*0.17 ± 0.05
0.13
1.20 Max
11.80
0˚ – 5˚
28
114
15
8.20 Max
0.10
+0.07
–0.08
0.50 ± 0.10
0.80
0.45 Max
0.20 ± 0.06
0.15 ± 0.04
Unit: mm
HN58V256A Series, HN58V257A Series
Rev.5.00, Nov. 17.2003, page 22 of 22
Package Dimensions (cont.)
HN58V257AT Series (TFP-32DA, TFP-32DAV)
0.10
0.08 M
0.50
8.00
*0.22 ± 0.08
14.00 ± 0.20
1.20 Max
12.40
32
116
17
*0.17 ± 0.05
0.13 ± 0.05
0˚ – 5˚
8.20 Max
0.45 Max
0.50 ± 0.10
0.80
0.20 ± 0.06
0.125 ± 0.04
Package Code
JEDEC
JEITA
Mass
(reference value)
TFP-32DA, TFP-32DAV
Conforms
Conforms
0.26 g
*Dimension including the plating thickness
Base material dimension
Unit: mm
Revision History HN58V256A/HN58V257A Series Data Sheet
Contents of Modification Rev. Date
Page Description
0.0 Mar. 15. 1995 Initial issue
0.1 Aug. 7. 1995
4
4
Determination of package type:
HN58V256AT series (TFP-28DB)
Deletion of HN58V256AP series (DP-28)
Deletion of HN58V256AFPI-12/15
Deletion of HN58V256AT-12SR/15SR
Deletion of HN58V257AT-12SR/15SR
Absolute Maximum Ra ting
Deletion of Device Group
Deletion of Operating temperature range
− 20 to + 85°C and − 40 to +85°C
Recommended DC Operating Conditions
Deletion of Device Group
Deletion of Operating temperature range
−20//85°C and −40//85°C
Deletion of note 4
Change order of notes
1.0 Apr. 12. 1995
2
3
3
4
4
5
6
Change of format
Operating Information
Deletion of HN58V256A-15 and HN58V257A-15
Deletion of note 1
Deletion of Compatible type No.
Deletion of Operating temperature range
Pin Description
Addition of note 1
Block Diagram
Addition of note 1
Mode Selection
Addition of note 3
Absolute Maximum Ra tings
Addition of note 4
Recommended DC operating Condition
VIH (min) 2.4 V to 1.9 V
Addition of note 4
DC Characteristics
ICC3 (max): 8/12/20/30 mA to 8/12/15/30 mA
AC Characteristics
Test condition: Input pulse levels: 0 V to 3.0 V to
0.4 V to 2.4 V(VCC ≤ 3.6 V), 0.4 V to 3.0 V(VCC > 3.6V)
Addition of note 2
Read Timing Waveform: Addition of note 1
Write Cycle: tDS (min): 50 ns to 70 ns
Addition of note 4, 5
Byte Write Timing Waveform (1) and (2): Addition of note 1
Page Write Timing Waveform (1) and (2): Addition of note 2
Revision Record (cont.)
Contents of Modification Rev. Date
Page Description
1.0 Apr. 12. 1995 6
16
Timing Waveforms
Data Polling Timing Waveform: Addition of note 1
Toggle bit Waveform: Addition of note 4
Functional Description
Data Protection 2-(2) Addition of figure
2.0 Mar. 4. 1997 16 Functional Description
Data protection 3: Addition of note
3.0 May. 20. 1997 16
Functional Description
Data protection 3: Change of Description
4.0 Oct. 24. 1997 8 Timing Waveforms
Read Timing Waveform: Correct error
5.00 Nov. 17. 2003
2
20-22
Change format issued by Renesas Technology Corp.
Ordering Information
Addition of HN58V256AFP-12E, HN58V256AT-12E, HN58V257AT-12E
Package Dimensions
FP-28D to FP-28D, FP-28DV
TFP-28DB to TFP-28DB, TFP-28DBV
TFP-32DA to TFP-32DA, TFP-32DAV
©
2003. Renesas Technolo
gy
Corp., All ri
g
hts reserved. Printed in Japan
.
Colo
p
hon 1.0
Keep safet
y
first in
y
our circuit desi
g
ns
!
1. Renesas Technolo
gy
Corp. puts the maximum effort into makin
g
semiconductor products better and more reliable, but there is alwa
y
s the possibilit
y
that trouble
m
a
y
occur with them. Trouble with semiconductors ma
y
lead to personal in
j
ur
y
, fire or propert
y
dama
g
e
.
Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary
circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's
application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party.
2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data,
diagrams, charts, programs, algorithms, or circuit application examples contained in these materials.
3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of
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The information described here may contain technical inaccuracies or typographical errors.
Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors.
Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor
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.
7
. If these products or technolo
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ies are sub
j
ect to the Japanese export control restrictions, the
y
must be exported under a license from the Japanese
g
overnment and
cannot
e imported into a countr
other than the approved destination.
An
y
diversion or reexport contrar
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to the export control laws and re
g
ulatio
n
s of Japan and/or the countr
y
of destination is prohibited
.
8. Please contact Renesas Technolo
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ales Strate
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oda-ku, Tok
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o 100-0004, Japa
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htt
p
://www.renesas.co
m
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To our customers,
Old Company Name in Catalogs and Other Documents
On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology
Corporation, and Renesas Electronics Corporation took over all the business of both
companies. Therefore, although the old company name remains in this document, it is a valid
Renesas Electronics document. We appreciate your understanding.
Renesas Electronics website: http://www.renesas.com
April 1st, 2010
Renesas Electronics Corporation
Issued by: Renesas Electronics Corporation (http://www.renesas.com)
Send any inquiries to http://www.renesas.com/inquiry.
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1. All information included in this document is current as of the date this document is issued. Such information, however, is
subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please
confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to
additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website.
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(Note 1) “Renesas Electronics” as used in this document means Renesas Electronics Corporation and also includ es i ts majority-
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