ADZS-BF-EZEXT-1 - Analog Devices

ADSP-BF561 EZ-KIT Lite®

Evaluation System Manual

Revision 3.3, July 2012

Part Number

82-000811-01

Analog Devices, Inc.

One Technology Way

Norwood, Mass. 02062-9106

ment may not be reproduced in any form without prior, express written

consent from Analog Devices, Inc.

Printed in the USA.

Disclaimer

Analog Devices, Inc. reserves the right to change this product without

prior notice. Information furnished by Analog Devices is believed to be

accurate and reliable. However, no responsibility is assumed by Analog

Devices for its use; nor for any infringement of patents or other rights of

third parties which may result from its use. No license is granted by impli-

cation or otherwise under the patent rights of Analog Devices, Inc.

Trademark and Service Mark Notice

The Analog Devices logo, Blackfin, CrossCore, EngineerZone,

EZ-Extender, EZ-KIT Lite, and VisualDSP++ are registered trademarks of

Analog Devices, Inc.

All other brand and product names are trademarks or service marks of

their respective owners.

Regulatory Compliance

The ADSP-BF561 EZ-KIT Lite is designed to be used solely in a labora-

tory environment. The board is not intended for use as a consumer end

product or as a portion of a consumer end product. The board is an open

system design which does not include a shielded enclosure and therefore

may cause interference to other electrical devices in close proximity. This

board should not be used in or near any medical equipment or RF devices.

The ADSP-BF561 EZ-KIT Lite has been certified to comply with the

essential requirements of the European EMC directive 89/336/EEC

amended by 93/68/EEC and therefore carries the “CE” mark.

The ADSP-BF561 EZ-KIT Lite has been appended to Analog Devices,

Inc. Technical File (TCF) referenced ‘DSPTOOLS1’ dated

December 21, 1997 and was awarded CE Certification by an appointed

European Competent Body as listed below.

Technical Certificate No: Z600ANA1.016

Issued by: Technology International (Europe) Limited

60 Shrivenham Hundred Business Park

Shrivenham, Swindon, SN6 8TY, UK

The EZ-KIT Lite evaluation system contains ESD (electrostatic discharge)

sensitive devices. Electrostatic charges readily accumulate on the human

body and equipment and can discharge without detection. Permanent

damage may occur on devices subjected to high-energy discharges. Proper

ESD precautions are recommended to avoid performance degradation or

loss of functionality. Store unused EZ-KIT Lite boards in the protective

shipping package.

ADSP-BF561 EZ-KIT Lite Evaluation System Manual   v 
  CONTENTS
PREFACE
Product Overview  ...........................................................................  xi
Purpose of This Manual  ................................................................  xiii
Intended Audience  ........................................................................  xiii
Manual Contents  ........................................................................... xiv
What’s New in This Manual ........................................................... xiv
Technical Support  ........................................................................... xv
Supported Processors ...................................................................... xvi
Product Information  ...................................................................... xvi
Analog Devices Web Site  .......................................................... xvi
EngineerZone .......................................................................... xvii
Related Documents ...................................................................... xviii
Notation Conventions .................................................................. xviii
USING THE ADSP-BF561 EZ-KIT LITE
Package Contents .......................................................................... 1-2
Default Configuration ................................................................... 1-3
CCES Install and Session Startup  .................................................. 1-4
Session Startup  ........................................................................ 1-6

Contents
vi ADSP-BF561 EZ-KIT Lite Evaluation System Manual
VisualDSP++ Install and Session Startup  .......................................  1-8
CCES Evaluation License  ...........................................................  1-10
VisualDSP++ Evaluation License .................................................  1-11
Memory Map  .............................................................................  1-11
LEDs and Push Buttons ..............................................................  1-14
Audio Interface ...........................................................................  1-15
Video Interface ...........................................................................  1-16
Board Design Database ...............................................................  1-17
Example Programs  ......................................................................  1-18
Flash Programming Utility ..........................................................  1-18
ADSP-BF561 EZ-KIT LITE HARDWARE REFERENCE
System Architecture  ......................................................................  2-2
External Bus Interface Unit  .....................................................  2-3
SPORT Audio Interface  ..........................................................  2-3
SPI Interface  ...........................................................................  2-3
Programmable Flags  ................................................................  2-4
PPI Interfaces  .........................................................................  2-5
Video Output (PPI1) ..........................................................  2-7
Video Input (PPI0) .............................................................  2-7
UART Port  .............................................................................  2-8
Expansion Interface .................................................................  2-8
JTAG Emulation Port  .............................................................  2-9

ADSP-BF561 EZ-KIT Lite Evaluation System Manual vii
Contents
Jumper and DIP Switch Settings .................................................. 2-10
Video Configuration Switch (SW2)  ....................................... 2-10
Boot Mode Switch (SW3) ...................................................... 2-11
Push Button Enable Switch (SW4) ......................................... 2-12
PPI Clock Select Switch (SW5) .............................................. 2-13
Test DIP Switches (SW10 and SW11) .................................... 2-13
Audio Enable Switch (SW12)  ................................................ 2-13
SPIS1/SPISS Select (SW13) ................................................... 2-14
Video Encoder Clock Select Jumper (JP1)  .............................. 2-14
VDDINT Select Jumpers (JP2 and JP3) ................................. 2-14
UART Loop Jumper (P1) ....................................................... 2-15
LEDs and Push Buttons  .............................................................. 2-15
Reset Push Button (SW1)  ...................................................... 2-16
Programmable Flag Push Buttons (SW6–9)  ............................ 2-16
Power LED (LED1) ............................................................... 2-16
Reset LED (LED2) ................................................................ 2-17
USB Monitor LED (ZLED3) ................................................. 2-17
User LEDs (LED5–12, LED13–20)  ....................................... 2-17
Connectors ................................................................................. 2-18
Expansion Interface (J1–3)  .................................................... 2-19
Audio (J4 and J5)  .................................................................. 2-19
Video (J6)  ............................................................................. 2-20
Power (J7) ............................................................................. 2-20
RS-232 (P2)  .......................................................................... 2-20

Contents

viii ADSP-BF561 EZ-KIT Lite Evaluation System Manual

SPORT1 (P3) ....................................................................... 2-21

SPI (P5) ................................................................................ 2-21

USB Debug Agent Connector (ZJ1) ...................................... 2-21

JTAG (ZP4) .......................................................................... 2-22

ADSP-BF561 EZ-KIT LITE BILL OF MATERIALS

ADSP-BF561 EZ-KIT LITE SCHEMATIC

INDEX

ADSP-BF561 EZ-KIT Lite Evaluation System Manual ix

PREFACE

Thank you for purchasing the ADSP-BF561 EZ-KIT Lite®, Analog

Devices, Inc. evaluation system for Blackfin® processors.

Blackfin processors embody a type of embedded processor designed specif-

ically to meet the computational demands and power constraints of

today’s embedded audio, video, and communications applications. They

deliver breakthrough signal-processing performance and power efficiency

within a reduced instruction set computing (RISC) programming model.

Blackfin processors support a media instruction set computing (MISC)

architecture. This architecture is the natural merging of RISC, media

functions, and digital signal processing (DSP) characteristics. Blackfin

processors deliver signal-processing performance in a microprocessor-like

environment.

Based on the Micro Signal Architecture (MSA), Blackfin processors com-

bine a 32-bit RISC instruction set, dual 16-bit multiply accumulate

(MAC) DSP functionality, and eight-bit video processing performance

that had previously been the exclusive domain of very-long instruction

word (VLIW) media processors.

x ADSP-BF561 EZ-KIT Lite Evaluation System Manual

The evaluation board is designed to be used in conjunction with the

CrossCore® Embedded Studio (CCES) and VisualDSP++® development

environments to test the capabilities of the ADSP-BF561 Blackfin proces-

sors. The VisualDSP++ development environment gives you the ability to

perform advanced application code development and debug, such as:

• Create, compile, assemble, and link application programs written

in C++, C, and ADSP-BF561 assembly

• Load, run, step, halt, and set breakpoints in application programs

• Read and write data and program memory

• Read and write core and peripheral registers

• Plot memory

Access to the ADSP-BF561 processor from a personal computer (PC) is

achieved through a USB port or an optional JTAG emulator. The USB

interface gives unrestricted access to the ADSP-BF561 processor and the

evaluation board peripherals. Analog Devices JTAG emulators offer faster

communication between the host PC and target hardware. Analog Devices

carries a wide range of in-circuit emulation products. To learn more about

Analog Devices emulators and processor development tools, go to

http://www.analog.com/dsp/tools.

The ADSP-BF561 EZ-KIT Lite provides example programs to demon-

strate the capabilities of the evaluation board.

ADSP-BF561 EZ-KIT Lite Evaluation System Manual xi

Preface

Product Overview

The board features:

• Analog Devices ADSP-BF561 Blackfin processor

• 256-pin mini-BGA package

•30MHz CLKIN oscillator

• Synchronous dynamic random access memory (SDRAM)

• 64 MB (16M x 16 bits x 2 chips)

• Flash memory

• 8 MB (4M x 16 bits)

• Analog audio interface

• AD1836 A – Analog Devices 96 kHz audio codec

• 4 input RCA phono jacks (2 stereo channels)

• 6 output RCA phono jacks (3 stereo channels)

• Analog video interface

• ADV7183A video decoder w/ 3 input RCA phono jacks

• ADV7179 video encoder w/ 3 output RCA phono jacks

• Universal asynchronous receiver/transmitter (UART)

• ADM3202 RS-232 line driver/receiver

• DB9 male connector

Product Overview

xii ADSP-BF561 EZ-KIT Lite Evaluation System Manual

•LEDs

• 20 LEDs: 1 power (green), 1 board reset (red), 1 USB (red),

16 general-purpose (amber), and 1 USB monitor (amber)

• Push buttons

• 5 push buttons with debounce logic: 1 reset,

4 programmable flags

• Expansion interface

•PPI0, PPI1, SPI, EBIU, Timers11-0, UART,

programmable flags, SPORT0, SPORT1

• Other features

• JTAG ICE 14-pin header

The EZ-KIT Lite board holds 8 MB of flash memory, which can be used

to store user-specific boot code, allowing the board to run as a stand-alone

unit. The board also holds 512-Mb SDRAM, which can be used at run-

time. For more information see “Memory Map” on page 1-11.

SPORT0 interfaces with the AD1836A audio codec, facilitating creation of

audio signal processing applications. SPORT0 also attaches to an off-board

connector to allow communication with other serial devices. For informa-

tion about SPORT0, see “SPORT Audio Interface” on page 2-3.

The parallel peripheral interfaces (PPIs) of the processor connect to both a

video encoder and video decoder, facilitating creation of video signal pro-

cessing applications. For information on how the board utilizes the

processor’s PPIs, see “PPI Interfaces” on page 2-5.

The UART of the processor connects to an RS-232 line driver and a DB9

male connector, allowing you to interface with a PC or other serial device.

For information about the UART, see “UART Port” on page 2-8.

ADSP-BF561 EZ-KIT Lite Evaluation System Manual xiii

Preface

Additionally, the EZ-KIT Lite board provides access to most of the pro-

cessor’s peripheral ports. Access is provided in the form of a

three-connector expansion interface. For information about the expansion

interface, see “Expansion Interface” on page 2-8.

Purpose of This Manual

The ADSP-BF561 EZ-KIT Lite Evaluation System Manual provides

instructions for installing the product hardware (board). The text

describes operation and configuration of the board components and pro-

vides guidelines for running your own code on the ADSP-BF561 EZ-KIT

Lite. Finally, a schematic and a bill of materials are provided as a reference

for future designs.

Intended Audience

The primary audience for this manual is a programmer who is familiar

with Analog Devices processors. This manual assumes that the audience

has a working knowledge of the appropriate processor architecture and

instruction set.

Programmers who are unfamiliar with Analog Devices processors can use

this manual but should supplement it with other texts that describe your

target architecture. For the locations of these documents, see “Related

Documents”.

Programmers who are unfamiliar with CCES or VisualDSP++ should refer

to the online help and user’s manuals.

Manual Contents

xiv ADSP-BF561 EZ-KIT Lite Evaluation System Manual

Manual Contents

The manual consists of:

• Chapter 1, “Using the ADSP-BF561 EZ-KIT Lite” on page 1-1

Describes the EZ-KIT Lite functionality from a programmer’s per-

spective and provides an easy-to-access memory map

• Chapter 2, “ADSP-BF561 EZ-KIT Lite Hardware Reference” on

page 2-1

Provides information on the EZ-KIT Lite hardware components.

•AppendixA, “ADSP-BF561 EZ-KIT Lite Bill Of Materials” on

page A-1

Provides a list of components used to manufacture the EZ-KIT

Lite board.

• Appendix B, “ADSP-BF561 EZ-KIT Lite Schematic” on page B-1

Provides the resources to allow EZ-KIT Lite board-level debugging

or to use as a reference design. Appendix B is part of the online

help.

What’s New in This Manual

This is revision 3.3 of the ADSP-BF561 EZ-KIT Lite Evaluation System

Manual. The manual has been updated to include CCES information. In

addition, modifications and corrections based on errata reports against the

previous manual revision have been made.

For the latest version of this manual, please refer to the Analog Devices

Web site.

ADSP-BF561 EZ-KIT Lite Evaluation System Manual xv

Preface

Technical Support

You can reach Analog Devices processors and DSP technical support in

the following ways:

• Post your questions in the processors and DSP support community

at EngineerZone®:

http://ez.analog.com/community/dsp

• Submit your questions to technical support directly at:

http://www.analog.com/support

• E-mail your questions about processors, DSPs, and tools develop-

ment software from CrossCore Embedded Studio or

VisualDSP++:

Choose Help > Email Support. This creates an e-mail to

processor.tools.support@analog.com and automatically attaches

your CrossCore Embedded Studio or VisualDSP++ version infor-

mation and license.dat file.

• E-mail your questions about processors and processor applications

to:

processor.support@analog.com or

processor.china@analog.com (Greater China support)

•In the USA only, call 1-800-ANALOGD (1-800-262-5643)

• Contact your Analog Devices sales office or authorized distributor.

Locate one at:

www.analog.com/adi-sales

Supported Processors

xvi ADSP-BF561 EZ-KIT Lite Evaluation System Manual

• Send questions by mail to:

Processors and DSP Technical Support

Analog Devices, Inc.

Three Technology Way

P.O. Box 9106

Norwood, MA 02062-9106

USA

Supported Processors

This evaluation system supports Analog Devices ADSP-BF561 Blackfin

embedded processors.

Product Information

Product information can be obtained from the Analog Devices Web site

and the online help system.

Analog Devices Web Site

The Analog Devices Web site, www.analog.com, provides information

about a broad range of products—analog integrated circuits, amplifiers,

converters, and digital signal processors.

To access a complete technical library for each processor family, go to

http://www.analog.com/processors/technical_library. The manuals

selection opens a list of current manuals related to the product as well as a

link to the previous revisions of the manuals. When locating your manual

title, note a possible errata check mark next to the title that leads to the

current correction report against the manual.

Also note, myAnalog is a free feature of the Analog Devices Web site that

allows customization of a Web page to display only the latest information

ADSP-BF561 EZ-KIT Lite Evaluation System Manual xvii

Preface

about products you are interested in. You can choose to receive weekly

e-mail notifications containing updates to the Web pages that meet your

interests, including documentation errata against all manuals.

myAnalog provides access to books, application notes, data sheets, code

examples, and more.

Visit myAnalog (found on the Analog Devices home page) to sign up. If

you are a registered user, just log on. Your user name is your e-mail

address.

EngineerZone

EngineerZone is a technical support forum from Analog Devices. It allows

you direct access to ADI technical support engineers. You can search

FAQs and technical information to get quick answers to your embedded

processing and DSP design questions.

Use EngineerZone to connect with other DSP developers who face similar

design challenges. You can also use this open forum to share knowledge

and collaborate with the ADI support team and your peers. Visit

http://ez.analog.com to sign up.

Related Documents

For additional information about the product, refer to the following

publications.

Notation Conventions

Text conventions used in this manual are identified and described as

follows.

Table 1. Related Processor Publications

Title Description

ADSP-BF561 Blackfin Embedded Symmetric

Multiprocessor Data Sheet

General functional description, pinout, and

timing of the processor

ADSP-BF561 Blackfin Processor Hardware

Reference

Description of the internal processor archi-

tecture and all register functions

Blackfin Processor Programming Reference Description of all allowed processor assembly

instructions

Example Description

Close command

(File menu)

Titles in reference sections indicate the location of an item within the

development environment’s menu system (for example, the Close com-

mand appears on the File menu).

{this | that} Alternative required items in syntax descriptions appear within curly

brackets and separated by vertical bars; read the example as this or

that. One or the other is required.

[this | that] Optional items in syntax descriptions appear within brackets and sepa-

rated by vertical bars; read the example as an optional this or that.

[this,…] Optional item lists in syntax descriptions appear within brackets delim-

ited by commas and terminated with an ellipse; read the example as an

optional comma-separated list of this.

.SECTION Commands, directives, keywords, and feature names are in text with

letter gothic font.

ADSP-BF561 EZ-KIT Lite Evaluation System Manual xix

Preface

filename Non-keyword placeholders appear in text with italic style format.

Note: For correct operation, ...

A Note provides supplementary information on a related topic. In the

online version of this book, the word Note appears instead of this

symbol.

Caution: Incorrect device operation may result if ...

Caution: Device damage may result if ...

A Caution identifies conditions or inappropriate usage of the product

that could lead to undesirable results or product damage. In the online

version of this book, the word Caution appears instead of this symbol.

Warning: Injury to device users may result if ...

A Warning identifies conditions or inappropriate usage of the product

that could lead to conditions that are potentially hazardous for the

devices users. In the online version of this book, the word Warning

appears instead of this symbol.

Example Description







Notation Conventions

xx ADSP-BF561 EZ-KIT Lite Evaluation System Manual

ADSP-BF561 EZ-KIT Lite Evaluation System Manual 1-1

1 USING THE ADSP-BF561

EZ-KIT LITE

This chapter provides specific information to assist you with development

of programs for the ADSP-BF561 EZ-KIT Lite evaluation system.

The information appears in the following sections.

•“Package Contents” on page 1-2

Lists the items contained in your ADSP-BF561 EZ-KIT Lite

package.

•“Default Configuration” on page 1-3

Shows the default configuration of the ADSP-BF561 EZ-KIT Lite.

•“CCES Install and Session Startup” on page 1-4

Instructs how to start a new or open an existing

ADSP-BF561EZ-KIT Lite session using CCES.

•“VisualDSP++ Install and Session Startup” on page 1-8

Instructs how to start a new or open an existing

ADSP-BF561EZ-KIT Lite session using VisualDSP++.

•“CCES Evaluation License” on page 1-10

Describes the CCES demo license shipped with the EZ-KIT Lite.

•“VisualDSP++ Evaluation License” on page 1-11

Describes the VisualDSP++ demo license shipped with the EZ-KIT

Lite.

•“Memory Map” on page 1-11

Defines the ADSP-BF561 EZ-KIT Lite’s external memory map.

Package Contents

1-2 ADSP-BF561 EZ-KIT Lite Evaluation System Manual

•“LEDs and Push Buttons” on page 1-14·

Describes the board’s LEDs and push buttons.

•“Audio Interface” on page 1-15

Describes the board’s audio interface.

•“Video Interface” on page 1-16

Describes the board’s video interface.

•“Board Design Database” on page 1-17

Describes the board design.

•“Example Programs” on page 1-18

Provides information about the example programs included in the

ADSP-BF561 EZ-KIT Lite evaluation system.

•“Flash Programming Utility” on page 1-18

Highlights the advantages of the Flash Programmer utility.

For information on the graphical user interface, including the boot load-

ing, target options, and other facilities of the EZ-KIT Lite system, refer to

the online help.

For more detailed information about the ADSP-BF561 Blackfin proces-

sor, see the documents referred to at “Related Documents”.

Package Contents

Your ADSP-BF561 EZ-KIT Lite evaluation system package contains the

following items.

• ADSP-BF561 EZ-KIT Lite board

• Universal 7V DC power supply

• USB 2.0 cable

ADSP-BF561 EZ-KIT Lite Evaluation System Manual 1-3

Using the ADSP-BF561 EZ-KIT Lite

If any item is missing, contact the vendor where you purchased your

EZ-KIT Lite or contact Analog Devices, Inc.

Default Configuration

The ADSP-BF561 EZ-KIT Lite board is designed to run outside your per-

sonal computer as a standalone unit. You do not have to open your

computer case.

When removing the EZ-KIT Lite board from the package, handle the

board carefully to avoid the discharge of static electricity, which may

damage some components. Figure 1-1 shows the default jumper settings,

DIP switch, connector locations, and LEDs used in installation. Confirm

that your board is set up in the default configuration before using the

board.

The EZ-KIT Lite evaluation system contains ESD (electrostatic

discharge) sensitive devices. Electrostatic charges readily accumu-

late on the human body and equipment and can discharge without

detection. Permanent damage may occur on devices subjected to

high-energy discharges. Proper ESD precautions are recommended

to avoid performance degradation or loss of functionality. Store

unused EZ-KIT Lite boards in the protective shipping package.

CCES Install and Session Startup

1-4 ADSP-BF561 EZ-KIT Lite Evaluation System Manual

CCES Install and Session Startup

For information about CCES and to download the software, go to

www.analog.com/CCES. A link for the ADSP-BF561 EZ-KIT Lite Board

Support Package (BSP) for CCES can be found at

http://www.analog.com/Blackfin/EZKits.

Follow these instructions to ensure correct operation of the product soft-

ware and hardware.

Figure 1-1. EZ-KIT Lite Hardware Setup

ADSP-BF561 EZ-KIT Lite Evaluation System Manual 1-5

Using the ADSP-BF561 EZ-KIT Lite

Step 1: Connect the EZ-KIT Lite board to a personal computer (PC) run-

ning CCES using one of two options: an Analog Devices emulator or via

the debug agent.

Using an Emulator:

1. Plug one side of the USB cable into the USB connector of the emu-

lator. Plug the other side into a USB port of the PC running

CCES.

2. Attach the emulator to the header connector ZP4 (labeled JTAG) on

the EZ-KIT Lite board.

Using the on-board Debug Agent:

1. Plug one side of the USB cable into the USB connector of the

debug agent ZJ1 (labeled USB).

2. Plug the other side of the cable into a USB port of the PC running

CCES.

Step 2: Attach the provided cord and appropriate plug to the power

adaptor.

1. Plug the jack-end of the power adaptor into the power connector

J7 (labeled Power) on the EZ-KIT Lite board.

2. Plug the other side of the power adaptor into a power outlet. The

power LED (labeled LED1) is lit green when power is applied to the

board.

3. Power the emulator (if used). Plug the jack-end of the assembled

power adaptor into the emulator and plug the other side of the

power adaptor into a power outlet. The enable/power is lit green

when power is applied.

CCES Install and Session Startup

1-6 ADSP-BF561 EZ-KIT Lite Evaluation System Manual

Step 3 (if connected through the debug agent): Verify that the yellow

USB monitor LED (labeled ZLED3) on the debug agent is on. This signifies

that the board is communicating properly with the host PC and ready to

run CCES.

Session Startup

It is assumed that the CrossCore Embedded Studio software is installed

and running on your PC.

Note: If you connect the board or emulator first (before installing

CCES) to the PC, the Windows driver wizard may not find the

board drivers.

1. Navigate to the CCES environment via the Start menu.

Note that CCES is not connected to the target board.

2. Use the system configuration utility to connect to the EZ-KIT Lite

board.

If a debug configuration exists already, select the appropriate

configuration and click Apply and Debug or Debug. Go to step 8.

To create a debug configuration, do one of the following:

• Click the down arrow next to the little bug icon, select

Debug Configurations

• Choose Run > Debug Configurations.

The Debug Configuration dialog box appears.

3. Select CrossCore Embedded Studio Application and click

(New launch configuration).

The Select Processor page of the Session Wizard appears.

ADSP-BF561 EZ-KIT Lite Evaluation System Manual 1-7

Using the ADSP-BF561 EZ-KIT Lite

4. Ensure Blackfin is selected in Processor family. In Processor type,

select ADSP-BF561. Click Next.

The Select Connection Type page of the Session Wizard appears.

5. Select one of the following:

• For standalone debug agent connections, EZ-KIT Lite and

click Next.

• For emulator connections, Emulator and click Next.

The Select Platform page of the Session Wizard appears.

6. Do one of the following:

• For standalone debug agent connections, ensure that the

selected platform is ADSP-BF561 EZ-KIT Lite via Debug

Agent.

• For emulator connections, choose the type of emulator that

is connected to the board.

7. Click Finish to close the wizard.

The new debug configuration is created and added to the pro-

gram(s) to load list.

8. In the Program(s) to load section, choose the program to load

when connecting to the board. If not loading any program upon

connection to the target, do not make any changes.

Note that while connected to the target, there is no way to choose a

program to download. To load a program once connected, termi-

nate the session.

VisualDSP++ Install and Session Startup

1-8 ADSP-BF561 EZ-KIT Lite Evaluation System Manual

To delete a configuration, go to the Debug Configurations dialog

box and select the configuration to delete. Click and choose Yes

when asked if you wish to delete the selected launch configuration.

Then Close the dialog box.

To disconnect from the target board, click the terminate button

(red box) or choose Run > Terminate.

To delete a session, choose Target > Session > Session List. Select

the session name from the list and click Delete. Click OK.

VisualDSP++ Install and Session Startup

For information about VisualDSP++ and to download the software, go to

www.analog.com/VisualDSP.

1. Verify that the yellow USB monitor LED (ZLED3, located near the

USB connector) is lit. This signifies that the board is communicat-

ing properly with the host PC and is ready to run VisualDSP++.

2. If you are running VisualDSP++ for the first time, navigate to the

VisualDSP++ environment via the Start > Programs menu. The

main window appears. Note that VisualDSP++ does not connect to

any session. Skip the rest of this step to step 3.

If you have run VisualDSP++ previously, the last opened session

appears on the screen. You can override the default behavior and

force VisualDSP++ to start a new session by pressing and holding

down the Ctrl key while starting VisualDSP++. Do not release the

Ctrl key until the Session Wizard appears on the screen. Go to

step 4.

ADSP-BF561 EZ-KIT Lite Evaluation System Manual 1-9

Using the ADSP-BF561 EZ-KIT Lite

3. To connect to a new EZ-KIT Lite session, start Session Wizard by

selecting one of the following.

• From the Session menu, New Session.

• From the Session menu, Session List. Then click New Ses-

sion from the Session List dialog box.

• From the Session menu, Connect to Target.

4. The Select Processor page of the wizard appears on the screen.

Ensure Blackfin is selected in Processor family. In Choose a target

processor, select ADSP-BF561. Click Next.

5. The Select Connection Type page of the wizard appears on the

screen. Select EZ-KIT Lite and click Next.

6. The Select Platform page of the wizard appears on the screen.

In the Select your platform list, select ADSP-BF561 EZ-KIT Lite

via Debug Agent. In Session name, highlight or specify the session

name.

The session name can be a string of any length; although, the box

displays approximately 32 characters. The session name can

include space characters. If you do not specify a session name,

VisualDSP++ creates a session name by combining the name of the

selected platform with the selected processor. The only way to

change a session name later is to delete the session and to open a

new session.

Click Next.

7. The Finish page of the wizard appears on the screen. The page dis-

plays your selections. If you are satisfied, click Finish. If not, click

Back to make changes.

CCES Evaluation License

1-10 ADSP-BF561 EZ-KIT Lite Evaluation System Manual

To disconnect from a session, click the disconnect button

or select Session > Disconnect from Target.

To delete a session, select Session > Session List. Select the session

name from the list and click Delete. Click OK.

CCES Evaluation License

The ADSP-BF561 EZ-KIT Lite software is part of the Board Support

Package (BSP) for the Blackfin ADSP-BF56x family. The EZ-KIT Lite is

a licensed product that offers an unrestricted evaluation license for 90 days

after activation. Once the evaluation period ends, the evaluation license

becomes permanently disabled. If the evaluation license is installed but

not activated, it allows 10 days of unrestricted use and then becomes dis-

abled. The license can be re-enabled by activation.

An evaluation license can be upgraded to a full license. Licenses can be

purchased from:

• Analog Devices directly. Call (800) 262-5645 or 781-937-2384 or

go to:

http://www.analog.com/buyonline.

• Analog Devices, Inc. local sales office or authorized distributor. To

locate one, go to:

http://www.analog.com/salesdir/continent.asp.

The EZ-KIT Lite hardware must be connected and powered up to

use CCES with a valid evaluation or full license.

ADSP-BF561 EZ-KIT Lite Evaluation System Manual 1-11

Using the ADSP-BF561 EZ-KIT Lite

VisualDSP++ Evaluation License

The ADSP-BF561 EZ-KIT Lite installation is part of the VisualDSP++

installation. The EZ-KIT Lite is a licensed product that offers an unre-

stricted evaluation license for the first 90 days. Once the initial

unrestricted 90-day evaluation license expires:

• VisualDSP++ allows a connection to the ADSP-BF561 EZ-KIT

Lite via the USB Debug Agent interface only. Connections to sim-

ulators and emulation products are no longer allowed.

• The linker restricts a user’s program to 41 KB of memory for code

space with no restrictions for data space.

To avoid errors when opening VisualDSP++, the EZ-KIT Lite

hardware must be connected and powered up. This is true for using

VisualDSP++ with a valid evaluation or full license.

Memory Map

The EZ-KIT Lite board includes two types of external memory, 64-MB

SDRAM and 8-MB flash. See the external memory map in Table 1-1. The

complete configuration of the ADSP-BF561 processor internal SRAM is

detailed in Figure 1-2.

Table 1-1. EZ-KIT Lite External Memory Map

Start Address End Address Description

0x00000000 0x3FFFFFF SDRAM bank 0; see “Memory Map” on page 1-11

0x20000000 0x207FFFFF ASYNC memory bank 0; see “Memory Map” on page 1-11.

All other locations Not used

Memory Map

1-12 ADSP-BF561 EZ-KIT Lite Evaluation System Manual

The 8 MB of flash memory is organized as 4M x 16 bit and mapped into a

ADSP-BF561 processor’s ASYNC memory bank 0. The AMS0 memory

select signal connects to the output enable pin of flash memory.

The 64 MB of SDRAM is organized as 16M x 32 bits wide. The proces-

sor’s memory select pin SMS0 is configured for SDRAM. Three SDRAM

control registers must be initialized in order to access the SDRAM

memory.

Figure 1-2. ADSP-BF561 Processor Internal Memory Map

L1 SCRATCHPAD SRAM (4K)

L1 INSTRUCTION SRAM/CACHE (16K)

L1 INSTRUCTION SRAM (16K)

L1 DATA BANK B SRAM/CACHE (16K)

L1 DATA BANK B SRAM (16K)

L1 DATA BANK A SRAM/CACHE (16K)

L1 DATA BANK A SRAM (16K)

CORE A MEMORY MAP CORE B MEMORY MAP

CORE MMR REGISTERS CORE MMR REGISTERS

SYSTEM MMR REGISTERS

L1 SCRATCHPAD SRAM (4K)

RESERVED

L1 INSTRUCTION SRAM/CACHE (16K)

L1 INSTRUCTION SRAM (16K)

L1 DATA BANK B SRAM/CACHE (16K)

L1 DATA BANK B SRAM (16K)

L1 DATA BANK A SRAM/CACHE (16K)

L1 DATA BANK A SRAM (16K)

L2 SRAM (128K)

0XFFE0 0000

0XFFC0 0000

0XFFB0 1000

0XFFB0 0000

0XFFA1 4000

0XFFA1 0000

0XFFA0 4000

0XFFA0 0000

0XFF90 8000

0XFF90 4000

0XFF90 0000

0XFF80 8000

0XFF80 4000

0XFF80 0000

0XFF70 1000

0XFF70 0000

0XFF61 4000

0XFF50 4000

0XFF50 0000

0XFF40 8000

0XFF40 4000

0XFF40 0000

0XFEB2 0000

0XFEB0 0000

0XEF00 0800

0XFF61 0000

0XFF60 4000

0XFF60 0000

0XFF50 8000

0XFFFF FFFF

RESERVED

ADSP-BF561 EZ-KIT Lite Evaluation System Manual 1-13

Using the ADSP-BF561 EZ-KIT Lite

When in a CCES or VisualDSP++ session, you can configure the SDRAM

registers automatically:

• CCES users, choose Target > Settings > Target Options > Use

XML reset values

• VisualDSP++ users, choose Settings > Target Options > Use XML

reset values

The EBIU_SDGCTL, EBIU_SDBCTL, and EBIU_SDRRC register values have been

set in the ADSP-BF561-proc.xml file found in your System\ArchDef folder.

These values can be changed to be more optimal depending on the SCLK

frequency.

The values in Table 1-2 are set by default whenever bank 0 is accessed

through the debugger (for example, when viewing memory windows or

loading a program). The numbers are derived for maximum flexibility and

work for a system clock frequency between 60 MHz and 133 MHz.

The EBIU_SDGCTL register can be written once after the processor comes

out of reset. Therefore, the user code should not re-initialize the register.

Clearing the Use XML reset values check box allows manual configura-

tion of the EBIU registers. For more information, see online help.

Table 1-2. EZ-KIT Lite Session SDRAM Default Settings

EBIU_SDGCTL 0x0091998D Calculated with SCLK = 133 MHz

EBIU_SDBCTL 0x00000013

EBIU_SDRRC 0x000001CF Calculated with SCLK = 120 MHz

LEDs and Push Buttons

1-14 ADSP-BF561 EZ-KIT Lite Evaluation System Manual

Automatic configuration of SDRAM is not optimized for a specific SCLK

frequency. Table 1-3 shows the optimized configuration of the SDRAM

registers using a 120 MHz SCLK. The frequency of 120 MHz is the maxi-

mum SCLK frequency when using a 600 MHz core frequency, the

maximum frequency for the EZ-KIT Lite. Only the EBIU_SDRRC register

needs to be modified in the user code to achieve maximum performance.

For more information, see “External Bus Interface Unit” on page 2-3.

An example program is included in the EZ-KIT installation direc-

tory to demonstrate the SDRAM interface setup.

LEDs and Push Buttons

The EZ-KIT Lite provides four push buttons and sixteen LEDs for gen-

eral-purpose IO.

Sixteen LEDs, labeled LED5 through LED20, are controlled by the proces-

sor’s programmable flags PF32 through PF47 (equivalent to PPI0_D15–8

and PPI1_D15–8). These LEDs are accessed through the FLAG 2 registers.

First, the direction must be configured to output by setting the bits of the

FIO2_DIR register to 1. Then the value of the LEDs are modified using one

of the FIO2_FLAG_D, FIO2_FLAG_C, FIO2_FLAG_S, or FIO2_FLAG_T registers.

The four general-purpose push buttons are labeled SW6 through SW9. The

buttons connect to the programmable flags PF8–5. A status of each

Table 1-3. SDRAM Optimum Settings1

1 Calculated with SCLK = 120 MHz

EBIU_SDGCTL 0x0091998D

EBIU_SDBCTL 0x00000013

EBIU_SDRRC 0x000003A0

ADSP-BF561 EZ-KIT Lite Evaluation System Manual 1-15

Using the ADSP-BF561 EZ-KIT Lite

individual button can be read through the FIO0_FLAG_D register. A switch

is being pressed-on when the corresponding bit of the register reads 1.

When the switch is released, the bit reads 0. A connection between the

push button and PF input is established through the SW4 DIP switch.

For information on how to disconnect the switch from the programmable

flag and use it for another objective, see “Push Button Enable Switch

(SW4)”.

An example program is included in the EZ-KIT Lite installation

directory to demonstrate functionality of the LEDs and push

buttons.

Audio Interface

The AD1836A audio codec provides three channels of stereo audio output

and two channels of multichannel 96 kHz input. The SPORT0 interface of

the processor links with the stereo audio data input and output pins of the

AD1836A codec. The processor is capable of transferring data to the

audio codec in time-division multiplexed (TDM) or 2-wire serial interface

(TWI) mode.

In TWI mode, the codec can operate at a 96 kHz sample rate but restricts

the output to two channels. In TDM mode, the codec can operate at a

maximum of 48 kHz sample rate but allows simultaneous use of all input

and output channels. When using TWI mode, the TSCLK0 and RSCLK0 pins

(as well as the TFS0 and RFS0 pins of the processor) must be tied together

externally to the processor. This is accomplished with the SW4 DIP switch.

See “Push Button Enable Switch (SW4)” on page 2-12 for more

information.

The AD1836A audio codec’s internal configuration registers are config-

ured using the processor’s PF4 programmable flag pin, used as the select

for the audio device. For more information on how to configure the

multichannel codec, go to www.analog.com/AD1836A.

Video Interface

1-16 ADSP-BF561 EZ-KIT Lite Evaluation System Manual

The AD1836A codec reset is controlled by the processor’s programmable

flag PF15. When PF15 is 0, the reset is asserted. When PF15 is 1, the reset is

de-asserted. Note that when PF15 is not driven (configured as input), the

AD1836A reset is asserted due to the pull-down resistor. See “Programma-

ble Flags” on page 2-4 for more information.

Example programs are included in the EZ-KIT Lite installation

directory to demonstrate the AD1836A codec operation.

Video Interface

The board supports video input and output applications. The ADV7179

video encoder provides up to three output channels of analog video, while

the ADV7183A video decoder provides up to three input channels of ana-

log video. The video encoder connects to the parallel peripheral

interface 1 (PPI1), while the video decoder connects to the parallel periph-

eral interface 0, (PPI0). Each PPI interface has an individual clock that is

configured by the SW5 switch settings. See “PPI Clock Select Switch

(SW5)” on page 2-13 for more information.

Both the encoder and the decoder connect to the parallel peripheral inter-

faces (PPI input clock) of the processor. For additional information on the

video interface hardware, refer to “PPI Interfaces” on page 2-5.

For the video interface to be operational, the following basic steps must be

performed.

1. Configure the SW2 DIP switch as required by the application. Refer

to “Video Configuration Switch (SW2)” on page 2-10 for details.

2. De-assert the video device’s reset by setting high a corresponding

programmable flag. PF14 controls the ADV7179 encoder’s reset,

while PF13 controls the ADV7183A decoder’s reset.

ADSP-BF561 EZ-KIT Lite Evaluation System Manual 1-17

Using the ADSP-BF561 EZ-KIT Lite

3. If using the ADV7183A decoder:

• Enable device by driving programmable flag output PF2 to

• Select PPI0 clock; for details, refer to “PPI Clock Select

Switch (SW5)” on page 2-13.

4. Program internal registers of the video device in use. Both video

encoder and decoder use a 2-wire serial interface to access internal

registers. The PF0 programmable flag functions as a serial clock

(SCL), and PF1 functions as a serial data (SDAT).

5. Program the ADSP-BF561 processor’s PPI interfaces (configura-

tion registers, DMA, and so on).

Example programs are included in the EZ-KIT Lite installation

directory to demonstrate the capabilities of the video interface.

Board Design Database

A .zip file containing all of the electronic information required for the

design, layout, fabrication and assembly of the product is available for

download from the Analog Devices board design database at:

http://www.analog.com/board-design-database.

Example Programs

1-18 ADSP-BF561 EZ-KIT Lite Evaluation System Manual

Example Programs

Example programs are provided with the ADSP-BF561 EZ-KIT Lite to

demonstrate various capabilities of the product. The programs are

included in the product installation kit and can be found in the Examples

folder of the installation. Refer to a readme file provided with each exam-

ple for more information.

CCES users are encouraged to use the example browser to find examples

included with the EZ-KIT Lite Board Support Package.

Flash Programming Utility

The ADSP-BF561 EZ-KIT Lite evaluation system includes a flash pro-

gramming utility. The utility allows you to program flash memory on the

EZ-KIT Lite. The utility installed with VisualDSP++ is called Flash Pro-

grammer. The utility installed with CCES is called Device Programmer.

The flash programming driver is core-specific (core A) and must be loaded

to core A in order to operate correctly. The flash programming utility

relies on the user to set the correct core focus. To set the correct core,

select core A in the multiprocessor window before opening the utility

interface.

For more information on the flash programming utility, refer to the

online help.

ADSP-BF561 EZ-KIT Lite Evaluation System Manual 2-1

2 ADSP-BF561 EZ-KIT LITE

HARDWARE REFERENCE

This chapter describes the hardware design of the ADSP-BF561 EZ-KIT

Lite board. The following topics are covered.

•“System Architecture” on page 2-2

Describes the ADSP-BF561 EZ-KIT Lite configuration and

explains how the board components interface with the processor.

•“Jumper and DIP Switch Settings” on page 2-10

Shows the locations and describes the configuration jumpers and

switches.

•“LEDs and Push Buttons” on page 2-15

Shows the locations and describes the LEDs and push buttons.

•“Connectors” on page 2-18

Shows the locations and provides part numbers for the on-board

connectors. In addition, the manufacturer and part number infor-

mation is provided for the mating parts.

System Architecture

2-2 ADSP-BF561 EZ-KIT Lite Evaluation System Manual

System Architecture

This section describes the processor’s configuration on the EZ-KIT Lite

board.

This EZ-KIT Lite has been designed to demonstrate the capabilities of the

ADSP-BF561 Blackfin processor. The processor has an IO voltage of

3.3V. The core voltage and the core clock rate can be set on the fly by the

processor. The input clock is 30 MHz.

Figure 2-1. System Architecture

ADSP-BF561 EZ-KIT Lite Evaluation System Manual 2-3

ADSP-BF561 EZ-KIT Lite Hardware Reference

External Bus Interface Unit

The external bus interface unit (EBIU) connects external memory to the

ADSP-BF561 processor. It includes a 32-bit wide data bus, an address bus

(A25–2), and a control bus. All of the 8-bit, 16-bit, and 32-bit accesses are

supported. On the EZ-KIT Lite board, the EBI unit connects to SDRAM

and flash memory. For more information on using the external memory

see “Memory Map” on page 1-11.

All of the address, data, and control signals are available externally via the

expansion interface connectors (J1–3). The pinout of these connectors can

be found in “ADSP-BF561 EZ-KIT Lite Schematic” on page B-1.

SPORT Audio Interface

The SPORT0 interface connects to the AD1836A audio codec and the

expansion interface. The AD1836A codec uses both the primary and sec-

ondary data transmit and receive pins to input and output data from the

audio input and outputs.

The SPORT1 interface connects to the SPORT connector (P3).

The pinout of the SPORT and expansion interface connectors can be found

in “ADSP-BF561 EZ-KIT Lite Schematic” on page B-1.

SPI Interface

The processor’s serial peripheral interface (SPI) connects to the AD1836A

audio codec and the expansion interface. The SPI connection to the

AD1836A codec is used to access the control registers of the device. The

PF4 flag of the processor acts as the device select for the SPI port.

The SPI signals are available on the expansion interface and on the SPI

connector (P5). The pinout for the interface can be found in

“ADSP-BF561 EZ-KIT Lite Schematic” on page B-1.

System Architecture
2-4 ADSP-BF561 EZ-KIT Lite Evaluation System Manual
Programmable Flags
The processor has 48 programmable flag pins (PFs). Many of the flags are 
multi-functional and depend on the processor’s setup. Table 2-1 shows 
how the programmable flag pins are used on the EZ-KIT Lite. 
Table 2-1. Programmable Flag Connections
Processor PF Pin Processor Function EZ-KIT Lite Function
PF0 SPI select S, timer 0  Serial clock for programming ADV7179 video 
encoder and ADV7183A video decoder.
PF1 SPI select 1, timer 1 Serial data for programming ADV7179 video encoder 
and ADV7183A video decoder.
PF2 SPI select 2, timer 2 ADV7183A video decoder’s OE.
PF3 SPI select 3, timer 3 ADV7183A FIELD pin. See “Video Configuration 
Switch (SW2)” on page 2-10.
PF4 SPI select 4, timer 4 AD1836A audio codec’s SPI select.
PF5 SPI select 5, timer 5 Push button (SW6). See “LEDs and Push Buttons” on 
page 1-14 and “Push Button Enable Switch (SW4)” 
on page 2-12 for information on how to disable the 
push button.
PF6 SPI select 6, timer 6 Push button (SW7). See “LEDs and Push Buttons” on 
page 1-14 and “Push Button Enable Switch (SW4)” 
on page 2-12 for information on how to disable the 
push button.
PF7 SPI select 7, timer 7 Push button (SW8). See “LEDs and Push Buttons” on 
page 1-14 and “Push Button Enable Switch (SW4)” 
on page 2-12 for information on how to disable the 
push button.
PF8 Push button (SW9). See “LEDs and Push Buttons” 
on page 1-14 and “Push Button Enable Switch 
(SW4)” on page 2-12 for information on how to dis-
able the push button.
PF9–12 Not used
PF13 ADV7183A video decoder’s reset

ADSP-BF561 EZ-KIT Lite Evaluation System Manual 2-5

ADSP-BF561 EZ-KIT Lite Hardware Reference

PPI Interfaces

The ADSP-BF561 processor employs two independent parallel peripheral

interfaces (PPIs), PPI0 and PPI1. Each PPI interface is a half-duplex,

bi-directional bus consisting of 16 bits of data, a dedicated input clock,

PF14 ADV7179 video encoder’s reset

PF15 AD1836 codec’s reset

PF16 SPORT0 transmit frame sync pin

PF17 SPORT0 transmit data secondary pin

PF18 SPORT0 transmit data primary pin

PF19 SPORT0 receive frame sync pin

PF20 SPORT0 receive data secondary pin

PF21 SPORT1 transmit frame pin

PF22 SPORT1 transmit data secondary pin

PF23 SPORT1 transmit data primary pin

PF24 SPORT1 receive frame sync pin

PF25 SPORT1 receive data secondary pin

PF26 UART transmit pin

PF27 UART receive pin

PF28 SPORT0 receive serial clock pin

PF29 SPORT0 transmit serial clock pin

PF30 SPORT1 receive serial clock pin

PF31 SPORT1 transmit serial clock pin

PF39–32 PPI1 data 15–8 LED13–20

PF47–40 PPI0 data 15–8 LED5–12

Table 2-1. Programmable Flag Connections (Cont’d)

Processor PF Pin Processor Function EZ-KIT Lite Function

System Architecture
2-6 ADSP-BF561 EZ-KIT Lite Evaluation System Manual
and synchronization signals. The ADSP-BF561 EZ-KIT Lite board uti-
lizes the PPI interfaces for video input and video output. 
The PPI0 interface is configured to input video data from the ADV7183A 
video decoder device: bits 7–0 connect to the video decoder’s data outputs. 
The PPI1 interface is configured to output video data to the ADV7179 
video encoder device: bits 7–0 connect to the video encoder’s data inputs.
Each PPI interface has a dedicated clock input configured independently 
by the SW5 switch. The clock source can be one of the following: 27 MHz 
crystal oscillator, ADV7183A video decoder’s clock output, or external 
clock from the expansion interface. See “PPI Clock Select Switch (SW5)” 
on page 2-13 for more information about the switch. 
The SW2 switch provides a flexible connection between dedicated synchro-
nization IOs (SYNC1 and SYNC2 of each PPI interface) and the encoder’s 
and decoder’s horizontal and vertical synchronization pins. See “Video 
Configuration Switch (SW2)” on page 2-10 for more information about 
the switch. For a detailed description of the ADSP-BF561 processor’s PPI 
interfaces, refer to the ADSP-BF561 Blackfin Processor Hardware Reference.
Table 2-2 describes the PPI pins of the EZ-KIT Lite board. 
Table 2-2. PPI Connections
Processor PPI Pin Other Processor 
Function
EZ-KIT Lite Function
PPI0 bits 7–0 ADV7183A data outputs P15–8
PPI1 bits 7–0 ADV7179 data inputs P7–0
PPI0 SYNC1 Timer 8 ADV7179 HSYNC. For more information, see “Video 
Configuration Switch (SW2)” on page 2-10.
PPI0 SYNC2 Timer 9 ADV7179 VSYNC. For more information, see “Video 
Configuration Switch (SW2)” on page 2-10.
PPI0 clock A choice of ADV7183A output clock, a local 
27 MHz oscillator, or an external clock from 
ADSP-BF533/BF561 Blackfin EZ-Extender®.

ADSP-BF561 EZ-KIT Lite Evaluation System Manual 2-7

ADSP-BF561 EZ-KIT Lite Hardware Reference

Video Output (PPI1)

The PPI1 interface is configured as output and connects to the on-board

video encoder device, ADV7179. The ADV7179 encoder generates three

analog video channels on DAC A, DAC B, and DAC C. The PPI1 bits 7–0 con-

nect to P7–0 of the encoder’s pixel inputs. The encoder’s input clock is

fixed and comes from an on-board 27 MHz oscillator.

The encoder’s synchronization signals, HSYNC and VSYNC, can be config-

ured as inputs or outputs. Video blanking control signal is at level 1. The

HSYNC and VSYNC signals can connect to SYNC1 and SYNC2 of the processor’s

PPI1 interface via the SW2 switch, as described in “Video Configuration

Switch (SW2)” on page 2-10.

Video Input (PPI0)

The PPI0 interface is configured as input and connects to the on-board

video decoder device, ADV7183A. The ADV7183A decoder receives three

analog video channels on AIN1, AIN4, and AIN5 input. The decoder’s pixel

data outputs P15–8 drive the PPI0 inputs 8–0. The decoder’s 27 MHz pixel

clock output can be selected to drive any of the PPI clocks as shown in

Table 2-7 on page 2-13.

PPI1 SYNC1 Timer 10 ADV7183A HSYNC. For more information, see

“Video Configuration Switch (SW2)” on page 2-10.

PPI1 SYNC2 Timer 11 ADV7183A VSYNC. For more information, see

“Video Configuration Switch (SW2)” on page 2-10.

PPI1 clock A choice of ADV7183A output clock, a local

2 7 M H z o s c i l l a t o r , o r a n e x t e r n a l c l o c k f r o m

ADSP-BF53x/BF561 Blackfin EZ-Extender.

Table 2-2. PPI Connections (Cont’d)

Processor PPI Pin Other Processor

Function

EZ-KIT Lite Function

System Architecture

2-8 ADSP-BF561 EZ-KIT Lite Evaluation System Manual

Synchronization outputs of the decoder, HS/HACTIVE, VS/VACTIVE, and

FIELD can connect to the processor’s PPI0_SYNC1, PPI0_SYNC2, and PF3

flag via the SW2 DIP switch, as described in “Video Configuration Switch

(SW2)” on page 2-10.

UART Port

The processor’s universal asynchronous receiver/transmitter (UART) port

connects to the ADM3202 RS-232 line driver as well as to the expansion

interface. The RS-232 line driver is attached to the DB9 male connector,

providing an interface to a personal computer and other serial devices.

Expansion Interface

The expansion interface consists of the three 90-pin connectors, J1–3.

Table 2-3 shows the interfaces each connector provides. For the exact pin-

out of the connectors, refer to “ADSP-BF561 EZ-KIT Lite Schematic” on

page B-1. The mechanical dimensions of the connectors can be obtained

from Technical Support.

Table 2-3. Connector Interfaces

Connector Interfaces

J1 5V, GND, address, data, PPI0 3–0, PF15–6, PF4

J2 3.3V, GND, SPI, NMI, PPI0 SYNC3–1, SPORT0, SPORT1, PF15–0, EBUI control sig-

nals

J3 5V, 3.3V, GND, UART, PPI1 15–0, reset, video control signals

ADSP-BF561 EZ-KIT Lite Evaluation System Manual 2-9

ADSP-BF561 EZ-KIT Lite Hardware Reference

Limits to the current and to the interface speed must be taken into consid-

eration when using the expansion interface. The maximum current limit is

dependent on the capabilities of the used regulator. Additional circuitry

also can add extra loading to signals, decreasing their maximum effective

speed.

Analog Devices does not support and is not responsible for the

effects of additional circuitry.

JTAG Emulation Port

The JTAG emulation port allows an emulator to access internal and exter-

nal memories of the processor through a 6-pin interface. The JTAG

emulation port of the processor also connects to the USB debugging inter-

face. When an emulator connects to the board at ZP4, the USB debugging

interface is disabled. See “JTAG (ZP4)” on page 2-22 for more informa-

tion about the JTAG connector.

To learn more about available emulators, go to

http://www.analog.com/processors/tools/blackfin.

Jumper and DIP Switch Settings

2-10 ADSP-BF561 EZ-KIT Lite Evaluation System Manual

Jumper and DIP Switch Settings

This section describes functionality of the jumpers and DIP switches. The

jumper and DIP switch locations are shown in Figure 2-2.

Video Configuration Switch (SW2)

The video configuration switch (SW2) determines how some video signals

from the ADV7183A video decoder and ADV7179 video encoder are

routed to the processor’s PPIs. The switch also determines if the PF2 pin

controls the OE signal of the ADV7183A video decoder outputs. See

Table 2-4.

Figure 2-2. DIP Switch Locations

ADSP-BF561 EZ-KIT Lite Evaluation System Manual 2-11

ADSP-BF561 EZ-KIT Lite Hardware Reference

Positions 1 thorough 5 of SW2 determine how and if the SYNC1, SYNC2, and

FIELD control signals of the PPI0 and PPI1 interfaces are routed to the pro-

cessor’s PPIs. In standard configuration of the encoder and decoder, this is

not necessary because the processor is capable of reading the control infor-

mation embedded in the data stream.

Position 6 of SW2 determines whether PF2 connects to the OE signal of the

ADV7183A device. When the switch is OFF, PF2 can be used for other

operations, and the decoder output enable is held high with a pull-up

resistor.

Boot Mode Switch (SW3)

Positions 1 and 2 of the SW3 switch set the boot mode of the processor, as

described in Table 2-5. Position 3 sets the processor’s PLL on boot—

when the position is ON, the PLL is in bypass.

Table 2-4. Video Configuration Switch (SW2)

Switch Position (Default) Processor Signal Video Signal

1 (OFF)PPI1 SYNC1 ADV7179

2 (OFF)PPI0 SYNC1 ADV7183A

3 (OFF)PPI1 SYNC2 ADV7183A

4 (OFF)PPI1 SYNC2 ADV7179

5 (OFF)PF3 (FIELD) ADV7183A

6 (ON)PF2 ADV7183A

Jumper and DIP Switch Settings

2-12 ADSP-BF561 EZ-KIT Lite Evaluation System Manual

Push Button Enable Switch (SW4)

Positions 1 through 4 of the push button enable switch (SW4) allow to dis-

connect the drivers associated with the push buttons from the PF pins of

the processor. Positions 5 and 6 connect the transmit and receive frame

syncs and clocks of SPORT0. This is important when the AD1836A audio

codec and the processor are communicating in 2-wire interface (TWI)

mode. Table 2-6 shows which PF is driven when the switch is ON.

Table 2-5. Boot Mode Select Switch (SW3)

Position 1 BMODE0 Position 2 BMODE1 Boot Mode

ON ON Execute from 16-bit external

memory

(Bypass Boot ROM)

OFF ON Boot from 8-bit/16-bit flash

(default)

ON OFF Boot from SPI host slave mode

OFF OFF Boot from SPI serial EEPROM

(16-, 24-bit address range)

Table 2-6. Push Button Enable Switch (SW4)

Switch Position Default Setting Pin # Signal (Side 1) Pin # Signal (Side 2)

1ON 1 SW6 12 PF5

2ON 2 SW7 11 PF6

3ON 3 SW8 10 PF7

4ON 4 SW9 9 PF8

5OFF 5 TFS0 8 RFS0

6OFF 6 RSCLK0 7 TSCLK0

ADSP-BF561 EZ-KIT Lite Evaluation System Manual 2-13

ADSP-BF561 EZ-KIT Lite Hardware Reference

PPI Clock Select Switch (SW5)

The SW5 switch controls a clock selection of the PPI interfaces as described

in Table 2-7 and Table 2-8.

Test DIP Switches (SW10 and SW11)

Two DIP switches (SW10 and SW11) are located on the bottom of the

board. The switches are used only for testing and should remain in the OFF

position.

Audio Enable Switch (SW12)

The audio enable switch (SW12) disconnects the audio signals from the

processor. The default is all positions ON.

Table 2-7. PPICLK1 Clock Source Setup

SW5 Position 1

PPI0_CKSEL0

SW5 Position 2

PPI0_CKSEL1

PPIxCLK1 Source

ON ON 27 MHz oscillator (default)

OFF ON ADV7183 clock out

XOFFExpansion interface

Table 2-8. PPICLK2 Clock Source Setup

SW5 Position 3

PPI1_CKSEL0

SW5 Position 4

PPI1_CKSEL1

PPICLK2 Source

ON ON 27 MHz oscillator (default)

OFF ON ADV7183 clock out

XOFFExpansion interface

Jumper and DIP Switch Settings

2-14 ADSP-BF561 EZ-KIT Lite Evaluation System Manual

SPIS1/SPISS Select (SW13)

The SPIS1/SPISS select switch (SW13) disconnects the SPIS1 and SPISS sig-

nals from the board, making them available on the SPI connector (P5).

The default is the ON position.

Video Encoder Clock Select Jumper (JP1)

The video encoder clock select jumper (JP1) determines the source of the

ADV7179 video encoder’s clock. The jumper setting is shown in

Table 2-9.

VDDINT Select Jumpers (JP2 and JP3)

The processor internal voltage (VDDINT) select jumpers (JP2–3) determine

the source of the processor’s internal voltage. For the core clock set at

533 MHz and higher, select the on-board external regulator for VDDINT.

The jumper settings are shown in Table 2-10.

Table 2-9. Video Encoder Clock Select Jumper (JP1)

JP1 Position Mode

1 and 2 Input clock for encoder is generated from 27 MHz oscillator (default)

2 and 3 Input clock for encoder is generated from output clock of decoder. This is

used when synchronizing the encoder and decoder clock is required.

Table 2-10. Processor Internal Voltage Select Jumpers (JP2 and JP3)

JP2 JP3 VDDINT Source

Not populated 1 and 2 ON Provided by the on-board external regulator

Populated 2 and 3 ON Provided by the processor through the VROUT pins

(internal regulator)

ADSP-BF561 EZ-KIT Lite Evaluation System Manual 2-15

ADSP-BF561 EZ-KIT Lite Hardware Reference

UART Loop Jumper (P1)

The UART loop jumper (P1) is for looping the transmit and receive sig-

nals. The default is the OFF position.

LEDs and Push Buttons

This section describes functionality of the LEDs and push buttons.

Figure 2-3 shows the locations of the LEDs and push buttons.

Figure 2-3. LED and Push Button Locations

LEDs and Push Buttons

2-16 ADSP-BF561 EZ-KIT Lite Evaluation System Manual

Reset Push Button (SW1)

The RESET push button resets all of the ICs on the board. One exception is

the USB interface chip (U34). The chip is not being reset when the push

button is pressed after the USB cable has been plugged in and communi-

cation with the PC has been initialized correctly. Once communication is

initialized, the only way to reset the USB is by powering down the board.

Programmable Flag Push Buttons (SW6–9)

Four push buttons, SW6–9, are provided for general-purpose user input.

The buttons connect to the programmable flag pins of the processor (PF5–

8). The push buttons are active high and, when pressed, send a high (1) to

the processor. Refer to “LEDs and Push Buttons” on page 1-14 for more

information on how to use PFs when programming the processor. The

push button enable switch (SW4) is capable of disconnecting the push but-

tons from its associated PF (refer to “Push Button Enable Switch (SW4)”

on page 2-12). The programmable flag pins and corresponding switches

are shown in Table 2-11.

Power LED (LED1)

When LED1 is lit (green), it indicates that power is being supplied to the

board properly.

Table 2-11. Programmable Flag Switches

Processor Programmable Flag Pin Push Button Reference Designator

PF5 SW6

PF6 SW7

PF7 SW8

PF8 SW9

ADSP-BF561 EZ-KIT Lite Evaluation System Manual 2-17

ADSP-BF561 EZ-KIT Lite Hardware Reference

Reset LED (LED2)

When LED2 is lit, it indicates that the master reset of all major ICs is

active.

USB Monitor LED (ZLED3)

The USB monitor LED (ZLED3) indicates that USB communication has

been initialized successfully and you can connect to the processor using an

EZ-KIT Lite session. This takes approximately 15 seconds. If the LED

does not light, try cycling power on the board and/or reinstalling the USB

driver.

When the development software is actively communicating with

the EZ-KIT Lite target board, the LED can flicker, indicating

communications handshake.

User LEDs (LED5–12, LED13–20)

Sixteen LEDs connect to the processor’s programmable flags. Eight LEDs

labeled LED5 through LED12 are controlled by programmable flags PF40

through PF47 (equivalent to PPI0_D15–8). Eight LEDs labeled LED13

through LED20 are controlled by programmable flags PF32 through PF39

(equivalent to PPI1_D15–8). To learn how to use the LEDs, refer to “LEDs

and Push Buttons” on page 1-14.

Table 2-12. User LEDs

LED Reference Designator Flag Port Name LED Reference Designator Flag Port Name

LED5 PB40 LED13 PB32

LED6 PB41 LED14 PB33

LED7 PB42 LED15 PB34

LED8 PB43 LED16 PB35

LED9 PB44 LED17 PB36

Connectors

2-18 ADSP-BF561 EZ-KIT Lite Evaluation System Manual

Connectors

This section describes the connector functionality and provides informa-

tion about mating connectors. The connector locations are shown in

Figure 2-4.

LED10 PB45 LED18 PB37

LED11 PB46 LED19 PB38

LED12 PB47 LED20 PB39

Figure 2-4. Connector Locations

Table 2-12. User LEDs (Cont’d)

LED Reference Designator Flag Port Name LED Reference Designator Flag Port Name

ADSP-BF561 EZ-KIT Lite Evaluation System Manual 2-19

ADSP-BF561 EZ-KIT Lite Hardware Reference

Expansion Interface (J1–3)

Three board-to-board connector footprints provide signals for most of the

processor’s peripheral interfaces. The connectors are located at the bottom

of the board. For more information about the interface, see “Expansion

Interface” on page 2-8. For the availability and pricing of the J1, J2, and

J3 connectors, contact Samtec.

Audio (J4 and J5)

Part Description Manufacturer Part Number

90-position 0.05" spacing, SMT

(J1, J2, J3)

SAMTEC SFC-145-T2-F-D-A

Mating Connector

90-position 0.05” spacing

(through hole)

SAMTEC TFM-145-x1 series

90-position 0.05” spacing

(surface mount)

SAMTEC TFM-145-x2 series

90-position 0.05” spacing

(low cost)

SAMTEC TFC-145 series

Part Description Manufacturer Part Number

2x2 RCA jacks (J4) SWITCHCRAFT PJRAS2X2S01X

3x2 RCA jacks (J5) SWITCHCRAFT PJRAS3X2S01X

Mating Connector

Two channel RCA interconnect

cable

MONSTER CABLE BI100-1M

Connectors

2-20 ADSP-BF561 EZ-KIT Lite Evaluation System Manual

Video (J6)

Power (J7)

The power connector provides all of the power necessary to operate the

EZ-KIT Lite board.

The power connector supplies DC power to the EZ-KIT Lite board.

RS-232 (P2)

Part Description Manufacturer Part Number

3x2 RCA jacks (J6) SWITCHCRAFT PJRAS3X2S01X

Part Description Manufacturer Part Number

2.5 mm power jack (J7) SWITCHCRAFT RAPC712X

Mating Power Supply (shipped with EZ-KIT Lite)

7V power supply CUI INC. DMS070214-P6P-SZ

Part Description Manufacturer Part Number

DB9, male, right angle (P2) TYCO 5747250-4

Mating Assembly

2m female-to-female cable DIGI-KEY AE1016-ND

ADSP-BF561 EZ-KIT Lite Evaluation System Manual 2-21

ADSP-BF561 EZ-KIT Lite Hardware Reference

SPORT1 (P3)

The SPORT1 connector is linked to a 20-pin connector. The connector’s

pinout can be found in “ADSP-BF561 EZ-KIT Lite Schematic” on

page B-1.

SPI (P5)

The SPI connector is linked to a 12-pin connector. The connector’s pin-

out can be found in “ADSP-BF561 EZ-KIT Lite Schematic” on page B-1.

USB Debug Agent Connector (ZJ1)

The USB debug agent connector is the connecting point for the JTAG

USB debug agent interface. The JTAG header (ZP4) should not be used

whenever ZJ1 and its mating cable are used to communicate to the proces-

sor via CCES or VisualDSP++.

Part Description Manufacturer Part Number

IDC header FCI 68737-420HLF

Mating Connectors

IDC socket DIGI-KEY S4210-ND

Part Description Manufacturer Part Number

IDC header SULLINS GEC06DAAN

Mating Assembly

IDC socket DIGI-KEY S4207-ND

Connectors

2-22 ADSP-BF561 EZ-KIT Lite Evaluation System Manual

JTAG (ZP4)

The JTAG header is the connecting point for a JTAG in-circuit emulator

pod. When an emulator connects to the JTAG header, the USB debug

interface is disabled.

Pin 3 is missing to provide keying. Pin 3 in the mating connector

should have a plug.

When using an emulator with the EZ-KIT Lite board, follow the

connection instructions provided with the emulator.

ADSP-BF561 EZ-KIT Lite Evaluation System Manual A-1

A ADSP-BF561 EZ-KIT LITE BILL

OF MATERIALS

The bill of materials corresponds to “ADSP-BF561 EZ-KIT Lite Sche-

matic” on page B-1.

Ref. Qty. Description Reference Designator Manufacturer Part Number

1174LVC14A

SOIC14

U47 TI 74LVC14AD

2 2 IDT74FCT3244

APY SSOP20

U13,U30 IDT IDT74FCT3244APYG

3 1 12.288MHZ

OSC003

U16 EPSON SG-8002CA MP

4 1 NDS8434A SO-8 U29 FAIRCHILD NDS8434A

5 2 MT48LC16M16

A2TG-75

TSOP54

U32-33 MICRON MT48LC16M16A2P-75

6 1 27MHZ OSC003 U17 EPSON SG-8002CA MP

7 2 IDT2305-1DC

SOIC8

U19-20 INTE-

GRATED SYS

ICS9112AM-16LFT

8 1 SN74LVC1G32

SOT23-5

U10 TI SN74LVC1G32DBVR

9 1 30MHZ OSC003 U14 EPSON SG-8002CA MP

10 1 BF561

M29W640D

"U27"

U27 ST MICRO M29W640DT 90N6E

11 2 FDC658P

SOT23-6

U28,U49 FAIRCHILD FDC658P

A-2 ADSP-BF561 EZ-KIT Lite Evaluation System Manual

12 1 ADM708SARZ

SOIC8

U46 ANALOG

DEVICES

ADM708SARZ

13 1 ADP3338AKCZ-

33 SOT-223

VR3 ANALOG

DEVICES

ADP3338AKCZ-3.3-RL

14 1 ADP3339AKCZ-

5 SOT-223

VR1 ANALOG

DEVICES

ADP3339AKCZ-5-R7

15 1 ADP3336ARMZ

MSOP8

VR2 ANALOG

DEVICES

ADP3336ARMZ-REEL7

16 1 10MA

AD1580BRTZ

SOT23D

D1 ANALOG

DEVICES

AD1580BRTZ-REEL7

17 4 ADG752BRTZ

SOT23-6

U22-23,U25-26 ANALOG

DEVICES

ADG752BRTZ-REEL

18 3 AD8061ARTZ

SOT23-5

U1-3 ANALOG

DEVICES

AD8061ARTZ-R2

19 1 ADM3202ARNZ

SOIC16

U21 ANALOG

DEVICES

ADM3202ARNZ

20 8 AD8606ARZ

SOIC8

U5-7,U9,U11-12,

U18,U24

ANALOG

DEVICES

AD8606ARZ

21 1 AD1836AASZ

MQFP52

U15 ANALOG

DEVICES

AD1836AASZ

22 1 ADSP-BF561SK

BCZ MBGA256

U48 ANALOG

DEVICES

ADSP-BF561SKBCZ-6V

23 1 ADV7179KCPZ

LFCSP40

U8 ANALOG

DEVICES

ADV7179KCPZ

24 1 ADV7183BKSTZ

LQFP80

U4 ANALOG

DEVICES

ADV7183BKSTZ

25 2 ADP1864AUJZ

SOT23-6

VR5-6 ANALOG

DEVICES

ADP1864AUJZ-R7

26 5 RUBBER FOOT M1-5 MOUSER 517-SJ-5018BK

Ref. Qty. Description Reference Designator Manufacturer Part Number

ADSP-BF561 EZ-KIT Lite Evaluation System Manual A-3

ADSP-BF561 EZ-KIT Lite Bill Of Materials

27 1 PWR

2.5MM_JACK

CON005

J7 SWITCH-

CRAFT

RAPC712X

28 1 RCA 2X2

CON013

J4 SWITCH-

CRAFT

PJRAS2X2S01X

29 5 MOMENTARY

SWT013

SW1,SW6-9 PANASONIC EVQ-PAD04M

30 3 .05 45X2

CON019

J1-3 SAMTEC SFC-145-T2-F-D-A

31 3 DIP6 SWT017 SW2,SW4,SW10 CTS 218-6LPST

32 2 RCA 3X2

CON024

J5-6 SWITCH-

CRAFT

PJRAS3X2S01X

33 4 DIP4 SWT018 SW3,SW5,SW11-12 ITT TDA04HOSB1

34 1 DIP2 SWT020 SW13 C&K CKN9064-ND

35 1 IDC 2X1

IDC2X1

P1 FCI 90726-402HLF

36 1 IDC 2X1

IDC2X1

JP2 FCI 90726-402HLF

37 2 IDC 3X1

IDC3X1

JP1,JP3 FCI 90726-403HLF

38 1 IDC 10X2

IDC10X2

P3 BURG-FCI 54102-T08-10LF

39 4 IDC

2PIN_JUMPER_

SHORT

SJ1-4 DIGI-KEY S9001-ND

40 1 DB9 9PIN

DB9M

P2 TYCO 5747250-4

41 1 IDC 6X2

IDC6X2

P5 FCI 68737-412HLF

42 1 5A RESETABLE

FUS005

F1 MOUSER 650-RGEF500

Ref. Qty. Description Reference Designator Manufacturer Part Number

A-4 ADSP-BF561 EZ-KIT Lite Evaluation System Manual

43 14 0 1/4W 5% 1206 R43-44,R55,R71,

R73,R83,R133,

R159,R163,R223-

225,R247,R257

KOA 0.0ECTRk7372

BTTED

44 16 YELLOW

LED001

LED5-20 PANASONIC LN1461C

45 12 330PF 50V 5%

0805

C82,C84,C86,

C92-100

AVX 08055A331JAT

46 48 0.01UF 100V

10% 0805

C3,C5,C28,C41,

C49,C69-70,C74-75,

C101,C112-114,

C127,C134,C136-

138,C140-141,C146,

C149-150,C154,

C156-157,C165-166,

C168,C173-174,

C176,C181-182,

C185-188,C190,

C192-194,C200-203,

C249,C256

AVX 08051C103KAT2A

47 8 0.22UF 25V 10%

0805

C104,C106-108,

C125,C129,C143,

C162

AVX 08053C224KAT2A

Ref. Qty. Description Reference Designator Manufacturer Part Number

ADSP-BF561 EZ-KIT Lite Evaluation System Manual A-5

ADSP-BF561 EZ-KIT Lite Bill Of Materials

48 69 0.1UF 50V 10%

0805

C1-2,C4,C12,C19-

20,C22,C27,C29-30,

C35,C37,C48,C51-

52,C54-60,C65-66,

C71,C73,C83,C85,

C87-91,C102,C109-

111,C115,C122-124,

C126,C131-132,

C135,C139,C145,

C147-148,C151-152,

C155,C158-159,

C164,C167,C171-

172,C175,C177-179,

C183-184,C189,

C191,C196,

C198-199

AVX 08055C104KAT

49 10 1000PF 50V 5%

0805

C23,C25,C33,C36,

C38-40,C67-68,

C133

AVX 08055A102JAT2A

50 3 10UF 16V 10%

CT17,CT23-24 SPRAGUE 293D106X9016C2TE3

51 43 10K 1/10W 5%

0805

R2,R7,R11-12,R14,

R24,R42,R45-47,

R52,R57,R85,R87-

88,R98,R131,R143,

R158,R160-162,

R167-170,R174-177,

R181-183,R189-190,

R196,R229,R239,

R246,R248-251

VISHAY CRCW080510K0

JNEA

52 9 33 1/10W 5%

0805

R39,R41,R59-61,

R165-166,R171-172

VISHAY CRCW080533R0

JNEA

53 2 4.7K 1/10W 5%

0805

R86,R90 VISHAY CRCW08054K70

JNEA

54 1 1.5K 1/10W 5%

0805

R1 VISHAY CRCW08051K50

FKEA

Ref. Qty. Description Reference Designator Manufacturer Part Number

A-6 ADSP-BF561 EZ-KIT Lite Evaluation System Manual

55 1 1.2K 1/8W 5%

1206

R23 VISHAY CRCW12061K20

JNEA

56 6 49.9K 1/8W 1%

1206

R108-113 VISHAY CRCW120649K9

FKEA

57 12 100PF 100V 5%

1206

C6-11,C26,C34,

C61-63,C72

AVX 12061A101JAT2A

58 6 10UF 16V 10% B CT1-4,CT15-16 AVX TAJB106K016R

59 4 100 1/10W 5%

0805

R242-245 VISHAY CRCW0805100

RJNEA

60 6 220PF 50V 10%

1206

C13-18 AVX 12061A221JAT2A

61 4 600 100MHZ

200MA 0603

FER18-21 DIGI-KEY 490-1014-2-ND

62 1 2A S2A

DO-214AA

D7 VISHAY S2A-E3

63 12 600 100MHZ

500MA 1206

FER2-4,FER6,FER8-

12,FER14-16

STEWARD HZ1206B601R-10

64 4 237.0 1/8W 1%

1206

R25-26,R53-54 VISHAY CRCW1206237

RFKEA

65 4 750.0K 1/8W 1%

1206

R132,R156,R164,

R173

VISHAY CRCW1206750

KFKEA

66 16 5.76K 1/8W 1%

1206

R8,R15-16,R40,R49-

50,R58,R62-64,R69-

70,R121-124

VISHAY CRCW12065K76

FKEA

67 6 11.0K 1/8W 1%

1206

R144-149 VISHAY CRCW120611K0

FKEA

68 8 120PF 50V 5%

1206

C103,C105,C128,

C130,C142,C144,

C161,C163

AVX 12065A121JAT2A

69 12 75 1/8W 5%

1206

R4-6,R100-102,

R104-105,R107,

R114,R134-135

VISHAY CRCW120675R0

JNEA

Ref. Qty. Description Reference Designator Manufacturer Part Number

ADSP-BF561 EZ-KIT Lite Evaluation System Manual A-7

ADSP-BF561 EZ-KIT Lite Bill Of Materials

70 1 68UF 6.3V

20% D

CT22 AVX TAJD686K016R

71 6 680PF 50V 1%

0805

C116-121 AVX 08055A681FAT2A

72 5 10UF 25V

+80-20% 1210

C31,C47,C50,C195,

C197

DIGI-KEY 587-1393-2-ND

73 6 2.74K 1/8W 1%

1206

R150-155 VISHAY CRCW12062K74

FKEA

74 12 5.49K 1/8W 1%

1206

R17-22,R27,R30-31,

R34-35,R38

VISHAY CRCW12065K49

FKEA

75 6 3.32K 1/8W 1%

1206

R137-142 VISHAY CRCW12063K32

FKEA

76 6 1.65K 1/8W 1%

1206

R28-29,R32-33,R36-

VISHAY CRCW12061K65

FKEA

77 10 10UF 16V 20%

CAP002

CT5-14 PANASONIC EEE1CA100SR

78 1 10UH 20%

IND001

L11 TDK 445-2014-1-ND

79 6 0 1/10W 5%

0805

R66,R99,R103,

R106,R178,R192

VISHAY CRCW08050000

Z0EA

80 1 190 100MHZ 5A

FER002

FER22 MURATA DLW5BSN191SQ2

81 4 22 1/10W 5%

0805

R67-68,R187-188 VISHAY 541-22ATR-ND

82 6 0.68UH 10%

0805

L1-4,L6,L8 MURATA LQM21NNR68K10D

83 1 .082UF 50V 5%

0805

C64 AVX 08055C823JAT2A

84 1 1A ZHCS1000

SOT23-312

D5 ZETEX ZHCS1000TA pb-free

85 3 2.2UH 10% 0805 L5,L7,L9 DIGI-KEY 490-1119-2-ND

Ref. Qty. Description Reference Designator Manufacturer Part Number

A-8 ADSP-BF561 EZ-KIT Lite Evaluation System Manual

86 3 1UF 10V 10%

0805

C21,C24,C32 AVX 0805ZC105KAT2A

87 1 76.8K 1/10W 1%

1206

R48 VISHAY CRCW120676K8

FKEA

88 1 147.0K 1/10W

1% 1206

R56 VISHAY CRCW1206147

KFKEA

89 10 10 62.5MW 5%

RNS006

RN1,RN4-12 PANASONIC EXB-38V100JV

90 2 68PF 50V 5%

0603

C160,C257 AVX 06035A680JAT2A

91 2 470PF 50V 5%

0603

C153,C258 AVX 06033A471JAT2A

92 2 0 1/10W 5%

0603

R74,R254 PHYCOMP 232270296001L

93 2 24.9K 1/10W 1%

0603

R72,R256 DIGI-KEY 311-24.9KHTR-ND

94 2 10UF 16V 10%

1210

C169,C260 AVX 1210YD106KAT2A

95 1 680 1/8W 5%

1206

R119 VISHAY CRCW1206680RFNEA

96 1 150.0 1/8W 1%

1206

R3 VISHAY CRCW1206150RFKEA

97 1 GREEN LED001 LED1 PANASONIC LN1361CTR

98 1 RED LED001 LED2 PANASONIC LN1261CTR

99 2 1000PF 50V 5%

1206

C43,C46 AVX 12065A102JAT2A

100 6 2200PF 50V 5%

1206

C76-81 AVX 12065A222JAT050

101 6 1K 1/8W 5%

1206

R10,R115-118,R136 VISHAY CRCW12061K00

FKEA

Ref. Qty. Description Reference Designator Manufacturer Part Number

ADSP-BF561 EZ-KIT Lite Evaluation System Manual A-9

ADSP-BF561 EZ-KIT Lite Bill Of Materials

102 2 100K 1/8W 5%

1206

R9,R13 VISHAY CRCW1206100K

FKEA

103 17 270 1/8W 5%

1206

R120,R213-220,

R230-237

VISHAY CRCW1206270

RJNEA

104 6 604.0 1/8W 1%

1206

R125-130 VISHAY CRCW1206604R

FKEA

105 4 1UF 20V 20% A CT25-28 AVX TAJA105K020R

106 1 255.0K 1/10W

1% 0603

R89 VISHAY CRCW06032553FK

107 2 80.6K 1/10W 1%

0603

R80,R255 DIGI-KEY 311-80.6KHRCT-ND

108 2 6.8UH 25%

IND009

L10,L12 DIGI-KEY 308-1328-1-ND

109 2 4A SSB43L

DO-214AA

D4,D8 VISHAY SSB43L

110 2 5A

MBRS540T3G

SMC

D2-3 ON SEMI MBRS540T3G

111 1 0.027 1/2W 1%

1206

R79 SUSUMU RL1632T-R027-F-N

112 1 54.9K 1/10W 1%

0603

R252 VISHAY CRCW060354K9

FKEA

113 1 0.047 1/2W 1%

1206

R253 SUSUMU RL1632S-R047-F

114 2 100UF 6.3V

20%C

CT19,CT29 SANYO 6TPB100MC

Ref. Qty. Description Reference Designator Manufacturer Part Number

A-10 ADSP-BF561 EZ-KIT Lite Evaluation System Manual

A B C

20 Cotton Road

Nashua, NH 03063

A B C D

PH: 1-800-ANALOGD

Title

Size Board No.

Date Sheet of

DEVICES

ANALOG

Rev

ADSP-BF561 EZ-KIT LITE

A0185-2003 2.3

ADSP-BF561 EZ-KIT Lite

Schematic

11-7-2007_15:11 1 14

TITLE

3.3V

R4B

R3B

R2B

R1BR1A

R2A

R4A

R3A

R4B

R3B

R2B

R1BR1A

R2A

R4A

R3A

R4B

R3B

R2B

R1BR1A

R2A

R4A

R3A

R4B

R3B

R2B

R1BR1A

R2A

R4A

R3A

R4B

R3B

R2B

R1BR1A

R2A

R4A

R3A

3.3V

R4B

R3B

R2B

R1BR1A

R2A

R4A

R3A

OE OUT

R4B

R3B

R2B

R1BR1A

R2A

R4A

R3A

R4B

R3B

R2B

R1BR1A

R2A

R4A

R3A

R4B

R3B

R2B

R1BR1A

R2A

R4A

R3A

CLK2

CLK1

GND

CLK3VDD

CLK4

CLKOUTREF

A B C

20 Cotton Road

Nashua, NH 03063

A B C D

PH: 1-800-ANALOGD

Title

Size Board No.

Date Sheet of

DEVICES

ANALOG

Rev

ADSP-BF561 EZ-KIT LITE

A0185-2003 2.3

SWE

SRAS

SMS3

SMS2

SMS1

SMS0

SCAS

RESET

BR BGH

AWE

ARE

AOE

AMS3

AMS2

AMS1

AMS0

ABE3

ABE2

ABE1

ABE0

XTAL

SCLK1

SCLK0

SCKE

SA10

NMI1

NMI0

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

D15

D14

D13

D12

D11

D10

CLKIN

BYPASS

BMODE1

BMODE0

ARDY

A25

A24

A23

A22

A21

A20

A19

A18

A17

A16

A15

A14

A13

A12

A11

A10

SDQM0/

SDQM1/

SDQM2/

SDQM3/

1234

OFF OFF

RESERVED

8-BIT FLASH

SPI SROM 8-BIT

SPI SROM 16-BIT

ONON

OFF ON

OFF

BMODE1

1 2 BOOT MODE

BMODE0

DEFAULT

SW3: BOOT MODE/BYPASS Select

(Default = OFF, ON, ON, OFF)

11-7-2007_15:11 142

1SW3

SWT018

DIP4

R65

0805

DNP

M10

N10

B16

C15

F12

F16

F14

H12

H15

H16

E12

L16

C16

E14

D15

D16

E15

F13

F15

P11

D11

B10

A11

A12

G12

G13

G15

H13

H14

J15

J13

J16

K14

K15

K13

L15

K12

M15

J12

D13

G11

B15

G10

B14

C14

F11

B12

E11

B13

A14

A15

A13

C12

C10

D10

A10

E10

U48

MBGA256

ADSP-BF561SKBCZ

DSP - EXT MEM INTERFACE

U20

SOIC8

IDT2305-1DC

C42

0805

0.1UF

DNP

0805

R51

DNP

RN4

RNS006

RN9

RNS006

RN10

RNS006

1 3

U14

OSC003

30MHZ

RN7

RNS006

10K

0805

R167

A[25:2]

A14

A22

A25

A24

A23

A21

A20

A19

A18

A17

A16

A15

A12

A11

A10

A13

10K

0805

R170

10K

0805

R168

SCLK0

ABE0

SRAS

ABE2

ABE1

CLK_OUT_EXP2

CLK_OUT_EXP1

10K

0805

R176

10K

0805

R169

ABE3

SMS3

SMS2

SMS1

SMS0

SA10

SWE

SCAS

RN8

RNS006

RN6

RNS006

RN12

RNS006

RN11

RNS006

RN5

RNS006

0805

R188

0805

R187

R60

0805

R67

R68

0805

10K

R42

R196

0805

10K

R160

0805

10K

OSC_30MHZ

EXT_DSP_CLK

NMI1

NMI0

BMODE1

BMODE0

DSP_BYPASS

DSPCK_30MHZ

A2_S

A3_S

A4_S

A5_S

A6_S

A7_S

A8_S

A9_S

A10_S

A11_S

A12_S

A13_S

A14_S

A15_S

A16_S

A17_S

A18_S

A19_S

A20_S

A21_S

A22_S

A23_S

A24_S

A25_S

A3_S

A4_S

A13_S

A12_S

A11_S

A10_S

A9_S

A8_S

A7_S

A6_S

A5_S

A[25:2]_S

A2_S

A15_S

A14_S

A16_S

A17_S

A18_S

A19_S

A20_S

A21_S

A22_S

A23_S

A24_S

A25_S

RESET

ARDY

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

D15

D14

D13

D12

D11

D10

D[31:0]

ABE0_S

ABE1_S

ABE2_S

ABE3_S

BGH

AOE

ARE

AWE

AMS0

AMS1

AMS2

AMS3

SRAS_S

SCAS_S

SWE_S

SA10_S

SMS0_S

SMS1_S

SMS2_S

SMS3_S

SCKE

SCLK0_S

SCLK1_S

3.3V

SHGND

3.3V

TRST EMU

TX/PF26

TSCLK1/PF31

TSCLK0/PF29

TMS

TFS1/PF21

TFS0/PF16

TDOTDI

TCK

SLEEP

SCK

RX/PF27

RSCLK1/PF30

RSCLK0/PF28

RFS1/PF24

RFS0/PF19

PF9

PF8

PF7/SPIS7/TMR7

PF6/SPIS6/TMR6

PF5/SPIS5/TMR5

PF4/SPIS4/TMR4

PF3/SPIS3/TMR3

PF2/SPIS2/TMR2

PF15/TMRXCLK

PF14

PF13

PF12

PF11

PF10

PF1/SPIS1/TMR1

PF0/SPISS/TMR0

MOSI

MISO

DTIPRI/PF23

DT1SEC/PF22

DT0SEC/PF17

DT0PRI/PF18

DR1SEC/PF25

DR1PRI

DR0SEC/PF20

DR0PRI

A B C

20 Cotton Road

Nashua, NH 03063

A B C D

PH: 1-800-ANALOGD

Title

Size Board No.

Date Sheet of

DEVICES

ANALOG

Rev

ADSP-BF561 EZ-KIT LITE

A0185-2003 2.3

1 2

R4B

R3B

R2B

R1BR1A

R2A

R4A

R3A

VROUT2

VROUT1

VDDINT9

VDDINT8

VDDINT7

VDDINT6

VDDINT5

VDDINT4

VDDINT3

VDDINT2

VDDINT14

VDDINT13

VDDINT12

VDDINT11

VDDINT10

VDDINT1

VDDEXT9

VDDEXT8

VDDEXT7

VDDEXT6

VDDEXT5

VDDEXT4

VDDEXT3

VDDEXT23

VDDEXT22

VDDEXT21

VDDEXT20

VDDEXT2

VDDEXT19

VDDEXT18

VDDEXT17

VDDEXT16

VDDEXT15

VDDEXT14

VDDEXT13

VDDEXT12

VDDEXT11

VDDEXT10

VDDEXT1

NC1

NC0

GND9

GND8

GND7

GND6

GND5

GND41

GND40

GND4 GND39

GND38

GND37

GND36

GND35

GND34

GND33

GND32

GND31

GND30

GND3

GND29

GND28

GND27

GND26

GND25

GND24

GND23

GND22GND21

GND20

GND2

GND19

GND18

GND17

GND16

GND15

GND14

GND13

GND12

GND11

GND10

GND1

3.3V

DA_EMULATOR_TCK

DA_EMULATOR_TDI

DA_EMULATOR_TDO

DA_EMULATOR_TMS

DA_GP0

DA_GP1

DA_GP2

DA_GP3

GND

SHGND

TCK

TDI

TDO

TMS

DA_EMULATOR_EMU

DA_EMULATOR_SELECT

DA_EMULATOR_TRST

DA_SOFT_RESET

EMU

RESET

TRST

DEBUG_AGENT

http://www.analog.com

Engineer to Engineer Note EE-68 which can be found at

When designing your JTAG interface please refer to the

All USB interface circuitry is considered proprietary and has

been omitted from this schematic.

DSP JTAG HEADER

GENERAL PURPOSE / PUSH BUTTON STATUS INPUT/ UART SIGNAL

GENERAL PURPOSE / PUSH BUTTON STATUS INPUT

GENERAL PURPOSE

PF15

PF14

PROGR. FLAG

AD1836 CODEC RESET

ADV7179 VIDEO ENCODER RESET

ADV7183A VIDEO DECODER RESETPF13

PF12 GENERAL PURPOSE

PF11

PF10 GENERAL PURPOSE

PF9

PF8 GENERAL PURPOSE / PUSH BUTTON STATUS INPUT

PF7

PF6 GENERAL PURPOSE / PUSH BUTTON STATUS INPUT/ UART SIGNAL

PF5

FUNCTION

PF4 GENERAL PURPOSE / AD1836 LATCH SIGNAL

PF3 GENERAL PURPOSE / VIDEO DECODER FIELD

PF2 GENERAL PURPOSE / VIDEO DECODER OUTPUT ENABLE

PF1

PF0 GENERAL PURPOSE / I2C SERIAL CLOCK/SPISS

GENERAL PURPOSE / I2C SERIAL DATA/SPISEL1

SPI

SPORT1

SW13: SPIS1/SPISS Select

11-7-2007_15:11 3 14

R90

4.7K

0805

EMULATOR_EMU

0805

R239

10K

DSP_VDD_INTDSP_VDD_EXT

C11

F10

G14

H10

C13

H9 J11

J14

K10

L11

L14

N12

N14

P12

P2D14 P5

E13

M13

G16

K16

L10

M14

T12

A16

T16

B11

D12

E16

K11

H11

J10

U48

MBGA256

ADSP-BF561SKBCZ

RN1

RNS006

SW13

DIP2

SWT020

DSP - PROGR. FLAGS, SPI

DR1SEC

DR1PRI

L12

P16

M12

T14

M16

N15

T15

R15

R12

N11

R16

N13

P15

P13

T13

M11

T11

R10 N9

L13

P14

T10

N16

R14

R13

P10 R11

U48

MBGA256

ADSP-BF561SKBCZ

IDC6X2

1817

1615

1413

1211

1P3

IDC10X2

ZP4

IDC7X2

0805

10K

R85R87

10K

0805

SPIS1

SPISS

PF1

PF0

PF15

PF14

PF13

PF12

PF11

PF10

PF9

PF8

PF7

PF6

PF5

PF4

PF3

PF2

PF15

PF14

PF13

PF[15:0]

4.7K

0805

R86

0805

10K

R88

RSCLK1

TFS1

TSCLK1

VROUT

EMU

TDO

TSCLK0

RSCLK1

RFS1

DR1PRI

DR1SEC

DT1SEC

DT1PRI

TFS1

TSCLK1

RSCLK0

MOSI

MISO

SCK

RFS0

DR0PRI

DR0SEC

TFS0

DT0PRI

DT0SEC

EMULATOR_TDO

EMULATOR_TDI

EMULATOR_TRST

EMULATOR_TCK

EMULATOR_TMS

TDO

RESET

DA_SOFT_RESET

VDEC_RESET

VENC_RESET

AD1836_RESET

EMU

MISO

MOSI

SCK

SPIS1

SPISS

RFS1

DT1SEC

DT1PRI

OE OUT

3.3V

3.3V 3.3V

CLK2

CLK1

GND

CLK3VDD

CLK4

CLKOUTREF

1A1

1A2

1A3

1A4

2A2

2A3

2A4

1Y1

1Y2

1Y3

1Y4

2Y1

2Y2

2A1

2Y4

2Y3

OE1

OE2

1A1

1A2

1A3

1A4

2A2

2A3

2A4

1Y1

1Y2

1Y3

1Y4

2Y1

2Y2

2A1

2Y4

2Y3

OE1

OE2

PPI1_SYN3

PPI1_SYN2/TMR11

PPI1_SYN1/TMR10

PPI1_D9/PF33

PPI1_D8/PF32

PPI1_D7

PPI1_D6

PPI1_D5

PPI1_D4

PPI1_D3

PPI1_D2

PPI1_D15/PF39

PPI1_D14/PF38

PPI1_D13/PF37

PPI1_D12/PF36

PPI1_D11/PF35

PPI1_D10/PF34

PPI1_D1

PPI1_D0

PPI1_CLK

PPI0_SYN3

PPI0_SYN2/TMR9

PPI0_SYN1/TMR8

PPI0_D9/PF41

PPI0_D8/PF40

PPI0_D7

PPI0_D6

PPI0_D5

PPI0_D4

PPI0_D3

PPI0_D2

PPI0_D15/PF47

PPI0_D14/PF46

PPI0_D13/PF45

PPI0_D12/PF44

PPI0_D11/PF43

PPI0_D10/PF42

PPI0_D1

PPI0_D0

PPI0_CLK

A B C

20 Cotton Road

Nashua, NH 03063

A B C D

PH: 1-800-ANALOGD

Title

Size Board No.

Date Sheet of

DEVICES

ANALOG

Rev

ADSP-BF561 EZ-KIT LITE

A0185-2003 2.3

1 2 3 4

PPIxCLK

ONON

OFF ON

OFF EXPANSION_CLK

1 or 3

PPIxCLK_SEL0 PPIxCLK_SEL1

2 or 4

PPI_27MHZ_CLK

SW5: PPI CLK Routing Select

VDEC_CLKOUT

(Default: 1 = OFF, 2 = ON, 3 = ON, 4 = ON)

11-7-2007_15:11 4 14

4 5

DIP4

SWT018

SW5

DSP - PPI0 AND PPI1

MBGA256

U48

ADSP-BF561SKBCZ

U22

SOT23-6

ADG752BRTZ 4

U23

SOT23-6

ADG752BRTZ

SSOP20

U30

IDT74FCT3244APY

SSOP20

U13

IDT74FCT3244APY

U19

SOIC8

IDT2305-1DC

R171

0805

PPI1_D0

PPI1_D[15:0]

PPI1_D8

PPI1_D9

PPI1_D10

PPI1_D11

PPI1_D12

PPI1_D13

PPI1_D14

PPI1_D15

PPI1_D1

PPI1_D2

PPI1_D3

PPI1_D4

PPI1_D5

PPI1_D6

PPI1_D7

PPI1_D8

PPI1_D9

PPI1_D10

PPI1_D11

PPI1_D12

PPI1_D13

PPI1_D14

PPI1_D15

0805

R66

EXT_27MHZ_CLK

VDEC_CLKOUT

PPI_27MHZ_CLK

R181

0805

10K

R182

0805

10K

R175

0805

10K

R174

0805

10K

EXP_PPI0_CLK

EXP_PPI1_CLK

PPI1_CLK

U26

SOT23-6

ADG752BRTZ 4

U25

SOT23-6

ADG752BRTZ

1206

270

R220 270

1206

R219

1206

270

R218 270

1206

R217

1206

270

R216 270

1206

R215

YELLOW

LED001

LED7

LED001

YELLOW

LED8

YELLOW

LED001

LED9

YELLOW

LED001

LED10

YELLOW

LED001

LED11

LED001

YELLOW

LED12

YELLOW

LED001

LED18

YELLOW

LED001

LED19

270

1206

R236

1206

270

R235

PPI0_CLK

0805

R165

0805

R172

R166

0805

R178

OSC27MOSC_27M 0805

R59

1 3

U17

OSC003

27MHZ

VDEC_27MHZ_CLK

VENC_27MHZ_CLK

0805

10K

R162

YELLOW

LED001

LED15

LED001

YELLOW

LED16

YELLOW

LED001

LED17

LED001

YELLOW

LED20

1206

270

R237 270

1206

R232

270

1206

R234

1206

270

R233

YELLOW

LED001

LED14

270

1206

R231

YELLOW

LED001

LED13

270

1206

R230

YELLOW

LED001

LED6

270

1206

R214

YELLOW

LED001

LED5

270

1206

R213

PPI0CLK_SEL0

PPI0CLK_SEL1

PPI1CLK_SEL0

PPI1CLK_SEL1

PPI0_SYNC3

PPI0_SYNC2

PPI0_SYNC1

PPI0_CLK PPI1_CLK

PPI1_SYNC1

PPI1_SYNC2

PPI1_SYNC3

PPI0_D15

PPI0_D14

PPI0_D13

PPI0_D12

PPI0_D11

PPI0_D10

PPI0_D9

PPI0_D8

PPI0_D[15:0] PPI0_D15

PPI0_D14

PPI0_D13

PPI0_D12

PPI0_D11

PPI0_D10

PPI0_D9

PPI0_D8

PPI0_D7

PPI0_D6

PPI0_D5

PPI0_D4

PPI0_D3

PPI0_D2

PPI0_D1

PPI0_D0

A10

A11

A12_NC

CKE

CLK

DQ0

DQ1

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ8

DQ9

DQMH

DQML

CAS

RAS

BA1

BA0

3.3V

A10

A11

A12_NC

CKE

CLK

DQ0

DQ1

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ8

DQ9

DQMH

DQML

CAS

RAS

BA1

BA0

WP/VPP

BYTE VSS2

VSS1

VCC

RDY

D15

D14

D13

D12

D11

D10

A21

A20

A19

A18

A17

A16

A15

A14

A13

A12

A11

A10

A B C

20 Cotton Road

Nashua, NH 03063

A B C D

PH: 1-800-ANALOGD

Title

Size Board No.

Date Sheet of

DEVICES

ANALOG

Rev

ADSP-BF561 EZ-KIT LITE

A0185-2003 2.3

4M x 16

0x2000 0000

0x0000 0000 0x03FF FFFF

0x207F FFFF

END

ASYNC Memory Bank 0

BANK

SDRAM 64MB

(256Mb x 2 Chips)

FLASH A (8MB)

SDRAM Bank 0 64MB SDRAM

DEVICE

8MB FLASH

START

Memory Map

11-7-2007_15:11 5 14

MEMORY - FLASH & SDRAM

47 46

TSOP48

U27

M29W640D

R177

0805

10K

FLASH_WP

FLASH_RP

R190

0805

10K

U33

TSOP54

MT48LC16M16A2TG-75

FLASH_RDY

R183

0805

10K

R189

0805

10K

AWE

AMS0

AOE

D[31:0]

D10

D11

D13

D14

D19

D21

D24

D25

D26

D31

D30

D29

D28

D27

D23

D22

D20

D18

D17

D16

D15

D12

D10

D11

D12

D13

D14

D15

ABE3

ABE2

SMS0

SCKE

ABE1

ABE0

SRAS

SCAS

SWE

SA10

U32

TSOP54

MT48LC16M16A2TG-75

SCLK0

A[25:2]

A19

A18

A14

A13

A11

A10

A18

A14

A13

A11

A10

A22

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

3.3V

AGND

3.3V

12 456

A B C

20 Cotton Road

Nashua, NH 03063

A B C D

PH: 1-800-ANALOGD

Title

Size Board No.

Date Sheet of

DEVICES

ANALOG

Rev

ADSP-BF561 EZ-KIT LITE

A0185-2003 2.3

1 2 3 4

OE OUT

PD/RST

IN2R+/CR2/CR2

IN2R-/CR1/CR1

NC/IN2R1/IN2R+

NC/IN2R2/IN2R-

NC/IN2L2/IN2L-

NC/IN2L1/IN2L+

IN2L-/CL1/CL1

IN2L+/CL2/CL2

FILTD

FILTR

OUT3R-

OUT3R+

OUT3L-

OUT3L+

OUT2R-

OUT2R+

OUT2L-

OUT2L+

OUT1R-

OUT1R+

OUT1L-

OUT1L+

IN1R-

IN1R+

IN1L-

IN1L+

COUT

CDATA

CCLK

CLATCH

MCLK

DLRCLK

DBCLK

ASDATA1

ASDATA2

ALRCLK

ABCLK

DSDATA2

DSDATA1

DSDATA3

Default = All Off

For Test Purposes

DAC1 RIGHT

DAC2 LEFT

DAC2 RIGHT

DAC3 LEFT

DAC3 RIGHT

ADC2 LEFT

ADC2 RIGHT

AUDIO CODEC

DAC1

DAC2

DAC3

ADC1

ADC2

IN (J5)OUT (J4)

RIGHT (RED)

LEFT (WHITE)

DAC1 LEFT

DAC1 RIGHT

ADC1 RIGHT

ADC1 LEFT

DAC1 LEFT

SW10: Audio Loopback

11-7-2007_15:11 6 14

SOIC8

AD8606ARZ

SOIC8

U12

AD8606ARZ

MQFP52

U15

AD1836AASZ

1 3

12.288MHZ

OSC003

U16

4 5

DIP4

SWT018

SW12

AUDIO CODEC

1SW10

DIP6

SWT017

SOIC8

AD8606ARZ

CON024

AD1836_RESET

AD1836_VREF

R46

0805

10K R47

0805

10K10K

0805

R45

CON024

PF4

R158

0805

10K

MISO

MOSI

TSCLK0

DT0SEC

DT0PRI

TFS0

SCK

AD1836_CLK

IN2L1

0.1UF

0805

C123

10UF

CT16

AD1836_CLK

IN1L+

OUT1L+

OUT1L-

OUT1R-

OUT1R+

0805

R61

IN1R-

IN1R+

IN1L-

IN2R1

IN2R2

IN2L2

10K

0805

R57

R44

1206

R43 0

1206

R55

SOIC8

U12

AD8606ARZ

R159

1206

DAC1_LEFT

CAP002

10UF

CT7

49.9K

1206

R109

DAC1_RIGHT

CAP002

10UF

CT8

OUT3R+

OUT3R-

OUT3L-

OUT2R-

OUT2L-

1206

2.74K

R150

0805

1000PF

C40

10UF

CT15

0805

0.1UF

C124

0805

10K

R161

1000PF

0805

C38

0805

1000PF

C39 1000PF

0805

C133

OUT1L+

OUT1L-

OUT1R+

OUT1R-

OUT2L+

OUT2R+

OUT3L+

5.49K

1206

R30

11.0K

1206

R145

1206

2.74K

R151

1206

604.0

R126

220PF

1206

C14

1.65K

1206

R29

100PF

1206

3.32K

1206

R138

5.49K

1206

R18

680PF

0805

C117

330PF

0805

C96

2200PF

1206

C77

5.49K

1206

R27

1206

604.0

R125

220PF

1206

C13

1.65K

1206

R28

100PF

1206

3.32K

1206

R137

5.49K

1206

R17

680PF

0805

C116

330PF

0805

C95

11.0K

1206

R144

2200PF

1206

C76 49.9K

1206

R108

1206

R71

DR0SEC

DR0PRI

RSCLK0

RFS0

DAC1_LEFT

DAC1_RIGHT

DAC2_LEFT

DAC2_RIGHT

DAC3_LEFT

DAC3_RIGHT

ADC2_RIGHT

ADC2_LEFT

ADC1_RIGHT

ADC1_LEFT

AGND

A B C

20 Cotton Road

Nashua, NH 03063

A B C D

PH: 1-800-ANALOGD

Title

Size Board No.

Date Sheet of

DEVICES

ANALOG

Rev

ADSP-BF561 EZ-KIT LITE

A0185-2003 2.3

DAC2 RIGHT DAC3 RIGHT

DAC3 LEFT

DAC2 LEFT

11-7-2007_15:11 7 14

CON024

220PF

1206

C17

SOIC8

AD8606ARZ

SOIC8

AD8606ARZ

AUDIO OUT

AD1836_VREF

SOIC8

AD8606ARZ

OUT2L+

OUT2L-

OUT3L+

OUT3L-

OUT3R+

OUT3R-

OUT2R-

OUT2R+

49.9K

1206

R113

DAC3_RIGHT

CAP002

10UF

CT12

DAC3_LEFT

49.9K

1206

R112

CAP002

10UF

CT11

49.9K

1206

R110

DAC2_LEFT

CAP002

10UF

CT9

49.9K

1206

R111

DAC2_RIGHT

CAP002

10UF

CT10

1206

604.0

R130

2200PF

1206

C81

5.49K

1206

R38

11.0K

1206

R149

2200PF

1206

C80

1206

604.0

R129

1.65K

1206

R36

100PF

1206

C10

3.32K

1206

R141

5.49K

1206

R21

11.0K

1206

R148

5.49K

1206

R35

1206

2.74K

R155 220PF

1206

C18

1.65K

1206

R37

100PF

1206

C11

3.32K

1206

R142

5.49K

1206

R22

680PF

0805

C121

330PF

0805

C100

1206

2.74K

R154

680PF

0805

C120

330PF

0805

C99

SOIC8

AD8606ARZ

1206

2.74K

R153

5.49K

1206

R34

1206

604.0

R127

220PF

1206

C16

1.65K

1206

R33

100PF

1206

3.32K

1206

R140

5.49K

1206

R20

680PF

0805

C119

330PF

0805

C98

11.0K

1206

R147

2200PF

1206

C78

1206

2.74K

R152

5.49K

1206

R31

1206

604.0

R128

220PF

1206

C15

1.65K

1206

R32

100PF

1206

3.32K

1206

R139

5.49K

1206

R19

680PF

0805

C118

330PF

0805

C97

11.0K

1206

R146

2200PF

1206

C79

AGND

AGND AGND

AGND

A B C

20 Cotton Road

Nashua, NH 03063

A B C D

PH: 1-800-ANALOGD

Title

Size Board No.

Date Sheet of

DEVICES

ANALOG

Rev

ADSP-BF561 EZ-KIT LITE

A0185-2003 2.3

ADC1 RIGHT

ADC1 LEFT

ADC2 RIGHT

ADC2 LEFT

14811-7-2007_15:11

CON013

6U18

SOIC8

AD8606ARZ

2U11

SOIC8

AD8606ARZ

6U11

SOIC8

AD8606ARZ

2U18

SOIC8

AD8606ARZ

U24

SOIC8

AD8606ARZ

SOIC8

AD8606ARZ

SOIC8

AD8606ARZ

AUDIO IN

AD1836_VREF

IN2R1

IN2R2

IN2L1

IN2L2

U24

SOIC8

AD8606ARZ

100PF

C34

1206

C25

1000PF

0805

C23

1000PF

0805

C26

100PF

1206

1000PF

C33

0805

1000PF

C36

0805

750.0K

R173

1206

C163

120PF

5.76K

R70

1206

5.76K

R64

1206

120PF

C161

1206

5.76K

R69

1206

5.76K

R124

1206

CAP002

10UF

CT14

1206

100PF

C61

1206

FER9

600

ADC2_RIGHT

IN1R-

237.0

R25

1206

120PF

C103

1206

R15

5.76K

1206

R122

5.76K

1206

10UF

CT6

CAP002

ADC1_RIGHT

FER11

1206

600

100PF

C63

1206

750.0K

R132

1206

5.76K

1206

R16

5.76K

1206

C105

120PF

237.0

R26

1206 IN1R+

ADC1_LEFT

IN1L+

IN1L-

FER10

1206

600

ADC2_LEFT

R123

5.76K

1206

CT5

10UF

CAP002

R40

5.76K

1206

120PF

C130

R50

5.76K

1206

C128

120PF

1206

R53

237.0

1206

R49

5.76K

1206

C62

100PF

1206

R54

237.0

1206

R156

750.0K

1206

5.76K

R121 R62

5.76K

1206

R164

750.0K

1206

FER12

1206

600

C72

100PF

1206

C142

120PF

1206

R58

5.76K

1206

R63

5.76K

1206

120PF

C144

CT13

10UF

CAP002

AGND2

A3V

AGND2

A B C

20 Cotton Road

Nashua, NH 03063

A B C D

PH: 1-800-ANALOGD

Title

Size Board No.

Date Sheet of

DEVICES

ANALOG

Rev

ADSP-BF561 EZ-KIT LITE

A0185-2003 2.3

1 2 3 4

ALSB

BLANK

CLOCK

COMP

DAC_A

DAC_B

DAC_C

FIELD/VSYNC

GND1

GND10

GND2

GND3

GND4

GND5

GND6

GND7

GND8

GND9

HSYNC

RSET

SCLOCK

SCRESET/RTC

SDATA

TTX

TTXREQ

VAA1

VAA2

VAA3

VAA4

VAA5

VREF

RESET

JUMPER

SHORTING

CVSB

Component Video

S Video

Composite Video

Differential Component Video

CVSB

DAC B

DAC C

DAC A

VIDEO ENCODER

DAC A DAC B DAC C

G B R

VUY

Y C

SW11: Video Loopback

Default = All Off

For Test Purposes

SJ1

DEFAULT=1&2

14911-7-2007_16:46

LFCSP40

ADV7179KCPZ

4 5

DIP4

SWT018

SW11

VIDEO ENCODER (VIDEO OUT)

1206

R133

CON024

VENC_RESET

R143

0805

10K 1206

100K

VENC_HS

VENC_VS

3V_B

1206

1.2K

R23

3V_B 150.0

1206

10K

0805

R14

SOT23D

AD1580BRTZ

VIDEO_DAC_B

PF[15:0] PF1

PF0

PPI1_D[15:0] PPI1_D6

PPI1_D5

PPI1_D4

PPI1_D3

PPI1_D2

PPI1_D1

PPI1_D7

PPI1_D0

100K

1206

R13 2.2UH

0805

0.1UF

0805

C12

0805

330PF

C86

SOT23-5

AD8061ARTZ

2.2UH

0805

2.2UH

0805

0.68UH

L1 0.68UH

0805

0.68UH

0805

0.68UH

0805

0.68UH

L8 0.68UH

0805

SOT23-5

AD8061ARTZ

SOT23-5

AD8061ARTZ

330PF

0805

C92

1206

R136

0805

0.1UF

C115

1206

R107

1206

R115

1206

R116

0805

330PF

C82 75

1206

R135 330PF

0805

C94

0805

330PF

C93

1206

R134

1206

330PF

0805

C84

1206

R118

1206

R117

1206

R105

1206

R104

1206

R10

1206

R114

VIDEO_DAC_C

VIDEO_DAC_A

VIDEO_DAC_C

VIDEO_DAC_B

VIDEO_AVIN1

VIDEO_AVIN5

VIDEO_AVIN4

VDEC_CLKOUT

VENC_27MHZ_CLK 1

JP1

IDC3X1

AGND2

1.8V

A1.8V

3.3V

AGND2

AGND2AGND2

AGND2 AGND2

A3V A5V

AGND2

3.3V

A B C

20 Cotton Road

Nashua, NH 03063

A B C D

PH: 1-800-ANALOGD

Title

Size Board No.

Date Sheet of

DEVICES

ANALOG

Rev

ADSP-BF561 EZ-KIT LITE

A0185-2003 2.3

123456

AGND1

AGND2

AGND3

AGND4

AGND5

AIN1

AIN10

AIN11

AIN12

AIN2

AIN3

AIN4

AIN5

AIN6

AIN7

AIN8

AIN9

ALSB

AVDD

CAPC1

CAPC2

CAPY1

CAPY2

CML

DGND1

DGND2

DGND3

DGND4

DGND5

DVDD1

DVDD2

DVDD3

DVDDIO1

DVDDIO2

ELPF

FIELD

LLC1

LLC2

NC[AEF]

NC[AFF]

NC[AGND6]

NC[CLKIN]

NC[GPO0]

NC[GPO1]

NC[GPO2]

NC[GPO3]

NC[ISO]

NC[DV]

NC[HREF]

NC[LLCREF]

NC[RD]

NC[VREF]

P10

P11

P12

P13

P14

P15

PVDD

REFOUT

SCLK

SDA

SFL[HFF]

XTAL

XTAL1

PWRDN

RESET

SW2: Video Sync Signals and Encoder Enable Select

CVBSCVBSComposite Video

AVIN1 AVIN4 AVIN5

YS Video

Differential Component Video

AVIN5

AVIN4

AVIN1

CVBS

(RED) IN

DAC_B

DAC_C

DAC_D

AVIN4

AVIN1

AVIN5

(WHITE) OUT

V U

VIDEO DECODER

OFF = Encoder digital interface always disabled

the encoder digital interface

ON = PF2 Used to enable or disable

Function

1-5

Position

Connect video sync signals to DSP

Note: Signal Names in brackets refer to ADV7183KST

Defalut = OFF, OFF, OFF, OFF, OFF, ON

11-7-2007_15:11 10 14

1206

FER2

600

1206

FER1

DNP

600

1206

FER14

600

1206

FER13

DNP

600

LQFP80

ADV7183BKSTZ

CON024

SW2

SWT017

DIP6

VIDEO DECODER (VIDEO IN)

1206

FER17

DNP

600

1206

FER15

600

0.1UF

0805

C57

0805

1000PF

C67

0805

1000PF

C68

0805

0.01UF

0805

.082UF

C64

PVDD_ADV7183

1.5K

0805

10UF

CT2

10UF

CT4 0.1UF

0805

C59

0.1UF

0805

10UF

CT1

10UF

CT3

1206

R102

1206

R101

0.1UF

0805

C54

0.1UF

0805

C56

0.1UF

0805

0.1UF

0805

0.1UF

0805

C73

PPI0_D[15:0]

PPI0_D1

PPI0_D6

PPI0_D5

PPI0_D4

PPI0_D3

PPI0_D2

PPI0_D7

PPI0_D0

VIDEO_AVIN1

PF[15:0] PF1

PF0

VDEC_HREF

R41

0805

VDEC_VREF

VDEC_CLKOUT

10K

0805

R24

0805

R39

VDEC_RESET

VDEC_27MHZ_CLK

VIDEO_AVIN5

VIDEO_AVIN4

0805

0.1UF

C60

0.1UF

0805

C66

TP1

TP2

TP3

U10

SOT23-5

SN74LVC1G32

0805

0.01UF

C74

0805

0.1UF

C55 0.01UF

0805

R99

0805

10K

R11

10K

0805

R12

0805

R103

0805

0.1UF

C65

0805

10K

R131 10K

0805

1206

R100

0805

R106

0805

10K

0.1UF

0805

C58 PPI1_SYNC1

PPI0_SYNC1

PPI0_SYNC2

PPI1_SYNC2

PF3

PF2 PF[15:0]

VDEC_FIELD

VENC_VS

VDEC_VS

VDEC_HS

VENC_HS

DVDD_ADV7183

PVDD_ADV7183

3.3V

PFI

RESETMR

PFO

RESET

3.3V

5V 3.3V

3.3V

C1+

C1-

C2+

C2-

R1INR1OUT

R2INR2OUT

T1OUT

T2IN T2OUT

V-

V+

T1IN

A B C

20 Cotton Road

Nashua, NH 03063

A B C D

PH: 1-800-ANALOGD

Title

Size Board No.

Date Sheet of

DEVICES

ANALOG

Rev

ADSP-BF561 EZ-KIT LITE

A0185-2003 2.3

123456

JUMPER

SHORTING

SW4 PB Enable Switch

POWER RESET

RESET

Function

Connects the push buttons to the Programmable Flags of the DSP

Useful if using the PFs for another purpose.

Position

1-4

5,6

PF5

PF6

PF7

PF8

NOTE: Remove R192 when populating R191 and R184

UART

Default = ON, ON, ON, ON, OFF, OFF

OFF, OFF = AD1836A -> TDM Mode

ON, ON = AD1836A -> I2S Mode

SJ2

DEFAULT=NOT INSTALLED

11-7-2007_16:46 11 14

6 7

SW4

SWT017

DIP6

RESET, PUSH-BUTTON SWITCHES, UART

TFS0

RSCLK0

0603

FER18

600

0603

FER20

600

0603

FER19

600

0603

FER21

600

0805

R191

DNP

R184

0805

DNP

DB9M

RFS0

1P1

IDC2X1

1312

10 7

U21

SOIC16

ADM3202ARNZ

TSCLK0

1 2

SOIC14

U47

74LVC14A

0805

0.1UF

C158

0805

10K

R98

PF6

PF5

PF[15:0]

PF8

PF7

PF6

PF5

SOIC8

U46

ADM708SARZ

R192

0805

SWT013

MOMENTARY

SW6

MOMENTARY

SWT013

SW7

SWT013

MOMENTARY

SW8

MOMENTARY

SWT013

SW9

100

0805

R245

1206

R225

5 6

SOIC14

U47

74LVC14A

0805

100

R244 0

1206

R224

SOIC14

U47

74LVC14A

SWT013

MOMENTARY

SW1

0.1UF

0805

C159

0.1UF

0805

C147

0805

0.1UF

C148

LED001

RED

LED2

1206

270

R120

13 12

SOIC14

U47

74LVC14A

10K

0805

R251

1206

680

R119

GREEN

LED001

LED1

0805

10K

R229

1206

R223

11 10

SOIC14

U47

74LVC14A

1206

R247

0805

10K

R250

100

0805

R243

SOIC14

U47

74LVC14A

1UF

CT27

1UF

CT28

10K

0805

R249

0805

10K

R248

0805

100

R242

1UF

CT26

1UF

CT25

0805

10K

R246

DA_SOFT_RESET

RESET

3.3V

A B C

20 Cotton Road

Nashua, NH 03063

A B C D

PH: 1-800-ANALOGD

Title

Size Board No.

Date Sheet of

DEVICES

ANALOG

Rev

ADSP-BF561 EZ-KIT LITE

A0185-2003 2.3

EXPANSION INTERFACE (TYPE B)

11-7-2007_15:11 12 14

DSP_VDD_EXT

EXTENDER CARD CONNECTORS

1112

1314

1516

1718

2122

2324

2526

2728

3132

3334

3536

3738

4142

4344

4546

4748

5152

5354

5556

5758

6162

6364

6566

6768

7172

7374

7576

7778

8182

8384

8586

8788

CON019

PF13

PF11

PF9

PF4

PF10

PF12

PF14

PF8

PF6

PF7

PF3

PF1PF0

PF2

PF0

PF5

PF15

PF[15:0]

ABE3

EXT_27MHZ_CLK

PPI1_SYNC1

PPI1_SYNC2

EXT_DSP_CLK

RSCLK1

MISO

MOSI

ABE0

ABE2

SMS0

SMS2

SWE

SA10

SRAS

ARE

ARDY

SMS3

AMS0

AMS1

AMS2

AMS3

SCAS

SCKE

DR0PRI

DR0SEC

PPI0_SYNC1

PPI0_SYNC2

PPI1_SYNC3

PPI1_D15

PPI1_D9

PPI1_D7

PPI1_D5

PPI1_D3

PPI1_D1

PPI1_D2

PPI1_D4

PPI1_D6

PPI1_D8

PPI1_D10

PPI1_D12

PPI1_D14

PPI1_D0

PPI1_D11

PPI1_D13

PPI1_D[15:0]

D30D31

D16

D18

D26

D28

D24

D22

D20

D17

D19

D21

D23

D25

D27

D29

D10

D14

D12

D2D3

D11

D13

D15

D[31:0]

EXP_PPI1_CLK

RESET

VDEC_HS

VDEC_FIELD

VDEC_HREF

TX RX

PPI0_SYNC3

A20

A22

A21

A23

A19 A18

A16

A14

A12

A10

A17

A15

A13

A11

A25 A24

A[25:2]

EXP_PPI0_CLK AWE

AOE

TSCLK0

TFS0

DT0PRI

DT0SEC

TSCLK1

TFS1

DT1PRI

DT1SEC

CLK_OUT_EXP1

SCK

NMI0

DR1SEC

DR1PRI

RFS1

RFS0

RSCLK0

SMS1

CLK_OUT_EXP2

VDEC_VREF

BGH

VDEC_VS

ABE1

1112

1314

1516

1718

2122

2324

2526

2728

3132

3334

3536

3738

4142

4344

4546

4748

5152

5354

5556

5758

6162

6364

6566

6768

7172

7374

7576

7778

8182

8384

8586

8788

CON019

1112

1314

1516

1718

2122

2324

2526

2728

3132

3334

3536

3738

4142

4344

4546

4748

5152

5354

5556

5758

6162

6364

6566

6768

7172

7374

7576

7778

8182

8384

8586

8788

CON019

PPI0_D7

PPI0_D9

PPI0_D11

PPI0_D13

PPI0_D4

PPI0_D6

PPI0_D8

PPI0_D10

PPI0_D12

PPI0_D14

PPI0_D2

PPI0_D0

PPI0_D3

PPI0_D1

PPI0_D15

PPI0_D5

PPI0_D[15:0]

PGND

PGND PGND

COPPER

PGATEFB

COMP

GND

MSC009

RUBBER FOOT

SHGND

1.8V A1.8V3.3V

OUT1

OUT2

OUT3

IN1

IN2

FBSD GND

MSC009

RUBBER FOOT MSC009

RUBBER FOOT

A B C

20 Cotton Road

Nashua, NH 03063

A B C D

PH: 1-800-ANALOGD

Title

Size Board No.

Date Sheet of

DEVICES

ANALOG

Rev

ADSP-BF561 EZ-KIT LITE

A0185-2003 2.3

3.3V

SHGND

3.3V

SHGND

GND

INPUT OUTPUT1

OUTPUT2

A5V

GND

INPUT OUTPUT1

OUTPUT2

A3V

PGND

PGATEFB

COMP

GND

PGND

PGND COPPER

JUMPER

SHORTING

JUMPER

SHORTING

Current 500mA

Current 1.5A

Current 2A

Current 1A

Current 1.5A

SJ3

DEFAULT=INSTALLED

SJ4

DEFAULT=1&2

11-7-2007_16:46 13 14

R79

0.027

1206

0603

54.9K

R252

1206

0.047

R253

100UF

CT29

CT19

100UF

DNP

0603

1UF

C259

C170

1UF

0603

DNP

UNREG_IN

SSB43L

DO-214AA

C169

10UF

1210

IND009

6.8UH

L12

DO-214AA

SSB43L

4 1

SOT23-6

FDC658P

U49

0603

R254

1210

10UF

C260

3 6

2SOT23-6

ADP1864AUJZ

VR6

0603

80.6K

R255

0603

68PF

C257

0603

470PF

C258

0603

24.9K

R256

DSP_VDD_INT

1206

R257

JP3

IDC3X1

L10

6.8UH

IND009

R89

255.0K

0603

R74

0603

R80

80.6K

0603

C160

68PF

0603

C153

470PF

0603

1206

FER16

6000

1206

R73

3 2

SOT-223

VR3

ADP3338AKCZ-33

0805

1UF

C32

1206

FER6

600

1206

R163

3 2

SOT-223

VR1

ADP3339AKCZ-5

UNREG_IN

10UF

CT23

10K

0805

R52

U29

SO-8

NDS8434A

1 2

JP2

IDC2X1 1A

SOT23-312

ZHCS1000

C48

0805

0.1UF

R83

1206

C180

470PF

1206

DNP

UNREG_IN

POWER

MH8MH7MH6

MH5

M5M4M3M2

1206

FER8

600

1206

FER3

600

1206

FER4

600

MH4

147.0K

R56

1206

76.8K

R48

1206 0805

1UF

C24

0805

1UF

C21

4MSOP8

VR2

ADP3336ARMZ

DO-214AA

CT22

68UF

TP10

0805

0.1UF

C122 10UF

CT24 0.1UF

0805

C29

10UF

CT17 TP9TP6

MH2 MH1 MH3

TP4

0805

0.1UF

C35 TP5 TP11TP8

L11

10UH

IND001

C46

1206

1000PF

FER22

FER002

190

FUS005

CON005

7_0V_POWER

C43

1206

1000PF 2

VR5

ADP1864AUJZ

SOT23-6

TP12

U28

FDC658P

SOT23-6

R72

24.9K

0603

MBRS540T3G

SMC

MBRS540T3G

SMC

UNREG_IN

VROUT DSP_VDD_EXT

DSP_VDD_INT

DSP_VDD_EXT

3V_B

TP13

3.3V

3.3V 3.3V 3.3V

3.3V

AGND2

A3V A3V A3VA5V A5VA5V

AGND

AGND AGND AGND

A5V

AGND

A5V

AGND

A5V

AGND

A5V A5V

AGND

A5V

AGND2

3.3V

3.3V 3.3V3.3V3.3V

3.3V 3.3V 3.3V

3.3V

3.3V3.3V

A B C

20 Cotton Road

Nashua, NH 03063

A B C D

PH: 1-800-ANALOGD

Title

Size Board No.

Date Sheet of

DEVICES

ANALOG

Rev

ADSP-BF561 EZ-KIT LITE

A0185-2003 2.3

AGND2

3.3V5V

SDRAM

ADG752 ADG752

AD8606 AD8606AD8606AD8606 AD8606 AD8061AD8061 AD8061

U18

ADG752 ADG752

ADM3202ADM708SAR IDT74FCT3244APY

SDRAM

74LVC14A AD8606

U12 AD8606

AD8606 SN74AHC1G08

IDT2305 M29W640D

ADV7179

27MHZ OSC

ADSP-DM203

U17 U19 U27

U32U33

U47 U5

U6 U24 U11 U9 U10 U3 U2 U1 U22 U23

U8 U4 U46 U21 U13 U25 U14

30MHZ OSC

U15U15

U26

U48

U30

ADV7183 IDT74FCT3244APY

AD1836 U15

Expansion Interface Expansion Interface

11-7-2007_15:11 14 14

0.01UF

0805

C181

1210

10UF

C195 C198

0.1UF

08051210

10UF

C197 C27

0.1UF

0805

1210

10UF

C31

DVDD_ADV7183

C112

0805

0.01UF 0805

0.1UF

C87

0.01UF

0805

C113

0805

0.1UF

C132

C28

0805

0.01UF

0805

0.01UF

C166

0805

0.01UF

C165

0.01UF

0805

C127

0.01UF

0805

C141

0.01UF

0805

C249

0805

0.1UF

C88

0.1UF

0805

C111

0805

0.1UF

C110

0805

0.1UF

C109

0.1UF

0805

C90

0.1UF

0805

C102

0805

0.1UF

C89

0.1UF

0805

C91

0.01UF

0805

C114

0805

0.01UF

C101

0805

0.01UF

C150

0805

0.01UF

C149

0805

0.01UF

C69

0805

0.1UF

C83C70

0805

0.01UF0.1UF

0805

C85

0805

0.1UF

C71C20

0.1UF

0805

0.22UF

0805

C104

0.22UF

0805

C129

0.22UF

0805

C143

0.22UF

0805

C162

0.22UF

0805

C107

0.22UF

0805

C108

0.1UF

0805

C22

0805

0.1UF

C131

0805

0.1UF

C37

0805

0.1UF

C19

0.01UF

0805

C134

0.22UF

0805

C106

0805

0.22UF

C125

0.01UF

0805

C256

C188

0805

0.01UF

0805

0.01UF

C187

0805

0.01UF

C190

0805

0.01UF

C203

0805

0.01UF

C202

0805

0.1UF

C191

0805

0.1UF

C189

0805

0.1UF

C183 C182

0805

0.01UF

0805

0.01UF

C200

0805

0.01UF

C201

0805

0.01UF

C186

0805

0.01UF

C185

0805

0.1UF

C184

0805

0.01UF

C168

0805

0.01UF

C157 0.01UF

0805

C156

0805

0.01UF

C136

0805

0.1UF

C135

0805

0.1UF

C126

0805

0.01UF

C41

0805

0.01UF

C146

0.1UF

0805

C167

0805

0.1UF

C177

0.1UF

0805

C171

0805

0.1UF

C139

0.1UF

0805

C164

0805

0.1UF

C52

0805

0.01UF

C138

0.01UF

0805

C176

0805

0.1UF

C152

0.1UF

0805

C178

0805

0.1UF

C172

0.1UF

0805

C145

0.01UF

0805

C154

0805

0.01UF

C173

10UF

1210

C47

10UF

1210

C50

0.1UF

0805

C51

0.1UF

0805

C175

0.1UF

0805

C155

0805

0.1UF

C179

0.1UF

0805

C151

0805

0.1UF

C30

0805

0.01UF

C174

0.01UF

0805

C49

0.01UF

0805

C140

0.01UF

0805

C137

DECOUPLING CAPS

3V_B

DSP_VDD_INT

0.01UF

0805

C75

DSP_VDD_EXT

0.01UF

0805

C192 C193

0805

0.01UF C194

0805

0.01UF

C196

0.1UF

0805

C199

0.1UF

0805

ADSP-BF561 EZ-KIT Lite Evaluation System Manual I-1 
IINDEX
 
Numerics
2-wire interface (TWI) mode, 1-15, 1-17, 
2-12
A
A25-2 address bus pins, 2-3
AD1836A audio codecs, 1-15, 2-3, 2-4, 
2-12
ADV7179 video encoders
video interface, 1-16
clock select jumper (JP1), 2-14
configuration switch (SW2), 2-10
PPI1 interface, 2-6, 2-7
programmable flags, 2-4
reset, 1-16
ADV7183A video decoders
video interface, 1-16
clock select switch (SW5), 2-13
configuration switch (SW2), 2-10
PPI0 interface, 2-6, 2-7
programmable flags, 2-4
reset, 1-16
AIN1/4/5 analog video channels, 2-7
AMS0 memory select pins, 1-12
analog
audio interface, See SPORT0
video interface, See video interface
architecture, of this EZ-KIT Lite, 2-2
ASYNC (asynchronous memory control) 
banks, 1-11
audio
codecs, See AD1836A
connectors (J4-5), 2-19
enable switch (SW12), 2-13
interface, See SPORT
B
bill of materials, A-1
BMODE1-0 (boot mode select) pins, 2-12
board design database, 1-17
board schematic (ADSP-BF561), B-1
boot mode select switch (SW3), 2-11
C
clock select switch, of PPIs (SW5), 2-13
codecs, See AD1836A
configuration, of this EZ-KIT Lite, 1-3
connectors
diagram of locations, 2-18
DB9 (UART), xii, 2-8
J1-3 (expansion), 2-8, 2-19
J4-5 (audio), 2-19
J6 (video), 2-20
J7 (power), 2-20
P2 (RS-232), xi, 2-20
P3 (SPORT1), 2-3, 2-21
P5 (SPI), 2-3, 2-14, 2-21
P9 (SPORT0), 2-21
ZJ1 (USB), 1-5, 2-21
ZP4 (JTAG), 2-22
contents, of this EZ-KIT Lite package, 1-2

Index
I-2 ADSP-BF561 EZ-KIT Lite Evaluation System Manual
core
clock rate, 2-2, 2-14
frequency, 1-14
voltage, 2-2
D
DAC A/B/C analog audio channels, 2-7
DB9 (UART) connector, xii, 2-8, 2-20
default configuration, of this EZ-KIT Lite, 
1-3
DIP switches
diagram of locations, 1-3, 2-10
SW10-11 (test), 2-13
SW2 (video config), 1-16, 2-8
SW4 (push button enable), 1-15, 2-12, 
2-16
E
EBIU
address bus (A25-2) pins, 2-3
control signals, 2-3, 2-8
EBIU_SDBCTL register, 1-13, 1-14
EBIU_SDGCTL register, 1-13, 1-14
EBIU_SDRRC register, 1-13, 1-14
evaluation license
CCES, 1-10
example programs, 1-18
expansion interface, 2-3, 2-8, 2-19
external bus interface unit, See EBIU
external memory
See also flash memory, SDRAM
memory map, 1-11
via JTAG, 2-9
EZ-KIT Extender boards, 2-6
F
features, of this EZ-KIT Lite, xi
FIELD (ADV7183A) control signal, 2-4, 
2-8, 2-11
FIO0_FLAG_D registers, 1-15
FIO2_DIR register, 1-14
FIO2_FLAG_C/D/S/T registers, 1-14
flag pins, See programmable flags (PFs)
flash
memory, 2-3
ports (PB47-32), 2-17
frequency, 1-13, 1-14
G
general-purpose IO pins, 1-14, 2-4, 2-12, 
2-16
GND signals, 2-8
H
HSYNC signals, 2-6, 2-7
I
input clocks, 1-16, 2-2, 2-5, 2-7
installation, of this EZ-KIT Lite, 1-8
CCES, 1-4
interfaces, See video, SPORT0, SPI, 
expansion
internal memory
See also SRAM
map of the processor, 1-12
internal voltage (VDDINT), 2-14
IO voltage, 2-2

ADSP-BF561 EZ-KIT Lite Evaluation System Manual I-3
Index
J
JTAG
connector (ZP4), 2-9, 2-22
emulation port, 2-9
jumpers
JP1 (ADV7179 clock select), 2-14
JP2-3 (VDDINT source select), 2-14
P1 (UART loop), 2-15
L
LEDs
diagram of locations, 1-3, 2-15
LED13-20 (PF39-32), 1-14, 2-5, 2-17
LED1 (power), 2-16
LED2 (chip reset), 2-17
LED5-12 (PF47-40), 1-14, 2-5, 2-17
ZLED3 (USB monitor), 1-8, 2-17
M
Media Instruction Set Computing (MISC), 
ix
memory
map, of this EZ-KIT Lite, 1-11
select pins, See AMS2-0, SMS0
Micro Signal Architecture (MSA), ix
N
notation conventions, xviii
O
OE (ADV7183A) signal, 2-4, 2-10
oscillators, 2-6, 2-7, 2-13
P
P3 (SPORT0) connector, 2-3
package contents, 1-2
parallel peripheral interfaces (PPIs), 1-17, 
2-5, 2-10, 2-19
See also PPI0, PPI1
PB47-32 flash ports, 2-17
power
connector (J7), 2-20
LED (LED1), 2-16
PPI0_D15-8 bits, 1-14, 2-5
PPI0 interface
to ADV7183A decoder, 1-16, 2-7
clock select pin, 2-6, 2-7
D15-8 bits, 2-17
D7-0 bits, 2-6
SYNC2-1 signals, 2-6, 2-8, 2-11
PPI0_SYNC2-1 synchronization signals, 
2-8, 2-11
PPI1_D15-8 bits, 1-14, 2-5
PPI1 interface
to ADV7179 video encoder, 1-16, 2-7
clock select pin, 2-7
D15-8 bits, 2-17
D7-0 bits, 2-6, 2-7
HSYNC signals, 2-7
SYNC2-1 signals, 2-7, 2-11
PPI clock select switch (SW5), 1-16, 2-13
PPIxCLK signals, 2-13
product information, xvi
programmable flags (PFs)
connections, 2-4
PF0 (video serial clock), 1-17, 2-4
PF1 (video serial data), 1-17, 2-4
PF2 (DV7183A enable), 1-17, 2-4, 2-10, 
2-11
PF3 (ADV7183A field pin), 2-4, 2-8, 
2-11
PF4 (AD1836A SPI select), 1-15, 2-3, 
2-4
PF13 (ADV7183A reset), 1-16, 2-4
PF14 (ADV7179 reset), 1-16, 2-5
PF15 (AD1836A reset), 1-16, 2-5

Index
I-4 ADSP-BF561 EZ-KIT Lite Evaluation System Manual
programmable flags (PFs) (continued)
PF16-20 (SPORT0), 2-5
PF21-25 (SPORT1), 2-5
PF26-27 (UART), 2-5
PF28-29 (SPORT0 serial clock), 2-5
PF30-31 (SPORT1 serial clock), 2-5
PF39-32 (LED13-20), 2-5
PF47-40 (LED5-12), 1-14, 2-5
PF5-8 (general-purpose IO), 1-14, 2-4, 
2-12, 2-16
pull-down resistors, 1-16
pull-up resistors, 2-11
push buttons
See also switches by name (SWx), 1-14
diagram of locations, 2-15
enable switch (SW4), 2-12
R
RCA jacks, xi, 2-19
Reduced Instruction Set Computing 
(RISC), ix
related documents, xviii
reset
audio codec, 1-16
LED (LED2), 2-17
processor, 1-13
push buttons switch (SW1), 2-16
USB interface, 2-16
video encoder/decoder, 1-16, 2-4
RFS0 signal, 1-15, 2-12
RS-232 connector (P2), xi, 2-8
RSCLK0 signal, 1-15, 2-12
S
schematic, of ADSP-BF561 EZ-KIT Lite, 
B-1
SDRAM memory
connections, 2-3
control registers, 1-12
SDRAM memory (continued)
core MMRs, 1-12
data bank B SRAM, 1-12
data banks A, B SRAM, 1-12
default settings, 1-13
instruction SRAM, 1-12
instruction SRAM/CACHE, 1-12
optimum settings, 1-14
reserved, 1-12
scratch pad SRAM, 1-12
system MMRs, 1-12
serial
clock pin (SCL), 1-17, 2-4
data pin (SDAT), 1-17
video data, 2-4
serial peripheral interface (SPI), 2-3, 2-4, 
2-14
setup, of this EZ-KIT Lite, 1-4
SMS0 memory select pins, 1-12
SPIS1/SPISS signals, 2-14
SPORT
audio interface, 2-3
SPORT0
audio interface, xii, 1-15
connector (P3), 2-21
receive data secondary pin (PF20), 2-5
receive frame sync pin (PF19), 2-5
receive serial clock pin (PF28), 2-5
transmit data primary pin (PF18), 2-5
transmit data secondary pin (PF17), 2-5
transmit frame sync pin (PF16), 2-5
transmit serial clock pin (PF29), 2-5
SPORT1
receive data secondary pin (PF25), 2-5
receive frame sync pin (PF24), 2-5
receive serial clock pin (PF29), 2-5
transmit data primary pin (PF23), 2-5
transmit data secondary pin (PF22), 2-5
transmit frame pin (PF21), 2-5
transmit serial clock pin (PF31), 2-5

ADSP-BF561 EZ-KIT Lite Evaluation System Manual I-5
Index
SRAM data bank A, 1-12
startup, of this EZ-KIT Lite, 1-8
CCES, 1-4
SW10-11 (test) DIP switches, 2-13
SW12 (audio enable) switch, 2-13
SW13 (SPIS1/SPISS select) switch, 2-14
SW1 (reset) push button, 2-16
SW2 (video config) DIP switch, 1-16, 2-6, 
2-7, 2-8, 2-11
SW3 (boot mode) switch, 2-11
SW4 (push button enable) DIP switch, 
1-15, 2-12, 2-16
SW5 (PPI clock select) switch, 1-16, 2-6, 
2-13
SW6-9 (general input) push buttons, 1-14, 
2-4, 2-12, 2-16
synchronous dynamic random access 
memory, See SDRAM
system
architecture, of EZ-KIT Lite, 2-2
clock (SCLK), 1-13
T
technical support, xv
test DIP switches (SW10-11), 2-13
TFS0 signal, 1-15, 2-12
time-division multiplexed (TDM) mode, 
1-15
timers11-8, 2-6
timers7-0, 2-4
TSCLK0 signal, 1-15, 2-12
U
UART
loop jumper (P1), 2-15
port, xii, 2-8
transmit/receive pins (PF26-27), 2-5
universal asynchronous 
receiver/transmitter, See UART port
USB
cable, 1-2
connector (ZJ1, 1-5
debug agent connector (ZJ1), 2-21
interface, 2-9, 2-16, 2-22
monitor LED (ZLED3), 2-17
user LEDs (LED5-12, LED13-20), 2-17
V
VDDINT signal, 2-14
very-long instruction word (VLIW), ix
video
channels, 2-7
configuration switch (SW2), 2-10
connector (J6), 2-20
control signals, 2-7, 2-8
decoders, See ADV7183A
encoders, See ADV7179
input (PPI0), 2-7
interface, 1-16
output (PPI1), 2-7
VisualDSP++
environment, 1-8
VROUT pins, 2-14
VSYNC signals, 2-6, 2-7

Index

I-6 ADSP-BF561 EZ-KIT Lite Evaluation System Manual

Mouser Electronics

Authorized Distributor

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