HY5V22GF-P - Hynix Semiconductor, Inc.

HY5V22GF

4 Banks x 1M x 32Bit Synchronous DRAM

This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume

any responsibility for use of circuits described. No patent licenses are implied.

Rev. 0.3/Nov. 01

DESCRIPTION

The Hynix HY5V22G is a 134,217,728-bit CMOS Synchronous DRAM, ideally suited for the memory applications

which require wide data I/O and high bandwidth. HY5V22G is organized as 4banks of 1,048,576x32.

HY5V22G is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are

synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high band-

width. All input and output voltage levels are compatible with LVTTL.

Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write

cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count

sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate

command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined

design is not restricted by a `2N` rule.)

FEATURES

• JEDEC standard 3.3V power supply

• All device pins are compatible with LVTTL interface

• 90Ball FBGA with 0.8mm of pin pitch

• All inputs and outputs referenced to positive edge of

system clock

• Data mask function by DQM0,1,2 and 3

• Internal four banks operation

• Auto refresh and self refresh

• 4096 refresh cycles / 64ms

• Programmable Burst Length and Burst Type

- 1, 2, 4, 8 or full page for Sequential Burst

- 1, 2, 4 or 8 for Interleave Burst

• Programmable CAS Latency ; 2, 3 Clocks

• Burst Read Single Write operation

ORDERING INFORMATION

Part No. Clock Frequency Power Organization Interface Package

HY5V22GF-H 133MHz

Normal 4Banks x 1Mbits

x32 LVTTL 90Ball FBGA

HY5V22GF-P 100MHz

Rev. 0.3/Nov. 01 3

HY5V22GF

PIN CONFIGURATION

PIN DESCRIPTION

PIN PIN NAME DESCRIPTION

CLK Clock The system clock input. All other inputs are registered to the SDRAM on the

rising edge of CLK.

CKE Clock Enable Controls internal clock signal and when deactivated, the SDRAM will be one

of the states among power down, suspend or self refresh

CS Chip Select Enables or disables all inputs except CLK, CKE and DQM

BA0, BA1 Bank Address Selects bank to be activated during RAS activity

Selects bank to be read/written during CAS activity

A0 ~ A11 Address Row Address : RA0 ~ RA11, Column Address : CA0 ~ CA7

Auto-precharge flag : A10

RAS, CAS, WE

Row Address Strobe,

Column Address Strobe,

Write Enable

RAS, CAS and WE define the operation

Refer function truth table for details

DQM0~3 Data Input/Output Mask Controls output buffers in read mode and masks input data in write mode

DQ0 ~ DQ31 Data Input/Output Multiplexed data input / output pin

VDD/VSS Power Supply/Ground Power supply for internal circuits and input buffers

VDDQ/VSSQ Data Output Power/Ground Power supply for output buffers

NC No Connection No connection

Top View

(11mmx13mm)

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

DQ26 DQ24 VSS

DQ28 VDDQ VSSQ

VSSQ DQ27 DQ25

VSSQ DQ29 DQ30

VDDQ DQ31 NC

VSS DQM3 A3

A4 A5 A6

A7 A8 NC

CLK CKE A9

DQM1 NC NC

VDDQ DQ8 VSS

VSSQ DQ10 DQ9

VSSQ DQ12 DQ14

DQ11 VDDQ VSSQ

DQ13 DQ15 VSS

VDD DQ23 DQ21

VDDQ VSSQ DQ19

DQ22 DQ20 VDDQ

DQ17 DQ18 VDDQ

NC DQ16 VSSQ

A2 DQM2 VDD

A10 A0 A1

NC BA1 A11

BA0 CS# RAS#

CAS# WE# DQM0

VDD DQ7 VSSQ

DQ6 DQ5 VDDQ

DQ1 DQ3 VDDQ

VDDQ VSSQ DQ4

VDD DQ0 DQ2

123 789456

Top View

(11mmx13mm)

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

DQ26 DQ24 VSS

DQ28 VDDQ VSSQ

VSSQ DQ27 DQ25

VSSQ DQ29 DQ30

VDDQ DQ31 NC

VSS DQM3 A3

A4 A5 A6

A7 A8 NC

CLK CKE A9

DQM1 NC NC

VDDQ DQ8 VSS

VSSQ DQ10 DQ9

VSSQ DQ12 DQ14

DQ11 VDDQ VSSQ

DQ13 DQ15 VSS

VDD DQ23 DQ21

VDDQ VSSQ DQ19

DQ22 DQ20 VDDQ

DQ17 DQ18 VDDQ

NC DQ16 VSSQ

A2 DQM2 VDD

A10 A0 A1

NC BA1 A11

BA0 CS# RAS#

CAS# WE# DQM0

VDD DQ7 VSSQ

DQ6 DQ5 VDDQ

DQ1 DQ3 VDDQ

VDDQ VSSQ DQ4

VDD DQ0 DQ2

123 789456

Rev. 0.3/Nov. 01 4

HY5V22GF

FUNCTIONAL BLOCK DIAGRAM

1Mbit x 4banks x 32 I/O Synchronous DRAM

X decoder

State Machine

A0

A1

A10

BA0

BA1

Address buffers

Address

Register

Mode Register

Row

Pre

Decoder

Column

Pre

Decoder

Column Add

Counter

Row Active

Column

Active

Burst

Counter

Data Out Control

CAS Latency

Refresh

Counter

DQ0

DQ1

DQ30

DQ31

Self Refresh Logic

& Timer

Pipe Line Control

I/O Buffer & Logic

Bank Select

Sense AMP & I/O Gate

CLK

CKE

CS

RAS

CAS

WE

DQM0

DQM1

DQM2

DQM3

x32 Bank 3

X decoder

Memory

Cell

Array

Y decoder

X decoder

1M x32 Bank 0

1M x32 Bank 1

1M x32 Bank 2

1M

Rev. 0.3/Nov. 01 5

HY5V22GF

ABSOLUTE MAXIMUM RATINGS

Note : Operation at above absolute maximum rating can adversely affect device reliability

DC OPERATING CONDITION (TA=0 to 70°C)

Note :

1.All voltages are referenced to VSS = 0V

2.VDD/VDDQ(min) is 3.15V for HY5V22GF-H/P

3.VIH (max) is acceptable 5.6V AC pulse width with ≤3ns of duration with no input clamp diodes

4.VIL (min) is acceptable -2.0V AC pulse width with ≤3ns of duration with no input clamp diodes

AC OPERATING CONDITION (TA=0 to 70°C, 3.0V ≤VDD ≤3.6V, VSS=0V - Note1)

Note :

1.3.15V ≤VDD ≤3.6V is applied for HY5V22GF-H/P

2.Output load to measure access times is equivalent to two TTL gates and one capacitor (30pF)

For details, refer to AC/DC output load circuit

Parameter Symbol Rating Unit

Ambient Temperature TA0 ~ 70 °C

Storage Temperature TSTG -55 ~ 125 °C

Voltage on Any Pin relative to VSS VIN, VOUT -1.0 ~ 4.6 V

Voltage on VDD relative to VSS VDD, VDDQ -1.0 ~ 4.6 V

Short Circuit Output Current IOS 50 mA

Power Dissipation PD1W

Soldering Temperature ⋅ Time TSOLDER 260 ⋅ 10 °C ⋅ Sec

Parameter Symbol Min Typ. Max Unit Note

Power Supply Voltage VDD, VDDQ 3.0 3.3 3.6 V 1,2

Input high voltage VIH 2.0 3.0 VDDQ + 0.3 V 1,3

Input low voltage VIL VSSQ - 0.3 0 0.8 V 1,4

Parameter Symbol Value Unit Note

AC input high / low level voltage VIH / VIL 2.4/0.4 V

Input timing measurement reference level voltage Vtrip 1.4 V

Input rise / fall time tR / tF 1 ns

Output timing measurement reference level Voutref 1.4 V

Output load capacitance for access time measurement CL 30 pF 2

Rev. 0.3/Nov. 01 6

HY5V22GF

CAPACITANCE (TA=25°C, f=1MHz, VDD=3.3V)

OUTPUT LOAD CIRCUIT

DC CHARACTERISTICS I (DC operating conditions unless otherwise noted)

Note :

1.VIN = 0 to 3.6V, All other pins are not under test = 0V

2.DOUT is disabled, VOUT=0 to 3.6V

Parameter Pin Symbol Min Max Unit

Input capacitance CLK CI1 2.5 3.5 pF

A0 ~ A10, BA0, BA1, CKE, CS, RAS,

CAS, WE, DQM0~3

CI22.5 3.8 pF

Data input / output capacitance DQ0 ~ DQ31 CI/O 46.5pF

Parameter Symbol Min. Max Unit Note

Input leakage current ILI -1 1 uA 1

Output leakage current ILO -1 1 uA 2

Output high voltage VOH 2.4 - V IOH = -2mA

Output low voltage VOL -0.4VIOL = +2mA

Vtt=1.4V

RT=500 Ω

30pF

Output

DC Output Load Circuit AC Output Load Circuit

Vtt=1.4V

RT=50 Ω

30pF

Output Z0 = 50Ω

Rev. 0.3/Nov. 01 7

HY5V22GF

DC CHARACTERISTICS II (DC operating conditions unless otherwise noted)

Note :

1.IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open

2.Min. of tRRC (Refresh RAS cycle time) is shown at AC CHARACTERISTICS I

Parameter Symbol Test Condition

Speed

Unit Note

-H -P

Operating Current IDD1

Burst Length=1, One bank active

tRAS ≥ tRAS(min), tRP ≥ tRP(min),

IOL=0mA

150 140 mA 1

Precharge Standby Current

in power down mode

IDD2P CKE ≤ VIL(max), tCK = 15ns 4

mA

IDD2PS CKE ≤ VIL(max), tCK = ∞4

Precharge Standby Current

in non power down mode

IDD2N

CKE ≥ VIH(min), CS ≥ VIH(min), tCK = 15ns

Input signals are changed one time during

2clks. All other pins ≥ VDD-0.2V or ≤ 0.2V

30

mA

IDD2NS CKE ≥ VIH(min), tCK = ∞

Input signals are stable. 20

Active Standby Current

in power down mode

IDD3P CKE ≤ VIL(max), tCK = 15ns 6

mA

IDD3PS CKE ≤ VIL(max), tCK = ∞6

Active Standby Current

in non power down mode

IDD3N

CKE ≥ VIH(min), CS ≥ VIH(min), tCK = 15ns

Input signals are changed one time during

2clks. All other pins ≥ VDD-0.2V or ≤ 0.2V

80

mA

IDD3NS CKE ≥ VIH(min), tCK = ∞

Input signals are stable 50

Burst Mode Operating

Current IDD4

tCK ≥ tCK(min),

tRAS ≥ tRAS(min), IOL=0mA

All banks active

CL=3

250 230 mA 1

CL=2

Auto Refresh Current IDD5 tRRC ≥ tRRC(min), 2 banks active 350 330 mA 2

Self Refresh Current IDD6 CKE ≤ 0.2V 4mA

Rev. 0.3/Nov. 01 8

HY5V22GF

AC CHARACTERISTICS I (AC operating conditions unless otherwise noted)

Note :

1.Assume tR / tF (input rise and fall time ) is 1ns

2.Access times to be measured with input signals of 1v/ns edge rate, 0.8v to 2.0v

3.Data-out hold time to be measured under 30pF load condition, without Vt termination

Parameter Symbol

-H -P

Unit Note

Min Max Min Max

System clock

cycle time

CAS Latency = 3 tCK3 7.5

1000

10

1000

ns

CAS Latency = 2 tCK2 10 10 ns

Clock high pulse width tCHW 2.5 - 3 - ns 1

Clock low pulse width tCLW 2.5 - 3 - ns 1

Access time from clock

CAS Latency = 3 tAC3 5.4 6 ns

2

CAS Latency = 2 tAC2 6 - 6 ns

Data-out hold time tOH 2.7 - 3 - ns 3

Data-Input setup time tDS 1.5 - 2 - ns 1

Data-Input hold time tDH 0.8 - 1 - ns 1

Address setup time tAS 1.5 - 2 - ns 1

Address hold time tAH 0.8 - 1 - ns 1

CKE setup time tCKS 1.5 - 2 - ns 1

CKE hold time tCKH 0.8 - 1 - ns 1

Command setup time tCS 1.5 - 2 - ns 1

Command hold time tCH 0.8 - 1 - ns 1

CLK to data output in low Z-time tOLZ 1.5 - 1 - ns

CLK to data output in

high Z-time

CAS Latency = 3 tOHZ3

5.4 6

ns

CAS Latency = 2 tOHZ2 ns

Rev. 0.3/Nov. 01 9

HY5V22GF

AC CHARACTERISTICS II (AC operating conditions unless otherwise noted)

Note :

1. A new command can be given tRRC after self refresh exit

Parameter Symbol

-H -P

Unit Note

Min Max Min Max

RAS cycle time

Operation tRC 65 - 70 - ns

Auto Refresh tRRC 65 - 70 - ns

RAS to CAS delay tRCD 20 - 20 - ns

RAS active time tRAS 45 120K 50 120K ns

RAS precharge time tRP 20 - 20 - ns

RAS to RAS bank active delay tRRD 15 - 20 - CLK

CAS to CAS delay tCCD 1 - 1 - CLK

Write command to data-in delay tWTL 0 - 0 - CLK

Data-in to precharge command tDPL 1 - 1 - CLK

Data-in to active command tDAL 4 - 3 - CLK

DQM to data-out Hi-Z tDQZ 2 - 2 - CLK

DQM to data-in mask tDQM 0 - 0 - CLK

MRS to new command tMRD 1 - 1 - CLK

Precharge to data

output Hi-Z

CAS Latency = 3 tPROZ3 3 - 3 - CLK

CAS Latency = 2 tPROZ2 2 - 2 - CLK

Power down exit time tPDE 1 - 1 - CLK

Self refresh exit time tSRE 1 - 1 - CLK 1

Refresh Time tREF - 64 - 64 ms

Rev. 0.3/Nov. 01 10

HY5V22GF

DEVICE OPERATING OPTION TABLE

HY5V22GF-H

HY5V22GF-P

CAS Latency tRCD tRAS tRC tRP tAC tOH

133MHz(7.5ns) 3CLKs 3CLKs 6CLKs 9CLKs 3CLKs 5.4ns 2.7ns

125MHz(8ns) 3CLKs 3CLKs 6CLKs 9CLKs 3CLKs 6ns 3ns

100MHz(10ns) 2CLKs 2CLKs 5CLKs 7CLKs 2CLKs 6ns 3ns

CAS Latency tRCD tRAS tRC tRP tAC tOH

100MHz(10ns) 2CLKs 2CLKs 5CLKs 7CLKs 2CLKs 6ns 3ns

83MHz(12ns) 2CLKs 2CLKs 5CLKs 7CLKs 2CLKs 6ns 3ns

66MHz(15ns) 2CLKs 2CLKs 4CLKs 6CLKs 2CLKs 6ns 3ns

Rev. 0.3/Nov. 01 11

HY5V22GF

COMMAND TRUTH TABLE

Note :

1. Exiting Self Refresh occurs by asynchronously bringing CKE from low to high

2. X = Don′t care, H = Logic High, L = Logic Low. BA =Bank Address, RA = Row Address, CA = Column Address,

Opcode = Operand Code, NOP = No Operation

Command CKEn-1 CKEn CS RAS CAS WE DQM ADDR A10/

AP BA Note

Mode Register Set H X LLLLX OP code

No Operation H X

HXXX

XX

LHHH

Bank Active H X L L H H X RA V

Read

HXLHLHXCA

L

V

Read with Autoprecharge H

Write

HXLHLLXCA

L

V

Write with Autoprecharge H

Precharge All Banks

HXLLHLXX

HX

Precharge selected Bank LV

Burst Stop H X L H H L X X

DQM H X V X

Auto Refresh H H L L L H X X

Self Refresh1

Entry H L LLLHX

X

Exit L H

HXXX

X

LHHH

Precharge

power down

Entry H L

HXXX

X

LHHH

Exit L H

HXXX

X

LHHH

Clock

Suspend

Entry H L

HXXX

X

XLVVV

Exit L H X X

Rev. 0.3/Nov. 01 12

HY5V22GF

PACKAGE INFORMATION