TPS2046, TPS2056
DUAL CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES
SLVS183 – APRIL 1999
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
features
D
135-mΩ -Maximum (5-V Input) High-Side
MOSFET Switch
D
250 mA Continuous Current per Channel
D
Independent Short-Circuit and Thermal
Protection With Overcurrent Logic Output
D
Operating Range . . . 2.7-V to 5.5-V
D
Logic-Level Enable Input
D
2.5-ms Typical Rise Time
D
Undervoltage Lockout
D
10 µA Maximum Standby Supply Current
D
Bidirectional Switch
D
Available in 8-pin SOIC and PDIP Packages
D
Ambient Temperature Range, –40°C to 85°C
D
2-kV Human-Body-Model, 200-V
Machine-Model ESD Protection
typical applications
D
Notebook, Desktop and Palmtop PCs
D
Monitors, Keyboards, Scanners, and
Printers
D
Digital Cameras, Phones, and PBXs
D
Hot-Insertion Applications
description
The TPS2046 and TPS2056 dual power-distribution switches are intended for applications where heavy
capacitive loads and short circuits are likely. These devices incorporate in single packages two 135-mΩ
N-channel MOSFET high-side power switches for power-distribution systems that require multiple power
switches. Each switch is controlled by a logic enable compatible with 5-V and 3-V logic. Gate drive is provided
by an internal charge pump that controls the power-switch rise times and fall times to minimize current surges
during switching. The charge pump requires no external components and allows operation from supplies as low
as 2.7 V.
When the output load exceeds the current-limit threshold or a short is present, the TPS2046 and TPS2056 limit
the output current to a safe level by switching into a constant-current mode, pulling the overcurrent (OCx) logic
output low. When continuous heavy overloads and short circuits increase the power dissipation in the switch
causing the junction temperature to rise, a thermal protection circuit shuts off the switch in overcurrent to prevent
damage. Recovery from a thermal shutdown is automatic once the device has cooled sufficiently. Internal
circuitry ensures the switch remains off until valid input voltage is present.
The TPS2046 and TPS2056 are designed to limit at 0.44-A load. These power distribution switches, available
in 8-pin small-outline integrated circuit (SOIC) and 8-pin plastic dual-in-line packages (PDIP), operate over an
ambient temperature range of –40°C to 85°C.
AVAILABLE OPTIONS
RECOMMENDED
MAXIMUM CONTINUOUS
TYPICAL
SHORT CIRCUIT CURRENT
PACKAGED DEVICES
TAENABLE
MAXIMUM
CONTINUOUS
LOAD CURRENT
(A)
SHORT
-
CIRCUIT
CURRENT
LIMIT AT 25°C
(A) SOIC
(D)†PDIP
(P)
–40°C to 85°CActive low 0.25 0.44 TPS2046D TPS2046P
–40°C to 85°CActive high 0.25 0.44 TPS2056D TPS2056P
†The D package is available taped and reeled. Add an R suffix to device type (e.g., TPS2046DR)
Copyright 1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
2
3
4
8
7
6
5
GND
IN
EN1
EN2
OC1
OUT1
OUT2
OC2
TPS2046
D OR P PACKAGE
(TOP VIEW)
1
2
3
4
8
7
6
5
GND
IN
EN1
EN2
OC1
OUT1
OUT2
OC2
TPS2056
D OR P PACKAGE
(TOP VIEW)
TPS2046, TPS2056
DUAL CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES
SLVS183 – APRIL 1999
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS2046 functional block diagram
†Current sense
Thermal
Sense
Driver Current
Limit
Charge
Pump
UVLO
CS †
Driver Current
Limit
CS †
Thermal
Sense
Charge
Pump
Power Switch
GND
EN1
IN
EN2
OC1
OUT1
OUT2
OC2
Terminal Functions
TERMINAL
NO.
I/O
DESCRIPTION
NAME D OR P
I/O
DESCRIPTION
TPS2046 TPS2056
EN1 3 – I Enable input. Logic low turns on power switch, IN-OUT1.
EN2 4 – I Enable input. Logic low turns on power switch, IN-OUT2.
EN1 – 3 I Enable input. Logic high turns on power switch, IN-OUT1.
EN2 – 4 I Enable input. Logic high turns on power switch, IN-OUT2.
GND 1 1 I Ground
IN 2 2 I Input voltage
OC1 8 8 O Overcurrent. Logic output active low, for power switch, IN-OUT1
OC2 5 5 O Overcurrent. Logic output active low, for power switch, IN-OUT2
OUT1 7 7 O Power-switch output
OUT2 6 6 O Power-switch output
TPS2046, TPS2056
DUAL CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES
SLVS183 – APRIL 1999
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
detailed description
power switch
The power switch is an N-channel MOSFET with a maximum on-state resistance of 135 mΩ (VI(IN) = 5 V).
Configured as a high-side switch, the power switch prevents current flow from OUTx to IN and IN to OUTx when
disabled. The power switch can supply a minimum of 250 mA per switch.
charge pump
An internal charge pump supplies power to the driver circuit and provides the necessary voltage to pull the gate
of the MOSFET above the source. The charge pump operates from input voltages as low as 2.7 V and requires
very little supply current.
driver
The driver controls the gate voltage of the power switch. To limit large current surges and reduce the associated
electromagnetic interference (EMI) produced, the driver incorporates circuitry that controls the rise times and
fall times of the output voltage. The rise and fall times are typically in the 2-ms to 4-ms range.
enable (ENx or ENx)
The logic enable disables the power switch and the bias for the charge pump, driver, and other circuitry to reduce
the supply current to less than 10 µA when a logic high is present on ENx (TPS2046) or a logic low is present
on ENx (TPS2056). A logic zero input on ENx or logic high on ENx restores bias to the drive and control circuits
and turns the power on. The enable input is compatible with both TTL and CMOS logic levels.
overcurrent (OCx)
The OCx open-drain output is asserted (active low) when an overcurrent or overtemperature condition is
encountered. The output will remain asserted until the overcurrent or overtemperature condition is removed.
current sense
A sense FET monitors the current supplied to the load. The sense FET measures current more efficiently than
conventional resistance methods. When an overload or short circuit is encountered, the current-sense circuitry
sends a control signal to the driver. The driver in turn reduces the gate voltage and drives the power FET into
its saturation region, which switches the output into a constant current mode and holds the current constant
while varying the voltage on the load.
thermal sense
The TPS2046 and TPS2056 implement a dual-threshold thermal trip to allow fully independent operation of the
power distribution switches. In an overcurrent or short-circuit condition the junction temperature rises. When
the die temperature rises to approximately 140°C, the internal thermal sense circuitry checks to determine which
power switch is in an overcurrent condition and turns off that switch, thus isolating the fault without interrupting
operation of the adjacent power switches. Hysteresis is built into the thermal sense, and after the device has
cooled approximately 20 degrees, the switch turns back on. The switch continues to cycle off and on until the
fault is removed. The (OCx) open-drain output is asserted (active low) when overtemperature or overcurrent
occurs.
undervoltage lockout
A voltage sense circuit monitors the input voltage. When the input voltage is below approximately 2 V , a control
signal turns off the power switch.
TPS2046, TPS2056
DUAL CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES
SLVS183 – APRIL 1999
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Input voltage range, VI(IN) (see Note1) –0.3 V to 6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, VO(OUTx) (see Note1) –0.3 V to VI(IN) + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI(ENx) or VI(ENx) –0.3 V to 6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, IO(OUTx) internally limited. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total power dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating virtual junction temperature range, TJ–40°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature soldering 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . .
Electrostatic discharge (ESD) protection: Human body model MIL-STD-883C 2 kV. . . . . . . . . . . . . . . . . . . . .
Machine model 0.2 kV. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.
NOTE 1: All voltages are with respect to GND.
DISSIPATION RATING TABLE
PACKAGE TA ≤ 25°C
POWER RATING DERATING FACTOR
ABOVE TA = 25°CTA = 70°C
POWER RATING TA = 85°C
POWER RATING
D725 mW 5.8 mW/°C464 mW 377 mW
P1175 mW 9.4 mW/°C752 mW 611 mW
recommended operating conditions
TPS2046 TPS2056
UNIT
MIN MAX MIN MAX
UNIT
Input voltage, VI(IN) 2.7 5.5 2.7 5.5 V
Input voltage, VI(ENx) or VI(ENx) 0 5.5 0 5.5 V
Continuous output current, IO(OUTx) 0 250 0 250 mA
Operating virtual junction temperature, TJ–40 125 –40 125 °C
TPS2046, TPS2056
DUAL CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES
SLVS183 – APRIL 1999
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating junction temperature range, VI(IN)= 5.5 V,
IO = rated current, VI(ENx) = 0 V, VI(ENx) = Hi (unless otherwise noted)
power switch
PARAMETER
TEST CONDITIONS†
TPS2046 TPS2056
UNIT
PARAMETER
TEST
CONDITIONS†
MIN TYP MAX MIN TYP MAX
UNIT
VI(IN) = 5 V,
IO = 0.1 A TJ = 25°C, 80 95 80 95
Static drain-source on-state
resistance, 5-V operation VI(IN) = 5 V,
IO = 0.1 A TJ = 85°C, 90 120 90 120
VI(IN) = 5 V,
IO = 0.1 A TJ = 125°C, 100 135 100 135 mΩ
DS(on) VI(IN) = 3.3 V,
IO = 0.1 A TJ = 25°C, 85 105 85 105
Static drain-source on-state
resistance, 3.3-V operation VI(IN) = 3.3 V,
IO = 0.1 A TJ = 85°C, 100 135 100 135
VI(IN) = 3.3 V,
IO = 0.1 A TJ = 125°C, 115 150 115 150
Rise time out
p
ut
VI(IN) = 5.5 V,
CL = 1 µF, TJ = 25°C,
RL = 20 Ω2.5 2.5
ms
r
Rise
time
,
o
u
tp
u
t
VI(IN) = 2.7 V,
CL = 1 µF, TJ = 25°C,
RL = 20 Ω3 3
ms
Fall time out
p
ut
VI(IN) = 5.5 V,
CL = 1 µF, TJ = 25°C,
RL = 20 Ω4.4 4.4
ms
f
Fall
time
,
o
u
tp
u
t
VI(IN) = 2.7 V,
CL = 1 µF, TJ = 25°C,
RL = 20 Ω2.5 2.5
ms
†Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account separately.
enable input ENx or ENx
PARAMETER
TEST CONDITIONS
TPS2046 TPS2056
UNIT
PARAMETER
TEST
CONDITIONS
MIN TYP MAX MIN TYP MAX
UNIT
VIH High-level input voltage 2.7 V ≤ VI(IN) ≤ 5.5 V 2 2 V
VIL
Low level in
p
ut voltage
4.5 V ≤ VI(IN) ≤ 5.5 V 0.8 0.8 V
V
IL
Lo
w-
le
v
el
inp
u
t
v
oltage
2.7 V≤ VI(IN) ≤ 4.5 V 0.4 0.4
II
In
p
ut current
TPS2046 VI(ENx) = 0 V or VI(ENx) = VI(IN) –0.5 0.5
µA
I
I
Inp
u
t
c
u
rrent
TPS2056 VI(ENx) = VI(IN) or VI(ENx) = 0 V –0.5 0.5 µ
A
ton T urn-on time CL = 100 µF, RL = 20 Ω 20 20 ms
toff Turn-off time CL = 100 µF, RL = 20 Ω40 40
current limit
PARAMETER
TEST CONDITIONS†
TPS2046 TPS2056
UNIT
PARAMETER
TEST
CONDITIONS†
MIN TYP MAX MIN TYP MAX
UNIT
IOS Short-circuit output current VI(IN) = 5 V, OUT connected to GND,
Device enable into short circuit. 0.345 0.44 0.525 0.345 0.44 0.525 A
†Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account separately.
TPS2046, TPS2056
DUAL CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES
SLVS183 – APRIL 1999
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating junction temperature range, VI(IN)= 5.5 V,
IO = rated current, VI(ENx) = 0 V, VI(ENx) = Hi (unless otherwise noted) (continued)
supply current
PARAMETE
TEST CONDITIONS
TPS2046 TPS2056
UNIT
R
TEST
CONDITIONS
MIN TYP MAX MIN TYP MAX
UNIT
Su
pp
ly
TJ = 25°C
0.015 1
Su ly
current, No Load VI(ENx) = VI(IN) –40°C ≤ TJ ≤ 125°C
10
µA
,
low-level
tt
on OUTx
VI(EN ) =0V
TJ = 25°C
0.015 1 µ
A
output
V
I(ENx) =
0
V
–40°C ≤ TJ ≤ 125°C
10
Su
pp
ly
V0V
TJ = 25°C
80 100
Su ly
current, No Load
V
I(ENx) =
0
V
–40°C ≤ TJ ≤ 125°C
100
µA
,
high-level
tt
on OUTx
VI(EN ) =V
I(IN)
TJ = 25°C
80 100 µ
A
output
V
I(ENx) =
V
I(IN) –40°C ≤ TJ ≤ 125°C
100
Leakage OUTx
connected
VI(ENx) = VI(IN) –40°C ≤ TJ ≤ 125°C TPS2046 100
µA
g
current connec
t
e
d
to ground VI(ENx) = 0 V –40°C ≤ TJ ≤ 125°C TPS2056 100 µ
A
Reverse
leakage
IN = high VI(ENx) = 0 V
TJ=25
°
C
TPS2046 0.3
µA
l
ea
k
age
current
g
impedance VI(ENx) = Hi
T
J =
25°C
TPS2056 0.3 µ
A
undervoltage lockout
PARAMETER
TEST CONDITIONS
TPS2046 TPS2056
UNIT
PARAMETER
TEST
CONDITIONS
MIN TYP MAX MIN TYP MAX
UNIT
Low-level input voltage 2 2.5 2 2.5 V
Hysteresis TJ = 25°C 100 100 mV
overcurrent OCx
PARAMETER
TEST CONDITIONS
TPS2046 TPS2056
UNIT
PARAMETER
TEST
CONDITIONS
MIN TYP MAX MIN TYP MAX
UNIT
Sink current†VO = 5 V 10 10 mA
Output low voltage IO = 5 mA, VOL(OCx)0.5 0.5 V
Off-state current†VO = 5 V, VO = 3.3 V 1 1 µA
†Specified by design, not production tested.
TPS2046, TPS2056
DUAL CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES
SLVS183 – APRIL 1999
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
RL CL
OUTx
trtf
90% 90%
10%
10%
50% 50%
90%
10%
VO(OUTx)
VI(ENx)
VO(OUTx)
VOLTAGE WAVEFORMS
TEST CIRCUIT
ton toff
50% 50%
90%
10%
VI(ENx)
VO(OUTx)
ton toff
Figure 1. Test Circuit and Voltage Waveforms
Figure 2. Turnon Delay and Rise Time
with 0.1-µF Load Figure 3. Turnoff Delay and Fall Time
with 0.1-µF Load
VO(OUTx)
(2 V/div)
0123456
t – Time – ms 78910
VI(IN) = 5 V
TA = 25°C
CL = 0.1 µF
VI(ENx)
(5 V/div)
0 1000 2000 3000
t – Time – ms 4000 5000
VI(IN) = 5 V
TA = 25°C
CL = 0.1 µF
VI(ENx)
(5 V/div)
VO(OUTx)
(2 V/div)
TPS2046, TPS2056
DUAL CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES
SLVS183 – APRIL 1999
8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
Figure 4. Turnon Delay and Rise Time
with 1-µF Load Figure 5. Turnoff Delay and Fall Time
with 1-µF Load
0123456
t – Time – ms 78910
VI(ENx)
(5 V/div)
VO(OUTx)
(2 V/div)
VI(IN) = 5 V
TA = 25°C
CL = 1 µF
RL = 20 Ω
0 2 4 6 8 10 12
t – Time – ms 14 16 18 20
VI(IN) = 5 V
TA = 25°C
CL = 1 µF
RL = 20 Ω
VI(ENx)
(5 V/div)
VO(OUTx)
(2 V/div)
Figure 6. TPS2046, Short-Circuit Current,
Device Enabled into Short
0123456
t – Time – ms 78910
IO(OUTx)
(0.2 A/div)
VI(IN) = 5 V
TA = 25°C
VI(ENx)
(5 V/div)
Figure 7. TPS2046, Threshold Trip Current
with Ramped Load on Enabled Device
0102030405060
t – Time – ms 70 80 90 100
IO(OUTx)
(0.5 A/div)
VI(IN) = 5 V
TA = 25°C
VO(OUTx)
(2 V/div)
TPS2046, TPS2056
DUAL CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES
SLVS183 – APRIL 1999
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
Figure 8. Inrush Current with 220-µF, 100-µF
and 47-µF Load Capacitance Figure 9. Ramped Load on Enabled Device
100 µF
220 µF
47 µF
0 2 4 6 8 10 12
t – Time – ms 14 16 18 20
VI(IN) = 5 V
TA = 25°C
RL = 20 Ω
VI(ENx)
(5 V/div)
IO(OUTx)
(0.2 A/div) VI(IN) = 5 V
TA = 25°C
0 20 40 60 80 100 120
t – Time – ms 140 160 180 200
VO(OCx)
(5 V/div)
IO(OUTx)
(0.5 A/div)
Figure 10. 4-Ω Load Connected
to Enabled Device
IO(OUTx)
(0.5 A/div)
VI(IN) = 5 V
TA = 25°C
0 200 400 600 800 1000
VO(OCx)
(5 V/div)
t – Time – µsFigure 11. 1-Ω Load Connected
to Enabled Device
VI(IN) = 5 V
TA = 25°C
0 200 400 600 800 1000
t – Time – µs
IO(OUTx)
(0.5 A/div)
VO(OCx)
(5 V/div)
TPS2046, TPS2056
DUAL CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES
SLVS183 – APRIL 1999
10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 12
4.5
4
3.5
32.5 3 3.5 4 4.5
Turnon Delay – ms
5
5.5
TURNON DELAY
vs
INPUT VOLTAGE
6
5 5.5 6
VI – Input Voltage – V
CL = 1 µF
RL = 20 Ω
TA = 25°C
Figure 13
15
13
9
72.5 3 3.5 4 4.5
Turnoff Delay – ms
TURNOFF DELAY
vs
INPUT VOLTAGE
5 5.5 6
11
VI – Input Voltage – V
CL = 1 µF
RL = 20 Ω
TA = 25°C
Figure 14
2.5
2.4
2.3 0 0.05 0.1 0.15 0.2 0.25
– Rise Time – ms
2.6
RISE TIME
vs
LOAD CURRENT
2.7
0.3 0.35 0.4
tr
IL – Load Current – A
VI (IN) = 5 V
TA = 25°C
Figure 15
2.75
2.7
2.65 0 0.05 0.1 0.15 0.2 0.25
– Fall Time – ms
2.8
FALL TIME
vs
LOAD CURRENT
2.85
0.3 0.35 0.4
tf
IL – Load Current – A
VI (IN) = 5 V
TA = 25°C
TPS2046, TPS2056
DUAL CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES
SLVS183 – APRIL 1999
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 16
140
120
100
–50 –25 0 25 50
– Supply Current, Output Enabled –
160
180
SUPPLY CURRENT, OUTPUT ENABLED
vs
JUNCTION TEMPERATURE
200
75 100 125 150
Aµ
TJ – Junction Temperature – °C
VI(IN) = 5.5 V
VI(IN) = 5 V
VI(IN) = 4 V
VI(IN) = 3.3 V
VI(IN) = 2.7 V
II(IN)
Figure 17
1000
600
200
–200
–50 –25 0 25 50 75
1400
1800
SUPPLY CURRENT, OUTPUT DISABLED
vs
JUNCTION TEMPERATURE
2000
100 125 150
1600
1200
800
400
0
– Supply Current, Output Disabled – nA
II(IN)
TJ – Junction Temperature – °C
VI(IN) = 5.5 V
VI(IN) = 5 V
VI(IN) = 4 V
VI(IN) = 2.7 V
Figure 18
140
120
1002.5 3 3.5 4 4.5
– Supply Current, Output Enabled –
160
180
SUPPLY CURRENT, OUTPUT ENABLED
vs
INPUT VOLTAGE
200
5 5.5 6
II(IN) Aµ
VI – Input Voltage – V
TJ = –40°C
TJ = 125°C
TJ = 85°C
TJ = 25°C
TJ = 0°C
Figure 19
800
400
0
–4002.5 3 3.5 4 4.5
1200
1600
SUPPLY CURRENT, OUTPUT DISABLED
vs
INPUT VOLTAGE
2000
5 5.5 6
– Supply Current, Output Disabled – nA
II(IN)
VI – Input Voltage – V
TJ = –40°C
TJ = 125°C
TJ = 85°CTJ = 25°C
TJ = 0°C
TPS2046, TPS2056
DUAL CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES
SLVS183 – APRIL 1999
12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 20
100
75
50
–50 –25 0 25 50 75
– Static Drain-Source On-State Resistance – m
125
150
STATIC DRAIN-SOURCE ON-STATE RESISTANCE
vs
JUNCTION TEMPERATURE
175
100 125 150
Ω
rDS(on)
TJ – Junction Temperature – °C
VI(IN) = 5 V
VI(IN) = 4.5 V
VI(IN) = 3.3 V
VI(IN) = 2.7 V
IO = 0.25 A
Figure 21
100
75
502.5 3 3.5 4 4.5
125
150
STATIC DRAIN-SOURCE ON-STATE RESISTANCE
vs
INPUT VOLTAGE
175
5 5.5 6
– Static Drain-Source On-State Resistance – mΩ
rDS(on)
VI – Input Voltage – V
TJ = –40°C
TJ = 125°C
TJ = 85°C
TJ = 25°C
TJ = 0°C
IO = 0.25 A
Figure 22
VI(IN) = 5 V
VI(IN) = 2.7 V
VI(IN) = 4.5 V
VI(IN) = 3.3 V
25
15
00.1 0.14 0.18
– Input-To-Output Voltage – mV
40
INPUT-TO-OUTPUT VOLTAGE
vs
LOAD CURRENT
45
0.22 0.3
VI(IN) –VO(OUTx)
IL – Load Current – A
35
30
20
10
5
0.26
TA = 25°C
Figure 23
TJ = –40°C
TJ = 25°C
TJ = 125°C
390
3502.5 3 3.5 4
– Short-circuit Output Current – mA
450
SHORT-CURCUIT OUTPUT CURRENT
vs
INPUT VOLTAGE
490
4.5 5 5.5
IOS
VI – Input Voltage – V
470
430
410
370
TPS2046, TPS2056
DUAL CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES
SLVS183 – APRIL 1999
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 24
0.69
0.67
0.652.5 3 3.5 4
Threshold Trip Current – A
0.71
THRESHOLD TRIP CURRENT
vs
INPUT VOLTAGE
0.73
4.5 5 65.5
VI – Input Voltage – V
TA = 25°C
Load Ramp = 1 A/10 ms
Figure 25
420
405
–50 –25 0 25 50
435
SHORTCIRCUIT OUTPUT CURRENT
vs
JUNCTION TEMPERATURE
450
75 100 125
TJ – Junction Temperature – °C
– Short-circuit Output Current – mA
IOS
VI(IN) = 5 V
VI(IN) = 4 V
VI(IN) = 2.7 V
445
440
430
425
415
410
Figure 26
2.2
2.1
2
–50 –25 0 25 50 75
UVLO – Undervoltage Lockout – V
2.3
2.4
UNDERVOLTAGE LOCKOUT
vs
JUNCTION TEMPERATURE
2.5
100 125 150
TJ – Junction Temperature – °C
Start Threshold
Stop Threshold
Figure 27
250
100
002 4 6
Current Limit Response –
350
Peak Current – A
CURRENT-LIMIT RESPONSE
vs
PEAK CURRENT
500
810
sµ
VI(INx) = 5 V
TA = 25°C
TPS2046, TPS2056
DUAL CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES
SLVS183 – APRIL 1999
14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 28
7
5.5
40246
Overcurrent OCx Time –
8.5
Peak Current – A
OVERCURRENT (OCx) RESPONSE TIME
vs
PEAK CURRENT
10
810
sµ
VI(IN) = 5 V
TA = 25°C
APPLICATION INFORMATION
IN
OC1
EN1
OC2
EN2 GND
0.1 µF
2
8
3
5
4
7
6
0.1 µF 22 µF
0.1 µF 22 µF
Load
Load
1
OUT1
OUT2
TPS2046
Power Supply
2.7 V to 5.5 V
Figure 29. Typical Application
power-supply considerations
A 0.01-µF to 0.1-µF ceramic bypass capacitor between IN and GND, close to the device, is recommended.
Placing a high-value electrolytic capacitor on the output pin(s) is recommended when the output load is heavy.
This precaution reduces power-supply transients that may cause ringing on the input. Additionally, bypassing
the output with a 0.01-µF to 0.1-µF ceramic capacitor improves the immunity of the device to short-circuit
transients.
TPS2046, TPS2056
DUAL CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES
SLVS183 – APRIL 1999
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
overcurrent
A sense FET is employed to check for overcurrent conditions. Unlike current-sense resistors, sense FETs do
not increase the series resistance of the current path. When an overcurrent condition is detected, the device
maintains a constant output current and reduces the output voltage accordingly. Complete shutdown occurs
only if the fault is present long enough to activate thermal limiting.
Three possible overload conditions can occur. In the first condition, the output has been shorted before the
device is enabled or before VI(IN) has been applied (see Figure 6). The TPS2046 and TPS2056 sense the short
and immediately switch into a constant-current output.
In the second condition, the short occurs while the device is enabled. At the instant the short occurs, very high
currents may flow for a short time before the current-limit circuit can react. After the current-limit circuit has
tripped (reached the overcurrent trip threshhold) the device switches into constant-current mode.
In the third condition, the load has been gradually increased beyond the recommended operating current. The
current is permitted to rise until the current-limit threshold is reached or until the thermal limit of the device is
exceeded (see Figure 7). The TPS2046 and TPS2056 are capable of delivering current up to the current-limit
threshold without damaging the device. Once the threshold has been reached, the device switches into its
constant-current mode.
OCx response
The OCx open-drain output is asserted (active low) when an overcurrent or overtemperature condition is
encountered. The output will remain asserted until the overcurrent or overtemperature condition is removed.
Connecting a heavy capacitive load to an enabled device can cause momentary false overcurrent reporting from
the inrush current flowing through the device, charging the downstream capacitor . An RC filter (see Figure 30)
can be connected to the OCx pin to reduce false overcurrent reporting caused by hot-plug switching events or
extremely high capacitive loads. Using low-ESR electrolytic capacitors on the output lowers the inrush current
flow through the device during hot-plug events by providing a low impedance energy source, thereby reducing
erroneous overcurrent reporting.
GND
IN
EN1
EN2
OC1
OC2
OUT1
OUT2
TPS2046
GND
IN
EN1
EN2
OC1
OC2
OUT1
OUT2
TPS2046
Rpullup
V+
Rfilter
Cfilter
To USB
Controller
V+
Rpullup
Figure 30. Typical Circuits for OC Pin and RC Filter for Damping Inrush OC Responses
TPS2046, TPS2056
DUAL CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES
SLVS183 – APRIL 1999
16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
power dissipation and junction temperature
The low on-resistance on the n-channel MOSFET allows small surface-mount packages, such as SOIC, to pass
large currents. The thermal resistances of these packages are high compared to that of power packages; it is
good design practice to check power dissipation and junction temperature. The first step is to find rDS(on) at the
input voltage and operating temperature. As an initial estimate, use the highest operating ambient temperature
of interest and read rDS(on) from Figure 21. Next, calculate the power dissipation using:
PD
+
rDS
(
on
)
I
2
Finally, calculate the junction temperature:
TJ
+
PD
R
q
JA
)
TA
Where: TA = Ambient Temperature °C
RθJA = Thermal resistance SOIC = 172°C/W, PDIP = 106°C/W
Compare the calculated junction temperature with the initial estimate. If they do not agree within a few degrees,
repeat the calculation, using the calculated value as the new estimate. Two or three iterations are generally
sufficient to get a reasonable answer.
thermal protection
Thermal protection prevents damage to the IC when heavy-overload or short-circuit faults are present for
extended periods of time. The faults force the TPS2046 and TPS2056 into constant current mode, which causes
the voltage across the high-side switch to increase; under short-circuit conditions, the voltage across the switch
is equal to the input voltage. The increased dissipation causes the junction temperature to rise to high levels.
The protection circuit senses the junction temperature of the switch and shuts it off. Hysteresis is built into the
thermal sense circuit, and after the device has cooled approximately 20 degrees, the switch turns back on. The
switch continues to cycle in this manner until the load fault or input power is removed.
The TPS2046 and TPS2056 implement a dual thermal trip to allow fully independent operation of the power
distribution switches. In an overcurrent or short-circuit condition the junction temperature will rise. Once the die
temperature rises to approximately 140°C, the internal thermal sense circuitry checks which power switch is
in an overcurrent condition and turns that power switch off, thus isolating the fault without interrupting operation
of the adjacent power switch. Should the die temperature exceed the first thermal trip point of 140°C and reach
160°C, both switches turn off. The OC open-drain output is asserted (active low) when overtemperature or
overcurrent occurs.
undervoltage lockout (UVLO)
An undervoltage lockout ensures that the power switch is in the off state at power up. Whenever the input voltage
falls below approximately 2 V, the power switch will be quickly turned off. This facilitates the design of
hot-insertion systems where it is not possible to turn off the power switch before input power is removed. The
UVLO will also keep the switch from being turned on until the power supply has reached at least 2 V, even if
the switch is enabled. Upon reinsertion, the power switch will be turned on with a controlled rise time to reduce
EMI and voltage overshoots.
TPS2046, TPS2056
DUAL CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES
SLVS183 – APRIL 1999
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
Universal Serial Bus (USB) applications
The Universal Serial Bus (USB) interface is a 12-Mb/s, or 1.5-Mb/s, multiplexed serial bus designed for
low-to-medium bandwidth PC peripherals (e.g., keyboards, printers, scanners, and mice). The four-wire USB
interface is conceived for dynamic attach-detach (hot plug-unplug) of peripherals. Two lines are provided for
differential data, and two lines are provided for 5-V power distribution.
USB data is a 3.3-V level signal, but power is distributed at 5 V to allow for voltage drops in cases where power
is distributed through more than one hub across long cables. Each function must provide its own regulated 3.3 V
from the 5-V input or its own internal power supply.
The USB specification defines the following five classes of devices, each differentiated by power-consumption
requirements:
D
Hosts/self-powered hubs (SPH)
D
Bus-powered hubs (BPH)
D
Low-power, bus-powered functions
D
High-power, bus-powered functions
D
Self-powered functions
Self-powered and bus-powered hubs distribute data and power to downstream functions. The TPS2046 and
TPS2056 can provide power-distribution solutions for many of these classes of devices.
bus-powered hubs
Bus-powered hubs obtain all power from upstream ports and often contain an embedded function. The hubs
are required to power up with less than one unit load. The BPH usually has one embedded function, and power
is always available to the controller of the hub. If the embedded function and hub require more than 100 mA
on power up, the power to the embedded function may need to be kept off until enumeration is completed. This
can be accomplished by removing power or by shutting off the clock to the embedded function. Power switching
the embedded function is not necessary if the aggregate power draw for the function and controller is less than
one unit load. The total current drawn by the bus-powered device is the sum of the current to the controller , the
embedded function, and the downstream ports, and it is limited to 500 mA from an upstream port.
low-power bus-powered functions and high-power bus-powered functions
Both low-power and high-power bus-powered functions obtain all power from upstream ports; low-power
functions always draw less than 100 mA, and high-power functions must draw less than 100 mA at power up
and can draw up to 500 mA after enumeration. If the load of the function is more than the parallel combination
of 44 Ω and 10 µF at power up, the device must implement inrush current limiting (see Figure 31).
TPS2046, TPS2056
DUAL CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES
SLVS183 – APRIL 1999
18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
IN
OC1
EN1
OC2
EN2 GND
0.1 µF2
8
3
5
4
7
6
0.1 µF 10 µF
0.1 µF 10 µF
GND
1
OUT1
OUT2
TPS2046
Power Supply
D+
D–
VBUS
Internal
Function
USB
Control
3.3 V
10 µFInternal
Function
Figure 31. High-Power Bus-Powered Function
USB power-distribution requirements
USB can be implemented in several ways, and, regardless of the type of USB device being developed, several
power distribution features must be implemented.
D
Bus-Powered Hubs must:
– Enable/disable power to downstream ports
– Power up at <100 mA
– Limit inrush current (<44 Ω and 10 µF)
D
Functions must:
– Limit inrush currents
– Power up at <100 mA
The feature set of the TPS2046 and TPS2056 allows them to meet each of these requirements. The integrated
current-limiting and overcurrent reporting is required by hosts and self-powered hubs. The logic-level enable
and controlled rise times meet the need of both input and output ports on bus-power hubs, as well as the input
ports for bus-power functions (see Figure 32).
TPS2046, TPS2056
DUAL CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES
SLVS183 – APRIL 1999
19
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
Figure 32. Bus-Powered Hub Implementation
DP1
DM1
DP2
DM2
DP3
DM3
DP4
PWRON1
OVRCUR1
PWRON2
OVRCUR2
PWRON3
OVRCUR3
PWRON4
OVRCUR4
DM4
DP0
DM0
VCC
XTAL1
XTAL2
OCSOFF
SN75240
EN1
IN
OC1
OUT1
D +
D –
5 V
GND
D +
D –
5 V
D +
D –
5 V
D +
D –
5 V
48-MHz
Crystal
Downstream
Ports
TUSB2040
Hub Controller
TPS2046
Tuning
Circuit
A
BC
D
33 µF†
SN75240
A
BC
D
GND
GND
GND
33 µF†
33 µF†
33 µF†
D +
D –
Upstream
Port
SN75240
A
B
5 V
GND
C
D
1 µF
GND
Ferrite Beads
Ferrite Beads
Ferrite Beads
Ferrite Beads
BUSPWR
GANGED
IN
GND
3.3 V
4.7 µF
0.1 µF
4.7 µF
EN2
OC2
OUT2
EN1
IN
OC1
OUT1
TPS2046
EN2
OC2
OUT2
0.1 µF
0.1 µF
GND
†USB rev 1.1 requires 120 µF per hub.
TPS76333
TPS2046, TPS2056
DUAL CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES
SLVS183 – APRIL 1999
20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
generic hot-plug applications (see Figure 33)
In many applications it may be necessary to remove modules or pc boards while the main unit is still operating.
These are considered hot-plug applications. Such implementations require the control of current surges seen
by the main power supply and the card being inserted. The most effective way to control these surges is to limit
and slowly ramp the current and voltage being applied to the card, similar to the way in which a power supply
normally turns on. Due to the controlled rise times and fall times of the TPS2046 and TPS2056, these devices
can be used to provide a softer start-up to devices being hot-plugged into a powered system. The UVLO feature
of the TPS2046 and TPS2056 also ensures the switch will be off after the card has been removed, and the switch
will be off during the next insertion. The UVLO feature guarantees a soft start with a controlled rise time for every
insertion of the card or module.
Power
Supply Block of
Circuitry
TPS2046
GND
IN
EN1
EN2
OC1
OUT1
OUT2
OC2
0.1 µF
1000 µF
Optimum
2.7 V to 5.5 V
PC Board
Overcurrent Response
Block of
Circuitry
Figure 33. Typical Hot-Plug Implementation
By placing the TPS2046 and TPS2056 between the VCC input and the rest of the circuitry, the input power will
reach these devices first after insertion. The typical rise time of the switch is approximately 2.5 ms, providng
a slow voltage ramp at the output of the device. This implementaion controls system surge currents and provides
a hot-plugging mechanism for any device.
PACKAGE OPTION ADDENDUM
www.ti.com 28-Aug-2010
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TPS2046D NRND SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Replaced by TPS2046BD
TPS2046DG4 NRND SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Samples Not Available
TPS2046DR NRND SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Samples Not Available
TPS2046DRG4 NRND SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Samples Not Available
TPS2046P NRND PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type Samples Not Available
TPS2046PE4 NRND PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type Samples Not Available
TPS2056D NRND SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Replaced by TPS2056AD
TPS2056DG4 NRND SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Samples Not Available
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
PACKAGE OPTION ADDENDUM
www.ti.com 28-Aug-2010
Addendum-Page 2
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS2046DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 23-Jul-2010
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS2046DR SOIC D 8 2500 340.5 338.1 20.6
PACKAGE MATERIALS INFORMATION
www.ti.com 23-Jul-2010
Pack Materials-Page 2
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