Rev. 0.3 10/12 Copyright © 2012 by Silicon Labs Si53301/4-EVB
Si53301/4-EVB
Si53301/4 EVALUATION BOARD USER’S GUIDE
Description
The Si53301/4-EVB is used for evaluation of the
Si533xx family of low-jitter clock buffers/level
translators. As shipped from the factory, this evaluation
board has the Si53301 device installed. The entire
Si533xx family of buf fers use th e same input cir cuits an d
output drivers, and all have the same jitter
specifications. Thus, this evaluation board can be used
to evaluate any Si533xx device. The Si53301 provides
pin-selectable clock output signal format, drive strength
control, optional clock division, and per-bank output
enable. The Si53304 provides pin-selectable clock
output signal format, drive strength control, and
individual output enable pins for each clock output.
EVB Features
Features of this evaluation board include:
Power supply connections for VDD, VDDOA and
VDDOB, GND
Jumpers for selection o f ou tput signa l form at, o utput
enable, input clock select and output divider
Jumpers to allo w self biasing of CMOS sing le-ended
inputs
SMA connectors for easy access to test and
evaluate the Si53301
Figure 1. Si53301/4 Evaluation Board
Si53301/4-EVB
2 Rev. 0.3
1. Supply Voltage
Three supply voltages are required: VDD, VDDOA, and VDDOB. These supply voltages are applied at the two
bottom corners of the evaluation board via J18 and J20, which are located on the bottom side of the evaluation
board and function as standof fs a s well as input s for the supp ly voltage s. Note that the J18 a nd J20 have silkscr een
on the top side of the evaluation board that identifies the J18 and J20 inputs. VDD powers the input buffers, mux,
and dividers. VDDOA and VDDOB provide power for the output drivers on CLK0,1,2 and CLK3,4,5, respectively.
The three input power supply voltages should all have a common external ground. A separate ground wire should
be run from the common power ground to the ground on both J18 and J20. VDD, VDDOA, and VDDOB can be
1.8 V ±5%, 2.5 V ±5%, or 3.3 V ±10%. VDDOA,B need to be set according to the output driver format as shown in
Table 1.
2. Clock Inputs
This evaluation board accepts differential clock inputs on SMA connectors labeled CLK0,CLK0B as well as
CLK1,CLK1B. A single-ended CMOS input with the same voltage swing as the VDD voltage may also be applied
to either CLK 0 and/o r CLK1. See “ 4.4. Jumpe rs P1 a nd P2” for m ore in form ation . The c loc k input t hat is active is
selected by JP1, which controls the CLK_SEL input pin 8.
3. Clock Outputs
Six clock outputs are presen t at the SMA connectors labele d Q0, 1, 2, 3, 4, 5. As built and delivered, the evaluation
board will support differ ential outputs that are LVDS, CML, or low-power LVPECL without any component changes.
S t andard LVPECL and HCSL outputs require output resistor and/or cap acitor changes. See the t able in Figure 3 for
these changes.
4. Jumpers
This evaluation board can be used to evaluate a Si53301 or Si53304; however, the Si53301 is installed on the
evaluation board. Refer to Figures 1, 2, and 3 and Tables 1 and 2 as needed for the following discussion about the
jumpers. Many of the inputs are shown on the evaluation board silkscreen a nd schemati c with du al names, such as
name1(name2), where name1 is the input pin name for the Si53301 and name2 is the input pin name for the
Si53304. In two cases, the input pin of the Si53301 is a no-connect (NC) when the Si53304 is a functional input.
4.1. Jumpers JP2 and JP3
Jumpers JP2 and JP3 set the level to SFOUTA1 and SFOUTA0 on input pins 2 and 3, respectively. Jumpers JP4
and JP5 set the level to SFOUTB1 and SFOUTB0 on input pins 22 and 23, respectively. These inputs have three
valid input levels: Ground, VDD, and Open. See Table 1.
4.2. Jumpers JP1 and JP6
For the Si53301 device, Jumper s JP1 and JP6 con trol the ou tput dividers for bank A (Q0,1,2) and bank B (Q3,4,5),
respectively. For the Si53304 device, Jumpers JP1 and JP6 control the enabling of output clocks Q1 and Q5,
respectively. See Table 2 for the settings of these jumpers.
4.3. Jumpers P3, P4, P5, P6, and P7
For the Si53301, these jumper s control CLK_SEL, OEA, and OEB. OEA is the enable fo r output clocks Q0,1,2, and
OEB is the enable for output clocks Q3,4,5. For the Si53304, these jumpers control CLK_SEL, OE1, OE2, OE3,
and OE4. See Table 3 for more information.
4.4. Jumpers P 1 and P 2
Jumpers P1 and P2 should be left open unless a single-ended input is applied to the CLK0 or CLK1 input. When a
jumper is placed across P1 (P2), the voltage from the VREF pin 17 is applied to the CLK0B (CLK1B) input pin so
that a CMOS input with a voltage swing of VDD (pin7) volts can be applied to the CLK0 (CLK1) pin. In addition,
some resistor and capacitor changes (described in the Figure 3 schematic near P1 and P2) must be made to the
evaluation board .
Si53301/4-EVB
Rev. 0.3 3
Table 1. JP2, JP3, JP4, and JP5 Output Signal Format
SFOUTX11SFOUTX01VDDOX=3.3V VDDOX=2.5V VDDOX=1.8V
Open2Open2LVPECL LVPECL N/A
Ground Ground LVDS LVDS LVDS
Ground VDD LVCMOS, 24 mA drive LVCMOS, 18 mA drive LVCMOS, 12 mA drive
VDD Ground LVCMOS, 18 mA drive LVCMOS, 12 mA drive LVCMOS, 9 mA drive
VDD VDD LVCMOS, 12 mA drive LVCMOS, 9 mA drive LVCMOS, 6 mA drive
Open2Ground LVCMOS, 6 mA drive LVCMOS, 4 mA drive LVCMOS, 2 mA drive
Open2VDD LVPECL Low power LVPECL Low power N/A
Ground Open2CML CML CML
VDD Open2HCSL HCSL HCSL
Notes:
1. Ground means short center pin to ground pin. VDD means short center pin to VD D pin.
Open means leave center pin open.
2. SFOUTX are three-level input pins.
Table 2. Jumper Selections for JP1,6
Si53301 Si53304
Signal* Jumper Jumper Position Jumper Position
Ground Open VDD Ground Open VDD
DIVA(OE1) JP1 /2 /1 /4 Q1 Disabled Q1 Enabled Q1 Enabled
DIVB(OE5) JP6 /2 /1 /4 Q5 Disabled Q5 Enabled Q5 Enabled
*Note: The signal name in parentheses applies to the Si53304 device, which is not installed from the factory.
Table 3. Jumper Selections for P3,4,5,6,7
Si53301 Si53304
Signal* Jumper Jumper Position Jumper Position
Shorted Open Shorted Open
CLK_SEL P3 CLK0 Selected CLK1 Selected CLK0 Selected CLK1 Selected
NC(OE1) P4 NA NA Q1 Disabled Q1 Enabled
OEA(OE2) P5 Q0,1,2 Disabled Q0,1,2 Enabled Q2 Disabled Q2 Enabled
OEB(OE3) P6 Q3,4,5 Disabled Q3,4,5 Enabled Q3 Disabled Q3 Enabled
NC(OE4) P7 NA NA Q4 Disabled Q4 Enabled
*Note: The signal name in parentheses applies to the Si53304 device, which is not installed from the factory.
Si53301/4-EVB
4 Rev. 0.3
VDD
GND
VDDOB
VDDOA
For CMOS input on CLK0/J13
Replace C13 with a short
Remove R25
Short pin 1 to pin 2 of P1
For CMOS input on CLK1/J15
Replace C19 with a short
Remove R28
Short pin 1 to pin 2 of P2
CLK0
CLK0B
CLK1
CLK1B
DIVA(OE0)
NC(OE1)
OEA(OE2)
OEB(OE3)
NC(OE4)
DIVB(OE5)
SFOUTA0
SFOUTA1
SFOUTB0
SFOUTB1
CLK_SEL
VREF
SFOUTA1
SFOUTA0
SFOUTB0
SFOUTB1
NC(OE4)
OEB(OE3)
OEA(OE2)
NC(OE1)
CLK1B
CLK1
VREF
VREF
DIVA(OE0)
DIVB(OE5)
CLK0
CLK0B
CLK_SEL
VDD
VDDOA
VDDOB
VDD
VDDOA
VDDOB
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
Q0
Q0B
Q1
Q1B
Q2
Q2B
Q3
Q3B
Q4
Q4B
Q5
R31
1K
J19
HEADER 1x1
1
J15
SMA
R36
1K
NI
R29
1K
P3
JUMPER
CLK_SEL
1 2
J16
SMA
J21
HEADER 1x1
1
P1
JUMPER
VREF
1 2
C18
1.0uF
C22
0.1uF
R26
1K
P5
JUMPER
OEA(OE2)
1 2
P7
JUMPER
NC(OE4)
1 2
U1
Si53301(Si53304)
VDD 7
CLK0
10
CLK0B
11
DIVA(OE0)
1
CLK1B
15
EPAD
33
Q0 5
Q0B 4
Q1 32
Q1B 31
Q3 28
Q3B 27
Q2B 29
Q2 30
VDDOA 18
VDDOB 19
CLK1
14
NC(OE1)
9
OEA(OE2)
12
OEB(OE3)
13
NC(OE4)
16
DIVB(OE5)
24
Q4 26
Q4B 25
Q5 21
Q5B 20
GND
6
VREF 17
SFOUTA0
3
SFOUTA1
2
SFOUTB0
22
SFOUTB1
23
CLK_SEL
8
JP2
HEADER 1x3
SFOUTA1
1
2
3
C17
1.0uF
C16
1.0uF
C130.1uF
R33
1K
NI
R30
49.9 JP3
HEADER 1x3
SFOUTA0
1
2
3
R28
49.9
R35
1K
NI
R27
49.9
C150.1uF
FB1
330 Ohm
J18
CONN TRBLK 2
1
2
C24
10uF
C25
10uF
C14
0.1uF
JP4
HEADER 1x3
SFOUTB0
1
2
3
JP1
HEADER 1x3
DIVA(OE0)
1
2
3
J14
SMA
P4
JUMPER
NC(OE1)
1 2
P6
JUMPER
OEB(OE3)
1 2
C20
0.1uF
C23
10uF
J20
CONN TRBLK 2
1
2
JP5
HEADER 1x3
SFOUTB1
1
2
3
P2
JUMPER
VREF
1 2
J13
SMA
R32
1K
NI
JP6
HEADER 1x3
DIVB(OE5)
1
2
3
R37
1K
NI
C210.1uF
R34
1K
NI
R25
49.9
FB3
330 Ohm
C19 0.1uF
J17
HEADER 1x1
1
FB2
330 Ohm
Figure 2. Schematic Main
Si53301/4-EVB
Rev. 0.3 5
Component Configurations For
Various Output Formats
R1, R2, R5,
R6, R9, R10,
R13,R14, R17,
R18,R21, R22
C1, C2, C3,
C4, C5, C6,
C7, C8, C9,
C10,C11,C12
R3, R4, R7,
R8, R11,R12,
R15,R16,R19,
R20,R23,R24
HCSL SAME BD 0 OHMS 0 NP
STANDARD LVPECL
0.1 uF 0 NPLOW POWER LVPECL
0.1 uF 0 See note
00.1 uF/0 ohmsLVDS AC/DC NP
00.1 uFCML NP
Note : 90 for VDD = 2.5V; 120 for VDD = 3.3V
42.20 OHMSHCSL ADD-IN 86.6
Output Format
Q0
Q1
/Q0
/Q1
Q2 /Q2
Q3
/Q3
Q4 /Q4
Q5 /Q5
All resistors on this page are located very close to the Si533xx device, caps are located very close to the SMA's
CMOS 0 OHMS 0 NP
Q0
Q1
Q2
Q3
Q4
Q5
Q0B
Q1B
Q2B
Q4B
Q3B
Q5B
J8
SMA
J8
SMA
R5 0R5 0 C3 0.1uFC3 0.1uF
R15
120
NI
R15
120
NI
J3
SMA
J3
SMA
R11
120
NI
R11
120
NI
C1 0.1uFC1 0.1uF
R9 0R9 0
R7
120
NI
R7
120
NI
R1 0R1 0
R3
120
NI
R3
120
NI
J2
SMA
J2
SMA
C11 0.1uFC11 0.1uF
J11
SMA
J11
SMA R22 0R22 0
C5 0.1uFC5 0.1uF
C10 0.1uFC10 0.1uF
J5
SMA
J5
SMA
R14 0R14 0 C8 0.1uFC8 0.1uF
R18 0R18 0
J10
SMA
J10
SMA
J7
SMA
J7
SMA
R6 0R6 0
R4
120
NI
R4
120
NI
C4 0.1uFC4 0.1uF
R2 0R2 0 C2 0.1uFC2 0.1uF
R8
120
NI
R8
120
NI
J4
SMA
J4
SMA
J1
SMA
J1
SMA
R12
120
NI
R12
120
NI
R10 0R10 0
R16
120
NI
R16
120
NI
R20
120
NI
R20
120
NI
C12 0.1uFC12 0.1uF
R21 0R21 0
R24
120
NI
R24
120
NI
J12
SMA
J12
SMA
C6 0.1uFC6 0.1uF
R17 0R17 0 C9 0.1uFC9 0.1uF
R23
120
NI
R23
120
NI
C7 0.1uFC7 0.1uF
J9
SMA
J9
SMA
R19
120
NI
R19
120
NI
J6
SMA
J6
SMA
R13 0R13 0
Figure 3. Schematic Outputs
Si53301/4-EVB
6 Rev. 0.3
5. Bill of Materials
Table 4. Si53301/4-EVB Bill of Materials
Qty Ref Value Rating Voltage Tol Type PCB
Footprint Mfr Part # Mfr
19 C1, C2, C3, C4,
C5, C6, C7, C8,
C9, C10, C11,
C12, C13, C14,
C15, C19, C20,
C21, C22
0.1 µF 10 V ±10% X7R C0402 C0402X7R100-104K Venkel
3 C16, C17, C18 1.0 µF 6.3 V ±10% X5R C0402 C0402X5R6R3-105K Venkel
3 C23, C24, C25 10 µF 10 V ±20% X7R C1206 C1206X7R100-106M Venkel
3 FB1, FB2, FB3 330 1500 mA SMT L0805 BLM21PG331SN1 MuRata
16 J1, J2, J3, J4,
J5, J6, J7, J8,
J9, J10, J11,
J12, J13, J14,
J15, J16
SMA SMA SMA-EDGE-3 142-0701-801 Johnson
Components
3 J17, J19, J21 Header
1x1 Header CONN-1X1 TSW-101-14-T-S Samtec
2 J18, J20 CONN
TRBLK 2 24 A Term
Blk CONN-TB-
1711026 1711026 Phoenix
Contact
6 JP1, JP2, JP3,
JP4, JP5, JP6 Header
1x3 Header CONN-1X3 TSW-103-07-T-S Samtec
9 JS1, JS2, JS3,
JS4, JS5, JS6,
JS7, JS8, JS9
Jumper
Shunt Shunt N/A SNT-100-BK-T Samtec
2 MH1, MH2 Screw/
Standoff HDW MH-125NP NSS-4-4-01/2399 Various
7 P1, P2, P3, P4,
P5, P6, P7 Jumper Header CONN1X2 TSW-102-07-L-S Samtec
12 R1, R2, R5, R6,
R9, R10, R13,
R14, R17, R18,
R21, R22
0 1 A Thick-
Film R0402 CR0402-16W-000 Venkel
4 R25, R27, R28,
R30 49.9 1/16 W ±1% Thick-
Film R0402 CR0402-16W-49R9F Venkel
3 R26, R29, R31 1 k1/16 W ±5% Thick-
Film R0402 CR0402-16W-102J Venkel
1 U1 Si53301 Timing QFN32M5X5
P0.5 Si53301-A-GM SiLabs
Si53301/4-EVB
Rev. 0.3 7
Not-Installed Components
12 R3, R4, R7, R8,
R11, R12, R15,
R16, R19, R20,
R23, R24
120 1/16 W ±1% Thick-
Film R0402 CR0402-16W-1200F Venkel
6 R32, R33, R34,
R35, R36, R37 1k1/16 W ±5% Thick-
Film R0402 CR0402-16W-102J Venkel
Table 4. Si53301/4-EVB Bill of Materials (Continued)
Qty Ref Value Rating Voltage Tol Type PCB
Footprint Mfr Part # Mfr
Si53301/4-EVB
8 Rev. 0.3
DOCUMENT CHANGE LIST
Revision 0.1 to Revision 0.3
Comprehensive rewrite of previous revision.
Si53301/4-EVB
Rev. 0.3 9
NOTES:
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