Aptina Confidential and Proprietary MT9V034: 1/3-Inch Wide-VGA Digital Image Sensor Features 1/3-Inch Wide-VGA CMOS Digital Image Sensor MT9V034 Data Sheet For the latest data sheet revision, refer to Aptina's Web site: www.aptina.com Features Table 1: * Array format: Wide-VGA, active 752H x 480V (360,960 pixels) * Global shutter photodiode pixels; simultaneous integration and readout * Monochrome or color: NIR enhanced performance for use with non-visible NIR illumination * Readout modes: progressive or interlaced * Shutter efficiency: >99% * Simple two-wire serial interface * Real-time exposure context switching - dual register set * Register lock capability * Window size: User programmable to any smaller format (QVGA, CIF, QCIF). Data rate can be maintained independent of window size * Binning: 2 x 2 and 4 x 4 of the full resolution * ADC: On-chip, 10-bit column-parallel (option to operate in 12-bit to 10-bit companding mode) * Automatic controls: Auto exposure control (AEC) and auto gain control (AGC); variable regional and variable weight AEC/AGC * Support for four unique serial control register IDs to control multiple imagers on the same bus * Data output formats: - Single sensor mode: 10-bit parallel/stand-alone 8-bit or 10-bit serial LVDS - Stereo sensor mode: Interspersed 8-bit serial LVDS * High dynamic range (HDR) mode Parameter Value Optical format Active imager size 1/3-inch 4.51mm(H) x 2.88mm(V) 5.35mm diagonal 752H x 480V 6.0 x 6.0m Monochrome or color RGB Bayer pattern Global shutter 27 Mp/s 27 MHz 752 x 480 60 fps (at full resolution) 10-bit column-parallel 4.8 V/lux-sec (550nm) >55dB linear; >110dB in HDR mode 3.3V +0.3V (all supplies) <160mW at maximum data rate (LVDS disabled); 120W standby power at 3.3V -30C to +70C ambient 48-pin CLCC Active pixels Pixel size Color filter array Shutter type Maximum data rate master clock Full resolution Frame rate ADC resolution Responsivity Dynamic range Supply voltage Power consumption Operating temperature Packaging Ordering Information Table 2: Security High dynamic range imaging Unattended surveillance Stereo vision Video as input Machine vision Automation PDF:6981573426/Source: 7298095240 MT9V034_DS - Rev. D Pub. 5/12 EN Available Part Numbers Part Number Applications * * * * * * * Key Performance Parameters 1 Number of Pins Description MT9V034C12STM 48-pin CLCC (monochrome) MT9V034C12STC MT9V034C12STMD ES MT9V034C12STMH ES MT9V034C12STCD ES MT9V034C12STCH ES 48-pin 48-pin 48-pin 48-pin 48-pin CLCC (color) Monochrome demo kit Monochrome head board Color demo kit Color head board . (c)2008 Aptina Imaging Corporation All rights reserved. Aptina Confidential and Proprietary MT9V034: 1/3-Inch Wide-VGA Digital Image Sensor Table of Contents Table of Contents Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Pixel Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Pixel Array Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Color Device Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Pixel Binning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Interlaced Readout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Automatic Black Level Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Other Limiting Factors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Output Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Output Data Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Serial Bus Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Start Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Slave Address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Acknowledge Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 No-Acknowledge Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Stop Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Bus Idle State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Data Bit Transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Two-Wire Serial Interface Sample Read and Write Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 16-Bit Write Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 16-Bit Read Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 8-Bit Write Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 8-Bit Read Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Register Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Lock All Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Lock Only Read Mode Registers (R0x0D and R0x0E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Real-Time Context Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Shadowed Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Feature Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 Operational Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 Master Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 Simultaneous Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 Sequential Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 Snapshot Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Signal Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 On-Chip Biases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 ADC Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 V_Step Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 Chip Version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 Window Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 Blanking Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 Pixel Integration Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 Total Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 PDF:6981573426/Source: 7298095240 MT9V034_DS - Rev. D Pub. 5/12 EN 2 . (c)2008 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9V034: 1/3-Inch Wide-VGA Digital Image Sensor Table of Contents Changes to Integration Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 Exposure Indicator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 High Dynamic Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 ADC Companding Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 Gain Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 Changes to Gain Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 Analog Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 Digital Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 Black Level Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 Row-wise Noise Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 Automatic Gain Control and Automatic Exposure Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 Pixel Clock Speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 Hard Reset of Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 Soft Reset of Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 STANDBY Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 Monitor Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 Read Mode Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 Column Flip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 Row Flip. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 Pixel Binning. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 Row Binning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 Column Binning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 Interlaced Readout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 LINE_VALID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 LVDS Serial (Stand-Alone/Stereo) Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 LVDS Output Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 LVDS Enable and Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 LVDS Data Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 Propagation Delays for PIXCLK and Data Out Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 Propagation Delays for FRAME_VALID and LINE_VALID Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 Two-Wire Serial Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 Minimum Master Clock Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 Appendix A - Power-On Reset and Standby Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 PDF:6981573426/Source: 7298095240 MT9V034_DS - Rev. D Pub. 5/12 EN 3 . (c)2008 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9V034: 1/3-Inch Wide-VGA Digital Image Sensor List of Figures List of Figures Figure 1: Figure 2: Figure 3: Figure 4: Figure 5: Figure 6: Figure 7: Figure 8: Figure 9: Figure 10: Figure 11: Figure 12: Figure 13: Figure 14: Figure 15: Figure 16: Figure 17: Figure 18: Figure 19: Figure 20: Figure 21: Figure 22: Figure 23: Figure 24: Figure 25: Figure 26: Figure 27: Figure 28: Figure 29: Figure 30: Figure 31: Figure 32: Figure 33: Figure 34: Figure 35: Figure 36: Figure 37: Figure 38: Figure 39: Figure 40: Figure 41: Figure 42: Figure 43: Figure 44: Figure 45: Figure 46: Figure 47: Figure 48: Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 48-Pin CLCC Package Pinout Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Typical Configuration (Connection)--Parallel Output Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Pixel Array Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Pixel Color Pattern Detail (Top Right Corner) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Spatial Illustration of Image Readout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Timing Example of Pixel Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Row Timing and FRAME_VALID/LINE_VALID Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Timing Diagram Showing a Write to R0x09 with the Value 0x0284 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Timing Diagram Showing a Read from R0x09; Returned Value 0x0284 . . . . . . . . . . . . . . . . . . . . . . . . .17 Timing Diagram Showing a Bytewise Write to R0x09 with the Value 0x0284 . . . . . . . . . . . . . . . . . . . .18 Timing Diagram Showing a Bytewise Read from R0x09; Returned Value 0x0284 . . . . . . . . . . . . . . . .18 Simultaneous Master Mode Synchronization Waveforms #1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 Simultaneous Master Mode Synchronization Waveforms #2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 Sequential Master Mode Synchronization Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 Snapshot Mode Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 Snapshot Mode Frame Synchronization Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Slave Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Signal Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 Latency When Changing Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 Sequence of Control Voltages at the HDR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 Sequence of Voltages in a Piecewise Linear Pixel Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 12- to 10-Bit Companding Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 Latency of Analog Gain Change When AGC Is Disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 Tiled Sample . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 Black Level Calibration Flow Chart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 Controllable and Observable AEC/AGC Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 Readout of Six Pixels in Normal and Column Flip Output Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 Readout of Six Rows in Normal and Row Flip Output Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 Readout of 8 Pixels in Normal and Row Bin Output Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 Readout of 8 Pixels in Normal and Column Bin Output Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 Spatial Illustration of Interlaced Image Readout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 Different LINE_VALID Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 Serial Output Format for a 6x2 Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 LVDS Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 Propagation Delays for PIXCLK and Data Out Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 Propagation Delays for FRAME_VALID and LINE_VALID Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 Two-wire Serial Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 Serial Host Interface Start Condition Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 Serial Host Interface Stop Condition Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 Serial Host Interface Data Timing for Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 Serial Host Interface Data Timing for Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 Acknowledge Signal Timing After an 8-Bit WRITE to the Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 Acknowledge Signal Timing After an 8-Bit READ from the Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 Typical Quantum Efficiency - Color. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 Typical Quantum Efficiency - Monochrome . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 48-Pin CLCC Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 Power-up, Reset, Clock and Standby Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 PDF:6981573426/Source: 7298095240 MT9V034_DS - Rev. D Pub. 5/12 EN 4 . (c)2008 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9V034: 1/3-Inch Wide-VGA Digital Image Sensor List of Tables List of Tables Table 1: Table 2: Table 3: Table 4: Table 5: Table 6: Table 7: Table 8: Table 9: Table 10: Table 11: Table 12: Table 13: Table 14: Table 15: Table 16: Table 17: Table 18: Table 19: Table 20: Key Performance Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Available Part Numbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Frame Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Frame Time--Long Integration Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Slave Address Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Real-Time Context-Switchable Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Default Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 LVDS Packet Format in Stand-Alone Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 LVDS Packet Format in Stereoscopy Mode (Stereoscopy Mode Bit Asserted) . . . . . . . . . . . . . . . . . . .70 Reserved Words in the Pixel Data Stream . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 SER_DATAOUT_* state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 SHFT_CLK_* state. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 LVDS AC Timing Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 DC Electrical Characteristics Over Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 Two-Wire Serial Bus Timing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 PDF:6981573426/Source: 7298095240 MT9V034_DS - Rev. D Pub. 5/12 EN 5 . (c)2008 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9V034: 1/3-Inch Wide-VGA Digital Image Sensor General Description General Description The MT9V034 is a 1/3-inch wide-VGA format CMOS active-pixel digital image sensor with global shutter and high dynamic range (HDR) operation. The sensor has specifically been designed to support the demanding interior and exterior surveillance imaging needs, which makes this part ideal for a wide variety of imaging applications in real-world environments. This wide-VGA CMOS image sensor features Aptina's breakthrough low-noise CMOS imaging technology that achieves CCD image quality (based on signal-to-noise ratio and low-light sensitivity) while maintaining the inherent size, cost, and integration advantages of CMOS. The active imaging pixel array is 752H x 480V. It incorporates sophisticated camera functions on-chip--such as binning 2 x 2 and 4 x 4, to improve sensitivity when operating in smaller resolutions--as well as windowing, column and row mirroring. It is programmable through a simple two-wire serial interface. The MT9V034 can be operated in its default mode or be programmed for frame size, exposure, gain setting, and other parameters. The default mode outputs a wide-VGA-size image at 60 frames per second (fps). An on-chip analog-to-digital converter (ADC) provides 10 bits per pixel. A 12-bit resolution companded for 10 bits for small signals can be alternatively enabled, allowing more accurate digitization for darker areas in the image. In addition to a traditional, parallel logic output the MT9V034 also features a serial lowvoltage differential signaling (LVDS) output. The sensor can be operated in a stereocamera, and the sensor, designated as a stereo-master, is able to merge the data from itself and the stereo-slave sensor into one serial LVDS stream. The sensor is designed to operate in a wide temperature range (-30C to +70C). Figure 1: Block Diagram Control Register Active-Pixel Sensor (APS) Array 752H x 480V Serial Register I/O Timing and Control Analog Processing ADCs Digital Processing Parallel Video Data Out Serial Video LVDS Out Slave Video LVDS In (for stereo applications only) PDF:6981573426/Source: 7298095240 MT9V034_DS - Rev. D Pub. 5/12 EN 6 . (c)2008 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9V034: 1/3-Inch Wide-VGA Digital Image Sensor General Description DOUT0 DOUT1 DOUT2 1 PIXCLK 2 SYSCLK 3 DGND 4 VDD SER_DATAOUT_P 5 SHFT_CLKOUT_N SER_DATAOUT_N 6 SHFT_CLKOUT_P VDDLVDS 48-Pin CLCC Package Pinout Diagram 48 47 46 45 44 43 BYPASS_CLKIN_P 9 40 VAAPIX SER_DATAIN_N 10 39 VAA SER_DATAIN_P 11 38 AGND LVDSGND 12 37 NC DGND 13 36 NC VDD 14 35 VAA DOUT5 15 34 AGND DOUT6 16 33 STANDBY DOUT7 17 32 RESET_BAR DOUT8 18 31 S_CTRL_ADR1 PDF:6981573426/Source: 7298095240 MT9V034_DS - Rev. D Pub. 5/12 EN 22 23 24 SDATA 21 FRAME_VALID 20 LINE_VALID 19 7 25 26 27 28 29 30 S_CTRL_ADR0 DOUT4 RSVD 41 OE 8 LED_OUT BYPASS_CLKIN_N STFRM_OUT DOUT3 SCLK 42 EXPOSURE 7 STLN_OUT LVDSGND DOUT9 Figure 2: . (c)2008 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9V034: 1/3-Inch Wide-VGA Digital Image Sensor Pin Descriptions Pin Descriptions Table 3: Pin Descriptions 48-Pin CLCC Numbers 29 10 Symbol Type Description RSVD SER_DATAIN_N Input Input 11 SER_DATAIN_P Input 8 BYPASS_CLKIN_N Input 9 BYPASS_CLKIN_P Input 23 25 EXPOSURE SCLK Input Input 28 30 OE S_CTRL_ADR0 Input Input 31 S_CTRL_ADR1 Input 32 33 47 24 RESET_BAR STANDBY SYSCLK SDATA Input Input Input I/O 22 STLN_OUT I/O 26 STFRM_OUT I/O 20 21 15 16 17 18 19 27 41 42 43 44 45 46 2 3 4 5 1, 14 LINE_VALID FRAME_VALID DOUT5 DOUT6 DOUT7 DOUT8 DOUT9 LED_OUT DOUT4 DOUT3 DOUT2 DOUT1 DOUT0 PIXCLK SHFT_CLKOUT_N SHFT_CLKOUT_P SER_DATAOUT_N SER_DATAOUT_P VDD Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Supply Connect to DGND. Serial data in for stereoscopy (differential negative). Tie to 1K pullup (to 3.3V) in non-stereoscopy mode. Serial data in for stereoscopy (differential positive). Tie to DGND in non-stereoscopy mode. Input bypass shift-CLK (differential negative). Tie to 1K pull-up (to 3.3V) in non-stereoscopy mode. Input bypass shift-CLK (differential positive). Tie to DGND in nonstereoscopy mode. Rising edge starts exposure in snapshot and slave modes. Two-wire serial interface clock. Connect to VDD with 1.5K resistor even when no other two-wire serial interface peripheral is attached. DOUT enable pad, active HIGH. Two-wire serial interface slave address select (see Table 6 on page 16). Two-wire serial interface slave address select (see Table 6 on page 16). Asynchronous reset. All registers assume defaults. Shut down sensor operation for power saving. Master clock (26.6 MHz; 13 MHz - 27 MHz). Two-wire serial interface data. Connect to VDD with 1.5K resistor even when no other two-wire serial interface peripheral is attached. Output in master mode--start line sync to drive slave chip in-phase; input in slave mode. Output in master mode--start frame sync to drive a slave chip inphase; input in slave mode. Asserted when DOUT data is valid. Asserted when DOUT data is valid. Parallel pixel data output 5. Parallel pixel data output 6. Parallel pixel data output 7. Parallel pixel data output 8. Parallel pixel data output 9. LED strobe output. Parallel pixel data output 4. Parallel pixel data output 3. Parallel pixel data output 2. Parallel pixel data output 1. Parallel pixel data output 0. Pixel clock out. DOUT is valid on rising edge of this clock. Output shift CLK (differential negative). Output shift CLK (differential positive). Serial data out (differential negative). Serial data out (differential positive). Digital power 3.3V. PDF:6981573426/Source: 7298095240 MT9V034_DS - Rev. D Pub. 5/12 EN 8 Note 1 2 . (c)2008 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9V034: 1/3-Inch Wide-VGA Digital Image Sensor Pin Descriptions Table 3: Pin Descriptions (continued) 48-Pin CLCC Numbers 35, 39 40 6 7, 12 13, 48 34, 38 36, 37 Symbol Type VAA VAAPIX VDDLVDS LVDSGND DGND AGND NC Supply Supply Supply Ground Ground Ground NC Notes: Figure 3: Description Note Analog power 3.3V. Pixel power 3.3V. Dedicated power for LVDS pads. Dedicated GND for LVDS pads. Digital GND. Analog GND. No connect. 3 1. Pin 29, (RSVD) must be tied to GND. 2. Output enable (OE) tri-states signals DOUT0-DOUT9, LINE_VALID, FRAME_VALID, and PIXCLK. 3. No connect. These pins must be left floating for proper operation. Typical Configuration (Connection)--Parallel Output Mode 10K 1.5K Master clock VDDLVDS VDD VAA VAAPIX VDD VAA VAAPIX SYSCLK OE RESET_BAR EXPOSURE STANDBY S_CTRL_ADR0 S_CTRL_ADR1 SCLK SDATA STANDBY from controller or digital GND Two-wire serial interface RSVD DGND LVDSGND DOUT(9:0) LINE_VALID FRAME_VALID PIXCLK To controller LED_OUT To LED output AGND 0.1F Note: PDF:6981573426/Source: 7298095240 MT9V034_DS - Rev. D Pub. 5/12 EN LVDS signals are to be left floating. 9 . (c)2008 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9V034: 1/3-Inch Wide-VGA Digital Image Sensor Pixel Data Format Pixel Data Format Pixel Array Structure The MT9V034 pixel array is configured as 809 columns by 499 rows, shown in Figure 4. The dark pixels are optically black and are used internally to monitor black level. Of the left 52 columns, 36 are dark pixels used for row noise correction. Of the top 14 rows of pixels, two of the dark rows are used for black level correction. Also, three black rows from the top black rows can be read out by setting the Show Dark Rows bit in the Read Mode register; setting Show Dark Columns will display the 36 dark columns. There are 753 columns by 481 rows of optically active pixels. While the sensor's format is 752 x 480, one additional active column and active row are included for use when horizontal or vertical mirrored readout is enabled, to allow readout to start on the same pixel. This one pixel adjustment is always performed, for monochrome or color versions. The active area is surrounded with optically transparent dummy pixels to improve image uniformity within the active area. Neither dummy pixels nor barrier pixels can be read out. Figure 4: Pixel Array Description (0, 0) active pixel 2 barrier + 8 (2 + 4 addressed + 2) dark + 2 barrier + 2 light dummy 4.92 x 3.05 mm2 Pixel Array 809 x 499 (753 x 481 active) 6.0m pixel light dummy pixel dark pixel 3 barrier + 38 (1 + 36 addressed + 1) dark + 9 barrier + 2 light dummy 2 barrier + 2 light dummy 2 barrier + 2 light dummy PDF:6981573426/Source: 7298095240 MT9V034_DS - Rev. D Pub. 5/12 EN 10 barrier pixel . (c)2008 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9V034: 1/3-Inch Wide-VGA Digital Image Sensor Color Device Limitations Figure 5: Pixel Color Pattern Detail (Top Right Corner) Column Readout Direction Row Readout Direction Active Pixel (0,0) Array Pixel (4,14) G B G B G B G B R G R G R G R G G B G B G B G B R G R G R G R G G B G B G B G B R G R G R G R G Color Device Limitations The color version of the MT9V034 does not support or offers reduced performance for the following functionalities. Pixel Binning Pixel binning is done on immediate neighbor pixels only, no facility is provided to skip pixels according to a Bayer pattern. Therefore, the result of binning combines pixels of different colors. See "Pixel Binning" on page 64 for additional information. Interlaced Readout Interlaced readout yields one field consisting only of red and green pixels and another consisting only of blue and green pixels. This is due to the Bayer pattern of the CFA. Automatic Black Level Calibration When the color bit is set (R0x0F[1]=1), the sensor uses black level correction values from one green plane, which are applied to all colors. To use the calibration value based on all dark pixels' offset values, the color bit should be cleared. Other Limiting Factors Black level correction and row-wise noise correction are applied uniformly to each color. The row-wise noise correction algorithm does not work well in color sensors. Automatic exposure and gain control calculations are made based on all three colors, not just the green channel. High dynamic range does operate in color; however, Aptina strongly recommends limiting use to linear operation where good color fidelity is required. PDF:6981573426/Source: 7298095240 MT9V034_DS - Rev. D Pub. 5/12 EN 11 . (c)2008 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9V034: 1/3-Inch Wide-VGA Digital Image Sensor Output Data Format Output Data Format The MT9V034 image data can be read out in a progressive scan or interlaced scan mode. Valid image data is surrounded by horizontal and vertical blanking, as shown in Figure 6. The amount of horizontal and vertical blanking is programmable through R0x05 and R0x06, respectively (R0xCD and R0xCE for context B). LV is HIGH during the shaded region of the figure. See "Output Data Timing" on page 13 for the description of FV timing. Figure 6: Spatial Illustration of Image Readout P0,0 P0,1 P0,2.....................................P0,n-1 P0,n P1,0 P1,1 P1,2.....................................P1,n-1 P1,n HORIZONTAL BLANKING VALID IMAGE Pm-1,0 Pm-1,1.....................................Pm-1,n-1 Pm-1,n Pm,0 Pm,1.....................................Pm,n-1 Pm,n 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 ..................................... 00 00 00 00 00 00 ..................................... 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 VERTICAL/HORIZONTAL BLANKING VERTICAL BLANKING 00 00 00 ..................................... 00 00 00 00 00 00 ..................................... 00 00 00 PDF:6981573426/Source: 7298095240 MT9V034_DS - Rev. D Pub. 5/12 EN 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 12 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 . (c)2008 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9V034: 1/3-Inch Wide-VGA Digital Image Sensor Output Data Format Output Data Timing The data output of the MT9V034 is synchronized with the PIXCLK output. When LINE_VALID (LV) is HIGH, one 10-bit pixel datum is output every PIXCLK period. Figure 7: Timing Example of Pixel Data ... LINE_VALID ... PIXCLK Blanking ... Valid Image Data P0 (9:0) DOUT(9:0) P1 (9:0) P2 (9:0) P3 (9:0) P4 (9:0) Blanking ... Pn-1 (9:0) Pn (9:0) The PIXCLK is a nominally inverted version of the master clock (SYSCLK). This allows PIXCLK to be used as a clock to latch the data. However, when column bin 2 is enabled, the PIXCLK is HIGH for one complete master clock master period and then LOW for one complete master clock period; when column bin 4 is enabled, the PIXCLK is HIGH for two complete master clock periods and then LOW for two complete master clock periods. It is continuously enabled, even during the blanking period. Setting R0x72 bit[4] = 1 causes the MT9V034 to invert the polarity of the PIXCLK. The parameters P1, A, Q, and P2 in Figure 8 are defined in Table 4. Figure 8: Row Timing and FRAME_VALID/LINE_VALID Signals ... FRAME_VALID ... LINE_VALID ... Number of master clocks Table 4: P1 A Q A Q A P2 Frame Time Parameter Name Equation Default Timing at 26.66 MHz A Active data time Context A: R0x04 Context B: R0xCC P1 Frame start blanking Context A: R0x05 - 23 Context B: R0xCD - 23 P2 Frame end blanking 23 (fixed) Q Horizontal blanking Context A: R0x05 Context B: R0xCD 752 pixel clocks = 752 master = 28.20s 71 pixel clocks = 71master = 2.66s 23 pixel clocks = 23 master = 0.86s 94 pixel clocks = 94 master = 3.52s PDF:6981573426/Source: 7298095240 MT9V034_DS - Rev. D Pub. 5/12 EN 13 . (c)2008 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9V034: 1/3-Inch Wide-VGA Digital Image Sensor Output Data Format Table 4: Frame Time (continued) Parameter Name Equation Default Timing at 26.66 MHz Row time Context A: R0x04 + R0x05 Context B: R0xCC + R0xCD V Vertical blanking Context A: (R0x06) x (A + Q) + 4 Context B: (R0xCE) x (A + Q) + 4 Nrows x (A + Q) Frame valid time Context A: (R0x03) x (A + Q) Context B: (R0xCB) x (A + Q) F Total frame time V + (Nrows x (A + Q)) 846 pixel clocks = 846 master = 31.72ms 38,074 pixel clocks = 38,074 master = 1.43ms 406,080 pixel clocks = 406,080 master = 15.23ms 444,154 pixel clocks = 444,154 master = 16.66ms A+Q Sensor timing is shown above in terms of pixel clock and master clock cycles (refer to Figure 7 on page 13). The recommended master clock frequency is 26.66 MHz. The vertical blanking and the total frame time equations assume that the integration time (Coarse Shutter Width plus Fine Shutter Width) is less than the number of active rows plus the blanking rows minus the overhead rows: Window Height + Vertical Blanking - 2 (EQ 1) If this is not the case, the number of integration rows must be used instead to determine the frame time, as shown in Table 5. In this example it is assumed that the Coarse Shutter Width Control is programmed with 523 rows, and the Fine Shutter Width Total is zero. For Simultaneous mode, if the exposure time registers (Coarse Shutter Width Total plus Fine Shutter Width Total) exceed the total readout time, then the vertical blanking time is internally extended automatically to adjust for the additional integration time required. This extended value is not written back to the vertical blanking registers. The Vertical Blank register can be used to adjust frame-to-frame readout time. This register does not affect the exposure time but it may extend the readout time. Table 5: Parameter Frame Time--Long Integration Time Name Equation (Number of Master Clock Cycles) Default Timing at 26.66 MHz Vertical blanking (long integration time) Context A: (R0x0B + 2 - R0x03) x (A + Q) + R0xD5 + 4 Context B: (R0xD2 + 2 - R0xCB) x (A + Q) + R0xD8 + 4 Total frame time (long integration time) Context A: (R0x0B + 2) x (A + Q) + R0xD5 + 4 Context B: (R0xD2 + 2) x (A + Q) + R0xD8 + 4 38,074 pixel clocks = 38,074 master = 1.43ms 444,154 pixel clocks = 444,154 master = 16.66ms V' F Notes: PDF:6981573426/Source: 7298095240 MT9V034_DS - Rev. D Pub. 5/12 EN 1. The MT9V034 uses column parallel analog-digital converters, thus short row timing is not possible. The minimum total row time is 690 columns (horizontal width + horizontal blanking). The minimum horizontal blanking is 61. When the window width is set below 627, horizontal blanking must be increased. 14 . (c)2008 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9V034: 1/3-Inch Wide-VGA Digital Image Sensor Serial Bus Description Serial Bus Description Registers are written to and read from the MT9V034 through the two-wire serial interface bus. The MT9V034 is a serial interface slave with four possible IDs (0x90, 0x98, 0xB0 and 0xB8) determined by the S_CTRL_ADR0 and S_CTRL_ADR1 input pins. Data is transferred into the MT9V034 and out through the serial data (SDATA) line. The SDATA line is pulled up to VDD off-chip by a 1.5K resistor. Either the slave or master device can pull the SDATA line down--the serial interface protocol determines which device is allowed to pull the SDATA line down at any given time. The registers are 16-bit wide, and can be accessed through 16- or 8-bit two-wire serial interface sequences. Protocol The two-wire serial interface defines several different transmission codes, as shown in the following sequence: 1. a start bit 2. the slave device 8-bit address 3. a(n) (no) acknowledge bit 4. an 8-bit message 5. a stop bit Start Bit The start bit is defined as a HIGH-to-LOW transition of the data line while the clock line is HIGH. Slave Address The 8-bit address of a two-wire serial interface device consists of 7 bits of address and 1 bit of direction. A "0" in the LSB of the address indicates write mode, and a "1" indicates read mode. As indicated above, the MT9V034 allows four possible slave addresses determined by the two input pins, S_CTRL_ADR0 and S_CTRL_ADR1. Acknowledge Bit The master generates the acknowledge clock pulse. The transmitter (which is the master when writing, or the slave when reading) releases the data line, and the receiver indicates an acknowledge bit by pulling the data line LOW during the acknowledge clock pulse. No-Acknowledge Bit The no-acknowledge bit is generated when the data line is not pulled down by the receiver during the acknowledge clock pulse. A no-acknowledge bit is used to terminate a read sequence. Stop Bit The stop bit is defined as a LOW-to-HIGH transition of the data line while the clock line is HIGH. PDF:6981573426/Source: 7298095240 MT9V034_DS - Rev. D Pub. 5/12 EN 15 . (c)2008 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9V034: 1/3-Inch Wide-VGA Digital Image Sensor Serial Bus Description Sequence A typical READ or WRITE sequence begins by the master sending a start bit. After the start bit, the master sends the slave device's 8-bit address. The last bit of the address determines if the request is a read or a write, where a "0" indicates a WRITE and a "1" indicates a READ. The slave device acknowledges its address by sending an acknowledge bit back to the master. If the request was a WRITE, the master then transfers the 8-bit register address to which a WRITE should take place. The slave sends an acknowledge bit to indicate that the register address has been received. The master then transfers the data 8 bits at a time, with the slave sending an acknowledge bit after each 8 bits. The MT9V034 uses 16-bit data for its internal registers, thus requiring two 8-bit transfers to write to one register. After 16 bits are transferred, the register address is automatically incremented, so that the next 16 bits are written to the next register address. The master stops writing by sending a start or stop bit. A typical READ sequence is executed as follows. First the master sends the write mode slave address and 8-bit register address, just as in the write request. The master then sends a start bit and the read mode slave address. The master then clocks out the register data 8 bits at a time. The master sends an acknowledge bit after each 8-bit transfer. The register address is automatically incremented after every 16 bits is transferred. The data transfer is stopped when the master sends a no-acknowledge bit. The MT9V034 allows for 8-bit data transfers through the two-wire serial interface by writing (or reading) the most significant 8 bits to the register and then writing (or reading) the least significant 8 bits to Byte-Wise Address register (0x0F0). Bus Idle State The bus is idle when both the data and clock lines are HIGH. Control of the bus is initiated with a start bit, and the bus is released with a stop bit. Only the master can generate the start and stop bits. Table 6: Slave Address Modes {S_CTRL_ADR1, S_CTRL_ADR0} Slave Address Write/Read Mode 00 0x90 0x91 0x98 0x99 0xB0 0xB1 0xB8 0xB9 Write Read Write Read Write Read Write Read 01 10 11 Data Bit Transfer One data bit is transferred during each clock pulse. The two-wire serial interface clock pulse is provided by the master. The data must be stable during the HIGH period of the serial clock--it can only change when the two-wire serial interface clock is LOW. Data is transferred 8 bits at a time, followed by an acknowledge bit. PDF:6981573426/Source: 7298095240 MT9V034_DS - Rev. D Pub. 5/12 EN 16 . (c)2008 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9V034: 1/3-Inch Wide-VGA Digital Image Sensor Two-Wire Serial Interface Sample Read and Write Sequences Two-Wire Serial Interface Sample Read and Write Sequences 16-Bit Write Sequence A typical write sequence for writing 16 bits to a register is shown in Figure 9. A start bit given by the master, followed by the write address, starts the sequence. The image sensor then gives an acknowledge bit and expects the register address to come first, followed by the 16-bit data. After each 8-bit the image sensor gives an acknowledge bit. All 16 bits must be written before the register is updated. After 16 bits are transferred, the register address is automatically incremented, so that the next 16 bits are written to the next register. The master stops writing by sending a start or stop bit. Figure 9: Timing Diagram Showing a Write to R0x09 with the Value 0x0284 SCLK SDATA R0x09 0xB8 ADDR START ACK 0000 0010 ACK 1000 0100 ACK STOP ACK 16-Bit Read Sequence A typical read sequence is shown in Figure 10. First the master has to write the register address, as in a write sequence. Then a start bit and the read address specifies that a read is about to happen from the register. The master then clocks out the register data 8 bits at a time. The master sends an acknowledge bit after each 8-bit transfer. The register address is auto-incremented after every 16 bits is transferred. The data transfer is stopped when the master sends a no-acknowledge bit. Figure 10: Timing Diagram Showing a Read from R0x09; Returned Value 0x0284 SCLK SDATA 0xB8 ADDR START PDF:6981573426/Source: 7298095240 MT9V034_DS - Rev. D Pub. 5/12 EN R0x09 ACK 0xB9 ADDR ACK ACK 17 1000 0100 0000 0010 ACK STOP NACK . (c)2008 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9V034: 1/3-Inch Wide-VGA Digital Image Sensor Two-Wire Serial Interface Sample Read and Write Sequences 8-Bit Write Sequence To be able to write 1 byte at a time to the register a special register address is added. The 8-bit write is done by first writing the upper 8 bits to the desired register and then writing the lower 8 bits to the Bytewise Address register (R0xF0). The register is not updated until all 16 bits have been written. It is not possible to just update half of a register. In Figure 11 on page 18, a typical sequence for 8-bit writing is shown. The second byte is written to the Bytewise register (R0xF0). Figure 11: Timing Diagram Showing a Bytewise Write to R0x09 with the Value 0x0284 SCLK SDATA 0xB8 ADDR 0000 0010 R0x09 0xB8 ADDR 1000 0100 R0xF0 STOP START ACK START ACK ACK ACK ACK ACK 8-Bit Read Sequence To read one byte at a time the same special register address is used for the lower byte. The upper 8 bits are read from the desired register. By following this with a read from the Bytewise Address register (R0xF0) the lower 8 bits are accessed (Figure 12). The master sets the no-acknowledge bits shown. Figure 12: Timing Diagram Showing a Bytewise Read from R0x09; Returned Value 0x0284 SCLK SDATA 0xB8 ADDR 0000 0010 0xB9 ADDR R0x09 START START ACK ACK NACK ACK SCLK SDATA 0xB8 ADDR 0xB9 ADDR R0xF0 1000 0100 STOP START START PDF:6981573426/Source: 7298095240 MT9V034_DS - Rev. D Pub. 5/12 EN ACK ACK 18 ACK NACK . (c)2008 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9V034: 1/3-Inch Wide-VGA Digital Image Sensor Two-Wire Serial Interface Sample Read and Write Sequences Register Lock Included in the MT9V034 is a register lock (R0xFE) feature that can be used as a solution to reduce the probability of an inadvertent noise-triggered two-wire serial interface write to the sensor. All registers, or only the Read Mode registers-R0x0D and R0x0E, can be locked. It is important to prevent an inadvertent two-wire serial interface write to the Read Mode registers in automotive applications since this register controls the image orientation and any unintended flip to an image can cause serious results. At power-up, the register lock defaults to a value of 0xBEEF, which implies that all registers are unlocked and any two-wire serial interface writes to the register gets committed. Lock All Registers If a unique pattern (0xDEAD) to R0xFE is programmed, any subsequent two-wire serial interface writes to registers (except R0xFE) are NOT committed. Alternatively, if the user writes a 0xBEEF to the register lock register, all registers are unlocked and any subsequent two-wire serial interface writes to the register are committed. Lock Only Read Mode Registers (R0x0D and R0x0E) If a unique pattern (0xDEAF) to R0xFE is programmed, any subsequent two-wire serial interface writes to R0x0D or R0x0E are NOT committed. Alternatively, if the user writes a 0xBEEF to register lock register, registers R0x0D and R0x0E are unlocked and any subsequent two-wire serial interface writes to these registers are committed. PDF:6981573426/Source: 7298095240 MT9V034_DS - Rev. D Pub. 5/12 EN 19 . (c)2008 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9V034: 1/3-Inch Wide-VGA Digital Image Sensor Two-Wire Serial Interface Sample Read and Write Sequences Real-Time Context Switching In the MT9V034, the user may switch between two full register sets (listed in Table 7) by writing to a context switch change bit in register 0x07. This context switch will change all registers (no shadowing) at the frame start time and have the new values apply to the immediate next exposure and readout time. Table 7: . Real-Time Context-Switchable Registers Register Name Column Start Row Start Window Height Window Width Horizontal Blanking Vertical Blanking Coarse Shutter Width 1 Coarse Shutter Width 2 Coarse Shutter Width Control Coarse Shutter Width Total Fine Shutter Width 1 Fine Shutter Width 2 Fine Shutter Width Total Read Mode High Dynamic Range enable ADC Resolution Control V1 Control - V4 Control Analog Gain Control Row Noise Correction Control 1 Tiled Digital Gain AEC/AGC Enable PDF:6981573426/Source: 7298095240 MT9V034_DS - Rev. D Pub. 5/12 EN Register Number (Hex) For Context A Register Number (Hex) for Context B 0x01 0x02 0x03 0x04 0x05 0x06 0x08 0x09 0x0A 0x0B 0xD3 0xD4 0xD5 0x0D [5:0] 0x0F [0] 0x1C [1:0] 0x31 - 0x34 0x35 0x70 [1:0] 0x80 [3:0] - 0x98 [3:0] 0xAF [1:0] 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF 0xD0 0xD1 0xD2 0xD6 0xD7 0xD8 0x0E [5:0] 0x0F [8] 0x1C [9:8] 0x39 -0x3C 0x36 0x70 [9:8] 0x80 [11:8] - 0x98 [11:8] 0xAF [9:8] 20 . (c)2008 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9V034: 1/3-Inch Wide-VGA Digital Image Sensor Registers Registers Caution Table 8: Writing and changing the value of a reserved register (word or bit) puts the device in an unknown state and may damage the device. Default Register Descriptions 1 = always 1; 0 = always 0; d = programmable; ? = read only Register Number (Hex) Description Data Format (Binary) Default Value (Hex) 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 Chip Version Column Start Row Start Context A Window Height Context A Window Width Context A Horizontal Blanking Context A Vertical Blanking Context A Chip Control1 Coarse Shutter Width 1 Context A Coarse Shutter Width 2 Context A Shutter Width Ctrl Context A Coarse Total Shutter Width Context A Reset Read Mode Context A Read Mode Context B Sensor Type, HDR Enable Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved LED_OUT Ctrl Companding Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 0001 0011 0010 0100 (LSB) 0000 00dd dddd dddd 0000 000d dddd dddd 0000 000d dddd dddd 0000 00dd dddd dddd 0000 00dd dddd dddd 0ddd dddd dddd dddd 0000 dddd dddd dddd 0ddd dddd dddd dddd 0ddd dddd dddd dddd 0000 00dd dddd dddd 0ddd dddd dddd dddd 0000 0000 0000 00dd 0000 0011 dddd dddd 0000 0000 00dd dddd 0000 000d 0000 00dd - - - - - - - - - - - 0000 0000 0000 00dd 0000 00dd 0000 00dd - - - - - - - - - - - Iter. 1: 0x1324 0x0001 0x0004 0x01E0 0x02F0 0x005E 0x002D 0x0388 0x01BB 0x01D9 0x0164 0x01E0 0x0000 0x0300 0x0000 0x0100 0x0040 0x8042 0x0022 0x2D32 0x0E02 0x0E32 0x2802 0x3E38 0x3E38 0x2802 0x0428 0x0000 0x0302 0x0040 0x0000 0x0000 0x01C1 0x0020 0x0020 0x0010 0x0010 0x0020 0x0004 0x000C PDF:6981573426/Source: 7298095240 MT9V034_DS - Rev. D Pub. 5/12 EN 21 . (c)2008 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9V034: 1/3-Inch Wide-VGA Digital Image Sensor Registers Table 8: Default Register Descriptions (continued) 1 = always 1; 0 = always 0; d = programmable; ? = read only Register Number (Hex) Description Data Format (Binary) Default Value (Hex) 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x40 0x42 0x46 0x47 0x48 0x4C 0x60 0x61 - 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x70 0x71 0x72 0x73 - 0x7E 0x7F 0x80 0x81 0x82 0x83 0x84 Reserved Reserved Reserved Reserved VREF_ADC Control Reserved Reserved Reserved Reserved V1 Context A V2 Context A V3 Context A V4 Context A Analog Gain Context A Analog Gain Context B Reserved Reserved V1 Control Context B V2 Control Context B V3 Control Context B V4 Control Context B Reserved Frame Dark Average Dark Avg Thresholds BL Calib Control Black Level Calibration Value BL Calib Step Size Reserved Unused Reserved Reserved Reserved Reserved Reserved Reserved Row Noise Corr Control Row Noise Constant Pixclk, FV, LV Ctrl Unused Digital Test Pattern Tile Weight/Gain X0_Y0 Tile Weight/Gain X1_Y0 Tile Weight/Gain X2_Y0 Tile Weight/Gain X3_Y0 Tile Weight/Gain X4_Y0 - - - - 0000 0000 0000 0ddd - - - - 0000 0000 000d dddd 0000 0000 000d dddd 0000 0000 000d dddd 0000 0000 000d dddd 0000 0000 0ddd dddd 0000 0000 0ddd dddd - - 0000 0000 00dd dddd 0000 0000 00dd dddd 0000 0000 00dd dddd 0000 0000 00dd dddd 0000 0000 ???? ???? 0000 0000 ???? ???? dddd dddd dddd dddd 0000 0000 ddd0 000d 0000 0000 dddd dddd 0000 0000 000d dddd 0000 0000 0000 0000 - - - - - - - 0000 00dd 0000 00dd 0000 00dd dddd dddd 0000 0000 000d dddd - 0ddd ddd dddd dddd 0000 dddd dddd dddd 0000 dddd dddd dddd 0000 dddd dddd dddd 0000 dddd dddd dddd 0000 dddd dddd dddd 0x0010 0x0010 0x0020 0x0004 0x0000 0x0004 0x0007 0x0004 0x0003 0x0027 0x001A 0x0005 0x0003 0x0010 0x0010 0x0000 0x0000 0x27 0x26 0x5 0x3 RO RO 0x231D 0x0080 0x0000 0x0002 0x0000 0x0000 0x0000 RO RO RO RO 0x0000 0x0000 0x002A 0x0000 0x0000 0x0000 0x04F4 0x04F4 0x04F4 0x04F4 0x04F4 PDF:6981573426/Source: 7298095240 MT9V034_DS - Rev. D Pub. 5/12 EN 22 . (c)2008 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9V034: 1/3-Inch Wide-VGA Digital Image Sensor Registers Table 8: Default Register Descriptions (continued) 1 = always 1; 0 = always 0; d = programmable; ? = read only Register Number (Hex) Description Data Format (Binary) Default Value (Hex) 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F 0xA0 0xA1 0xA2 0xA3 0xA4 0XA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF 0xB0 0xB1 Tile Weight/Gain X0_Y1 Tile Weight/Gain X1_Y1 Tile Weight/Gain X2_Y1 Tile Weight/Gain X3_Y1 Tile Weight/Gain X4_Y1 Tile Weight/Gain X0_Y2 Tile Weight/Gain X1_Y2 Tile Weight/Gain X2_Y2 Tile Weight/Gain X3_Y2 Tile Weight/Gain X4_Y2 Tile Weight/Gain X0_Y3 Tile Weight/Gain X1_Y3 Tile Weight/Gain X2_Y3 Tile Weight/Gain X3_Y3 Tile Weight/Gain X4_Y3 Tile Weight/Gain X0_Y4 Tile Weight/Gain X1_Y4 Tile Weight/Gain X2_Y4 Tile Weight/Gain X3_Y4 Tile Weight/Gain X4_Y4 Tile Coord. X 0/5 Tile Coord. X 1/5 Tile Coord. X 2/5 Tile Coord. X 3/5 Tile Coord. X 4/5 Tile Coord. X 5/5 Tile Coord. Y 0/5 Tile Coord. Y 1/5 Tile Coord. Y 2/5 Tile Coord. Y 3/5 Tile Coord. Y 4/5 Tile Coord. Y 5/5 AEC/AGC Desired Bin AEC Update Frequency Unused AEC LPF AGC Update Frequency AGC LPF Max Analog Gain AEC MInimum Exposure AEC Maximum Exposure Bin Difference Threshold AEC/AGC Enable A/B AEC/AGC Pix Count LVDS Master Ctrl 0000 dddd dddd dddd 0000 dddd dddd dddd 0000 dddd dddd dddd 0000 dddd dddd dddd 0000 dddd dddd dddd 0000 dddd dddd dddd 0000 dddd dddd dddd 0000 dddd dddd dddd 0000 dddd dddd dddd 0000 dddd dddd dddd 0000 dddd dddd dddd 0000 dddd dddd dddd 0000 dddd dddd dddd 0000 dddd dddd dddd 0000 dddd dddd dddd 0000 dddd dddd dddd 0000 dddd dddd dddd 0000 dddddddd dddd 0000 dddd dddd dddd 0000 dddd dddd dddd 0000 00dd dddd dddd 0000 00dd dddd dddd 0000 00dd dddd dddd 0000 00dd dddd dddd 0000 00dd dddd dddd 0000 00dd dddd dddd 0000 000d dddd dddd 0000 000d dddd dddd 0000 000d dddd dddd 0000 000d dddd dddd 0000 000d dddd dddd 0000 000d dddd dddd 0000 0000 00dd dddd 0000 0000 0000 dddd 0000 0000 0000 0000 0000 0000 0000 00dd 0000 0000 0000 dddd 0000 0000 0000 00dd 0000 0000 0ddd dddd dddd dddd dddd dddd dddd dddd dddd dddd 0000 0000 dddd dddd 0000 00dd 0000 00dd dddd dddd dddd dddd 0000 0000 0000 dddd 0x04F4 0x04F4 0x04F4 0x04F4 0x04F4 0x04F4 0x04F4 0x04F4 0x04F4 0x04F4 0x04F4 0x04F4 0x04F4 0x04F4 0x04F4 0x04F4 0x04F4 0x04F4 0x04F4 0x04F4 0x0000 0x0096 0x012C 0x01C2 0x0258 0x02F0 0x0000 0x0060 0x00C0 0x0120 0x0180 0x01E0 0x003A 0x0002 0x0000 0x0000 0x0002 0x0002 0x0040 0x0001 0x01E0 0x0014 0x0003 0xABE0 0x0002 PDF:6981573426/Source: 7298095240 MT9V034_DS - Rev. D Pub. 5/12 EN 23 . (c)2008 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9V034: 1/3-Inch Wide-VGA Digital Image Sensor Registers Table 8: Default Register Descriptions (continued) 1 = always 1; 0 = always 0; d = programmable; ? = read only Register Number (Hex) Description Data Format (Binary) Default Value (Hex) 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0XBB 0xBC 0xBD - 0xBE 0xBF 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xF0 0xFE LVDS Shift Clk Ctrl LVDS Data Ctrl Data Stream Latency LVDS Internal Sync LVDS Payload Control Stereoscop. Error Ctrl Stereoscop. Error Flag LVDS Data Output AGC Gain Output AEC Gain Output AGC/AEC Current Bin Reserved Interlace Field Blank Mon Mode Capture Ctrl Reserved Anti-eclipse Controls Reserved Reserved Reserved NTSV FV and LV Control NTSC Horiz Blank Ctrl NTSC Vert Blank Ctrl Column Start Context B Row Start Context B Window Height Context B Window Width Context B Horizontal Blanking Context B Vertical Blanking Context B Coarse SW1 Context B Coarse SW2 Context B Shutter Width Ctrl Context B Coarse Shutter Width Total Context B Fine SW1 Context A Fine SW2 Context A Fine Shutter Width Total Context A Fine SW1 Context B Fine SW2 Context B Fine Shutter Width Total Context B Monitor Mode Bytewise Addr Register Lock 0000 0000 000d 0ddd 0000 0000 000d 0ddd 0000 0000 0000 00dd 0000 0000 0000 000d 0000 0000 0000 000d 0000 0000 0000 0ddd 0000 0000 0000 000? ???? ???? ???? ???? 0000 0000 0??? ???? ???? ???? ???? ???? 0000 0000 00?? ???? 0000 0000 0000 0000 0000 000d dddd dddd 0000 0000 dddd dddd 0000 00?? ???? ???? 00dd d000 d100 0000 0000 000? ???? ???? 0000 0000 ???? ???? 0000 0000 ???? ???? 0000 0000 0000 00dd dddd dddd dddd dddd dddd dddd dddd dddd 0000 00dd dddd dddd 0000 000d dddd dddd 0000 000d dddd dddd 0000 00dd dddd dddd 0000 00dd dddd dddd 0ddd dddd dddd dddd 0ddd dddd dddd dddd 0ddd dddd dddd dddd 0000 00dd dddd dddd 0ddd dddd dddd dddd 0000 00dd dddd dddd 0000 00dd dddd dddd 0000 0ddd dddd dddd 0000 0ddd dddd dddd 0000 0ddd dddd dddd 0000 0ddd dddd dddd 0000 0000 0000 000d 0000 0000 dddd dddd dddd dddd dddd dddd 0x0010 0x0010 0x0000 0x0000 0x0000 0x0000 RO RO RO RO RO 0x0000 0x0016 0x000A RO 0x0840 0x007F 0x007F 0x007F 0x0 0x4416 0x4421 0x001 0x004 0x1E0 0x2F0 0x5E 0x2D 0x1DE 0x1DF 0x064 0x1E0 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0xBEEF Note: PDF:6981573426/Source: 7298095240 MT9V034_DS - Rev. D Pub. 5/12 EN The MT9V034 requires R0x07[9] to be set to "0" for normal operation. The power-on default value sets this bit to "1." 24 . (c)2008 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9V034: 1/3-Inch Wide-VGA Digital Image Sensor Registers Shadowed Register Some sensor settings cannot be changed during frame readout. For example, changing Window Width R0x04 part way through frame readout results in inconsistent LV behavior. To avoid this, the MT9V034 double-buffers many registers by implementing a "pending" and a "live" version. Two-wire serial interface reads and writes access the pending register. The live register controls the sensor operation. The value in the pending register is transferred to a live register at a fixed point in the frame timing, called "frame-start." Frame-start is defined as the point at which the first dark row is read out. By default, this occurs four row times before FRAME_VALID (FV) goes HIGH. To determine which registers or register fields are double-buffered in this way, see the "Shadowed" column in Table 9. Notation used in the register description table: * Shadowed N = No. The register value is updated and used immediately. Y = Yes. The register value is updated at next frame start. Frame start is defined as when the first dark row is read out. By default this is four rows before FV goes HIGH. * Read/Write R = Read-only register/bit. W = Read/Write register/bit. Table 9 provides a detailed description of the registers. Bit fields that are not identified in the table are read only. Table 9: Bit Register Descriptions Bit Name Default in Hex (Dec) Bit Description 0x00/0xFF (0/255) Chip Version 15:0 Chip Version Chip version--read-only Shadowed Legal Values (Dec) 0x1324 (4900) 0x01 (1) Column Start Context A 9:0 Column Start The first column to be read out (not counting dark columns that may be read). To window the image down, set this register to the starting X value. Readable/active columns are 1-752. 0x02 (2) Row Start Context A 8:0 Row Start The first row to be read out (not counting any dark rows that may be read). To window the image down, set this register to the starting Y value. Setting a value less than four is not recommended since the dark rows should be read using R0x0D. 0x03 (3) Window Height Context A 8:0 Window Height Number of rows in the image to be read out (not counting any dark rows or border rows that may be read). 0x04 (4) Window Width Context A 9:0 Window Width Number of columns in image to be read out (not counting any dark columns or border columns that may be read). Read/ Write R 001 (1) Y 1-752 W 004 (4) N 4-482 W 1E0 (480) Y 1-480 W 2F0 (752) N 1-752 W 0x05 (5) Horizontal Blanking Context A PDF:6981573426/Source: 7298095240 MT9V034_DS - Rev. D Pub. 5/12 EN 25 . (c)2008 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9V034: 1/3-Inch Wide-VGA Digital Image Sensor Registers Table 9: Bit 9:0 Register Descriptions (continued) Bit Name Shadowed Legal Values (Dec) Read/ Write 05E (94) Y 61-1023 W 002D (45) N 2-32288 W 0 Y 0, 2, 3 W 1 Y 0,1, 3 W 0 Y 0,1 W 0 Y 0,1 W 1 Y 0,1 W Default in Hex (Dec) Bit Description Horizontal Blanking Number of blank columns in a row. Minimum horizontal blanking is 61 for normal mode, 71 for column bin 2 mode, and 91 for column bin 4 mode 0x06 (6) Vertical Blanking Context A 14:0 Vertical Blank Number of blank rows in a frame. V-Blank value must meet the following minimums: Linear Mode: V-Blank (min) = (SW_total - SW1 + 7) = SW_total - R0x08 + 7 If manual exposure, then SW_total = R0x0B. If auto-exposure mode then SW_total = R0xAD. High Dynamic Range Mode: If Auto-Knee Point disabled, then above equations apply. If Auto-Knee Point enabled, then V-Blank (min) = (t2 + t3 + 7). Note: Calculate t2 and t3 taking into account AutoExposure setting. Note: When Sequential Mode is enabled, this register is ineffective. Vertical blank = exposure + 6 rows. 0x07 (7) Chip Control 2:0 Scan Mode 4-3 5 6 7 0 = Progressive scan. 1 = Not valid. 2 = Two-field Interlaced scan. Even-numbered rows are read first, and followed by odd-numbered rows. 3 = Single-field Interlaced scan. If start address is even number, only even-numbered rows are read out; if start address is odd number, only odd-numbered rows are read out. Effective image size is decreased by half. Sensor Operating 0 = Slave mode. The user is allowed to initiate exposure Mode and readout. 1 = Master mode. Sensor generates its own exposure and readout timing according to simultaneous/ sequential mode control bit. 2 = Invalid mode. 3 = Snapshot mode. The user triggers the start of frame by providing a pulse at EXPOSURE pin. Stereoscopy Mode 0 = Stereoscopy disabled. Sensor is stand-alone and the PLL generates a 320 MHz (x12) clock. Typical maximum cable length is 8 meters. 1 = Stereoscopy enabled. The PLL generates a 540 MHz (x18) clock. Typical maximum cable length is 5 meters. Stereoscopic 0 = Stereoscopic master. Master/Slave 1 = Stereoscopic slave. Stereoscopy mode should be mode enabled when using this bit. Parallel Output 0 = Disable parallel output, LV and FV. Dout[9:0], Enable FRAME_VALID, and LINE_VALID are forced to logic "0" in sensor digital core. It does not control pads. 1= Enable parallel output. PDF:6981573426/Source: 7298095240 MT9V034_DS - Rev. D Pub. 5/12 EN 26 . (c)2008 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9V034: 1/3-Inch Wide-VGA Digital Image Sensor Registers Table 9: Register Descriptions (continued) Bit Bit Name 8 Simultaneous/ Sequential Mode Bit Description 0 = Sequential mode. Pixel and column readout take place only after exposure is complete. 1 = Simultaneous mode. Pixel and column readout take place in conjunction with exposure. 9 Reserved 0 = Normal (recommended) operation. 1 = Reserved function. Do not use. 15 Context A/B 0 = Context A registers are used. Select 1 = Context B registers are used. 0x08 (8) Coarse Shutter Width 1 Context A 14:0 Coarse Shutter The row number in which the first knee occurs. This Width 1 may be used when high dynamic range is enabled (R0x0F[0] = 1) and exposure knee point auto adjust is disabled (R0x0A[8] = 0). This register is not shadowed, but any change made does not take effect until the following new frame. This register's minimum value is 2, for either linear or HDR modes. Note: t1 = Shutter width 1; t2 = Shutter width 2 - Shutter width 1; t3 = total integration - Shutter width 2. 0x09 (9) Coarse Shutter Width 2 Context A 14:0 Course Shutter The row number in which the second knee occurs. Width 2 This may be used only when high dynamic range is enabled and exposure knee point auto adjust control bit is disabled. This register is not shadowed, but any change made does not take effect until the following new frame. Note: t1 = Shutter width 1; t2 = Shutter width 2 - Shutter 1; t3 = Total integration - Shutter width 2. 0x0A (10) Shutter Width Control Context A 3:0 T2 Ratio When Exposure Knee Point Auto Adjust is enabled, then one-half to the power of this value indicates the ratio of duration time t2, when saturation control gate is adjusted to level V2, to total coarse integration. This register is not shadowed, but any change made does not take effect until the following new frame. T2 = Total coarse integration x (1/2)t2_ratio. 7:4 T3 Ratio When Exposure Knee Point Auto Adjust is enabled, then one-half to the power of this value indicates the ratio of duration time t3, when saturation control gate is adjusted to level V3, to total coarse integration. This register is not shadowed, but any change made does not take effect until the following new frame. t3 = Total integration x (1/2)t3_ratio. Note: t3 = Total integration - t2 - t1. PDF:6981573426/Source: 7298095240 MT9V034_DS - Rev. D Pub. 5/12 EN 27 Shadowed Legal Values (Dec) Read/ Write 1 Y 0,1 W 1(1) Y 0, 1 W 0 Y 0, 1 W 1BB (443) N 0-32765 W 1D9 (473) N 0-32765 W 4 N 0-15 W 6 N 0-15 W Default in Hex (Dec) . (c)2008 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9V034: 1/3-Inch Wide-VGA Digital Image Sensor Registers Table 9: Bit Register Descriptions (continued) Bit Name Bit Description 8 Exposure Knee 0 = Auto adjust disabled. Point Auto Adjust 1 = Auto adjust enabled. Enable 9 Single Knee 0 = Single knee disabled. Enable 1 = Single knee enabled. 0x0B (11) Coarse Shutter Width Total Context A 14:0 Coarse Shutter Total integration time in number of rows. This value is Width Total used only when AEC is disabled only (bit 0 of R0xAF). This register is not shadowed, but any change made does not take effect until the following new frame. 0x0C (12) Reset 0 Soft Reset Setting this bit will cause the sensor to abandon the current frame by resetting all digital logic except twowire serial interface configuration. This is a selfresetting register bit and should always read "0." (This bit de-asserts internal active LOW reset signal for 15 clock cycles.) 1 Auto Block Soft Setting this bit causes the sensor to reset the automatic Reset gain and exposure control logic. This is a self-resetting register bit and should always read "0." (This bit deasserts internal active LOW reset signal for 15 clock cycles.) 0x0D (13) Read Mode Context A 1:0 Row Bin 0 = Normal operation. 1 = Row bin 2. Two pixel rows are read per row output. Image size is effectively reduced by a factor of 2 vertically while data rate and pixel clock are not affected. Resulting frame rate is increased by 2. 2 = Row bin 4. Four pixel rows are read per row output. Image size is effectively reduced by a factor of 4 vertically while data rate and pixel clock are not affected. Resulting frame rate is increased by 4. 3 = Not valid. 3:2 Column Bin 0 = Normal operation. 1 = Column bin 2. When set, image size is reduced by a factor of 2 horizontally. Frame rate is not affected but data rate and pixel clock are reduced by one-half that of master clock. 2 = Column bin 4. When set, image size is reduced by a factor of 4 horizontally. Frame rate is not affected but data rate and pixel clock are reduced by one-fourth that of master clock. 3 = Not valid. PDF:6981573426/Source: 7298095240 MT9V034_DS - Rev. D Pub. 5/12 EN 28 Shadowed Legal Values (Dec) Read/ Write 1 N 0, 1 W 0 N 0, 1 W 1E0 (480) N 0-32765 W 0 N 0, 1 W 0 Y 0, 1 W 0 Y 0, 1, 2 W 0 Y 0, 1, 2 W Default in Hex (Dec) . (c)2008 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9V034: 1/3-Inch Wide-VGA Digital Image Sensor Registers Table 9: Bit 4 Register Descriptions (continued) Bit Name Bit Description Row Flip Read out rows from bottom to top (upside down). When set, row readout starts from row (Row Start + Window Height) and continues down to (Row Start + 1). When clear, readout starts at Row Start and continues to (Row Start + Window Height - 1). This ensures that the starting color is maintained. This one pixel adjustment is always performed, for monochrome or color versions. 5 Column Flip Read out columns from right to left (mirrored). When set, column readout starts from column (Col Start + Window Width) and continues down to (Col Start + 1). When clear, readout starts at Col Start and continues to (Col Start + Window Width - 1). This ensures that the starting color is maintained. This one pixel adjustment is always performed, for monochrome or color versions. 6 Show Dark Rows When set, three dark rows are output before the active window. Frame valid is thus asserted earlier than normal. This has no effect on integration time or frame rate. Whether the dark rows are shown in the image or not the definition frame start is before the dark rows are read out. 7 Show Dark When set, 36 dark columns are output before the active Columns pixels in a line. Line valid is thus asserted earlier than normal, and the horizontal blank time is shortened by 36 pixel clocks. 9:8 Reserved Reserved. 0x0E (14) Read Mode Context B 1:0 Row Bin 0 = Normal Operation 1 = Row bin 2. Two pixel rows are read per row output. Image size is effectively reduced by a factor of 2 vertically while data rate and pixel clock are not affected. Resulting frame rate is increased by 2. 2 = Row bin 4. Four pixel rows are read per row output. Image size is effectively reduced by a factor of 4 vertically w Resulting frame rate is increased by 4. 3 = Invalid 0x0F (15) Sensor Type Control 0 High Dynamic 0 = Linear operation. If Linear mode is selected, then Range Context A Exposure Knee Point Auto Adjust must also be enabled (R0x0A[8] = 1). 1 = High Dynamic Range. Voltage and shutter width must be correctly set for saturation control to operate. PDF:6981573426/Source: 7298095240 MT9V034_DS - Rev. D Pub. 5/12 EN 29 Shadowed Legal Values (Dec) Read/ Write 0 Y 0, 1 W 0 Y 0, 1 W 0 Y 0, 1 W 0 Y 0, 1 W Default in Hex (Dec) 3 3 0 Y 0, 1, 2 W 0 N 0, 1 W . (c)2008 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9V034: 1/3-Inch Wide-VGA Digital Image Sensor Registers Table 9: Bit Register Descriptions (continued) Bit Name 1 Color/Mono Sensor Control 8 High Dynamic Range Context B Bit Description This bit controls some color-specific logic in Black Level Correction. 0 = Monochrome 1 = Color It should generally be left at "0" for all part types, it is not required to be set for color sensors to operate properly. When set, it applies an unequal offset to the color planes. For most applications on color parts the bit is best left cleared (monochrome), especially for machine vision applications where predictable image offsets are required. For Black Level Calibration (BLC), when this bit is set, the sensor uses black level correction values from one green plane, which are applied to all colors. Since this bit applies offsets to the color plane, BLC results may be affected. 0 = Linear operation. If Linear mode is selected, then Exposure Knee Point Auto Adjust must also be enabled (R0xD1[8] = 1). 1 = High Dynamic Range. Voltage and shutter width must be correctly set for saturation control to operate. Shadowed Legal Values (Dec) Read/ Write 0 Y 0, 1 W 1 N 0, 1 W 0, 1 W 0, 1 W 2, 3 W 2,3 W Default in Hex (Dec) 0x1B (27) LED_OUT Control 0 Disable LED_OUT Disable LED_OUT output. 0 Y When cleared, the output pin LED_OUT is pulsed HIGH when the sensor is undergoing exposure. When enabled: If enabled (set to 1), and Invert LED_OUT is disabled, the output pin LED_OUT is held in logic LOW state. If enabled and Invert LED_OUT is enabled, output pin LED_OUT is held in a logic HIGH state. 1 Invert LED_OUT Invert polarity of LED_OUT output. 0 Y When set, the output pin LED_OUT is pulsed LOW when the sensor is undergoing exposure. 0x1C (28) ADC Companding Mode 1:0 ADC Mode 0 = Invalid. 2 N Context A 1 = Invalid. 2 = 10-bit linear. 3 = 12-to10-bit companding. 9:8 ADC Mode 0 = Invalid. 3 N Context B 1 = Invalid. 2 = 10-bit linear. 3 = 12-to10-bit companding. 0x2C (44) - 0x3C (60) Analog Controls Note: These registers are not shadowed, but any change made does not take effect until the following new frame. PDF:6981573426/Source: 7298095240 MT9V034_DS - Rev. D Pub. 5/12 EN 30 . (c)2008 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9V034: 1/3-Inch Wide-VGA Digital Image Sensor Registers Table 9: Bit Register Descriptions (continued) Bit Name Bit Description 0x2C (44) VREF_ADC Control 2:0 VREF_ADC Voltage 0 = VREF_ADC = 1.0V. Level 1 = VREF_ADC = 1.1V. 2 = VREF_ADC = 1.2V. 3 = VREF_ADC = 1.3V. 4 = VREF_ADC = 1.4V.(Note: Effective ADC reference voltage is 1.0V.) 5 = VREF_ADC = 1.5V. 6 = VREF_ADC = 1.6V. 7 = VREF_ADC = 2.1V. Range: 1.0-2.1V; Default: 1.4V Note: This register is not shadowed, but any change made does not take effect until the following new frame. 0x31 (49) V1 Control Context A 5:0 V1 voltage level For bits (5:0) = 0 to 5, V_step = bits (5:0) * 200mV + 0.2V. Range: 0.2 - 1.2V For bits (5:0) = 6 to 63 V_step = bits (5:0) * 23.5mV + 1.62V Range: 1.76-3.1V Note: Equation and range are determined with the assumption that VAA = 3.3V. They may vary with actual VAA voltage. Default: 2.54V Usage: Vstep1 HDR voltage 0x32 (50) V2 Control Context A 5:0 V2 voltage level For bits (5:0) = 0 to 5, V_step = bits (5:0) * 200mV + 0.2V. Range: 0.2 - 1.2V Shadowed Legal Values (Dec) Read/ Write 4 N 0-7 W 27 (39) N 0-63 W 1A (26) N 0-63 W Default in Hex (Dec) For bits (5:0) = 6 to 63 V_step = bits (5:0) * 23.5mV + 1.62V Range: 1.76-3.1V Note: equation and range are determined with the assumption that VAA = 3.3V. They may vary with actual VAA voltage. Default: 2.23V Usage: Vstep2 HDR voltage PDF:6981573426/Source: 7298095240 MT9V034_DS - Rev. D Pub. 5/12 EN 31 . (c)2008 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9V034: 1/3-Inch Wide-VGA Digital Image Sensor Registers Table 9: Bit Register Descriptions (continued) Bit Name Shadowed Legal Values (Dec) Read/ Write 05 (5) N 0-63 W 03 (3) N 0-63 W 10 (16) N 16-64 W 0 N 0, 1 W 10 (16) N 16-64 W 1 N 0, 1 W Default in Hex (Dec) Bit Description 0x33 (51) V3 Control Context A 5:0 V3 voltage level For bits (5:0) = 0 to 5, V_step = bits (5:0) * 200mV + 0.2V. Range: 0.2 - 1.2V For bits (5:0) = 6 to 63 V_step = bits (5:0) * 23.5mV + 1.62V Range: 1.76-3.1V Note: equation and range are determined with the assumption that VAA = 3.3V. They may vary with actual VAA voltage. Default: 1.2V Usage: Vstep3 HDR voltage. 0x34 (52) V4 Control Context A 5:0 V4 voltage level For bits (5:0) = 0 to 5, V_step = bits (5:0) * 200mV + 0.2V. Range: 0.2 - 1.2V For bits (5:0) = 6 to 63 V_step = bits (5:0) * 23.5mV + 1.62V Range: 1.76-3.1V Note: equation and range are determined with the assumption that VAA = 3.3V. They may vary with actual VAA voltage. Default: 0.8V Usage: Vstep HDR parking voltage, also provides antiblooming when Vstep is disabled. 0x35 (53) Analog Gain Context A 6:0 Global Analog Analog gain = bits (6:0) x 0.0625 Gain Range: 16 dec - 64dec for 1X-4X respectively Column amplifier common gain. Note: No exception detection is installed, user needs to be cautious when programming 15 Global Analog When this bit is set, analog gain will be forced to 0.75X. Gain Attenuation 0x36 (54) Analog Gain Context B 6:0 Global Analog Analog gain = bits (6:0) x 0.0625 Gain Range: 16 dec -64dec for 1X-4X respectively 15 Global Analog Gain Attenuation Column amplifier common gain. Note: No exception detection is installed, user needs to be cautious when programming When this bit is set, analog gain will be forced to 0.75X. 0x39 (57) V1 Control Context B PDF:6981573426/Source: 7298095240 MT9V034_DS - Rev. D Pub. 5/12 EN 32 . (c)2008 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9V034: 1/3-Inch Wide-VGA Digital Image Sensor Registers Table 9: Bit 5:0 Register Descriptions (continued) Bit Name V1 Voltage Level Shadowed Legal Values (Dec) Read/ Write 27 (39) N 0-63 W 36 (38) N 0-63 W 05 (5) N 0-63 W Default in Hex (Dec) Bit Description For bits (5:0) = 0 to 5, V_step = bits (5:0) * 200mV + 0.2V. Range: 0.2 - 1.2V For bits (5:0) = 6 to 63 V_step = bits (5:0) * 23.5mV + 1.62V Range: 1.76-3.1V Note: equation and range are determined with the assumption that VAA = 3.3V. They may vary with actual VAA voltage. Default: 2.54V Usage: Vstep 1 HDR voltage 0x3A (58) V2 Control Context B 5:0 V2 Voltage Level For bits (5:0) = 0 to 5, V_step = bits (5:0) * 200mV + 0.2V. Range: 0.2 - 1.2V For bits (5:0) = 6 to 63 V_step = bits (5:0) * 23.5mV + 1.62V Range: 1.76-3.1V Note: Equation and range are determined with the assumption that VAA = 3.3V. They may vary with actual VAA voltage. Default: 2.51V Usage: Vstep2 HDR voltage 0x3B (59) V3 Control Context B 5:0 V3 Voltage Level For bits (5:0) = 0 to 5, V_step = bits (5:0) * 200mV + 0.2V. Range: 0.2 - 1.2V For bits (5:0) = 6 to 63 V_step = bits (5:0) * 23.5mV + 1.62V Range: 1.76-3.1V Note: Equation and range are determined with the assumption that VAA = 3.3V. They may vary with actual VAA voltage. Default: 1.2V Usage: Vstep3 HDR voltage 0x3C (60) V4 Control Context B PDF:6981573426/Source: 7298095240 MT9V034_DS - Rev. D Pub. 5/12 EN 33 . (c)2008 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9V034: 1/3-Inch Wide-VGA Digital Image Sensor Registers Table 9: Bit 5:0 Register Descriptions (continued) Bit Name Default in Hex (Dec) Bit Description For bits (5:0) = 0 to 5, V_step = bits (5:0) * 200mV + 0.2V. Range: 0.2 - 1.2V For bits (5:0) = 6 to 63 V_step = bits (5:0) * 23.5mV + 1.62V Range: 1.76-3.1V Note: Equation and range are determined with the assumption that VAA = 3.3V. They may vary with actual VAA voltage. Default: 0.8V Usage: Vstep HDR parking voltage, also provides antiblooming when Vstep is disabled. 0x42 (66) Frame Dark Average 7:0 Frame Dark The value read is the frame averaged black level, that is, Average used in the black level algorithm calculations. 0x46 (70) Dark Average Thresholds 7:0 Lower threshold Lower threshold for targeted black level in ADC LSBs. 15:8 V4 Voltage Level Upper threshold Upper threshold for targeted black level in ADC LSBs. 0x47 (71) Black Level Calibration Control 0 Manual Override Manual override of black level correction. 1 = Override automatic black level correction with programmed values. (R0x48). 0 = Normal operation (default). 7:5 Frames to average Two to the power of this value decide how many frames over to average over when the black level algorithm is in the averaging mode. In this mode the running frame average is calculated from the following formula: Running frame ave = Old running frame ave - (old running frame ave)/2n + (new frame ave)/ 2n. 0x48 (72) Black Level Calibration Value Context A 7:0 Black Level Analog calibration offset: Negative numbers are Calibration Value represented with two's complement, which is shown in the following formula: Sign = bit 7 (0 is positive, 1 is negative). If positive offset value: Magnitude = bit 6:0. If negative offset value: Magnitude = not (bit 6:0) + 1. During two-wire serial interface read, this register returns the user-programmed value when manual override is enabled (R0x47 bit 0); otherwise, this register returns the result obtained from the calibration algorithm. 0x4C (76) Black Level Calibration Value Step Size 4:0 Step Size of This is the size calibration value may change (positively Calibration Value or negatively) from frame to frame. Note: 1 calib LSB = 1/2 ADC LSB, assuming analog gain = 1. PDF:6981573426/Source: 7298095240 MT9V034_DS - Rev. D Pub. 5/12 EN 34 03 (3) Shadowed Legal Values (Dec) Read/ Write N 0-63 W 0 R 1D (29) 23 (35) N 0-255 W N 0-255 W 0 N 0, 1 W 4 N 0-7 W - N -127 to 127 RW 02 N 0-31 W . (c)2008 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9V034: 1/3-Inch Wide-VGA Digital Image Sensor Registers Table 9: Bit Register Descriptions (continued) Bit Name Bit Description 0x70 (112) Row Noise Correction Control 0 Enable Noise 0 = Normal operation Correction 1 = Enable row noise cancellation algorithm. When this Context A bit is set, on a per row basis, the dark average will be subtracted from each pixel in the row, and then a constant (R 0x71) will be added. 1 Use black level 0 = Use the average value of the dark columns read out average Context A in each row as dark average. 1 = Use black level frame average from the dark rows in the row noise correction algorithm for low gains. Note that this frame average was taken before the last adjustment of the offset DAC for that frame, so it might be slightly off. 8 Enable noise 0 = Normal operation correction 1 = Enable row noise cancellation algorithm. When this Context B bit is set, on a per row basis, the dark average will be subtracted from each pixel in the row, and then a constant (R0x71) will be added. 9 Use black level 0 = Use the average value of the dark columns read out average Context B in each row as dark average. 1 = Use black level frame average from the dark rows in the row noise correction algorithm for low gains. Note that this frame average was taken before the last adjustment of the offset DAC for that frame, so it might be slightly off. 0x71 (113) Row Noise Constant 9:0 Row noise Constant used in the row noise cancellation algorithm. constant It should be set to the dark level targeted by the black level algorithm plus the noise expected between the averaged values of dark columns. At default the constant is set to 42 LSB. 0x72 (114) Pixel Clock, FRAME and LINE VALID Control 0 Invert LINE VALID Invert LINE_VALID. When set, LINE_VALID will be reset to logic '0' when PDOUT is valid. 1 Invert Frame Valid Invert FRAME_VALID. When set, FRAME_VALID is reset to logic "0" when the frame is valid. 2 XOR Line Valid 1 = LINE_VALID = "Continuous" LINE_VALID XOR FRAME_VALID 0 = LINE_VALID is determined by bit 3. Ineffective if Continuous Line Valid is set. 3 Continuous Line 1 = "Continuous" LINE_VALID (continue producing Valid LINE_VALID during vertical blank). 0 = Normal LINE_VALID (default, no LINE_VALID during vertical blank). 4 Invert Pixel Clock Invert pixel clock. When set, LINE_VALID, FRAME_VALID, and PDOUT will be set up to the rising edge of pixel clock, PIXCLK. When clear, they are set up to the falling edge of PIXCLK. PDF:6981573426/Source: 7298095240 MT9V034_DS - Rev. D Pub. 5/12 EN 35 Shadowed Legal Values (Dec) Read/ Write 0 N 0, 1 W 0 N 0, 1 W 0 N 0, 1 W 0 N 0, 1 W 2A (42) Y 0-1023 W 0 Y 0, 1 W 0 Y 0, 1 W 0 Y 0, 1 W 0 Y 0, 1 W 0 Y 0, 1 W Default in Hex (Dec) . (c)2008 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9V034: 1/3-Inch Wide-VGA Digital Image Sensor Registers Table 9: Bit Register Descriptions (continued) Bit Name Bit Description 0x7F (127) Digital Test Pattern 9:0 Two-wire Serial The 10-bit test data in this register is used in place of Interface Test the data from the sensor. The data is inserted at the Data beginning of the digital signal processing. Both test enable (bit 13) and use two-wire serial interface (bit 10) must be set. 10 Use Two-wire 0 = Use Gray Shade Test Pattern as test data. Serial Interface 1 = Use Two-wire Serial Interface Test Data (bits 9:0) as Test Data test data. 12:11 Gray Shade Test 0 = None. Pattern 1 = Vertical Shades. 2 = Horizontal Shades. 3 = Diagonal Shade. When bits (12:11) 0, the MT9V034 generates a gray shaded test pattern to be used as digital test data. Ineffective when Use Two-wire Serial Interface Test Data (bit 10) is set. 13 Test Enable Enable the use of test data/gray-shaded test pattern in the signal chain. The data will be inserted instead of data from the ADCs. When using this mode, disable Row Noise Correction (R0x70 bit 0 and bit 8). If Row Noise Correction is enabled, the row-wise correction algorithm will process the test data values and the result will not be accurate. 14 Flip Two-Wire Use only when bit 10 is set. Serial Interface When set, the Two-Wire Test Data (bits 9:0) will be used Test Data in place of the data from ADC/memory on odd columns, while complement of the same data will be used on even columns. 0x80 (128) - 0x98 (152) Tiled Digital Gain 3:0 Tile Gain Tile Digital Gain = Bits (3:0) * 0.25 Context A See "Digital Gain" on page 58 for additional information. 7:4 Sample Weight To indicate the weight of individual tile used in the automatic gain/exposure control algorithm. See "Automatic Gain Control and Automatic Exposure Control" on page 61 for additional information. 11:8 Tile Gain Context Tile Digital Gain = Bits (3:0) * 0.25 B See "Digital Gain" on page 58 for additional information. See "Digital Gain" on page 58, for 0x99 (153) - 0xA4 (164) detailed descriptions. 0x99 (153) Digital Tile Coordinate 1 - X-direction The starting x-coordinate of digital tiles X0_*. 9:0 X 0/5 0x9A (154) Digital Tile Coordinate 2 - X-direction The starting x-coordinate of digital tiles X1_*. 9:0 X 1/5 Shadowed Legal Values (Dec) Read/ Write 000 N 0-1023 W 0 N 0, 1 W 0 N 0-3 W 0 Y 0, 1 W 0 N 0, 1 W 4 (4) Y 1-15 W F (15) Y 1-15 W 4 (4) Y 1-15 W 000 (0) N 0-752 W 096 (150) N 0-752 W Default in Hex (Dec) 0x9B (155) Digital Tile Coordinate 3 - X-direction PDF:6981573426/Source: 7298095240 MT9V034_DS - Rev. D Pub. 5/12 EN 36 . (c)2008 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9V034: 1/3-Inch Wide-VGA Digital Image Sensor Registers Table 9: Bit 9:0 Register Descriptions (continued) Bit Name X 2/5 Bit Description The starting x-coordinate of digital tiles X2_*. 0x9C (156) Digital Tile Coordinate 4 - X-direction The starting x-coordinate of digital tiles X3_*. 9:0 X 3/5 0x9D (157) Digital Tile Coordinate 5 - X-direction The starting x-coordinate of digital tiles X4_*. 9:0 X 4/5 0x9E (158) Digital Tile Coordinate 6 - X-direction The ending x-coordinate of digital tiles X4_*. 9:0 X 5/5 0x9F (159) Digital Tile Coordinate 1 - Y-direction The starting y-coordinate of digital tiles *_Y0. 8:0 Y 0/5 0xA0 (160) Digital Tile Coordinate 2 - Y-direction The starting y-coordinate of digital tiles *_Y1. 8:0 Y 1/5 0xA1 (161) Digital Tile Coordinate 3 - Y-direction The starting y-coordinate of digital tiles *_Y2. 8:0 Y 2/5 0xA2 (162) Digital Tile Coordinate 4 - Y-direction The starting y-coordinate of digital tiles *_Y3. 8:0 Y 3/5 0xA3 (163) Digital Tile Coordinate 5 - Y-direction The starting y-coordinate of digital tiles *_Y4. 8:0 Y 4/5 0xA4 (164) Digital Tile Coordinate 6 - Y-direction The ending y-coordinate of digital tiles *_Y4. 8:0 Y 5/5 0xA5 (165) AEC/AGC Desired Bin 5:0 Desired Bin User-defined "desired bin" that gives a measure of how bright the image is intended to be. 0xA6 (166) AEC Update Frequency 3:0 Exp Skip Frame The number of frames that the AEC must skip before updating the exposure register (R0xBB). PDF:6981573426/Source: 7298095240 MT9V034_DS - Rev. D Pub. 5/12 EN Shadowed Legal Values (Dec) Read/ Write 12C (300) N 0-752 W 1C2 (450) N 0-752 W 258 (600) N 0-752 W 2F0 (752) N 0-752 W 000 (0) N 0-480 W 060 (96) N 0-480 W 0C0 (192) N 0-480 W 120 (288) N 0-480 W 180 (384) N 0-480 W 1E0 (480) N 0-480 W 3A (58) Y 1-64 W 2 Y 0-15 W Default in Hex (Dec) 37 . (c)2008 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9V034: 1/3-Inch Wide-VGA Digital Image Sensor Registers Table 9: Bit Register Descriptions (continued) Bit Name Bit Description 0xA8 (168) AEC Low Pass Filter 1:0 Exp LPF This value plays in role in determining the increment/ decrement size of exposure value from frame to frame. If current bin 0 (R0xBC), Shadowed Legal Values (Dec) Read/ Write 0 Y 0-2 W 2 Y 0-15 W 2 Y 0-2 W Default in Hex (Dec) When Exp LPF = 0: Actual new exposure = Calculated new exposure. When Exp LPF = 1: if |(Calculated. new exp - current exp) | > (current exp / 4), Actual new exposure = Calculated new exposure, otherwise Actual new exposure = Current exp +/- (calc new exp/2) When Exp LPF = 2: if |(Calculated new exp - current exp) | > (current exp / 4), Actual new exposure = Calc. new exposure, otherwise Actual new exposure = Current exp +/- (calc new exp/4) 0xA9 (169) AGC Output Update Frequency 3:0 Gain Skip Frame The number of frames that the AGC must skip before updating the gain register (R0xBA). 0xAA (170) AGC Low Pass Filter 1:0 Gain LPF This value plays a role in determining the increment/ decrement size of gain value from frame to frame. If current bin (R0xBC) 0 When Gain LPF = 0: Actual new gain = Calculated new gain When Exp LPF = 1: if |(Calculated new gain - current gain) | > (current gain/ 4), Actual new gain = Calculated new gain, otherwise Actual new gain = Current gain (calculated new gain/ 2) When Exp LPF = 2: if |(Calculated new gain - current gain) | > (current gain / 4), Actual new gain = Calculated new gain, otherwise Actual new gain = Current gain (calculated new gain/ 4). 0xAB (171) Maximum Analog Gain PDF:6981573426/Source: 7298095240 MT9V034_DS - Rev. D Pub. 5/12 EN 38 . (c)2008 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9V034: 1/3-Inch Wide-VGA Digital Image Sensor Registers Table 9: Bit Register Descriptions (continued) Bit Name Bit Description 6:0 Maximum Analog This register is used by the automatic gain control (AGC) Gain as the upper threshold of gain. This ensures the new calibrated gain value will not exceed that which MT9V034 supports. Range: 16 dec -64 dec for 1X-4X respectively Note: No exception detection is installed, user needs to be cautious when programming. 0xAC (172) Minimum Coarse Shutter Width 15:0 Minimum Coarse This register is used by the automatic exposure control Shutter Width (AEC) as the lower threshold of exposure. This ensures Total the new calibrated integration value will not exceed that which MT9V034 supports. 0xAD (173) Maximum Coarse Shutter Width 15:0 Maximum Coarse This register is used by the automatic exposure control (AEC) as the upper threshold of exposure. This ensures Shutter Width the new calibrated integration value will not exceed Total that which MT9V034 supports. 0xAE (174) AGC/AEC Bin Difference Threshold 7:0 Bin Difference This register is used by the AEC if exposure reaches the Threshold Minimum Coarse Shutter Width value (R0xAC). Then if the difference between desired bin (R0xA5) and current bin (R0xBC) is larger than the threshold, the exposure will be increased. 0xAF (175) AGC/AEC Enable 0 AEC Enable 0 = Disable Automatic Exposure Control. Context A 1 = Enable Automatic Exposure Control. 1 AGC Enable 0 = Disable Automatic Gain Control. Context A 1 = Enable Automatic Gain Control. 8 AEC Enable 0 = Disable Automatic Exposure Control. Context B 1 = Enable Automatic Exposure Control. 9 AGC Enable 0 = Disable Automatic Gain Control. Contest B 1 = Enable Control. 0xB0 (176) AGC/AEC Pixel Count 15-0 Pixel Count The number of pixel used for the AEC/AGC histogram. 0xB1 (177) LVDS Master Control 0 PLL Bypass 0 = Internal shift-CLK is driven by PLL. 1 = Internal shift-CLK is sourced from the LVDS_BYPASS_CLK. 1 LVDS Power-down 0 = Normal operation. 1 = Power-down LVDS block. 2 PLL Test Mode 0 = Normal operation. 1 = The PLL output frequency is equal to the system clock frequency (26.6 MHz). 3 LVDS Test Mode 0 = Normal operation. 1 = The SER_DATAOUT_P drives a square wave in both stereo and stand-alone modes). In stereo mode, ensure that SER_DATAIN_P is logic "0." 0xB2 (178) LVDS Shift Clock Control PDF:6981573426/Source: 7298095240 MT9V034_DS - Rev. D Pub. 5/12 EN Shadowed Legal Values (Dec) Read/ Write 40 (64) N 16-64 W 1 N 1-32765 W 01E0 (480) N 1-32765 W 14 (20) Y 0-63 W 1 Y 0, 1 W 1 Y 0, 1 W 0 Y 0, 1 W 0 Y 0, 1 W ABE0 (44,000) Y 0-65535 W 0 Y 0, 1 W 1 Y 0, 1 W 0 Y 0, 1 W 0 Y 0, 1 W Default in Hex (Dec) 39 . (c)2008 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9V034: 1/3-Inch Wide-VGA Digital Image Sensor Registers Table 9: Bit Register Descriptions (continued) Bit Name Bit Description 2:0 Shift-clk Delay The amount of shift-CLK delay that minimizes interElement Select sensor skew. 4 LVDS Clock When set, the LVDS clock (SHFT_CLKOUT) pins are Output Enable disabled. Has no effect on SER_DATAOUT pins. 0xB3 (179) LVDS Data Control 2:0 Data Delay The amount of data delay that minimizes inter-sensor Element Select skew. 4 LVDS Data Input When set, the LVDS Data Receiver (SER_DATAIN) pins Enable are disabled. If this bit is changed, it is mandatory that a soft reset (R0x0C) is then issued for proper operation. 0xB4 (180) LVDS Latency 1:0 Stream Latency The amount of delay so that the two streams are in Select sync. 0xB5 (181) LVDS Internal Sync 0 LVDS Internal When set, the MT9V034 generates sync pattern (data Sync Enable with all zeros except start bit) on LVDS_SER_DATA_OUT. 0xB6 (182) LVDS Payload Control 0 Use 10-bit Pixel When set, all 10 bits will contain pixel (with embedded Enable controls) in standalone mode. If clear, payload will be 8 bits of pixel with 2 bits of controls. 0xB7 (183) Stereoscopy Error Control 0 Enable Stereo Set this bit to enable stereo error detect mechanism. Error Detect 1 Enable Stick When set, the stereo error flag remains asserted once Stereo Error Flag an error is detected unless clear stereo error flag (bit 2) is set. 2 Clear Stereo Error Set this bit to clear the stereoscopy error flag (R0xB8 Flag returns to logic 0). 0xB8 (184) Stereoscopy Error Flag 0 Stereoscopy Error Stereoscopy error status flag. It is also directly Flag connected to the ERROR output pin. 0xB9 (185) LVDS Data Output 15:0 Combo Reg This 16-bit value contains both 8-bit pixel values from both stereoscopic master and slave sensors. It can be used in diagnosis to determine how well in sync the two sensors are. Captures the state when master sensor has issued a reserved byte and slave has not. Note: This register should be read from the stereoscopic master sensor only. 0xBA (186) AGC Gain Output 6:0 AGC Gain Status register to report the current gain value obtained from the AGC algorithm. 0xBB (187) AEC Exposure Output 15:0 AEC Exposure Status register to report the current exposure value obtained from the AEC algorithm. 0xBC (188) AGC/AEC Current Bin PDF:6981573426/Source: 7298095240 MT9V034_DS - Rev. D Pub. 5/12 EN 40 Shadowed Legal Values (Dec) Read/ Write 0 Y 0-7 W 1 Y 0, 1 W 0 Y 0-7 W 1 Y 0, 1 W 0 Y 0-3 W 0 Y 0, 1 W 0 Y 0, 1 W 0 Y 0, 1 W 0 Y 0, 1 W 0 Y 0, 1 W Default in Hex (Dec) R R 10 R 00C8 (200) R . (c)2008 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9V034: 1/3-Inch Wide-VGA Digital Image Sensor Registers Table 9: Bit 5:0 Register Descriptions (continued) Bit Name Default in Hex (Dec) Bit Description Status register to report the current bin of the histogram. 0xBF (191) Field Vertical Blank 8:0 Field Vertical The number of blank rows between odd and even fields. Blank Note: For interlace (both field) mode (R0x07 bits1:0) only. Shadowed Legal Values (Dec) Current Bin Note: When Field Vertical Blank is set to 0, the blank time between odd and even fields is one master clock cycle. 0xC0 (192) Monitor Mode Capture Control 7:0 Image Capture The number of frames to be captured during the wakeNumb up period when monitor mode is enabled. 0xC2 (194) Analog Controls 6 Reserved Reserved. Leave at "1" 7 Anti-Eclipse Setting this bit turns on anti-eclipse circuitry. Enable 13:11 V_rst_lim voltage V_rst_lim = bits [13:11] * 50mV + 1.90V Level Range: 1.90-2.25; Default: 1.95 V Usage: For anti-eclipse reference voltage control 0xC6 (198) NTSC Frame Valid Control 0 Extend Frame When set, frame valid is extended for half-line in length Valid at the odd field. 1 Replace FV/LV When set, frame valid and line valid is replaced by ped with Ped/Snyc and sync signals respectively. 0xC7 (198) NTSC Horizontal Blank Control 7:0 Front porch width The front porch width in number of master clock cycles. NTSC standard is 1.5sec 0.1sec 15:8 Sync Width The sync pulse width in number of master clock cycle. NTSC standard is 4.7sec 0.1sec. 0xC8 (200) NTSC Vertical Blank Control 7:0 Equalizing Pulse The pulse width in number of master clock cycles. NTSC Width standard is 2.3sec 0.1sec. 15:8 Vertical Serration The pulse width in number of master clock cycles. NTSC Width standard is 4.7sec 0.1sec. 0xC9 (201) Column Start Context B 9:0 Column Start The first column to be read out (not counting dark columns that may be read). To window the image down, set this register to the starting X value. 0xCA (202) Row Start Context B 8:0 Row Start The first row to be read out (not counting any dark rows that may be read). To window the image down, set this register to the starting Y value. Setting a value less than four is not recommended since the dark rows should be read using R0x0D. 0xCB (203) Window Height Context B PDF:6981573426/Source: 7298095240 MT9V034_DS - Rev. D Pub. 5/12 EN 41 Read/ Write R 016 (22) Y 1-255 W 0A (10) Y 1-255 W 1 0 N N 0, 1 0, 1 W W 1 N 0-7 W 0 Y 0, 1 W 0 Y 0, 1 W 16 (22) 44 (68) N 0-255 W N 0-255 W N 0-255 W N 0-255 W 000 (1) N 0-752 W 004 (4) N 4-2482 W 21 (33) 44 (68) . (c)2008 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9V034: 1/3-Inch Wide-VGA Digital Image Sensor Registers Table 9: Bit 8:0 Register Descriptions (continued) Bit Name Shadowed Legal Values (Dec) Read/ Write 1E0 (480) N 1-480 W 2F0 (752) N 1-752 W 05E (94) N 61-71023 W 002D (45) N 2-32288 W 1DE (478) N 0-32765 W Default in Hex (Dec) Bit Description Window Height Number of rows in the image to be read out (not counting any dark rows or border rows that may be read). 0xCC (204) Window Width Context B 9:0 Window Width Number of columns in image to be read out (not counting any dark columns or border columns that may be read). 0xCD(205) Horizontal Blanking Context B 9:0 Horizontal Number of blank columns in a row. Blanking Minimum horizontal blanking is 61 for normal mode, 71 for column bin 2 mode, and 91 for column bin 4 mode 0xCE(206) Vertical Blanking Context B 14:0 Vertical Blanking Number of blank rows in a frame. V-Blank value must meet the following minimums: Linear Mode: V-Blank (min) = (SW_total - SW1 + 7) = SW_total - R0x08 + 7 If manual exposure, then SW_total = R0xD2. If auto-exposure mode then SW_total = R0xAD. High Dynamic Range Mode: If Auto-Knee Point disabled, then above equations apply. If Auto-Knee Point enabled, then V-Blank (min) = (t2 + t3 + 7). Note: Calculate t2 and t3 taking into account Auto Exposure setting. Note: When Sequential Mode is enabled, this register is ineffective. Vertical blank = exposure + 6 rows. 0xCF(207) Coarse Shutter Width 1 Context B 14:0 Coarse Shutter The row number in which the first knee occurs. This Width 1 may be used when high dynamic range is enabled (R0x0F[8] = 1) is enabled & exposure knee point auto adjust is disabled (R0xD1[8] = 0). This register is not shadowed, but any change made does not take effect until the following new frame. This register minimum value is 2, for either linear or HDR modes. Note: t1 = Shutter width 1; t2 = Shutter width 2 - Shutter width 1; t3 = total integration - Shutter width 2 0xD0(208) Coarse Shutter Width 2 Context B PDF:6981573426/Source: 7298095240 MT9V034_DS - Rev. D Pub. 5/12 EN 42 . (c)2008 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9V034: 1/3-Inch Wide-VGA Digital Image Sensor Registers Table 9: Bit 14:0 Register Descriptions (continued) Bit Name Coarse Shutter Width 2 Bit Description The row number in which the second knee occurs. This may be used only when high dynamic range is enabled & exposure knee point auto adjust control bit is disabled. This register is not shadowed, but any change made does not take effect until the following new frame. Note: t1 = Shutter width 1; t2 = Shutter width 2 - Shutter width 1; t3 = total integration - Shutter width 2 0xD1(209) Shutter Width Control Context B 3:0 T2 Ratio One-half to the power of this value indicates the ratio of duration time t2, when saturation control gate is adjusted to level V2, to total coarse integration when exposure knee point auto adjust control bit is enabled. This register is not shadowed, but any change made does not take effect until the following new frame. 7:4 T3 Ratio Shadowed Legal Values (Dec) Read/ Write 1DE (479) N 0-32765 W 4 N 0-15 W 6 N 0-15 W 1 N 0,1 W 0 N 0,1 W 1E0 (480) N 0-32765 W Default in Hex (Dec) T2 = total coarse integration * (1/2)t2_ratio One-half to the power of this value indicates the ratio of duration time t3, when saturation control gate is adjusted to level V3, to total coarse integration when exposure knee point auto adjust control bit is enabled. This register is not shadowed, but any change made does not take effect until the following new frame. T3 = total coarse integration * (1/2)t3_ratio Note: t1 = total coarse integration - t2 - t3 Exposure Knee 0 = Auto adjust disabled. Point Auto Adjust 1 = Auto adjust enabled. Enable 9 Single Knee 1 = Single knee enabled. Enable 0xD2 (210) Coarse Shutter Width Total Context B 14:0 Coarse Shutter Total integration time in number of rows. This value is Width Total used only when AEC is disabled only (bit 0 of Register 175). This register is not shadowed, but any change made does not take effect until the following new frame. 0xD3 (211) Fine Shutter Width 1 Context A 8 PDF:6981573426/Source: 7298095240 MT9V034_DS - Rev. D Pub. 5/12 EN 43 . (c)2008 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9V034: 1/3-Inch Wide-VGA Digital Image Sensor Registers Table 9: Bit 10:0 Register Descriptions (continued) Bit Name Bit Description Fine Shutter Width 1 This register, combined with Coarse Shutter Width 1, defines the time when the first knee occurs. This may be used only when high dynamic range is enabled and the exposure knee point auto-adjust control bit is disabled. This register is not shadowed, but any change made does not take effect until the following new frame. Register units are master clock cycles. Operational maximum is (row time - 1) = (Window Width + HBLANK - 1) Total maximum is HBLANK (R0x05) + 751 = 1023 + 751 = 1774 Notes: t1 = Shutter width 1 t2 = Shutter width 2 - Shutter width 1 t3 = Total integration - Shutter width 2 0xD4 (212) Fine Shutter Width 2 Context A 10:0 Fine Shutter This register, combined with Coarse Shutter Width 2, Width 2 defines the time when the second knee occurs. This may be used only when high dynamic range is enabled and the exposure knee point auto-adjust control bit is disabled. This register is not shadowed, but any change made does not take effect until the following new frame. Register units are master clock cycles. Maximum is HBLANK (R0x05) + 751 = 1023 + 751 = 1774 Notes: t1 = Shutter width 1 t2 = Shutter width 2 - Shutter width 1 t3 = Total integration - Shutter width 2 0xD5 (213) Fine Shutter Width Total Context A 10:0 Fine Shutter This register, combined with Coarse Shutter Width Total Width Total, defines the total integration time. This register is not shadowed, but any change made does not take effect until the following new frame. Register units are master clock cycles. Maximum is HBLANK (R0x05) + 751 = 1023 + 751 = 1774 Note: When Coarse Shutter Width Total is zero, Minimum Fine Shutter Width = 260 0xD6 (214) Fine Shutter Width 1 Context B PDF:6981573426/Source: 7298095240 MT9V034_DS - Rev. D Pub. 5/12 EN Shadowed Legal Values (Dec) Read/ Write 0 (0) N 0-1774 W 0 (0) N 0-1774 W 0 (0) N 0-1774 W Default in Hex (Dec) 44 . (c)2008 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9V034: 1/3-Inch Wide-VGA Digital Image Sensor Registers Table 9: Bit 10:0 Register Descriptions (continued) Bit Name Bit Description Fine Shutter Width 1 This register, combined with Coarse Shutter Width 1, defines the time when the first knee occurs. This may be used only when high dynamic range is enabled and the exposure knee point auto adjust control bit is disabled. This register is not shadowed, but any change made does not take effect until the following new frame. Register units are master clock cycles. Maximum is HBLANK (R0x05) + 751 = 1023 + 751 = 1774 Notes: t1 = Shutter width 1 t2 = Shutter width 2 - Shutter width 1 t3 = Total integration - Shutter width 2 0xD7 (215) Fine Shutter Width 2 Context B 10:0 Fine Shutter This register, combined with Coarse Shutter Width 2, Width 2 defines the time when the second knee occurs. This may be used only when high dynamic range is enabled and the exposure knee point auto adjust control bit is disabled. This register is not shadowed, but any change made does not take effect until the following new frame. Register units are master clock cycles. Maximum is HBLANK (R0x05) + 751 = 1023 + 751 = 1774 Notes: t1 = Shutter width 1 t2 = Shutter width 2 - Shutter width 1 t3 = Total integration - Shutter width 2 0xD8 (216) Fine Shutter Width Total Context B 10:0 Fine Shutter This register, combined with Coarse Shutter Width Width Total Total, defines the total integration time. This register is not shadowed, but any change made does not take effect until the following new frame. Register units are in master clock cycles. Maximum is HBLANK (R0x05) + 751 = 1023 + 751 = 1774 Note: When Coarse Shutter Width Total is zero, Minimum Fine Shutter Width = 260 0xD9 (217) Monitor Mode 10:0 Monitor Mode Setting this bit puts the sensor into a cycle of sleeping Enable for approximately five minutes, and waking up to capture a programmable number of frames (Register 0XC0). Clearing this bit will resume normal operation. PDF:6981573426/Source: 7298095240 MT9V034_DS - Rev. D Pub. 5/12 EN Shadowed Legal Values (Dec) Read/ Write 0 (0) N 0-1774 W 0 (0) N 0-1774 W 0 (0) N 0-1774 W 0 (0) Y 0-1 W Default in Hex (Dec) 45 . (c)2008 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9V034: 1/3-Inch Wide-VGA Digital Image Sensor Registers Table 9: Bit Register Descriptions (continued) Bit Name Default in Hex (Dec) Bit Description 0xF0 (240) Bytewise Address Bytewise Address Special address to perform 8-bit reads and writes to the sensor. See Two-Wire Interface description for further details on how to use this functionality. 0xFE (254) Register Lock 15:0 Register Lock Code To lock all registers except R0xFE, program data with 0xDEAD; to unlock access to all registers, program data with 0xBEEF. To lock Registers 0x0D and 0x0E only, program data with 0xDEAF; to unlock, program data with 0xBEEF. While R0x0D and R0x0E are locked, any subsequent writes to those registers will be ignored until registers are unlocked. PDF:6981573426/Source: 7298095240 MT9V034_DS - Rev. D Pub. 5/12 EN 46 BEEF (48,879) Shadowed N Legal Values (Dec) 48879 (0xBEEF), 57005 (0xDEAD), 57007 (0xDEAF) Read/ Write W . (c)2008 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9V034: 1/3-Inch Wide-VGA Digital Image Sensor Feature Description Feature Description Operational Modes The MT9V034 works in master, snapshot, or slave mode. In master mode the sensor generates the readout timing. In snapshot mode it accepts an external trigger to start integration, then generates the readout timing. In slave mode the sensor accepts both external integration and readout controls. The integration time is programmed through the two-wire serial interface during master or snapshot modes, or controlled through an externally generated control signal during slave mode. Master Mode There are two possible operation methods for master mode: simultaneous and sequential. One of these operation modes must be selected through the two-wire serial interface. Simultaneous Master Mode In simultaneous master mode, the exposure period occurs during readout. The frame synchronization waveforms are shown in Figure 13 and Figure 14. The exposure and readout happen in parallel rather than sequential, making this the fastest mode of operation. Figure 13: Simultaneous Master Mode Synchronization Waveforms #1 Readout Time > Exposure Time LED_OUT Exposure Time Vertical Blanking FRAME_VALID LINE_VALID DOUT(9:0) Figure 14: xxx xxx xxx Simultaneous Master Mode Synchronization Waveforms #2 Exposure Time > Readout Time LED_OUT Exposure Time Vertical Blanking FRAME_VALID LINE_VALID DOUT(9:0) PDF:6981573426/Source: 7298095240 MT9V034_DS - Rev. D Pub. 5/12 EN xxx xxx 47 xxx . (c)2008 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9V034: 1/3-Inch Wide-VGA Digital Image Sensor Feature Description When exposure time is greater than the sum of vertical blank and window height, the number of vertical blank rows is increased automatically to accommodate the exposure time. Sequential Master Mode In sequential master mode the exposure period is followed by readout. The frame synchronization waveforms for sequential master mode are shown in Figure 15. The frame rate changes as the integration time changes. Figure 15: Sequential Master Mode Synchronization Waveforms Exposure Time LED_OUT FRAME_VALID LINE_VALID DOUT(9:0) xxx xxx xxx Snapshot Mode In snapshot mode the sensor accepts an input trigger signal which initiates exposure, and is immediately followed by readout. Figure 16 shows the interface signals used in snapshot mode. In snapshot mode, the start of the integration period is determined by the externally applied EXPOSURE pulse that is input to the MT9V034. The integration time is preprogrammed at R0x0B or R0xD2 through the two-wire serial interface. After the frame's integration period is complete the readout process commences and the syncs and data are output. Sensor in snapshot mode can capture a single image or a sequence of images. The frame rate may only be controlled by changing the period of the user supplied EXPOSURE pulse train. The frame synchronization waveforms for snapshot mode are shown in Figure 17. Figure 16: Snapshot Mode Interface Signals EXPOSURE SYSCLK PIXCLK CONTROLLER LINE_VALID FRAME_VALID MT9V034 DOUT(9:0) PDF:6981573426/Source: 7298095240 MT9V034_DS - Rev. D Pub. 5/12 EN 48 . (c)2008 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9V034: 1/3-Inch Wide-VGA Digital Image Sensor Feature Description Figure 17: Snapshot Mode Frame Synchronization Waveforms EXPOSURE Exposure Time LED_OUT FRAME_VALID LINE_VALID DOUT(9:0) xxx xxx xxx Slave Mode In slave mode, the exposure and readout are controlled using the EXPOSURE, STFRM_OUT, and STLN_OUT pins. When the slave mode is enabled, STFRM_OUT and STLN_OUT become input pins. The start and end of integration are controlled by EXPOSURE and STFRM_OUT pulses, respectively. While a STFRM_OUT pulse is used to stop integration, it is also used to enable the readout process. After integration is stopped, the user provides STLN_OUT pulses to trigger row readout. A full row of data is read out with each STLN_OUT pulse. The user must provide enough time between successive STLN_OUT pulses to allow the complete readout of one row. It is also important to provide additional STLN_OUT pulses to allow the sensors to read the vertical blanking rows. It is recommended that the user program the vertical blank register (R0x06) with a value of 4, and achieve additional vertical blanking between frames by delaying the application of the STFRM_OUT pulse. The elapsed time between the rising edge of STLN_OUT and the first valid pixel data is calculated for context A by [horizontal blanking register (R0x05) + 4] clock cycles. For context B, the time is (R0xCD + 4) clock cycles. Figure 18: Slave Mode Operation Exposure (input) STFRM_OUT (input) LED_OUT (output) STLN_OUT (input) LINE_V ALID (output) Integration T ime Vertical Blanking PDF:6981573426/Source: 7298095240 MT9V034_DS - Rev. D Pub. 5/12 EN 49 . (c)2008 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9V034: 1/3-Inch Wide-VGA Digital Image Sensor Feature Description Signal Path The MT9V034 signal path consists of a programmable gain, a programmable analog offset, and a 10-bit ADC. See "Black Level Calibration" on page 59 for the programmable offset operation description. Figure 19: Signal Path Gain Selection (R0x35 or R0x36 or result of AGC) Pixel Output (reset minus signal) Offset Correction Voltage (R0x48 or result of BLC) VREF (R0x2C) 10 (12) bit ADC ADC Data (9:0) C1 C2 On-Chip Biases ADC Voltage Reference The ADC voltage reference is programmed through R0x2C, bits 2:0. The ADC reference ranges from 1.0V to 2.1V. The default value is 1.4V. The increment size of the voltage reference is 0.1V from 1.0V to 1.6V (R0x2C[2:0] values 0 to 6). At R0x2C[2:0] = 7, the reference voltage jumps to 2.1V. It is very important to preserve the correct values of the other bits in R0x2C. The default register setting is 0x0004. This corresponds to 1.4V--at this setting 1mV input to the ADC equals approximately 1 LSB. V_Step Voltage Reference This voltage is used for pixel high dynamic range operations, programmable from R0x31 through R0x34 for Context A, or R0x39 through R0x3B for context B. Chip Version Chip version register R0x00 is read-only. Window Control Registers Column Start A/B, Row Start A/B, Window Height A/B (row size), and Window Width (column size) A/B control the size and starting coordinates of the window. The values programmed in the window height and width registers are the exact window height and width out of the sensor. The window start value should never be set below four. To read out the dark rows set bit 6 of R0x0D. In addition, bit 7 of R0x0D can be used to display the dark columns in the image. Note that there are Show Dark settings only for Context A. PDF:6981573426/Source: 7298095240 MT9V034_DS - Rev. D Pub. 5/12 EN 50 . (c)2008 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9V034: 1/3-Inch Wide-VGA Digital Image Sensor Feature Description Blanking Control Horizontal Blank and Vertical Blank registers R0x05 and R0x06 (B: 0xCD and R0xCE), respectively, control the blanking time in a row (horizontal blanking) and between frames (vertical blanking). * Horizontal blanking is specified in terms of pixel clocks. * Vertical blanking is specified in terms of numbers of rows. The actual imager timing can be calculated using Table 4 on page 13 and Table 5 on page 14 which describe "Row Timing and FV/LV signals." The minimum number of vertical blank rows is 4. PDF:6981573426/Source: 7298095240 MT9V034_DS - Rev. D Pub. 5/12 EN 51 . (c)2008 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9V034: 1/3-Inch Wide-VGA Digital Image Sensor Feature Description Pixel Integration Control Total Integration Total integration time is the result of coarse shutter width and fine shutter width registers, and depends also on whether manual or automatic exposure is selected. The actual total integration time, tINT is defined as: tINT = tINTCoarse + tINTFint (EQ 2) = (number of rows of integration x row time) + (number of pixels of integration x pixel time) where: Number of Rows of Integration (Auto Exposure Control: Enabled) When automatic exposure control (AEC) is enabled, the number of rows of integration may vary from frame to frame, with the limits controlled by R0xAC (minimum coarse shutter width) and R0xAD (maximum coarse shutter width). Number of Rows of Integration (Auto Exposure Control: Disabled) If AEC is disabled, the number of rows of integration equals the value in R0x0B. or If context B is enabled, the number of rows of integration equals the value in R0xD2. Number of Pixels of Integration The number of fine shutter width pixels is independent of AEC mode (enabled or disabled): * Context A: the number of pixels of integration equals the value in R0xD5. * Context B: the number of pixels of integration equals the value in R0xD8. Row Timing Context A: Row time = (R0x04 + R0x05) master clock periods (EQ 3) Context B: Row time = (R0xCC + R0xCD) master clock periods (EQ 4) Typically, the value of the Coarse Shutter Width Total registers is limited to the number of rows per frame (which includes vertical blanking rows), such that the frame rate is not affected by the integration time. If the Coarse Shutter Width Total is increased beyond the total number of rows per frame, the user must add additional blanking rows using the Vertical Blanking registers as needed. See descriptions of the Vertical Blanking registers, R0x06 and R0xCE in Table 8 on page 21 and Table 9 on page 25. A second constraint is that tINT must be adjusted to avoid banding in the image from light flicker. Under 60Hz flicker, this means the frame time must be a multiple of 1/120 of a second. Under 50Hz flicker, the frame time must be a multiple of 1/100 of a second. PDF:6981573426/Source: 7298095240 MT9V034_DS - Rev. D Pub. 5/12 EN 52 . (c)2008 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9V034: 1/3-Inch Wide-VGA Digital Image Sensor Feature Description Changes to Integration Time With automatic exposure control disabled (R0xAF[0] for context A, or R0xAF[8] for context B) and if the total integration time (R0x0B or R0xD2) is changed through the two-wire serial interface while FV is asserted for frame n, the first frame output using the new integration time is frame (n + 2). Similarly, when automatic exposure control is enabled, any change to the integration time for frame n first appears in frame (n + 2) output. The sequence is as follows: 1. During frame n, the new integration time is held in the R0x0B or R0D2 live register. 2. At the start of frame (n + 1), the new integration time is transferred to the exposure control module. Integration for each row of frame (n + 1) has been completed using the old integration time. The earliest time that a row can start integrating using the new integration time is immediately after that row has been read for frame (n + 1). The actual time that rows start integrating using the new integration time is dependent on the new value of the integration time. 3. When frame (n + 1) is read out, it is integrated using the new integration time. If the integration time is changed (R0x0B or R0xD2 written) on successive frames, each value written is applied to a single frame; the latency between writing a value and it affecting the frame readout remains at two frames. However, when automatic exposure control is disabled, if the integration time is changed through the two-wire serial interface after the falling edge of FV for frame n, the first frame output using the new integration time becomes frame (n + 3). Figure 20: Latency When Changing Integration FRAME_VALID New Integration Programmed Actual Integration Int = 200 rows Int = 300 rows Int = 200 rows Int = 300 rows LED_OUT Output image with Int = 200 rows Image Data Output image with Int = 300 rows Frame Start PDF:6981573426/Source: 7298095240 MT9V034_DS - Rev. D Pub. 5/12 EN 53 . (c)2008 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9V034: 1/3-Inch Wide-VGA Digital Image Sensor Feature Description Exposure Indicator The exposure indicator is controlled by: * R0x1B LED_OUT Control The MT9V034 provides an output pin, LED_OUT, to indicate when the exposure takes place. When R0x1B bit 0 is clear, LED_OUT is HIGH during exposure. By using R0x1B, bit 1, the polarity of the LED_OUT pin can be inverted. High Dynamic Range High dynamic range is controlled by: High Dynamic Enable Shutter Width 1 Shutter Width 2 Shutter Width Control V_Step Voltages Context A Context B R0x0F[0] R0x08 R0x09 R0x0A R0x31-R0x34 R0x0F[8] R0xCF R0xD0 R0xD1 R0x39-R0x3C In the MT9V034, high dynamic range (by setting R0x0F, bit 0 or 8 to 1) is achieved by controlling the saturation level of the pixel (HDR or high dynamic range gate) during the exposure period. The sequence of the control voltages at the HDR gate is shown in Figure 21. After the pixels are reset, the step voltage, V_Step, which is applied to HDR gate, is set up at V1 for integration time t1, then to V2 for time t2, then V3 for time t3, and finally it is parked at V4, which also serves as an antiblooming voltage for the photodetector. This sequence of voltages leads to a piecewise linear pixel response, illustrated (approximately) in Figure 21 and Figure 22 on page 55. Figure 21: Sequence of Control Voltages at the HDR Gate Exposure VAA (3.3V) V1~1.4V HDR Voltage PDF:6981573426/Source: 7298095240 MT9V034_DS - Rev. D Pub. 5/12 EN t1 54 V2~1.2V V3~1.0V V4~0.8V t2 t3 . (c)2008 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9V034: 1/3-Inch Wide-VGA Digital Image Sensor Feature Description Figure 22: Sequence of Voltages in a Piecewise Linear Pixel Response dV3 Output dV2 dV1 Light Intensity 1/t 1/t 1 1/t 2 3 The parameters of the step voltage V_Step which takes values V1, V2, and V3 directly affect the position of the knee points in Figure 22. Light intensities work approximately as a reciprocal of the partial exposure time. Typically, t1 is the longest exposure, t2 shorter, and so on. Thus the range of light intensities is shortest for the first slope, providing the highest sensitivity. The register settings for V_Step and partial exposures are: V1 = R0x31, bits 5:0 (Context B: R0x39, bits 5:0) V2 = R0x32, bits 5:0 (Context B: R0x3A, bits 5:0) V3 = R0x33, bits 5:0 (Context B: R0x3B, bits 5:0) V4 = R0x34, bits 5:0 (Context B: R0x3C, bits 5:0) t INT = t1 + t2 + t3 There are two ways to specify the knee points timing, the first by manual setting and the second by automatic knee point adjustment. Knee point auto adjust is controlled for context A by R0x0A[8] (where default is ON), and for context B by R0xD1[8] (where default is OFF ). When the knee point auto adjust enabler is enabled (set HIGH), the MT9V034 calculates the knee points automatically using the following equations: t 1 = tINT - t2 - t3 (EQ 5) t2 = tINT x (1/2)R0x0A[3:0] or R0xD1[3:0] (EQ 6) t3 = tINT x (1/2)R0x0A[7:4] or R0xD1[7:4] t t (EQ 7) t t As a default for auto exposure, 2 is 1/16 of INT, 3 is 1/64 of INT. When the auto adjust enabler is disabled (set LOW), t1, t2, and t3 may be programmed through the two-wire serial interface: t 1 = Coarse SW1 (row-times) + Fine SW1 (pixel-times) (EQ 8) t2 = Coarse SW2 - Coarse SW1 + Fine SW2 - Fine SW1 (EQ 9) t3 = Total Integration - t1 - t2 (EQ 10) t t = Coarse Total Shutter Width + Fine Shutter Width Total - 1 - 2 PDF:6981573426/Source: 7298095240 MT9V034_DS - Rev. D Pub. 5/12 EN 55 . (c)2008 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9V034: 1/3-Inch Wide-VGA Digital Image Sensor Feature Description For context A these become: t1 = R0x08 + R0xD3 (EQ 11) t2 = R0x09 - R0x08 + R0xD4 - R0xD3 (EQ 12) t (EQ 13) 3 = R0x0B + R0xD4 - t1 - t2 For context B these are: t 1 = R0xCF + R0xD6 t 2 = R0xD0 - R0xCF + R0xD7 - R0xD6 t (EQ 14) t (EQ 15) t 3 = R0xD2 + R0xD8 - 1 - 2 (EQ 16) In all cases above, the coarse component of total integration time may be based on the result of AEC or values in Reg0x0B and Reg0xD2, depending on the settings. Similar to Fine Shutter Width Total registers, the user must not set the Fine Shutter Width 1 or Fine Shutter Width 2 register to exceed the row time (Horizontal Blanking + Window Width). The absolute maximum value for the Fine Shutter Width registers is 1774 master clocks. ADC Companding Mode By default, ADC resolution of the sensor is 10-bit. Additionally, a companding scheme of 12-bit into 10-bit is enabled by the ADC Companding Mode register. This mode allows higher ADC resolution, which means less quantization noise at low-light, and lower resolution at high light, where good ADC quantization is not so critical because of the high level of the photon's shot noise. Figure 23: 12- to 10-Bit Companding Chart 10-bit Codes 1,024 768 8 to 1 Companding (2,048 4 to 1 Companding (1,536 512 256 2 to 1 Companding (256 No companding (256 256 512 1,024 PDF:6981573426/Source: 7298095240 MT9V034_DS - Rev. D Pub. 5/12 EN 384) 128) 12-bit Codes 256) 2,048 56 256) 4,096 . (c)2008 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9V034: 1/3-Inch Wide-VGA Digital Image Sensor Feature Description Gain Settings Changes to Gain Settings When the digital gain settings (R0x80-R0x98) are changed, the gain is updated on the next frame start. However, the latency for an analog gain change to take effect depends on the automatic gain control. If automatic gain control is enabled (R0xAF, bit 1 is set to HIGH), the gain changed for frame n first appears in frame (n + 1); if the automatic gain control is disabled, the gain changed for frame n first appears in frame (n + 2). Both analog and digital gain change regardless of whether the integration time is also changed simultaneously. Figure 24: Latency of Analog Gain Change When AGC Is Disabled FRAME_VALID New Gain Programmed Gain = 3.0X Actual Gain Gain = 3.5X Gain = 3.0X Output image with Gain = 3.0X Image Data Gain = 3.5X Output image with Gain = 3.5X Frame Start PDF:6981573426/Source: 7298095240 MT9V034_DS - Rev. D Pub. 5/12 EN 57 . (c)2008 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9V034: 1/3-Inch Wide-VGA Digital Image Sensor Feature Description Analog Gain Analog gain is controlled by: * R0x35 Global Gain context A * R0x36 Global Gain context B The formula for gain setting is: Gain = Bits[6:0] x 0.0625 (EQ 17) The analog gain range supported in the MT9V034 is 1X-4X with a step size of 6.25 percent. To control gain manually with this register, the sensor must NOT be in AGC mode. When adjusting the luminosity of an image, it is recommended to alter exposure first and yield to gain increases only when the exposure value has reached a maximum limit. Analog gain = bits (6:0) x 0.0625 for values 16-31 Analog gain = bits (6:0)/2 x 0.125 for values 32-64 For values 16-31: each LSB increases analog gain 0.0625v/v. A value of 16 = 1X gain. Range: 1X to 1.9375X. For values 32-64: each 2 LSB increases analog gain 0.125v/v (that is, double the gain increase for 2 LSB). Range: 2X to 4X. Odd values do not result in gain increases; the gain increases by 0.125 for values 32, 34, 36, and so on. Digital Gain Digital gain is controlled by: * R0x99-R0xA4 Tile Coordinates * R0x80-R0x98 Tiled Digital Gain and Weight In the MT9V034, the gain logic divides the image into 25 tiles, as shown in Figure 25 on page 59. The size and gain of each tile can be adjusted using the above digital gain control registers. Separate tile gains can be assigned for context A and context B. Registers 0x99-0x9E and 0x9F-0xA4 represent the coordinates X0/5-X5/5 and Y0/5-Y5/5 in Figure 25 on page 59, respectively. Digital gains of registers 0x80-0x98 apply to their corresponding tiles. The MT9V034 supports a digital gain of 0.25-3.75X. When binning is enabled, the tile offsets maintain their absolute values; that is, tile coordinates do not scale with row or column bin setting. Note: There is one exception, for the condition when Column Bin 4 is enabled (R0x0D[3:2] or R0x0E[3:2] = 2). For this case, the value for Digital Tile Coordinate X-direction must be doubled. The formula for digital gain setting is: Digital Gain = Bits[3:0] x 0.25 PDF:6981573426/Source: 7298095240 MT9V034_DS - Rev. D Pub. 5/12 EN 58 (EQ 18) . (c)2008 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9V034: 1/3-Inch Wide-VGA Digital Image Sensor Feature Description Figure 25: Tiled Sample X0/5 X1/5 X2/5 X3/5 Y0/5 x0_y0 x1_y0 X4/5 X5/5 x4_y0 Y1/5 x0_y1 x1_y1 x4_y1 x0_y2 x1_y2 x4_y2 x0_y3 x1_y3 x4_y3 x0_y4 x1_y4 x4_y4 Y2/5 Y3/5 Y4/5 Y5/5 Black Level Calibration Black level calibration is controlled by: * Frame Dark Average: R0x42 * Dark Average Thresholds: R0x46 * Black Level Calibration Control: R0x47 * Black Level Calibration Value: R0x48 * Black Level Calibration Value Step Size: R0x4C The MT9V034 has automatic black level calibration on-chip, and if enabled, its result may be used in the offset correction shown in Figure 26. Figure 26: Black Level Calibration Flow Chart Gain Selection (R0x35 or R0x36 or result of AGC) Pixel Output (reset minus signal) Offset Correction Voltage (R0x48 or result of BLC) VREF (R0x2C) 10 (12) bit ADC ADC Data (9:0) C1 C2 PDF:6981573426/Source: 7298095240 MT9V034_DS - Rev. D Pub. 5/12 EN 59 . (c)2008 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9V034: 1/3-Inch Wide-VGA Digital Image Sensor Feature Description The automatic black level calibration measures the average value of pixels from 2 dark rows (1 dark row if row bin 4 is enabled) of the chip. (The pixels are averaged as if they were light-sensitive and passed through the appropriate gain.) This row average is then digitally low-pass filtered over many frames (R0x47, bits 7:5) to remove temporal noise and random instabilities associated with this measurement. Then, the new filtered average is compared to a minimum acceptable level, low threshold, and a maximum acceptable level, high threshold. If the average is lower than the minimum acceptable level, the offset correction voltage is increased by a programmable offset LSB in R0x4C. (Default step size is 2 LSB Offset = 1 ADC LSB at analog gain = 1X.) If it is above the maximum level, the offset correction voltage is decreased by 2 LSB (default). To avoid oscillation of the black level from below to above, the region the thresholds should be programmed so the difference is at least two times the offset DAC step size. In normal operation, the black level calibration value/offset correction value is calculated at the beginning of each frame and can be read through the two-wire serial interface from R0x48. This register is an 8-bit signed two's complement value. However, if R0x47, bit 0 is set to "1," the calibration value in R0x48 is used rather than the automatic black level calculation result. This feature can be used in conjunction with the "show dark rows" feature (R0x0D[6]) if using an external black level calibration circuit. The offset correction voltage is generated according to the following formulas: Offset Correction Voltage = (8-bit signed two's complement calibration value,-127 to 127) x 0.5mV (EQ 19) ADC input voltage = (Pixel Output Voltage + Offset Correction Voltage) x Analog Gain (EQ 20) PDF:6981573426/Source: 7298095240 MT9V034_DS - Rev. D Pub. 5/12 EN 60 . (c)2008 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9V034: 1/3-Inch Wide-VGA Digital Image Sensor Feature Description Row-wise Noise Correction Row-wise noise correction is controlled by the following registers: * R0x70 Row Noise Control * R0x72 Row Noise Constant Row-wise noise cancellation is performed by calculating a row average from a set of optically black pixels at the start of each row and then applying each average to all the active pixels of the row. Read Dark Columns register bit and Row Noise Correction Enable register bit must both be set to enable row-wise noise cancellation to be performed. The behavior when Read Dark Columns register bit = 0 and Row Noise Correction Enable register bit = 1 is undefined. The algorithm works as follows: Logical columns 755-790 in the pixel array provide 36 optically black pixel values. Of the 36 values, two smallest value and two largest values are discarded. The remaining 32 values are averaged by summing them and discarding the 5 LSB of the result. The 10-bit result is subtracted from each pixel value on the row in turn. In addition, a positive constant will be added (Reg0x71, bits 7:0). This constant should be set to the dark level targeted by the black level algorithm plus the noise expected on the measurements of the averaged values from dark columns; it is meant to prevent clipping from negative noise fluctuations. Pixel value = ADC value - dark column average + R0x71[9:0] (EQ 21) Note that this algorithm does not work in color sensor. Automatic Gain Control and Automatic Exposure Control The integrated AEC/AGC unit is responsible for ensuring that optimal auto settings of exposure and (analog) gain are computed and updated every frame. AEC and AGC can be individually enabled or disabled by R0xAF. When AEC is disabled (R0xAF[0] = 0), the sensor uses the manual exposure value in coarse and fine shutter width registers. When AGC is disabled (R0xAF[1] = 0), the sensor uses the manual gain value in R0x35 or R0x36. See "Pixel Integration Control" on page 52 for more information. PDF:6981573426/Source: 7298095240 MT9V034_DS - Rev. D Pub. 5/12 EN 61 . (c)2008 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9V034: 1/3-Inch Wide-VGA Digital Image Sensor Feature Description Figure 27: Controllable and Observable AEC/AGC Registers EXP. LPF (R0xA8) MAX. EXPOSURE (R0xBD) EXP. SKIP (R0xA6) Coarse Shutter Width Total AEC UNIT CURRENT BIN (current luminance) (R0xBC) MIN EXPOSURE (R0xAC) DESIRED BIN (desired luminance) (R0xA5) AEC OUTPUT 16 0 To exposure timing control 1 R0xBB HISTOGRAM GENERATOR UNIT AGC OUTPUT MIN GAIN AEC ENABLE (R0xAF[0 or 8]) AGC UNIT MAX. GAIN (R0xAB) 1 To analog gain control 0 R0xBA GAIN LPF (R0xAB) GAIN SKIP (R0xA9) MANUAL GAIN AGC ENABLE A or B (R0xAF[1 or 9]) The exposure is measured in row-time by reading R0xBB. The exposure range is 1 to 2047. The gain is measured in gain-units by reading R0xBA. The gain range is 16 to 63 (unity gain = 16 gain-units; multiply by 1/16 to get the true gain). When AEC is enabled (R0xAF), the maximum auto exposure value is limited by R0xBD; minimum auto exposure is limited by AEC Minimum Exposure, R0xAC. Note: AEC does not support sub-row timing; calculated exposure values are rounded down to the nearest row-time. For smoother response, manual control is recommended for short exposure times. When AGC is enabled (R0xAF), the maximum auto gain value is limited by R0xAB; minimum auto gain is fixed to 16 gain-units. The exposure control measures current scene luminosity and desired output luminosity by accumulating a histogram of pixel values while reading out a frame. All pixels are used, whether in color or mono mode. The desired exposure and gain are then calculated from this for subsequent frame. When binning is enabled, tuning of the AEC may be required. The histogram pixel count register, R0xB0, may be adjusted to reflect the reduced pixel count. Desired bin register, R0xA5, may be adjusted as required. Pixel Clock Speed The pixel clock speed is same as the master clock (SYSCLK) at 26.66 MHz by default. However, when column binning 2 or 4 (R0x0D or R0x0E, bit 2 or 3) is enabled, the pixel clock speed is reduced by half and one-fourth of the master clock speed respectively. See "Read Mode Options" on page 63 and "Column Binning" on page 65 for additional information. PDF:6981573426/Source: 7298095240 MT9V034_DS - Rev. D Pub. 5/12 EN 62 . (c)2008 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9V034: 1/3-Inch Wide-VGA Digital Image Sensor Feature Description Hard Reset of Logic The RC circuit for the MT9V034 uses a 10k resistor and a 0.1F capacitor. The rise time for the RC circuit is 1s maximum. Soft Reset of Logic Soft reset of logic is controlled by: * R0x0C Reset Bit 0 is used to reset the digital logic of the sensor while preserving the existing two-wire serial interface configuration. Furthermore, by asserting the soft reset, the sensor aborts the current frame it is processing and starts a new frame. Bit 1 is a shadowed reset control register bit to explicitly reset the automatic gain and exposure control feature. These two bits are self-resetting bits and also return to "0" during two-wire serial interface reads. STANDBY Control The sensor goes into standby mode by setting STANDBY to HIGH. Once the sensor detects that STANDBY is asserted, it completes the current frame before disabling the digital logic, internal clocks, and analog power enable signal. To release the sensor out from the standby mode, reset STANDBY back to LOW. The LVDS must be powered to ensure that the device is in standby mode. See "Appendix A - PowerOn Reset and Standby Timing" on page 81 for more information on standby. Monitor Mode Control Monitor mode is controlled by: * R0xD9 Monitor Mode Enable * R0xC0 Monitor Mode Image Capture Control The sensor goes into monitor mode when R0xD9[0] is set to HIGH. In this mode, the sensor first captures a programmable number of frames (R0xC0), then goes into a sleep period for five minutes. The cycle of sleeping for five minutes and waking up to capture a number of frames continues until R0xD9[0] is cleared to return to normal operation. In some applications when monitor mode is enabled, the purpose of capturing frames is to calibrate the gain and exposure of the scene using automatic gain and exposure control feature. This feature typically takes less than 10 frames to settle. In case a larger number of frames is needed, the value of R0xC0 may be increased to capture more frames. During the sleep period, none of the analog circuitry and a very small fraction of digital logic (including a five-minute timer) is powered. The master clock (SYSCLK) is therefore always required. Read Mode Options (Also see "Output Data Format" on page 12 and "Output Data Timing" on page 13.) Column Flip By setting bit 5 of R0x0D or R0x0E the readout order of the columns is reversed, as shown in Figure 28 on page 64. PDF:6981573426/Source: 7298095240 MT9V034_DS - Rev. D Pub. 5/12 EN 63 . (c)2008 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9V034: 1/3-Inch Wide-VGA Digital Image Sensor Feature Description Row Flip By setting bit 4 of R0x0D or R0x0E the readout order of the rows is reversed, as shown in Figure 29 on page 64. Figure 28: Readout of Six Pixels in Normal and Column Flip Output Mode LINE_VALID Normal readout DOUT(9:0) Reverse readout DOUT(9:0) Figure 29: P4,1 (9:0) P4,2 (9:0) P4,3 (9:0) P4,4 (9:0) P4,5 (9:0) P4,6 (9:0) P4,n (9:0) P4,n-1 (9:0) P4,n-2 (9:0) P4,n-3 (9:0) P4,n-4 (9:0) P4,n-5 (9:0) Readout of Six Rows in Normal and Row Flip Output Mode LINE_VALID Normal readout DOUT(9:0) Reverse readout DOUT(9:0) Row4 (9:0) Row5 (9:0) Row6 (9:0) Row7 (9:0) Row8 7(9:0) Row9 (9:0) Row484 (9:0) Row483 (9:0) Row482 (9:0) Row481 (9:0) Row480 7(9:0) Row479 (9:0) Pixel Binning In addition to windowing mode in which smaller resolutions (CIF, QCIF) are obtained by selecting a smaller window from the sensor array, the MT9V034 also provides the ability to down-sample the entire image captured by the pixel array using pixel binning. There are two resolution options: binning 2 and binning 4, which reduce resolution by two or by four, respectively. Row and column binning are separately selected. Image mirroring options will work in conjunction with binning. For column binning, either two or four columns are combined by averaging to create the resulting column. For row binning, the binning result value depends on the difference in pixel values: for pixel signal differences of less than 200 LSB's, the result is the average of the pixel values. For pixel differences of greater than 200 LSB's, the result is the value of the darker pixel value. Binning operation increases SNR but decreases resolution. Enabling row bin2 and row bin4 improves frame rate by 2x and 4x, respectively. Column binning does not increase the frame rate. PDF:6981573426/Source: 7298095240 MT9V034_DS - Rev. D Pub. 5/12 EN 64 . (c)2008 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9V034: 1/3-Inch Wide-VGA Digital Image Sensor Feature Description Row Binning By setting bit 0 or 1 of R0x0D or R0x0E, only half or one-fourth of the row set is read out, as shown in Figure 30. The number of rows read out is half or one-fourth of the value set in R0x03. The row binning result depends on the difference in pixel values: for pixel signal differences less than 200 LSB's, the result is the average of the pixel values. For pixel differences of 200 LSB's or more, the result is the value of the darker pixel value. Column Binning For column binning, either two or four columns are combined by averaging to create the result. In setting bit 2 or 3 of R0x0D or R0x0E, the pixel data rate is slowed down by a factor of either two or four, respectively. This is due to the overhead time in the digital pixel data processing chain. As a result, the pixel clock speed is also reduced accordingly. Figure 30: Readout of 8 Pixels in Normal and Row Bin Output Mode LINE_VALID Normal readout DOUT(9:0) Row4 (9:0) Row5 (9:0) Row6 (9:0) Row7 (9:0) Row4 (9:0) Row6 (9:0) Row8 (9:0) Row10 (9:0) Row4 (9:0) Row8 (9:0) Row8 (9:0) Row9 (9:0) Row10 (9:0) Row11 (9:0) LINE_VALID Row Bin 2 readout DOUT(9:0) LINE_VALID Row Bin 4 readout DOUT(9:0) PDF:6981573426/Source: 7298095240 MT9V034_DS - Rev. D Pub. 5/12 EN 65 . (c)2008 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9V034: 1/3-Inch Wide-VGA Digital Image Sensor Feature Description Figure 31: Readout of 8 Pixels in Normal and Column Bin Output Mode _ Normal readout DOUT(9:0) D1 (9:0) D2 (9:0) D3 (9:0) D4 (9:0) D5 (9:0) D6 (9:0) D7 (9:0) D8 (9:0) PIXCLK LINE_VALID Column Bin 2 readout DOUT(9:0) D12 (9:0) D34 (9:0) D56 (9:0) D78 (9:0) PIXCLK LINE_VALID Column Bin 4 readout D1234 (9:0) DOUT(9:0) D5678 (9:0) PIXCLK Interlaced Readout The MT9V034 has two interlaced readout options. By setting R0x07[2:0] = 1, all the evennumbered rows are read out first, followed by a number of programmable field blanking rows (set by R0xBF[7:0]), then the odd-numbered rows, and finally the vertical blanking rows. By setting R0x07[2:0] = 2 only one field row is read out. Consequently, the number of rows read out is half what is set in the window height register. The row start register determines which field gets read out; if the row start register is even, then the even field is read out; if row start address is odd, then the odd field is read out. PDF:6981573426/Source: 7298095240 MT9V034_DS - Rev. D Pub. 5/12 EN 66 . (c)2008 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9V034: 1/3-Inch Wide-VGA Digital Image Sensor Feature Description Figure 32: Spatial Illustration of Interlaced Image Readout P4,1 P4,2 P4,3.....................................P4,n-1 P4,n P6,0 P6,1 P6,2.....................................P6,n-1 P6,n 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 VALID IMAGE - Even Field HORIZONTAL BLANKING Pm-2,0 Pm-2,2.....................................Pm-2,n-2 Pm-2,n Pm,2 Pm,2.....................................Pm,n-1 Pm,n 00 00 00 ..................................... 00 00 00 00 00 00 ..................................... 00 00 00 FIELD BLANKING P5,1 P5,2 P5,3.....................................P5,n-1 P5,n P7,0 P7,1 P7,2.....................................P7,n-1 P7,n 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 VALID IMAGE - Odd Field 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 Pm-3,1 Pm-3,2.....................................Pm-3,n-1 Pm-3,n Pm,1 Pm,1.....................................Pm,n-1 Pm,n VERTICAL BLANKING 00 00 00 ............................................................................................. 00 00 00 00 00 00 ............................................................................................. 00 00 00 When interlaced mode is enabled, the total number of blanking rows are determined by both Field Blanking register (R0xBF) and Vertical Blanking register (R0x06 or R0xCE). The followings are their equations. Field Blanking = R0xBF[7:0] (EQ 22) Vertical Blanking = R0x06[8:0] - R0xBF[7:0] (context A) or R0xCE[8:0] - R0xBF[7:0] (context B) (EQ 23) with minimum vertical blanking requirement = 4 (absolute minimum to operate; see Vertical Blanking Registers description for VBlank minimums for valid image output) (EQ 24) Similar to progressive scan, FV is logic LOW during the valid image row only. Binning should not be used in conjunction with interlaced mode. PDF:6981573426/Source: 7298095240 MT9V034_DS - Rev. D Pub. 5/12 EN 67 . (c)2008 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9V034: 1/3-Inch Wide-VGA Digital Image Sensor Feature Description LINE_VALID By setting bit 2 and 3 of R0x72, the LV signal can get three different output formats. The formats for reading out four rows and two vertical blanking rows are shown in Figure 33. In the last format, the LV signal is the XOR between the continuous LV signal and the FV signal. Figure 33: Different LINE_VALID Formats Default FRAME_VALID LINE_VALID Continuously FRAME_VALID LINE_VALID XOR FRAME_VALID LINE_VALID LVDS Serial (Stand-Alone/Stereo) Output The LVDS interface allows for the streaming of sensor data serially to a standard off-theshelf deserializer up to eight meters away from the sensor. The pixels (and controls) are packeted--12-bit packets for stand-alone mode and 18-bit packets for stereoscopy mode. All serial signalling (CLK and data) is LVDS. The LVDS serial output could either be data from a single sensor (stand-alone) or stream-merged data from two sensors (self and its stereoscopic slave pair). The appendices describe in detail the topologies for both stand-alone and stereoscopic modes. There are two standard deserializers that can be used. One for a stand-alone sensor stream and the other from a stereoscopic stream. The deserializer attached to a standalone sensor is able to reproduce the standard parallel output (8-bit pixel data, LV, FV, and PIXCLK). The deserializer attached to a stereoscopic sensor is able to reproduce 8bit pixel data from each sensor (with embedded LV and FV) and pixel-clk. An additional (simple) piece of logic is required to extract LV and FV from the 8-bit pixel data. Irrespective of the mode (stereoscopy/stand-alone), LV and FV are always embedded in the pixel data. In stereoscopic mode, the two sensors run in lock-step, implying all state machines are in the same state at any given time. This is ensured by the sensor-pair getting their sysclks and sys-resets in the same instance. Configuration writes through the two-wire serial interface are done in such a way that both sensors can get their configuration updates at once. The inter-sensor serial link is designed in such a way that once the slave PLL locks and the data-dly, shft-clk-dly and stream-latency-sel are configured, the master sensor streams valid stereo content irrespective of any variation voltage and/or temperature as long as it is within specification. The configuration values of data-dly, shft-clk-dly and stream-latency-sel are either predetermined from the board-layout or can be empirically determined by reading back the stereo-error flag. This flag is asserted when the two sensor streams are not in sync when merged. The combo_reg is used for out-of-sync diagnosis. PDF:6981573426/Source: 7298095240 MT9V034_DS - Rev. D Pub. 5/12 EN 68 . (c)2008 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9V034: 1/3-Inch Wide-VGA Digital Image Sensor Feature Description Figure 34: Serial Output Format for a 6x2 Frame Internal PIXCLK Internal Parallel Data P41 P42 P43 P44 P45 P46 P51 P52 P53 P54 P55 P56 Internal Line_Valid Internal Frame_Valid External Serial Data Out 1023 Notes: 0 1023 1 P41 P42 P43 P44 P45 P46 2 1 P51 P52 P53 P54 P55 P56 2 3 1. External pixel values of 0, 1, 2, 3, are reserved (they only convey control information). Any raw pixel of value 0, 1, 2 and 3 will be substituted with 4. 2. The external pixel sequence 1023, 0, 1023 is a reserved sequence (conveys control information for legacy support of MT9V021 applications). Any raw pixel sequence of 1023, 0, 1023 will be substituted with an output serial stream of 1023, 4, 1023. LVDS Output Format In stand-alone mode, the packet size is 12 bits (2 frame bits and 10 payload bits); 10-bit pixels or 8-bit pixels can be selected. In 8-bit pixel mode (R0xB6[0] = 0), the packet consists of a start bit, 8-bit pixel data (with sync codes), the line valid bit, the frame valid bit and the stop bit. For 10-bit pixel mode (R0xB6[0] = 1), the packet consists of a start bit, 10-bit pixel data, and the stop bit. Table 10: LVDS Packet Format in Stand-Alone Mode (Stereoscopy Mode Bit De-Asserted) 12-Bit Packet use_10-bit_pixels Bit De-Asserted (8-Bit Mode) use_10-bit_pixels Bit Asserted (10-Bit Mode) Bit[0] Bit[1] Bit2] Bit[3] Bit4] Bit[5] Bit[6] Bit[7] Bit[8] Bit[9] Bit[10] Bit[11] 1'b1 (Start bit) PixelData[2] PixelData[3] PixelData[4] PixelData[5] PixelData[6] PixelData[7] PixelData[8] PixelData[9] LINE_VALID FRAME_VALID 1'b0 (Stop bit) 1'b1 (Start bit) PixelData[0] PixelData[1] PixelData[2] PixelData[3] PixelData[4] PixelData[5] PixelData[6] PixelData[7] PixelData[8] PixelData[9] 1'b0 (Stop bit) In stereoscopic mode, the packet size is 18 bits (2 frame bits and 16 payload bits). The packet consists of a start bit, the master pixel byte (with sync codes), the slave byte (with sync codes), and the stop bit. PDF:6981573426/Source: 7298095240 MT9V034_DS - Rev. D Pub. 5/12 EN 69 . (c)2008 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9V034: 1/3-Inch Wide-VGA Digital Image Sensor Feature Description Table 11: LVDS Packet Format in Stereoscopy Mode (Stereoscopy Mode Bit Asserted) 18-bit Packet Function Bit[0] Bit[1] Bit[2] Bit[3] Bit[4] Bit[5] Bit[6] Bit[7] Bit[8] Bit[9] Bit[10] Bit[11] Bit[12] Bit[13] Bit[14] Bit[15] Bit[16] Bit[17] 1'b1 (Start bit) MasterSensorPixelData[2] MasterSensorPixelData[3] MasterSensorPixelData[4] MasterSensorPixelData[5] MasterSensorPixelData[6] MasterSensorPixelData[7] MasterSensorPixelData[8] MasterSensorPixelData[9] SlaveSensorPixelData[2] SlaveSensorPixelData[3] SlaveSensorPixelData[4] SlaveSensorPixelData[5] SlaveSensorPixelData[6] SlaveSensorPixelData[7] SlaveSensorPixelData[8] SlaveSensorPixelData[9] 1'b0 (Stop bit) Control signals LV and FV can be reconstructed from their respective preceding and succeeding flags that are always embedded within the pixel data in the form of reserved words. Table 12: Reserved Words in the Pixel Data Stream Pixel Data Reserved Word Flag 0 1 2 3 Precedes frame valid assertion Precedes line valid assertion Succeeds line valid de-assertion Succeeds frame valid de-assertion When LVDS mode is enabled along with column binning (bin 2 or bin 4, R0x0D[3:2], the packet size remains the same but the serial pixel data stream repeats itself depending on whether 2X or 4X binning is set: * For bin 2, LVDS outputs double the expected data (post-binning pixel 0,0 is output twice in sequence, followed by pixel 0,1 twice, . . .). * For bin 4, LVDS outputs 4 times the expected data (pixel 0,0 is output 4 times in sequence followed by pixel 0,1 times 4, . . .). The receiving hardware will need to undersample the output stream getting data either every 2 clocks (bin 2) or every 4 (bin 4) clocks. If the sensor provides a pixel whose value is 0,1, 2, or 3 (that is, the same as a reserved word) then the outgoing serial pixel value is switched to 4. PDF:6981573426/Source: 7298095240 MT9V034_DS - Rev. D Pub. 5/12 EN 70 . (c)2008 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9V034: 1/3-Inch Wide-VGA Digital Image Sensor Feature Description LVDS Enable and Disable The Table 13 and Table 14 further explain the state of the LVDS output pins depending on LVDS control settings. When the LVDS block is not used, it may be left powered down to reduce power consumption. Table 13: Table 14: SER_DATAOUT_* state R0xB1[1] LVDS power down R0xB3[4] LVDS data power down SER_DATAOUT_* 0 0 1 1 0 1 0 1 Active Active Z Z R0xB1[1] LVDS power down R0xB2[4] LVDS shift-clk power down SHFT_CLKOUT_* 0 0 1 1 0 1 0 1 Active Z Z Z SHFT_CLK_* state Note: PDF:6981573426/Source: 7298095240 MT9V034_DS - Rev. D Pub. 5/12 EN ERROR pin: When sensor is not in stereo mode, ERROR pin is at LOW. 71 . (c)2008 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9V034: 1/3-Inch Wide-VGA Digital Image Sensor Feature Description LVDS Data Bus Timing The LVDS bus timing waveforms and timing specifications are shown in Table 15 and Figure 35. Figure 35: LVDS Timing Data Rise/Fall Time (10% - 90%) Data Setup Time Data Hold Time LVDS Data Output (SER_DATAOUT_N/P) LVDS Clock Output (Shft_CLKOUT_N/P) Clock Rise/Fall Time (10% - 90%) Table 15: Clock Jitter LVDS AC Timing Specifications VPWR = 3.3V 0.3V; TJ = - 30C to +70C; output load = 100 ; frequency 27 MHz Parameter LVDS clock rise time LVDS clock fall time LVDS data rise time LVDS data fall time LVDS data setup time LVDS data hold time LVDS clock jitter PDF:6981573426/Source: 7298095240 MT9V034_DS - Rev. D Pub. 5/12 EN 72 Minimum Typical Maximum Unit - - - - 0.3 0.1 - 0.22 0.22 0.28 0.28 0.67 1.34 - 0.30 0.30 0.30 0.30 - - 92 ns ns ns ns ns ns ps . (c)2008 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9V034: 1/3-Inch Wide-VGA Digital Image Sensor Electrical Specifications Electrical Specifications Table 16: DC Electrical Characteristics Over Temperature VPWR = 3.3V 0.3V; TJ = - 30C to +70C; Output load = 10pF; Frequency 13 MHz to 27 MHz; LVDS off Symbol Definition VIH VIL IIN Input HIGH voltage Input LOW voltage Input leakage current VOH VOL IOH IOL IPWRA IPIX IPWRD ILVDS IPWRA Standby IPWRD Standby Clock Off IPWRD Standby Clock On Output HIGH voltage Output LOW voltage Output HIGH current Output LOW current Analog supply current Pixel supply current Digital supply current LVDS supply current Analog standby supply current Table 17: Condition Min. Typ. Max. Unit VPWR - 1.4 -5 - - - 1.3 5 V V A VPWR - 0.3 - -11 - - - - - - - - - - 12 1.1 42 13 0.2 - 0.3 - 11 20 3 60 16 3 V V mA mA mA mA mA mA A Digital standby supply current with STDBY = VDD, CLKIN = 0 MHz clock off - 0.1 10 A Digital standby supply current with STDBY= VDD, CLKIN = 27 MHz clock on - 1 2 mA Min. Typ. Max. Unit 250 - - - 400 50 mV mV 1.0 - 1.2 - 1.4 35 mV mV No pull-up resistor; VIN = VPWR or VGND IOH = -4.0mA IOL = 4.0mA VOH = VDD - 0.7 VOL = 0.7 Default settings Default settings Default settings, CLOAD = 10pF Default settings with LVDS on STDBY = VDD DC Electrical Characteristics VPWR = 3.3V 0.3V; TA = Ambient = 25C Symbol Definition Condition LVDS Driver DC Specifications |VOD| |DVOD| VOS DVOS Output differential voltage Change in VOD between complementary output states Output offset voltage Pixel array current RLOAD = 100 1% IOS IOZ 10 1 Digital supply current Output current when driver is tristate mA A LVDS Receiver DC Specifications VIDTH+ Iin Input differential Input current PDF:6981573426/Source: 7298095240 MT9V034_DS - Rev. D Pub. 5/12 EN | VGPD| < 925mV 73 -100 - - - 100 20 mV A . (c)2008 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9V034: 1/3-Inch Wide-VGA Digital Image Sensor Electrical Specifications Table 18: Absolute Maximum Ratings Caution Stresses greater than those listed may cause permanent damage to the device. Symbol Parameter Min. Max. Unit VSUPPLY ISUPPLY IGND VIN VOUT TSTGNote: Power supply voltage (all supplies) Total power supply current Total ground current DC input voltage DC output voltage Storage temperature -0.3 - - -0.3 -0.3 -40 4.5 200 200 VDD + 0.3 VDD + 0.3 +125 V mA mA V V C Note: Table 19: This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. AC Electrical Characteristics VPWR = 3.3V 0.3V; TJ = - 30C to +70C; Output Load = 10pF Symbol Definition SYSCLK Input clock frequency Clock duty cycle Input clock rise time Input clock fall time SYSCLK to PIXCLK propagation delay PIXCLK to valid DOUT(9:0) propagation delay Data setup time Data hold time PIXCLK to LV propagation delay PIXCLK to FV propagation delay tR tF tPLHP tPD tSD tHD tPFLR tPFLF PDF:6981573426/Source: 7298095240 MT9V034_DS - Rev. D Pub. 5/12 EN Condition Min. Typ. Max. Unit Note 1 13.0 45.0 - - 4 -3 14 14 5 5 26.6 50.0 3 3 6 0.6 16 16 7 7 27.0 55.0 5 5 8 3 - - 9 9 MHz % ns ns ns ns ns CLOAD = 10pF CLOAD = 10pF CLOAD = 10pF CLOAD = 10pF 74 ns ns . (c)2008 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9V034: 1/3-Inch Wide-VGA Digital Image Sensor Electrical Specifications Propagation Delays for PIXCLK and Data Out Signals The pixel clock is inverted and delayed relative to the master clock. The relative delay from the master clock (SYSCLK) rising edge to both the pixel clock (PIXCLK) falling edge and the data output transition is typically 7ns. Note that the falling edge of the pixel clock occurs at approximately the same time as the data output transitions. See Table 19 for data setup and hold times. Figure 36: Propagation Delays for PIXCLK and Data Out Signals tF tR SYSCLK tPLHP PIXCLK tPD tSD tHD DOUT(9:0) Propagation Delays for FRAME_VALID and LINE_VALID Signals The LV and FV signals change on the same rising master clock edge as the data output. The LV goes HIGH on the same rising master clock edge as the output of the first valid pixel's data and returns LOW on the same master clock rising edge as the end of the output of the last valid pixel's data. As shown in the "Output Data Timing" on page 13, FV goes HIGH 143 pixel clocks before the first LV goes HIGH. It returns LOW 23 pixel clocks after the last LV goes LOW. Figure 37: Propagation Delays for FRAME_VALID and LINE_VALID Signals t PFLR PDF:6981573426/Source: 7298095240 MT9V034_DS - Rev. D Pub. 5/12 EN t PFLF PIXCLK PIXCLK FRAME_VALID LINE_VALID FRAME_VALID LINE_VALID 75 . (c)2008 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9V034: 1/3-Inch Wide-VGA Digital Image Sensor Electrical Specifications Two-Wire Serial Bus Timing Detailed timing waveforms and parameters for the two-wire serial interface bus are shown in Figure and Table 20. Figure 38: Two-wire Serial Bus Timing tf_clk tr_clk tr_sdat tf_sdat 90% 90% 10% 10% t SRTH t SCLK t ASR t SCHW t t SDSW t AHR STPS t STPH SCLK SDATA Write Address Bit 7 Write Address Bit 0 Register Value Bit 0 Register Address Bit 7 ACK Write Start Stop t t t ASW SHDR AHW t SDSR SCLK SDATA Read Address Bit 7 Register Value Bit 0 ACK Read Start Table 20: Register Value Bit 7 Read Address Bit 0 Two-Wire Serial Bus Timing Parameters Test Conditions: 25C, 26.67 MHz, and 3.3V Symbol fSCLK tSCLK tr_sclk tf_sclk t r_sdat f_sdat tSRTS tSRTH t SDSW tSDHW tASW t AHW tSTPS tSTPH t ASR tAHR tSDSR t SDHR CIN_SI CLOAD_SD RSD t Parameter Serial interface input clock frequency Serial Input clock period SCLK duty cycle SCLK rise time SCLK fall time SDATA rise time SDATA fall time Start setup time Start hold time SDATA setup SDATA hold ACK setup time ACK hold time Stop setup time Stop hold time ACK setup time ACK hold time SDATA setup SDATA hold Serial interface input pin capacitance SDATA max load capacitance SDATA external pull-up resistor PDF:6981573426/Source: 7298095240 MT9V034_DS - Rev. D Pub. 5/12 EN Condition When active Min. 40 1.5 k pull-up WRITE/READ WRITE/READ WRITE WRITE WRITE WRITE WRITE/READ WRITE/READ READ READ READ READ 76 148 36.9 0 1.3 146 98.9 192 247 654 560 Typ. 50 165 6 180 9 150 36 5 36 146 107 624 1.61 228 284 655 595 3.5 15 1.5 Max. Unit 400 2.5 60 kHz sec % ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns pF pF k 167 37.6 12 37 148 144 229 287 690 596 . (c)2008 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9V034: 1/3-Inch Wide-VGA Digital Image Sensor Electrical Specifications Minimum Master Clock Cycles In addition to the AC timing requirements described in Table 20 on page 76, the two-wire serial bus operation also requires certain minimum master clock cycles between transitions. These are specified in Figures 39 through 44, in units of master clock cycles. Figure 39: Serial Host Interface Start Condition Timing 4 4 SCLK SDATA Figure 40: Serial Host Interface Stop Condition Timing 4 4 SCLK SDATA Note: Figure 41: All timing are in units of master clock cycle. Serial Host Interface Data Timing for Write 4 4 SCLK SDATA Note: PDF:6981573426/Source: 7298095240 MT9V034_DS - Rev. D Pub. 5/12 EN SDATA is driven by an off-chip transmitter. 77 . (c)2008 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9V034: 1/3-Inch Wide-VGA Digital Image Sensor Electrical Specifications Figure 42: Serial Host Interface Data Timing for Read 5 SCLK SDATA Note: Figure 43: SDATA is pulled LOW by the sensor, or allowed to be pulled HIGH by a pull-up resistor off-chip. Acknowledge Signal Timing After an 8-Bit WRITE to the Sensor 3 6 SCLK Sensor pulls down SDATA pin SDATA Figure 44: Acknowledge Signal Timing After an 8-Bit READ from the Sensor 6 7 SCLK SDATA Note: PDF:6981573426/Source: 7298095240 MT9V034_DS - Rev. D Pub. 5/12 EN Sensor tri-states SDATA pin (turns off pull down) After a READ, the master receiver must pull down SDATA to acknowledge receipt of data bits. When read sequence is complete, the master must generate a "No Acknowledge" by leaving SDATA to float HIGH. On the following cycle, a start or stop bit may be used. 78 . (c)2008 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9V034: 1/3-Inch Wide-VGA Digital Image Sensor Electrical Specifications Figure 45: Typical Quantum Efficiency - Color 45 Blue Green (B) Green (R) Red 40 Quantum Efficiency (%) 35 30 25 20 15 10 5 0 350 Figure 46: 450 550 650 750 850 Wavelength (nm) 950 1050 1150 Typical Quantum Efficiency - Monochrome 60 50 Quantum Efficiency (%) 40 30 20 10 0 350 450 550 650 750 850 950 1050 1150 Wavelength (nm) PDF:6981573426/Source: 7298095240 MT9V034_DS - Rev. D Pub. 5/12 EN 79 . (c)2008 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9V034: 1/3-Inch Wide-VGA Digital Image Sensor Package Dimensions Package Dimensions Figure 47: 48-Pin CLCC Package Outline Drawing 2.3 0.2 D 1.7 Seating plane Substrate material: alumina ceramic 0.7 thickness Wall material: alumina ceramic A Lid material: borosilicate glass 0.55 thickness 8.8 47X 1.0 0.2 0.8 TYP 4.4 48 48X 0.40 0.05 48X R 0.15 H CTR 1.75 O0.20 A B C 1 First clear pixel 5.215 4.84 4.4 O0.20 A B C 5.715 0.8 TYP 4X 10.9 0.1 CTR V CTR 11.43 8.8 Image sensor die: 0.675 thickness 0.2 5.215 5.715 11.43 Lead finish: Au plating, 0.50 microns minimum thickness over Ni plating, 1.27 microns minimum thickness C Optical area A B 0.05 1.400 0.125 0.90 for reference only 0.35 for reference only 0.10 A 10.9 0.1 CTR Optical center1 Optical area: Maximum rotation of optical area relative to package edges: 1 Maximum tilt of optical area relative to seating plane A : 50 microns Maximum tilt of optical area relative to top of cover glass D : 100 microns Note: 1. Optical center = package center. Notes: PDF:6981573426/Source: 7298095240 MT9V034_DS - Rev. D Pub. 5/12 EN 1. All dimensions in millimeters. 2. Optical center = Package center. 80 . (c)2008 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9V034: 1/3-Inch Wide-VGA Digital Image Sensor Appendix A - Power-On Reset and Standby Timing Appendix A - Power-On Reset and Standby Timing There are no constraints concerning the order in which the various power supplies are applied; however, the MT9V034 requires reset in order operate properly at power-up. Refer to Figure 48 for the power-up, reset, and standby sequences. Figure 48: Power-up, Reset, Clock and Standby Sequence Power up VDD, VDDLVDS, VAA, VAAPIX Active non-Low-Power Low-Power non-Low-Power Wake up Pre-Standby Standby Active Power down MIN 20 SYSCLK cycles RESET_BAR Note 3 STANDBY MIN 10 SYSCLK cycles SYSCLK MIN 10 SYSCLK cycles SCLK, SDATA Does not respond to serial interface when STANDBY = 1 Two-Wire Serial I/F DOUT[9:0] Driven = 0 DATA OUTPUT Notes: PDF:6981573426/Source: 7298095240 MT9V034_DS - Rev. D Pub. 5/12 EN MIN 10 SYSCLK cycles DOUT[9:0] Driven = 0 1. All output signals are defined during initial power-up with RESET_BAR held LOW without SYSCLK being active. To properly reset the rest of the sensor, during initial power-up, assert RESET_BAR (set to LOW state) for at least 750ns after all power supplies have stabilized and SYSCLK is active (being clocked). Driving RESET_BAR to LOW state does not put the part in a low power state. 2. Before using two-wire serial interface, wait for 10 SYSCLK rising edges after RESET_BAR is de-asserted. 3. Once the sensor detects that STANDBY has been asserted, it completes the current frame readout before entering standby mode. The user must supply enough SYSCLKs to allow a complete frame readout. See Table 4, "Frame Time," on page 13 for more information. 4. In standby, all video data and synchronization output signals are High-Z. 5. In standby, the two-wire serial interface is not active. 81 . (c)2008 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9V034: 1/3-Inch Wide-VGA Digital Image Sensor Revision History Revision History REv. D. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5/12 * Updated trademarks Rev. C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11/10 * Applied updated Aptina template Rev. B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9/10 * Updated to Aptina template Rev. A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10/08 * Initial release 10 Eunos Road 8 13-40, Singapore Post Center, Singapore 408600 prodmktg@aptina.com www.aptina.com Aptina, Aptina Imaging, and the Aptina logo are the property of Aptina Imaging Corporation All other trademarks are the property of their respective owners. This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. PDF:6981573426/Source: 7298095240 MT9V034_DS - Rev. D Pub. 5/12 EN 82 . (c)2008 Aptina Imaging Corporation All rights reserved.