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SY10E336
SY100E336
Micrel, Inc.
M9999-032206
hbwhelp@micrel.com or (408) 955-1690
FEATURES
■25Ω cutoff bus output
■Extended 100E VEE range of –4.2V to –5.5V
■50Ω receiver output
■Transmit and receive registers
■1500ps max. clock to bus
■1000ps max. clock to Q
■Internal edge slow-down capacitors on bus outputs
■Additional package ground pins
■Fully compatible with industry standard 10KH,
100K ECL levels
■Internal 75KΩ input pulldown resistors
■Fully compatible with Motorola MC10E/100E336
■Available in 28-pin PLCC package
DESCRIPTION
The SY10/100E336 offer three bus transceivers with
both transmit and receive registers and are designed for
use in new, high-performance ECL systems. The bus
outputs (BUS0 - BUS2) are designed to drive a 25Ω bus.
The receive outputs (Q0 – Q2) are specified for 50Ω. The
bus outputs feature a normal logic HIGH level (VOH) and a
cutoff LOW level when at a logic LOW. At cutoff, the outputs
go to –2.0V and the output emitter-follower is “off”,
presenting a high impedance to the bus. The bus outputs
have edge slow-down capacitors.
The Transmit Enable pins (TEN) determine whether
current data is held in the transmit register or new data is
loaded from the A/B inputs. A logic LOW on both of the bus
enable inputs (BUSEN), when clocked through the register,
disables the bus outputs to –2.0V.
The receiver section clocks bus data into the receive
registers after gating with the Receive Enable (RXEN)
input.
All registers are clocked by rising edge of CLK1 or CLK2
(or both).
Additional grounding is provided through the ground
pins (GND) which should be connected to 0V. The GND
pins are not electrically connected to the chip.
3-BIT REGISTERED
BUS TRANSCEIVER
Pin Function
A0–A2Data Inputs A
B0–B2Data Inputs B
TEN1, 2 Transmit Enable Inputs
RXEN Receive Enable Input
BUSEN1, 2 Bus Enable Inputs
CLK1, 2 Clock Inputs
BUS0–BUS225Ω Cutoff Bus Outputs
Q0–Q2Receive Data Outputs
VCCO VCC to Output
PIN NAMES
SY10E336
SY100E336
Rev.: G Amendment: /0
Issue Date: March 2006
BLOCK DIAGRAM
0
1DQ
DQ50
25 CUTOFF
0
1DQ
DQ50
25 CUTOFF
0
1DQ
DQ50
25 CUTOFF
Q0
BUS0
Q1
BUS1
Q2
BUS2
DQ
A0
B0
A1
B1
A2
B2
TEN1
TEN2
BUSEN1
BUSEN2
CLK1
CLK2
RXEN