92HD91B2X5NLGXWCX - Tempo Semiconductor

DATASHEET

SINGLE CHIP PC AUDIO SYSTEM

CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO 92HD91

TSI™ CONFIDENTIAL

1 V 1.6 09/14

92HD91

Description

The 92HD91 single-chip audio system is a low power

optimized, high fidelity, 4-channel audio codec with

integrated speaker amplifier, capless headphone amplifier,

and low drop out voltage regulator.

The high integration of the 92HD91 enables the smallest

PCB footprint with the lowest system BOM count and cost.

92HD91 provides high quality HD Audio capability to

notebook and business desktop PC applications.

Features

• 4 Channels (2 stereo DACs and 2 stereo ADCs) with

24-bit resolution

• Supports full-duplex stereo audio and simultaneous VoIP

• Provides a mono output

• 2.1 audio crossover support

• 3W/channel Class-D stereo BTL speaker amplifier

@ 4 ohms and 5V

• 10 band hardware parametric equalizer

• Hardware compressor limiter

• Capless headphone amplifier with charge

pump/LDO

• Combo Jack Support allowing for dual-function

headphone and headset detection

• Speaker Protection

• Dedicated BTL high pass filter

• Mono bandpass filter

• Full HDA015-B low power support

• Internal digital core LDO voltage regulator

• Microsoft WLP desktop premium logo compliant

• Dual SPDIF for WLP compliant support of

simultaneous HDMI and SPDIF output

• Support for 1.5V and 3.3V HDA signaling

• Two digital microphone inputs (mono, stereo, or

quad microphones)

• Microphone Mute Input (on WB revisions and

beyond)

• High performance analog mixer

• 2 adjustable VREF Out pins for analog microphone

bias

• 6 analog ports with port presence detect (5 single

ended, 1 BTL)

• Analog and digital PC Beep support

• AUX Audio Mode for playback and record

• 48-pad QFN RoHS packages in Commercial and

Industrial Temperature Ranges

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SINGLE CHIP PC AUDIO SYSTEM,CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO

Full HDA015-B low power support

• Audio inactivity transitions codec from D0 to D3 low power mode

• Resume from D3 to D0 with audio activity in < 10 msec

• D3 to D0 transition with < -65dB pop/click

• Port presence detect in D3 with or without bit clock

• PC beep wake up in D3

• Additional vendor specific modes for even lower power

Software Support

• Intuitive TSI HD Sound graphical user interface that allows configurability and preference set-

tings

• 12 band fully parametric equalizer

• Constant, system-level effects tuned to optimize a particular platform can be combined with

user-mode “presets” tailored for specific acoustical environments and applications

• System-level effects automatically disabled when external audio connections made

• Dynamics Processing

• Enables improved voice articulation

• Compressor/limiter allows higher average volume level without resonances or damage to

speakers.

• TSI Vista APO wrapper

• Enables multiple APOs to be used with the TSI Driver

• Microphone Beam Forming, Acoustic Echo Cancellation, and Noise Suppression

• Dynamic Stream Switching

• Improved multi-streaming user experience with less support calls

• Broad 3rd party branded software including Creative, Dolby, DTS, and SRS

TSI™ CONFIDENTIAL

3 V 1.6 09/14

92HD91

SINGLE CHIP PC AUDIO SYSTEM,CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO

TABLE OF CONTENTS

1. DESCRIPTION ........................................................................................................................ 11

1.1. Overview ..........................................................................................................................................11

1.2. Orderable Part Numbers ..................................................................................................................11

2. DETAILED DESCRIPTION ..................................................................................................... 12

2.1. Port Functionality .............................................................................................................................12

2.1.1. Port Characteristics ............................................................................................................13

2.1.2. Vref_Out .............................................................................................................................15

2.1.3. Jack Detect ........................................................................................................................15

2.1.4. SPDIF Output .....................................................................................................................15

2.2. Mono Output ....................................................................................................................................17

2.3. Mono output Band-Pass Filter .........................................................................................................18

2.3.1. Filter Description ................................................................................................................18

2.4. Mixer ................................................................................................................................................18

2.5. ADC Multiplexers .............................................................................................................................18

2.6. Power Management .........................................................................................................................19

2.7. AFG D0 ............................................................................................................................................20

2.8. AFG D1 ............................................................................................................................................20

2.9. AFG D2 ............................................................................................................................................20

2.10. AFG D3 ..........................................................................................................................................20

2.10.1. AFG D3cold .....................................................................................................................20

2.11. Vendor Specific Function Group Power States D4/D5 ..................................................................20

2.12. Low-voltage HDA Signaling ...........................................................................................................21

2.13. Multi-channel capture ....................................................................................................................21

2.14. EAPD .............................................................................................................................................23

2.15. Digital Microphone Support ...........................................................................................................27

2.16. Analog PC-Beep ............................................................................................................................31

2.17. Digital PC-Beep .............................................................................................................................33

2.18. Headphone Drivers ........................................................................................................................34

2.19. BTL Amplifier .................................................................................................................................34

2.20. BTL Amplifier High-Pass Filter .......................................................................................................34

2.20.1. Filter Description ..............................................................................................................35

2.21. EQ ..................................................................................................................................................35

2.22. Combo Jack Detection ...................................................................................................................35

2.23. GPIO ..............................................................................................................................................36

2.23.1. GPIO Pin mapping and shared functions .........................................................................36

2.23.2. SPDIF/Digital Microphone/GPIO Selection ......................................................................36

2.23.3. Digital Microphone/GPIO Selection .................................................................................36

2.24. HD Audio HDA015-B support ........................................................................................................36

2.25. Digital Core Voltage Regulator ......................................................................................................37

2.26. Aux Audio Support .........................................................................................................................38

2.26.1. General conditions in Aux Audio Mode: ...........................................................................38

2.26.2. Entering Aux Audio Mode ................................................................................................39

2.26.3. “Playback Path” Port Behavior (AnaIog I/O) ....................................................................40

2.26.4. When Port E presence detect = 0 ....................................................................................40

2.26.5. When Port E presence detect = 1 ....................................................................................40

2.26.6. “Record Path” Port Behavior (Analog I/O) .......................................................................41

2.26.7. SYSTEM DIAGRAMS (Analog I/O) ..................................................................................41

2.26.8. EAPD ...............................................................................................................................43

2.26.9. Analog PC_Beep .............................................................................................................43

2.26.10. Class-D BTL Issues .......................................................................................................44

2.26.11. Firmware/Software Requirements: .................................................................................44

2.27. Microphone Mute Input ..................................................................................................................44

3. CHARACTERISTICS ............................................................................................................... 45

3.1. Electrical Specifications ...................................................................................................................45

3.1.1. Absolute Maximum Ratings ...............................................................................................45

3.1.2. Recommended Operating Conditions ................................................................................45

3.2. 92HD91 Analog Performance Characteristics

.....................................................................................46

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3.3. Class-D BTL Amplifier Performance ................................................................................................50

3.4. Capless Headphone Supply Characteristics ....................................................................................51

3.5. AC Timing Specs .............................................................................................................................51

3.5.1. HD Audio Bus Timing .........................................................................................................51

3.5.2. SPDIF Timing .....................................................................................................................52

3.5.3. Digital Microphone Timing .................................................................................................52

3.5.4. GPIO Characteristics .........................................................................................................52

4. FUNCTIONAL BLOCK DIAGRAM .......................................................................................... 53

5. WIDGET DIAGRAM ................................................................................................................ 54

6. PORT AND PIN CONFIGURATIONS ..................................................................................... 55

6.1. Port Configurations ..........................................................................................................................55

6.2. Pin Configuration Default Register Settings .....................................................................................56

7. WIDGET INFORMATION ........................................................................................................ 57

7.1. Widget List .......................................................................................................................................58

7.2. Reset Key ........................................................................................................................................59

7.3. Root (NID = 00h): VendorID ............................................................................................................59

7.3.1. Root (NID = 00h): RevID ....................................................................................................60

7.3.2. Root (NID = 00h): NodeInfo ...............................................................................................60

7.4. AFG (NID = 01h): NodeInfo .............................................................................................................61

7.4.1. AFG (NID = 01h): FGType .................................................................................................61

7.4.2. AFG (NID = 01h): AFGCap ................................................................................................62

7.4.3. AFG (NID = 01h): PCMCap ...............................................................................................63

7.4.4. AFG (NID = 01h): StreamCap ............................................................................................64

7.4.5. AFG (NID = 01h): InAmpCap .............................................................................................65

7.4.6. AFG (NID = 01h): PwrStateCap .........................................................................................66

7.4.7. AFG (NID = 01h): GPIOCnt ...............................................................................................67

7.4.8. AFG (NID = 01h): OutAmpCap ..........................................................................................87

7.4.9. AFG (NID = 01h): PwrState ...............................................................................................68

7.4.10. AFG (NID = 01h): UnsolResp ..........................................................................................69

7.4.11. AFG (NID = 01h): GPIO ...................................................................................................70

7.4.12. AFG (NID = 01h): GPIOEn ...............................................................................................71

7.4.13. AFG (NID = 01h): GPIODir ..............................................................................................72

7.4.14. AFG (NID = 01h): GPIOWakeEn .....................................................................................73

7.4.15. AFG (NID = 01h): GPIOUnsol ..........................................................................................72

7.4.16. AFG (NID = 01h): GPIOSticky .........................................................................................73

7.4.17. AFG (NID = 01h): SubID ..................................................................................................73

7.4.18. AFG (NID = 01h): GPIOPlrty ............................................................................................74

7.4.19. AFG (NID = 01h): GPIODrive ...........................................................................................75

7.4.20. AFG (NID = 01h): DMic ....................................................................................................76

7.4.21. AFG (NID = 01h): DACMode ...........................................................................................77

7.4.22. AFG (NID = 01h): ADCMode ...........................................................................................78

7.4.23. AFG (NID = 01h): PortUse ...............................................................................................79

7.4.24. AFG (NID = 01h): ComJack .............................................................................................80

7.4.25. AFG (NID = 01h): VSPwrState .........................................................................................81

7.4.26. AFG (NID = 01h): AnaPort ...............................................................................................82

7.4.27. AFG (NID = 01h): AnaBTL ...............................................................................................83

7.4.28. AFG (NID = 01h): AnaBTLStatus .....................................................................................85

7.4.29. AFG (NID = 01h): AnaCapless .........................................................................................85

7.4.30. AFG (NID = 01h): Reset ...................................................................................................88

7.4.31. AFG (NID = 01h): DAC3OutAmp (Mono Out Volume) .....................................................89

7.4.32. AFG (NID = 01h): AnaBeep .............................................................................................90

7.4.33. AFG (NID = 01h): EAPD ..................................................................................................91

7.4.34. AFG (NID = 01h): ComboJackTime (Available only on WB revision and beyond) ..........94

7.5. PortA (NID = 0Ah): WCap ................................................................................................................96

7.5.1. PortA (NID = 0Ah): PinCap ................................................................................................97

7.5.2. PortA (NID = 0Ah): ConLst .................................................................................................98

7.5.3. PortA (NID = 0Ah): ConLstEntry0 ......................................................................................99

7.5.4. PortA (NID = 0Ah): InAmpLeft ............................................................................................99

7.5.5. PortA (NID = 0Ah): InAmpRight .......................................................................................100

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SINGLE CHIP PC AUDIO SYSTEM,CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO

7.5.6. PortA (NID = 0Ah): ConSelectCtrl ....................................................................................100

7.5.7. PortA (NID = 0Ah): PwrState ...........................................................................................101

7.5.8. PortA (NID = 0Ah): PinWCntrl ..........................................................................................101

7.5.9. PortA (NID = 0Ah): UnsolResp ........................................................................................102

7.5.10. PortA (NID = 0Ah): ChSense .........................................................................................103

7.5.11. PortA (NID = 0Ah): EAPDBTLLR ...................................................................................103

7.5.12. PortA (NID = 0Ah): ConfigDefault ..................................................................................104

7.6. PortB (NID = 0Bh): WCap ..............................................................................................................106

7.6.1. PortB (NID = 0Bh): PinCap ..............................................................................................108

7.6.2. PortB (NID = 0Bh): ConLst ...............................................................................................109

7.6.3. PortB (NID = 0Bh): ConLstEntry0 ....................................................................................110

7.6.4. PortB (NID = 0Bh): ConSelectCtrl ....................................................................................110

7.6.5. PortB (NID = 0Bh): PwrState ...........................................................................................110

7.6.6. PortB (NID = 0Bh): PinWCntrl ..........................................................................................111

7.6.7. PortB (NID = 0Bh): UnsolResp ........................................................................................112

7.6.8. PortB (NID = 0Bh): ChSense ...........................................................................................112

7.6.9. PortB (NID = 0Bh): EAPDBTLLR .....................................................................................113

7.6.10. PortB (NID = 0Bh): ConfigDefault ..................................................................................113

7.7. PortC (NID = 0Ch): WCap .............................................................................................................116

7.7.1. PortC (NID = 0Ch): PinCap ..............................................................................................117

7.7.2. PortC (NID = 0Ch): ConLst ..............................................................................................118

7.7.3. PortC (NID = 0Ch): ConLstEntry0 ....................................................................................119

7.7.4. PortC (NID = 0Ch): InAmpLeft .........................................................................................119

7.7.5. PortC (NID = 0Ch): InAmpRight .......................................................................................120

7.7.6. PortC (NID = 0Ch): ConSelectCtrl ...................................................................................120

7.7.7. PortC (NID = 0Ch): PwrState ...........................................................................................121

7.7.8. PortC (NID = 0Ch): PinWCntrl .........................................................................................121

7.7.9. PortC (NID = 0Ch): UnsolResp ........................................................................................122

7.7.10. PortC (NID = 0Ch): ChSense .........................................................................................123

7.7.11. PortC (NID = 0Ch): EAPDBTLLR ...................................................................................123

7.7.12. PortC (NID = 0Ch): ConfigDefault ..................................................................................124

7.8. PortD (NID = 0Dh): WCap .............................................................................................................127

7.8.1. PortD (NID = 0Dh): PinCap ..............................................................................................128

7.8.2. PortD (NID = 0Dh): ConLst ..............................................................................................129

7.8.3. PortD (NID = 0Dh): ConLstEntry0 ....................................................................................130

7.8.4. PortD (NID = 0Dh): ConSelectCtrl ...................................................................................130

7.8.5. PortD (NID = 0Dh): PwrState ...........................................................................................131

7.8.6. PortD (NID = 0Dh): PinWCntrl .........................................................................................132

7.8.7. PortD (NID = 0Dh): EAPDBTLLR .....................................................................................132

7.8.8. PortD (NID = 0Dh): ConfigDefault ....................................................................................132

7.9. PortE (NID = 0Eh): WCap ..............................................................................................................136

7.9.1. PortE (NID = 0Eh): PinCap ..............................................................................................137

7.9.2. PortE (NID = 0Eh): ConLst ...............................................................................................138

7.9.3. PortE (NID = 0Eh): ConLstEntry0 ....................................................................................139

7.9.4. PortE (NID = 0Eh): InAmpLeft ..........................................................................................139

7.9.5. PortE (NID = 0Eh): InAmpRight .......................................................................................140

7.9.6. PortE (NID = 0Eh): ConSelectCtrl ....................................................................................140

7.9.7. PortE (NID = 0Eh): PwrState ...........................................................................................141

7.9.8. PortE (NID = 0Eh): PinWCntrl ..........................................................................................141

7.9.9. PortE (NID = 0Eh): UnsolResp ........................................................................................142

7.9.10. PortE (NID = 0Eh): ChSense .........................................................................................142

7.9.11. PortE (NID = 0Eh): EAPDBTLLR ...................................................................................143

7.9.12. PortE (NID = 0Eh): ConfigDefault ..................................................................................143

7.10. PortF (NID = 0Fh): WCap ............................................................................................................146

7.10.1. PortF (NID = 0Fh): PinCap .............................................................................................147

7.10.2. PortF (NID = 0Fh): ConLst .............................................................................................148

7.10.3. PortF (NID = 0Fh): ConLstEntry0 ...................................................................................149

7.10.4. PortF (NID = 0Fh): InAmpLeft ........................................................................................149

7.10.5. PortF (NID = 0Fh): InAmpRight ......................................................................................150

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7.10.6. PortF (NID = 0Fh): ConSelectCtrl ..................................................................................150

7.10.7. PortF (NID = 0Fh): PwrState ..........................................................................................151

7.10.8. PortF (NID = 0Fh): PinWCntrl ........................................................................................151

7.10.9. PortF (NID = 0Fh): UnsolResp .......................................................................................152

7.10.10. PortF (NID = 0Fh): ChSense ........................................................................................153

7.10.11. PortF (NID = 0Fh): EAPDBTLLR .................................................................................153

7.10.12. PortF (NID = 0Fh): ConfigDefault .................................................................................154

7.11. MonoOut (NID = 10h): WCap ......................................................................................................157

7.11.1. MonoOut (NID = 10h): PinCap .......................................................................................158

7.11.2. MonoOut (NID = 10h): ConLst .......................................................................................159

7.11.3. MonoOut (NID = 10h): ConLstEntry0 .............................................................................160

7.11.4. MonoOut (NID = 10h): PwrState ....................................................................................160

7.11.5. MonoOut (NID = 10h): PinWCntrl ..................................................................................161

7.11.6. MonoOut (NID = 10h): ConfigDefault .............................................................................162

7.12. DMic0 (NID = 11h): WCap ...........................................................................................................165

7.12.1. DMic0 (NID = 11h): PinCap ...........................................................................................166

7.12.2. DMic0 (NID = 11h): InAmpLeft .......................................................................................167

7.12.3. DMic0 (NID = 11h): InAmpRight ....................................................................................168

7.12.4. DMic0 (NID = 11h): PwrState .........................................................................................168

7.12.5. DMic0 (NID = 11h): PinWCntrl .......................................................................................169

7.12.6. DMic0 (NID = 11h): UnsolResp ......................................................................................170

7.12.7. DMic0 (NID = 11h): ChSense ........................................................................................170

7.12.8. DMic0 (NID = 11h): ConfigDefault .................................................................................171

7.13. DMic1Vol (NID = 12h): WCap ......................................................................................................174

7.13.1. DMic1Vol (NID = 12h): ConLst .......................................................................................175

7.13.2. DMic1Vol (NID = 12h): ConLstEntry0 ............................................................................176

7.13.3. DMic1Vol (NID = 12h): InAmpLeft ..................................................................................176

7.13.4. DMic1Vol (NID = 12h): InAmpRight ...............................................................................176

7.13.5. DMic1Vol (NID = 12h): PwrState ...................................................................................177

7.14. DAC0 (NID = 13h): WCap ............................................................................................................178

7.14.1. DAC0 (NID = 13h): Cnvtr ...............................................................................................179

7.14.2. DAC0 (NID = 13h): OutAmpLeft .....................................................................................180

7.14.3. DAC0 (NID = 13h): OutAmpRight ..................................................................................181

7.14.4. DAC0 (NID = 13h): PwrState .........................................................................................181

7.14.5. DAC0 (NID = 13h): CnvtrID ............................................................................................182

7.14.6. DAC0 (NID = 13h): EAPDBTLLR ...................................................................................183

7.15. DAC1 (NID = 14h): WCap ............................................................................................................183

7.15.1. DAC1 (NID = 14h): Cnvtr ...............................................................................................185

7.15.2. DAC1 (NID = 14h): OutAmpLeft .....................................................................................186

7.15.3. DAC1 (NID = 14h): OutAmpRight ..................................................................................186

7.15.4. DAC1 (NID = 14h): PwrState .........................................................................................187

7.15.5. DAC1 (NID = 14h): CnvtrID ............................................................................................188

7.15.6. DAC1 (NID = 14h): EAPDBTLLR ...................................................................................188

7.16. ADC0 (NID = 15h): WCap ............................................................................................................189

7.16.1. ADC0 (NID = 15h): ConLst ............................................................................................190

7.16.2. ADC0 (NID = 15h): ConLstEntry0 ..................................................................................191

7.16.3. ADC0 (NID = 15h): Cnvtr ...............................................................................................191

7.16.4. ADC0 (NID = 15h): ProcState ........................................................................................192

7.16.5. ADC0 (NID = 15h): PwrState .........................................................................................193

7.16.6. ADC0 (NID = 15h): CnvtrID ............................................................................................194

7.17. ADC1 (NID = 1Bh): WCap ...........................................................................................................194

7.17.1. ADC1 (NID = 1Bh): ConLst ............................................................................................196

7.17.2. ADC1 (NID = 1Bh): ConLstEntry0 ..................................................................................196

7.17.3. ADC1 (NID = 1Bh): Cnvtr ...............................................................................................197

7.17.4. ADC1 (NID = 1Bh): ProcState ........................................................................................198

7.17.5. ADC1 (NID = 1Bh): PwrState .........................................................................................199

7.17.6. ADC1 (NID = 1Bh): CnvtrID ...........................................................................................200

7.18. ADC0Mux (NID = 17h): WCap .....................................................................................................201

7.18.1. ADC0Mux (NID = 17h): ConLst ......................................................................................202

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7.18.2. ADC0Mux (NID = 17h): ConLstEntry4 ...........................................................................203

7.18.3. ADC0Mux (NID = 17h): ConLstEntry0 ...........................................................................203

7.18.4. ADC0Mux (NID = 17h): OutAmpCap .............................................................................204

7.18.5. ADC0Mux (NID = 17h): OutAmpLeft ..............................................................................205

7.18.6. ADC0Mux (NID = 17h): OutAmpRight ...........................................................................205

7.18.7. ADC0Mux (NID = 17h): ConSelectCtrl ...........................................................................206

7.18.8. ADC0Mux (NID = 17h): PwrState ..................................................................................206

7.18.9. ADC0Mux (NID = 17h): EAPDBTLLR ............................................................................207

7.19. ADC1Mux (NID = 18h): WCap .....................................................................................................208

7.19.1. ADC1Mux (NID = 18h): ConLst ......................................................................................210

7.19.2. ADC1Mux (NID = 18h): ConLstEntry4 ...........................................................................210

7.19.3. ADC1Mux (NID = 18h): ConLstEntry0 ...........................................................................211

7.19.4. ADC1Mux (NID = 18h): OutAmpCap .............................................................................211

7.19.5. ADC1Mux (NID = 18h): OutAmpLeft ..............................................................................212

7.19.6. ADC1Mux (NID = 18h): OutAmpRight ...........................................................................212

7.19.7. ADC1Mux (NID = 18h): ConSelectCtrl ...........................................................................213

7.19.8. ADC1Mux (NID = 18h): PwrState ..................................................................................213

7.19.9. ADC1Mux (NID = 18h): EAPDBTLLR ............................................................................214

7.20. MonoMux (NID = 19h): WCap .....................................................................................................215

7.20.1. MonoMux (NID = 19h): ConLst ......................................................................................216

7.20.2. MonoMux (NID = 19h): ConLstEntry0 ............................................................................217

7.20.3. MonoMux (NID = 19h): ConSelectCtrl ...........................................................................217

7.20.4. MonoMux (NID = 19h): PwrState ...................................................................................217

7.21. MonoMix (NID = 1Ah): WCap ......................................................................................................218

7.21.1. MonoMix (NID = 1Ah): ConLst .......................................................................................220

7.21.2. MonoMix (NID = 1Ah): ConLstEntry0 .............................................................................220

7.21.3. MonoMix (NID = 1Ah): PwrState ....................................................................................221

7.22. Mixer (NID = 1Bh): WCap ............................................................................................................223

7.22.1. Mixer (NID = 1Bh): InAmpCap .......................................................................................224

7.22.2. Mixer (NID = 1Bh): ConLst .............................................................................................225

7.22.3. Mixer (NID = 1Bh): ConLstEntry4 ..................................................................................225

7.22.4. Mixer (NID = 1Bh): ConLstEntry0 ..................................................................................226

7.22.5. Mixer (NID = 1Bh): InAmpLeft0 ......................................................................................226

7.22.6. Mixer (NID = 1Bh): InAmpRight0 ...................................................................................227

7.22.7. Mixer (NID = 1Bh): InAmpLeft1 ......................................................................................227

7.22.8. Mixer (NID = 1Bh): InAmpRight1 ...................................................................................228

7.22.9. Mixer (NID = 1Bh): InAmpLeft2 ......................................................................................228

7.22.10. Mixer (NID = 1Bh): InAmpRight2 .................................................................................229

7.22.11. Mixer (NID = 1Bh): InAmpLeft3 ....................................................................................229

7.22.12. Mixer (NID = 1Bh): InAmpRight3 .................................................................................230

7.22.13. Mixer (NID = 1Bh): InAmpLeft4 ....................................................................................230

7.22.14. Mixer (NID = 1Bh): InAmpRight4 .................................................................................231

7.22.15. Mixer (NID = 1Bh): InAmpLeft5 ....................................................................................231

7.22.16. Mixer (NID = 1Bh): InAmpRight5 .................................................................................232

7.22.17. Mixer (NID = 1Bh): PwrState ........................................................................................232

7.23. MixerOutVol (NID = 1Ch): WCap .................................................................................................233

7.23.1. MixerOutVol (NID = 1Ch): ConLst ..................................................................................235

7.23.2. MixerOutVol (NID = 1Ch): ConLstEntry0 .......................................................................235

7.23.3. MixerOutVol (NID = 1Ch): OutAmpCap .........................................................................236

7.23.4. MixerOutVol (NID = 1Ch): OutAmpLeft ..........................................................................237

7.23.5. MixerOutVol (NID = 1Ch): OutAmpRight .......................................................................237

7.23.6. MixerOutVol (NID = 1Ch): PwrState ..............................................................................238

7.24. SPDIFOut0 (NID = 1Dh): WCap ..................................................................................................239

7.24.1. SPDIFOut0 (NID = 1Dh): PCMCap ................................................................................240

7.24.2. SPDIFOut0 (NID = 1Dh): StreamCap ............................................................................242

7.24.3. SPDIFOut0 (NID = 1Dh): OutAmpCap ...........................................................................242

7.24.4. SPDIFOut0 (NID = 1Dh): Cnvtr ......................................................................................243

7.24.5. SPDIFOut0 (NID = 1Dh): OutAmpLeft ...........................................................................244

7.24.6. SPDIFOut0 (NID = 1Dh): OutAmpRight .........................................................................245

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SINGLE CHIP PC AUDIO SYSTEM,CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO

7.24.7. SPDIFOut0 (NID = 1Dh): PwrState ................................................................................245

7.24.8. SPDIFOut0 (NID = 1Dh): CnvtrID ..................................................................................246

7.24.9. SPDIFOut0 (NID = 1Dh): DigCnvtr ................................................................................247

7.25. SPDIFOut1 (NID = 1Eh): WCap ..................................................................................................248

7.25.1. SPDIFOut1 (NID = 1Eh): PCMCap ................................................................................249

7.25.2. SPDIFOut1 (NID = 1Eh): StreamCap ............................................................................251

7.25.3. SPDIFOut1 (NID = 1Eh): OutAmpCap ...........................................................................251

7.25.4. SPDIFOut1 (NID = 1Eh): Cnvtr ......................................................................................252

7.25.5. SPDIFOut1 (NID = 1Eh): OutAmpLeft ...........................................................................253

7.25.6. SPDIFOut1 (NID = 1Eh): OutAmpRight .........................................................................254

7.25.7. SPDIFOut1 (NID = 1Eh): PwrState ................................................................................254

7.25.8. SPDIFOut1 (NID = 1Eh): CnvtrID ..................................................................................255

7.25.9. SPDIFOut1 (NID = 1Eh): DigCnvtr .................................................................................256

7.26. Dig0Pin (NID = 1Fh): WCap ........................................................................................................257

7.26.1. Dig0Pin (NID = 1Fh): PinCap .........................................................................................258

7.26.2. Dig0Pin (NID = 1Fh): ConLst .........................................................................................259

7.26.3. Dig0Pin (NID = 1Fh): ConLstEntry0 ...............................................................................260

7.26.4. Dig0Pin (NID = 1Fh): PwrState ......................................................................................260

7.26.5. Dig0Pin (NID = 1Fh): PinWCntrl ....................................................................................261

7.26.6. Dig0Pin (NID = 1Fh): UnsolResp ..................................................................................262

7.26.7. Dig0Pin (NID = 1Fh): ChSense ......................................................................................262

7.26.8. Dig0Pin (NID = 1Fh): ConfigDefault ...............................................................................263

7.27. Dig1Pin (NID = 20h): WCap .........................................................................................................265

7.27.1. Dig1Pin (NID = 20h): PinCap .........................................................................................267

7.27.2. Dig1Pin (NID = 20h): ConLst .........................................................................................268

7.27.3. Dig1Pin (NID = 20h): ConLstEntry0 ...............................................................................269

7.27.4. Dig1Pin (NID = 20h): PwrState ......................................................................................269

7.27.5. Dig1Pin (NID = 20h): PinWCntrl .....................................................................................270

7.27.6. Dig1Pin (NID = 20h): ConfigDefault ...............................................................................271

7.28. DigBeep (NID = 21h): WCap .......................................................................................................274

7.28.1. DigBeep (NID = 21h): OutAmpCap ................................................................................275

7.28.2. DigBeep (NID = 21h): OutAmpLeft ................................................................................275

7.28.3. DigBeep (NID = 21h): PwrState .....................................................................................276

7.28.4. DigBeep (NID = 21h): Gen .............................................................................................277

7.28.5. DigBeep (NID = 21h): Gain ............................................................................................277

7.29. AdvancedFunctions (NID = 22h): WCap ......................................................................................278

7.29.1. AdvancedFunctions (NID = 22h): Cntrl0 ........................................................................279

8. PINOUT AND PACKAGING .................................................................................................. 295

8.0.1. 48QFN Pin Table .............................................................................................................299

8.0.2. 48QFN Package Outline and Package Dimensions ........................................................298

8.1. Standard Reflow Profile Data ........................................................................................................299

9. DISCLAIMER ......................................................................................................................... 300

10. DOCUMENT REVISION HISTORY ..................................................................................... 301

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SINGLE CHIP PC AUDIO SYSTEM,CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO

LIST OF TABLES

Table 1. Port Functionality .............................................................................................................................12

Table 2. Analog Output Port Behavior ...........................................................................................................13

Table 3. 48pin Jack Detect ............................................................................................................................15

Table 4. SPDIF OUT 0 Behavior ....................................................................................................................16

Table 5. SPDIF OUT 1 Behavior ....................................................................................................................16

Table 6. Power Management .........................................................................................................................19

Table 7. Example channel mapping ...............................................................................................................22

Table 9. EAPD Pin Mode Select ....................................................................................................................24

Table 10. Control bit descriptions for BTL amplifier and Headphone amplifier enable configurations ...........24

Table 11. BTL Amp Enable Configuration ......................................................................................................24

Table 14. EAPD Analog PC_Beep behavior ..................................................................................................25

Table 15. EAPD Behavior ..............................................................................................................................25

Table 12. Headphone Amp Enable Configuration ..........................................................................................25

Table 13. Port E Headphone Amp Enable Configuration support by part and mode .....................................25

Table 16. Valid Digital Mic Configurations .....................................................................................................28

Table 17. DMIC_CLK and DMIC_0,1 Operation During Power States ..........................................................28

Table 18. Electrical Specification: Maximum Ratings ...................................................................................45

Table 19. Recommended Operating Conditions ............................................................................................45

Table 20. 92HD91 Analog Performance Characteristics ...............................................................................46

Table 21. Class-D BTL Amplifier Performance ..............................................................................................50

Table 22. Capless Headphone Supply ..........................................................................................................51

Table 23. HD Audio Bus Timing .....................................................................................................................51

Table 24. SPDIF Timing .................................................................................................................................52

Table 25. Digital Mic timing ............................................................................................................................52

Table 26. GPIO Characteristics .....................................................................................................................52

Table 27. Pin Configuration Default Settings .................................................................................................56

Table 28. Command Format for Verb with 4-bit Identifier ..............................................................................57

Table 29. Command Format for Verb with 12-bit Identifier ............................................................................57

Table 30. Solicited Response Format ............................................................................................................57

Table 31. Unsolicited Response Format ........................................................................................................57

Table 32. Widget List .....................................................................................................................................58

Table 33. 48QFN Pin Description ................................................................................................................296

Table 34. Standard Reflow Profile ...............................................................................................................299

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SINGLE CHIP PC AUDIO SYSTEM,CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO

LIST OF FIGURES

Figure 1. Multi-channel capture ......................................................................................................................22

Figure 2. Multi-channel timing diagram ..........................................................................................................22

Figure 3. HP EAPD Example to be replaced by single pin for internal amp ..................................................26

Figure 4. EAPD implementation .....................................................................................................................27

Figure 5. Single Digital Microphone (data is ported to both left and right channels .......................................29

Figure 6. Stereo Digital Microphone Configuration ........................................................................................30

Figure 7. Quad Digital Microphone Configuration ..........................................................................................31

Figure 8. Analog PC Beep Active ..................................................................................................................32

Figure 9. Analog PC Beep Flow chart ............................................................................................................33

Figure 10. Combo Jack ..................................................................................................................................35

Figure 11. Switching between Normal and Aux Audio Modes .......................................................................39

Figure 12. Aux Audio Playback When Nothing Plugged In (or System is not Docked) ..................................41

Figure 13. Aux Audio Playback When System Headphones are Plugged In .................................................42

Figure 14. Aux Audio Playback when the System is Docked and Headphones are Plugged In ....................42

Figure 15. Aux Audio Record when Nothing is Plugged In (or The System is not Docked) ...........................42

Figure 16. Aux Audio Record when the System is Docked with the System Microphone Plugged In ...........43

Figure 17. Aux Audio Record when the System is Docked with the Dock Microphone Plugged In ...............43

Figure 18. HD Audio Bus Timing ....................................................................................................................51

Figure 19. Functional Block Diagram .............................................................................................................53

Figure 20. Widget Diagram ............................................................................................................................54

Figure 21. Port Configurations .......................................................................................................................55

Figure 22. 48QFN Pin Assignment ..............................................................................................................295

Figure 23. 48QFN Package Diagram ...........................................................................................................298

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11 V 1.6 09/14

92HD91

SINGLE CHIP PC AUDIO SYSTEM,CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO

1. DESCRIPTION

1.1. Overview

The 92HD91 audio CODEC provides stereo 24- bit, full duplex resolution supporting sample rates up

to 192kHz by the DAC and ADC. SPDIF outputs support sample rates of 192kHz, 96kHz, 88.2kHz,

48kHz, and 44.1kHz. Additional sample rates are supported by the driver software.

An integrated BTL stereo amplifier is ideal for driving 4ohm or 8ohm integrated speakers in mobile

and ultra-mobile computers. For desktop computers or mobile computers using only one speaker,

the BTL output stage may be configured to support a single mono speaker.

The 92HD91 audio CODEC supports a wide range of desktop and laptop configurations. The 2 inde-

pendent SPDIF output interfaces provide connectivity to consumer electronic equipment or to a

home entertainment system. Simultaneous HDMI and SPDIF output is possible. All inputs can be

programmed with 0-30 dB gain in 10 dB steps allowing for line or microphone use of any input.

Port presence detect capabilities allow the CODEC to detect when audio devices are connected to

the CODEC. The fully parametric Internal EQ can be initiated upon headphone jack insertion and

removal for protection of notebook speakers.

The 92HD91 audio CODEC operates with a 3.3V digital supply and a 5V (4.75V allowed when using

external voltage regulator) analog supply. It allows for 1.5V and 3.3V HDA signaling; the correct sig-

nalling level is selected dynamically based on the power supply voltage on the DVDD-IO pin.

The 92HD91 audio CODEC is offered in a 48-pin QFN Environmental (ROHS) package.

1.2. Orderable Part Numbers

yy = silicon stepping/revision, contact sales for current data.

Add an “8” to the end for tape and reel delivery.

Please note that Industrial Temp is only available on revision WC and forward.

92HD91B1X5NLGXyyX Aux mode

92HD91B2X5NLGXyyX No Aux mode

92HD91B1X5NLGIyyX Aux mode Industrial Temp

92HD91B2X5NLGIyyX No Aux mode Industrial Temp

TSI™ CONFIDENTIAL

12 V 1.6 09/14

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2. DETAILED DESCRIPTION

2.1. Port Functionality

Multi-function (Input/Output) ports allow for the highest possible flexibility. 7 bi-directional ports, 2 are

headphone capable, support a wide variety of consumer desktop and mobile system use models.

• Port A supports

• Headphone Out

• Line Out

• Line Input

• Mic with 0/10/20/30 dB Boost

• Port B supports

• Capless Headphone Out

• Capless Line Out

•Port C

• Line In

• Line Out

• Mic with 0/10/20/30 dB Boost

• Port D supports

• BTL stereo output

• BTL (L+/L-) mono out

• Port E supports

• Line In

• Line Out

• Mic with 0/10/20/30 dB Boost

• Port F supports

• Line In

• Line Out

• Mic with 0/10/20/30 dB Boost

• Mono Out supports

• Line Out

Pins 48-QFN Port Input Output Headphone BTL Mic Bias

(Vref pin)

Input

boost amp

28/29 A Yes Yes Yes Yes Yes

31/32 B Yes Yes

19/20 C Yes Yes Yes Yes

40/41/43/44 D Yes Yes

15/16 E Yes Yes Yes

17/18 F Yes Yes Yes

25 Mono Out Yes

48 SPDIF_OUT0 Yes

46 DMIC1/SPDIFOUT1/ Yes Yes Yes

4 (CLK=2) DMIC0 Yes Yes

Table 1. Port Functionality

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2.1.1. Port Characteristics

Universal (Bi-directional) jacks are supported on ports A,C, E, and F. Ports A and B are designed to

drive 32 ohm (nominal) headphones or a 10K (nominal) load. Line Level outputs are intended to

drive an external 10K load (nominal) and an on board shunt resistor of 20-47K (nominal). However,

applications may support load impedances of 5K ohms and above. Input ports are 50K (nominal) at

the pin.

DAC full scale outputs and intended full scale input levels are 1V rms at 5V. Line output ports and

Headphone output ports on the 92HD93 codec may be configured for +3dBV full scale output levels

by using a vendor specific verb.

Output ports are always on to prevent pops/clicks associated with charging and discharging output

coupling capacitors. This maintains proper bias on output coupling caps even in power state D3 as

long as AVDD is available. Unused ports should be left unconnected. When updating existing

designs to use the 92HD93 codec, ensure that there are no conflicts between the output ports on the

92HD93 codec and existing circuitry.

AFG

Power

State

Input

Enable

Output

Enable

Used as output

for DAC/Mixer

Used as output

for analog

PC_Beep

Used as

input for

ADC, mixer

Port Behavior

D0-D2

1 1 Don't care Don't care

Yes Not allowed. Port is active as input.

No Not allowed. Inactive (Power Down) - Port keeps

output coupling caps charged if port uses caps.

1 0 NA NA Yes Active - Port enabled as input

1 0 NA NA No Inactive (Power Down) - Port keeps output coupling

caps charged if port uses caps.

currently used by DAC, mixer,

beep, or is traditional line or

headphone output NA

Active - Port enabled as output

not currently used by DAC, mixer,

beep and is capless HP/BTL port Inactive (Power Down)

0 0 NA NA NA Inactive (Power Down) - Port keeps output coupling

caps charged if port uses caps.

1 1 NA NA Don't care Not allowed. Inactive (Power Down) - Port keeps

output coupling caps charged if port uses caps.

1 0 NA NA Don't care Inactive (Power Down) - Port keeps output coupling

caps charged if port uses caps.

currently used by DAC, mixer,

beep, or is traditional line or

headphone output

Don't care Low power state. If enabled, Beep will output from

the port

not currently used by DAC, mixer,

beep and is capless HP/BTL port Don't care Inactive (Power Down)

0 0 NA NA Don't care Inactive (Power Down) - Port keeps output coupling

caps charged if port uses caps.

D3cold - - Inactive (lower power) - Port keeps output coupling

caps charged if port uses caps.

Table 2. Analog Output Port Behavior

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D4 - - Inactive (lower power) - Port keeps output coupling

caps charged if port uses caps.

D5 - - Off - Charge on coupling caps (if used) will not be

maintained.

AFG

Power

State

Input

Enable

Output

Enable

Used as output

for DAC/Mixer

Used as output

for analog

PC_Beep

Used as

input for

ADC, mixer

Port Behavior

Table 2. Analog Output Port Behavior

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2.1.2. Vref_Out

Ports C, & A support Vref_Out pins for biasing electret cartridge microphones. Settings of 80%

AVDD, 50% AVDD, GND, and Hi-Z are supported. Attempting to program a pin widget control with a

reserved or unsupported value will cause the associated Vref_Out pin to assume a Hi-Z state and

the pin widget control Vref_En field will return a value of ‘000’ (Hi-Z) when read.

2.1.3. Jack Detect

Plugs inserted to a jack on Ports A, B, C & SPDIFOUT0 are detected using SENSE_A. Plugs

inserted to a jack on Ports E,F, DMIC0, & SPDIFOUT1 are detected using SENSE_B. Per

HDA015-B, the detection circuit operates when the CODEC is in D0 - D3 and can also operate if

both the CODEC and Controller are in D3 (no bus clock.) Jack detection requires that all supplies

(analog and digital) are active and stable. When AVDD is not present, the value reported in the pin

widget is invalid.

When the HD Audio bus is in a low power state (reset asserted and clock stopped) the CODEC will

generate a Power State Change Request when a change in port connectivity is sensed and then

generate an unsolicited response after the HD Audio link has been brought out of a low power state

and the device has been enumerated. Per HDA015-B, this will take less than 10mS.

The following table summarizes the proper resistor tolerances for different analog supply voltages..

See reference design for more information on Jack Detect implementation.

2.1.4. SPDIF Output

Both SPDIF Outputs can operate at 44.1kHz, 48kHz, 88.2kHz, 96kHz and 192KHz as defined in the

Intel High Definition Audio Specification with resolutions up to 24 bits. This insures compatibility with

all consumer audio gear and allows for convenient integration into home theater systems and media

center PCs.

The two SPDIF output converters can not be aligned in phase with the DACs. Even when attached

to the same stream, the two SPDIF output converters may be misaligned with respect to their frame

boundaries.

AVdd Nominal

Voltage (+/- 5%)

Resistor Tolerance

Pull-Up

Resistor Tolerance

SENSE_A/B

4.75V 1% 1%

Resistor SENSE_A SENSE_B

39.2K PORT A (HP0) PORT E

20.0K PORT B (HP1) PORT F

10.0K PORT C DMIC0

5.11K SPDIFOUT0 SPDIFOUT1

(DMIC1)

2.49K Pull-up to AVDD Pull-up to AVDD

Table 3. 48pin Jack Detect

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SINGLE CHIP PC AUDIO SYSTEM,CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO

Per the HDA015-B , the SPDIF outputs support the ability to provide clocking information even when

no stream is selected for the converter, or when in a low power state. Also, the SPDIF output ports

support port presence detect.

SPDIF Outputs are outlined in tables below.

AFG Power

State RESET# Output

Enable

Converter

Dig

Enable

Stream

Keep

Alive

Enab

Pin Behavior

D0-D3 Asserted (Low) - - - - Hi-Z (internal pull-down enabled) immediately after

power on, otherwise the previous state is retained.

De-Asserted (High) Disabled - - - Hi-Z (internal pull-down enabled)

De-Asserted (High) Enabled Disabled - - Active - Pin drives 0 (internal pull-down NA)

De-Asserted (High) Enabled Enabled 0 - Active - Pin drives SPDIF-format, but data is zeroes

(internal pull-down NA)

De-Asserted (High) Enabled Enabled 1-15 - Active - Pin drives SPDIFOut0 data (internal pull-down

NA)

D1-D2

De-Asserted (High) Disabled - - - Hi-Z (internal pull-down enabled)

De-Asserted (High) Enabled

- - 0 Active - Pin drives 0 (internal pull-down NA)

Enabled - 1 Active - Pin drives SPDIF-format, but data is zeroes

(internal pull-down NA)

D3 De-Asserted (High)

- - - 0 Hi-Z (internal pull-down enabled)

Disabled - - 1 Hi-Z (internal pull-down enabled)

Enabled Enabled - 1 Active - Pin drives SPDIF-format, but data is zeroes

(internal pull-down NA)

D3cold - - - - - Hi-Z (internal pull-down enabled)

D4 - - - - - Hi-Z (port off)

D5 - - - - - Hi-Z (port off)

Table 4. SPDIF OUT 0 Behavior

AFG

Power

State

RESET# GPIO0

Enable

Input

Enable

Output

Enable

Convert

er Dig

Strea

m ID

Keep

Alive

Pin Behavior

D0-D3Asserted (Low)------

Hi-Z (internal pull-down enabled)

immediately after power on, otherwise

the previous state is retained.

D0-D3 De-Asserted

(High) Enabled-----

Active - Pin reflects GPIO0 configuration

(internal pull-down enabled)

D0-D3 De-Asserted

(High) Disabled Enabled Disabled - - - Pin functions as digital mic input

(internal pull-down enabled)

Table 5. SPDIF OUT 1 Behavior

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2.2. Mono Output

The Mono Out port source selection, power state, and mute characteristics are all independently

controlled by the mono output port controls. EQ does not apply to this path. An internal 2nd order

band-pass filter is provided to restrict the output frequencies when using mono out to drive an exter-

nal amplified sub-woofer.

The following sources are available for the Mono Out pin:

• DAC0 Output: When selected (by using the port connection list), the DAC0 left and right outputs

are summed together.

• DAC1 Output: When selected (by using the port connection list), the DAC1 left and right outputs

are summed together.

• Mixer Output: When selected (by using the port connection list), the mixer left and right outputs

are summed together.

The stereo inputs are scaled by -6dB and then summed to provide an output that is the average of

the two inputs. The full scale output at mono out is designed to be about 0dBV. It is not possible to

adjust to a +3dBV output level.

D0 De-Asserted

(High) Disabled

Disabled Disabled - - - Hi-Z (internal pull-down enabled)

- Enabled

Disabled - - Active - Pin drives 0 (internal pull-down

NA)

Enabled

0- Active - Pin drives SPDIF-format, but

data is zeroes (internal pull-down NA)

1-15 - Active - Pin drives SPDIFOut1 data

(internal pull-down NA)

D1-D2 De-Asserted

(High) Disabled Disabled

Disabled - - - Hi-Z (internal pull-down enabled)

Enabled

Disabled - - Active - Pin drives 0 (internal pull-down

NA)

Enabled

-0

Active - Pin drives 0 (internal pull-down

NA)

-1

Active - Pin drives SPDIF-format, but

data is zeroes (internal pull-down NA)

D3 De-Asserted

(High) Disabled Disabled

Disabled - - - Hi-Z (internal pull-down enabled)

Enabled

Disabled - - Hi-Z (internal pull-down enabled)

Enabled

- 0 Hi-Z (internal pull-down enabled)

-1

Active - Pin drives SPDIF-format, but

data is zeroes (internal pull-down NA)

D3cold - Disabled Disabled - - - - Hi-Z (internal pull-down enabled)

D4- ------Hi-Z (port off)

D5- ------Hi-Z (port off)

AFG

Power

State

RESET# GPIO0

Enable

Input

Enable

Output

Enable

Convert

er Dig

Strea

m ID

Keep

Alive

Pin Behavior

Table 5. SPDIF OUT 1 Behavior

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92HD91

SINGLE CHIP PC AUDIO SYSTEM,CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO

2.3. Mono output Band-Pass Filter

For many applications, the primary speakers are incapable of reproducing low frequency audio.

Therefore it is desirable to implement a woofer or sub-woofer speaker. The mono output is ideal for

this task.

However, the frequency response should be restricted to prevent interference with the primary

speakers. Typically an external filter, known as a cross-over filter, is used. The mono processing

path includes a band-pass filter with programmable high and low cut-off frequencies to eliminate the

need for an external filter.

2.3.1. Filter Description

The band-pass filter is derived from the common biquadratic filter and provides a 12dB/octave

roll-off. The filter may be programmed for a -3dB lower band edge of: 63Hz, 80Hz, 100Hz, 120Hz,

150Hz, 200Hz, 315Hz, or 400Hz. The filter may be programmed for a -3dB upper band edge of:

150Hz, 200Hz, 250Hz, 315Hz, 400Hz, 500Hz, 630Hz, or 800Hz.

The band-pass filter is enabled by default with a cut-off frequencies at 120Hz and 250Hz. The filter

may be bypassed using the associated verb (processing state verb).

The Analog PC_Beep input is not affected by the band-pass filter.

2.4. Mixer

The mixer supports independent gain (-34.5 to +12dB in 1.5dB steps) on each input as well as inde-

pendent mutes on each input. The following inputs are available:

•Port A

•Port C

•Port E

•Port F

•DAC 0

•DAC 1

2.5. ADC Multiplexers

The codec implements 2 ADC input multiplexers. These multiplexers incorporate the ADC record

gain function :(-16 to +30dB gain in 1dB steps) as an output amp and allow a preselection of one of

below possible inputs:

•Port A

•Port C

•Port E

•Port F

• Mixer Output

•DMIC 0

•DMIC 1

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2.6. Power Management

The HD Audio specification defines power states, power state widgets, and power state verbs.

Power management is implemented at several levels. The Audio Function Group (AFG) , all con-

verter widgets, and all pin complexes support the power state verb F05/705. Converter widgets are

active in D0 and inactive in D1-D3.

The following table describes what functionality is active in each power state.

The D3-default state is available for HD Audio compliance. The programmable values, exposed via

vendor-specific settings, are under TSI Device Driver control for further power reduction. The analog

mixer, line and headphone amps, port presence detect, and internal references may be disabled

using vendor specific verbs. Use of these vendor specific verbs will cause pops.

Function D0 D11

1. No DAC or ADC streams are active. Analog mixing and loop thru are supported.

D2 D3 D3cold Vendor

Specific D4

Vendor

SpecificD5

SPDIF Outputs On On On (idle) On (idle)5Off Off Off

Digital Microphone inputs On Off Off Off Off Off Off

DAC On Off Off Off Off Off Off

D2S On Off Off Off Off Off Off

ADC On Off Off Off Off Off Off

ADC Volume Control On Off Off Off Off Off Off

Ref ADC On Off Off Off Off Off Off

Analog Clocks On Off Off Off Off Off Off

GPIO pins On On On On5On On Off

VrefOut Pins On On Off Off Off Off Off

Input Boost On On Off Off Off Off Off

Analog mixer On On Off Off Off Off Off

Mixer Volumes On On Off Off Off Off Off

Analog PC_Beep On On On On Off Off Off

Digital PC_Beep On On On On5Off Off Off

Lo/HP Amps On On On Low Drive2

2. VAG is kept active when ports are disabled or in D3/D3cold/D4. PC_Beep is supported in D3 but may be attenuated and

distorted depending on load impedance. The codec will shut down the capless headphone amplifiers and BTL amplifier in

D3 and below. In D3, Hendrix/Kaveri will turn on the BTL and Capless amplifiers if activity is detected on the PC_BEEP

input and analog PC_Beep is enabled.

Low Drive2Low Drive2Off

Cap-less HP Amps On On On Low Drive2Low Drive2Low Drive2Off

BTL Amp On On On Low Drive2Off Off Off

VAG amp On On On Low Drive3

3. VAG is always ramped up and down gradually, except in the case of a sudden power removal. VAG is active in D2/D3 but

in a low power state.

Low Drive Low Drive Off

Port Sense OnOnOn On

4. Both AVDD and DVDD must be available for Port Sense to operate.

Off Off Off

Reference Bias generator On On On On On On Off

Reference Bandgap core On On On On On On Off

HD Audio-Link On On On On5

5. Not active if BITCLK is not running (Controller in D3), but can signal power state change request (PME)

Limited Off Off

Table 6. Power Management

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The default power state for the Audio Function Group after reset is D3.

2.7. AFG D0

The AFG D0 state is the active state for the device. All functions are active if their power state (if they

support power management at their node level) has been set to D0.

2.8. AFG D1

D1 is a lower power mode where all converter widgets are disabled. Analog mixer and port functions

are active. The part will resume from theD1 to theD0 state within 1 mS.

2.9. AFG D2

The D2 state further reduces power by disabling the mixer and port functions. The port amplifiers

and internal references remain active to keep port coupling caps charged and the system ready for a

quick resume to either the D1 or D0 state. The part will resume from the D2 state to the D0 state

within 2mS.

2.10. AFG D3

The D3-default state is available for HD Audio compliance. All converters are shut down. Port ampli-

fiers and references are active but in a low power state to prevent pops. Resume times may be lon-

ger than those from D2, but still less than 10mS to meet Intel low power goals. The default power

state for the Audio Function Group after power is applied is D3.

While in AFG D3, the HD Audio controller may be in a D0 state (HD Audio bus active) or in a D3

state (HD Audio bus held in reset with no Bit_Clk, SData_Out, or Sync activity.) The expected behav-

ior is as follows (see the HDA015-B section for more information):

2.10.1. AFG D3cold

The D3cold power state is the lowest power state available that does not use vendor specific verbs.

While in D3cold, the CODEC will still respond to bus requests to revert to a higher power state (dou-

ble AFG reset, link reset). However, audio processing, port presence detect, and other functions are

disabled. Per the HD Audio bus HDA015-B, the D3cold state is intended to be used just prior to

removing power to the CODEC. Typically, power will be removed within 200mS. However, the codec

may exit from the D3cold state by generating 2, back-to-back, AFG reset events. Resume time from

D3cold is less than 200mS.

2.11. Vendor Specific Function Group Power States D4/D5

The codec introduces vendor specific power states. A vendor defined verb is added to the Audio

Function Group that combines multiple vendor specific power control bits into logical power states

for use by the audio driver. The 2 states defined offer lower power than the 5 existing states defined

in the HD Audio specification and HDA015-B. The Vendor Specific D4 state provides lower digital

power consumption relative to D3cold by disabling HD Audio link responses. Vendor specific D5 fur-

Function HDA Bus active HDA Bus stopped

Port Presence Detect state change Unsolicited Response Wake Event followed by an unsolicited response

GPIO state change Unsolicited Response Wake Event followed by an unsolicited response

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ther reduces power consumption on the digital supply by turning off GPIO drivers, and reduces ana-

log power consumption by turning off all analog circuitry except for reset circuits.

States D4/D5 are not entered until D3cold has been requested so are actually D3cold options rather

than true, independent, power states. Software can pre-program the D4 or D5 state as a re-definition

of how the part will behave when the D3cold power state is requested or software may enter D3cold,

then set the D4 or D5 before performing the power state get command. The preferred method is to

request D3cold, then select D4 or D5 as desired.This will reduce the severity of pops encountered

when entering D4 or D5.

Both power states require a link reset or removal of DVDD to exit.

The CODEC may pop when using these verbs and transition times to an active state (D1 or D0 for

example) may take several seconds.

2.12. Low-voltage HDA Signaling

The codec is compatible with either 1.5V or 3.3V HDA bus signaling; in the 48QFN package the volt-

age selection is done dynamically based on the input voltage of DVDD_IO.

DVDD_IO is currently not a logic configuration pin, but rather provides the digital power supply to be

used for the HDA bus signals.

When in 1.5V mode, the codec can correctly decode BITCLK, SYNC, RESET# and SDO as they

operate at 1.5V; additionally it will drive SDI and SDO at 1.5V. None of the GPIOs are affected, as

they always function at their nominal voltage (DVDD or AVDD).

2.13. Multi-channel capture

The capability to assign multiple “ADC Converters” to the same stream is supported to meet the

microphone array requirements of Vista and future operating systems. Single converter streams are

still supported this is done by assigning unique non zero Stream IDs to each converter. All capture

devices (ADCs 0 and 1) may be used to create a multi-channel input stream. There are no restric-

tions regarding digital microphones.

The ADC Converters can be associated with a single stream as long the sample rate and the bits per

sample are the same. The assignment of converter to channel is done using the “CnvtrID” widget

and is restricted to even values. The ADC converters will always put out a stereo sample and there-

fore require 2 channels per converter.

The stream will not be generated unless all entries for the targeted converters are set identically, and

the total number of assigned converter channels matches the value in the NmbrChan field. These

are listed the “Multi-Converter Stream Critical Entries.” table.

An example of a 4 Channel Steam with ADC0 supplying channels 0&1 and ADC1 supplying chan-

nels 2 & 3 is shown below. A 4 Channel stream can be created by assigning the same non-zero

stream id “Strm= N” to both ADC0 and ADC1. The sample rates must be set the same and the num-

ber of channels must be set to 4 channels “NmbrChan = 0011”.

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Figure 1. Multi-channel capture

The following figure describes the bus waveform for a 24-bit, 48KHz capture stream with ID set to 1.

Figure 2. Multi-channel timing diagram

ADC1 CnvtrID (NID = 0x08)

[3:0] Ch = 2

ADC0 CnvtrID (NID = 0x07)

[3:0] Ch=0

Table 7. Example channel mapping

ADC[1:0] Cnvtr Bit Number Sub Field Name Description

[15] StrmType Stream Type (TYPE):

0: PCM

1: Non-PCM (not supported)

[14] FrmtSmplRate Sample Base Rate

0= 48kHz

1=44.1KHz

[13:11] SmplRateMultp Sample Base Rate Multiple

000=48kHz/44.1kHz or less

001= x2

010= x3 (not supported)

011= x4 192kHz only, 176.4 not supported

100-111= Reserved

Table 8: Mult-channel

Stream ID Data

Length

ADC0

Left Channel

ADC0

Right Channel

ADC1

Left Channel

ADC1

Right Channel

Stream ID Data

Length

ADC1

Left Channel

ADC1

Right Channel

ADC0

Left Channel

ADC0

Right Channel

ADC0.CnvrtID.Channel = 0

ADC1.CnvrtID.Channel = 2

ADC0.CnvrtID.Channel = 2

ADC1.CnvrtID.Channel = 0

00 0

SDI

BITCLK

1001100

STREAM ID DATA LENGTH

STREAM TAG

ADC0

L23

ADC0

R23

ADC0

ADC1

L23

ADC1

R23

ADC1

LEFT LEFTRIGHT RIGHT

ADC0 ADC1

DATA BLOCK

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2.14. EAPD

The EAPD pin (pin 47) is a dedicated, bi-directional control pin. Although named External Amplifier

Power Down (EAPD) by the HD Audio specification, this pin operates as an external amplifier power

up signal. The EAPD value is reflected on the EAPD pin; a 1 causes the external amplifier to power

up (equivalent to D0), and a 0 causes it to power down (equivalent to D3.) When the EAPD value =

1, the EAPD pin must be placed in a state appropriate to the current power state of the associated

Pin Widget even though the EAPD value (in the register) may remain 1. The default state of this pin

is 0 (driving low.) The pin defaults to an open-drain configuration (an external pull-up is recom-

mended.)

Per the HD Audio specification and HDA015-B, multiple ports may control EAPD. The EAPD pin

assumes the highest power state of all the the EAPD bits in all of the pin complexes. The default

value of EAPD is 1 (powered on), but the FG power state will override and the pin will be low. A port

will request External Amp Power Up when its power state is active (FG and pin widget power state is

D1 or D0) or (Analog PC_Beep is enabled and port is enabled as an output) and the port’s EAPD bit

is set to 1. The state of the EAPD pin (unless configured as an input or held low by an external circuit

when configured as an open drain output) will be the logical OR of the external amp power up

requests from all ports.

[10:8] SmplRateDiv Sample Base Rate Divisor

000= Divide by 1

001= Divide by 2 (not supported)

010= Divide by 3 (not supported)

011= Divide by 4 (not supported)

100= Divide by 5 (not supported)

101= Divide by 6 (not supported)

110= Divide by 7 (not supported)

111= Divide by 8 (not supported)

[6:4] BitsPerSmpl Bits per Sample

000= 8 bits (not supported)

001= 16 bits

010= 20 bits

011= 24 bits

100-111= Reserved

[3:0] NmbrChan Number of Channels

Number of channels for this stream in each “sample

block” of the “packets” in each “frame” on the link.

0000=1 channel (not supported)

0001 = 2 channels

…

1111= 16 channels.

[7:4] Strm Software-programmable integer representing link

stream ID used by the converter widget. By conven-

tion stream 0 is reserved as unused.

[3:0] Ch Integer representing lowest channel used by con-

verter.

0 and 2 are valid Entries

If assigned to the same stream, one ADC must be

assigned a value of 0 and the other ADC assigned a

value of 2.

Table 8: Mult-channel

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By default, the EAPD pin also functions as the Mute#/ShutDown# input for the internal BTL amplifier.

In this mode, a low value at the pin (either due to internal EAPD being 0, or to an external entity forc-

ing the pin low) will cause the internal BTL amplifier to mute or enter a low power state depending on

the amplifier configuration. (See below)

Vendor specific verbs are available to configure this pin. These verbs retain their values across link

and single function group resets but are set to their default values by a power on reset:

MODE1 MODE0 EAPD Pin Function Description

0 0 Open Drain I/O Value at pin is wired-AND of EAPD bit and external signal.(default)

0 1 CMOS Output Value of EAPD bit in pin widget is forced at pin

1 0 CMOS Input External signal controls internal amps. EAPD bit in pin widget ignored

1 1 CMOS Input External signal controls internal amps. EAPD bit in pin widget ignored

Table 9. EAPD Pin Mode Select

Control Flag Description

EAPD PIN MODE 1:0 Defines if EAPD pin is used as input, output, or bi-directional port (Open Drain)

BTL/HP SD 0 = Amp controlled by EAPD pin only (default) / 1 = Amp controlled by power state (pin and FG) only

BTL/HP SD MODE 0 = Amp will mute when disabled. / 1 = Amp will shut down (enter a low power state) when disabled (default

for YA forward)

BTL/HP SD INV 0 = AMP will power down (or mute) when EAPD pin is low (default) / 1 = Amp will power down (or mute)

when EAPD pin is high.

Table 10. Control bit descriptions for BTL amplifier and Headphone amplifier enable configurations

BTL SD BTL SD

MODE

BTL SD INV EAPD Pin

State

BTL Amp State

0 0 0 0 Amplifier is mute (default1)

1. EAPD bit is set to one by default but the EAPD state is 0 after power-on reset because the function group is not in D0. The

state after a single or double function group reset will be compliant with HDA015-B.

0 0 0 1 Amplifier is active

0 0 1 0 Amplifier is active

0 0 1 1 Amplifier is mute

0 1 0 0 Amplifier is in a low power state

0 1 0 1 Amplifier is active

0 1 1 0 Amplifier is active

0 1 1 1 Amplifier is in a low power state

1 0 NA NA Amplifier follows pin/function group power state and will mute when disabled

1 1 NA NA Amplifier follows pin/function group power state and will enter a low power

state when disabled

Table 11. BTL Amp Enable Configuration

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HP SD HP SD

MODE

HP SD INV EAPD Pin

State

Headphone Amp State

0 0 0 0 Amplifier is mute (default1)

0 0 0 1 Amplifier is active

0 0 1 0 Amplifier is active

0 0 1 1 Amplifier is mute

0 1 0 0 Amplifier is in a low power state

0 1 0 1 Amplifier is active

0 1 1 0 Amplifier is active

0 1 1 1 Amplifier is in a low power state

1 0 NA NA Amplifier follows pin/function group power state and will mute when disabled

1 1 NA NA Amplifier follows pin/function group power state and will enter a low power

state when disabled

Table 12. Headphone Amp Enable Configuration

1. EAPD bit is set to one by default but the EAPD state is 0 after power-on reset because the function group is not in D0. The

state after a single or double function group reset will be compliant with HDA015-B.

Port E Headphone Amp Enable Configuration Bits Normal Mode Aux Mode

SD (EAPD Pin or power setting) Not supported1

SD INV Not supported1supported2

SD MODE (power down or mute) Not supported1

Table 13. Port E Headphone Amp Enable Configuration support by part and mode

1. Port E not headphone capable on the 92HD94

2. Port E is typically connected to the dock headphone port. In Aux mode, EAPD will mute the record path on the 92HD94.

Analog

BEEP

enabled

EAPD Pin value1

1. When pin is enabled as Open Drain or CMOS output.

Description

0Forced to low when in D2

or D3

Follows description in HD Audio spec. External amplifier is shut down when pin or function

group power state is D2 or D3 independent of value in EAPD bit.

Forced low in D2 or D3

unless port is enabled as

output

Power state is ignored if port is enabled as output and port EAPD=1 to allow PC_Beep

support in D2 and D3

Table 14. EAPD Analog PC_Beep behavior

AFG

Power

State

RESET# Analog

PC_BEEP

Port Power

State Pin Behavior

D0-D3 Asserted (Low) - - Active low immediately after power on, otherwise the previous

state is retained across FG and link reset events

D0 De-Asserted (High) - - Active - Pin reflects EAPD bit unless held low by external source.

D1 De-Asserted (High) - D0-D1 Active - Pin reflects EAPD bit unless held low by external source.

D2 De-Asserted (High) Disabled D0-D2 Pin forced low to disable external amp

Table 15. EAPD Behavior

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Figure 3. HP EAPD Example to be replaced by single pin for internal amp

D2 De-Asserted (High) Enabled D0-D2 Active - EAPD Pin high if any port EAPD bit =1 and that port also

enabled as output.

D3 De-Asserted (High) Disabled D0-D3 Pin forced low to disable external amp

D3 De-Asserted (High) Enabled D0-D3 Active - EAPD Pin high if any port EAPD bit=1 and that port also

enabled as output.

D3cold De-Asserted (High) - - Pin forced low to disable external amp

D4 De-Asserted (High) - - Pin forced low to disable external amp

D5 De-Asserted (High) - - Pin Hi-Z (off)

AFG

Power

State

RESET# Analog

PC_BEEP

Port Power

State Pin Behavior

Table 15. EAPD Behavior

MUTE +

UP/DOWN

BUTTONS

KBC CODEC

SPKR AMP

SCAN

CODES

A_SD

A_EAPD

SPKR_EN#

GPIO_1

SYNC FROM AUDIO GUI TO KBC

SYNC FROM KBC TO OS

(MUTE LED ON

SAME BOARD)

HP AUDIO CONTROL BLOCK DIAGRAM

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Figure 4. EAPD implementation

2.15. Digital Microphone Support

The digital microphone interface permits connection of a digital microphone(s) to the CODEC via the

DMIC0, DMIC1, and DMIC_CLK 3-pin interface. The DMIC0 and DMIC1 signals are inputs that carry

individual channels of digital microphone data to the ADC. In the event that a single microphone is

used, the data is ported to both ADC channels. This mode is selected using a vendor specific verb

and the left time slot is copied to the ADC left and right inputs.

The DMIC_CLK output is controllable from 4.704Mhz, 3.528Mhz, 2.352Mhz, 1.176Mhz and is syn-

chronous to the internal master clock. The default frequency is 2.352Mhz.

The two DMIC data inputs are reported as two stereo input pin widgets that incorporate a boost

amplifier. The pin widgets are shown connected to the ADCs through the same multiplexors as the

analog ports. Although the internal implementation is different between the analog ports and the dig-

ital microphones, the functionality is the same. In most cases, the default values for the DMIC clock

rate and data sample phase will be appropriate and an audio driver will be able to configure and use

the digital microphones exactly like an analog microphone.

To conserve power, the analog portion of the ADC will be turned off if the D-mic input is selected.

When switching from the digital microphone to an analog input to the ADC, the analog portion of the

ADC will be brought back to a full power state and allowed to stabilize before switching from the dig-

ital microphone to the analog input. This should take less than 10mS.

DMIC pin widgets support port presence detect directly using SENSE-B input.

SMU MUTE OTHER

External

Power Amp

SD#

Internal BTL

Amp

EAPD PIN

Control

SD/Mute

CODEC

VDD

EAPD

SD/Mute

Internal

Headphone

Amp

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The codec supports the following digital microphone configurations:

Digital

Mics Data Sample ADC

Conn. Notes

0 N/A N/A No Digital Microphones

1 Single Edge 0, or 1

Available on either DMIC_0 or DMIC_1

When using a microphone that supports multiplexed operation (2-mics can share a

common data line), configure the microphone for “Left” and select mono operation using

the vendor specific verb.

“Left” D-mic data is used for ADC left and right channels.

2Double Edge on

either DMIC_0 or 1 0, or 1

Available on either DMIC_0 or DMIC_1, External logic required to support sampling on a

single Digital Mic pin channel on rising edge and second Digital Mic right channel on

falling edge of DMIC_CLK for those digital microphones that don’t support alternative

clock edge (multiplexed output) capability.

Double Edge on

one DMIC pin and

Single Edge on the

second DMIC pin.

0, or 1

Requires both DMIC_0 and DMIC_1, External logic required to support sampling on a

single Digital Mic pin channel on rising edge and second Digital Mic right channel on

falling edge of DMIC_CLK for those digital microphones that don’t support alternative

clock edge (multiplexed output) capability. Two ADC units are required to support this

configuration

4 Double Edge 0, or 1

Connected to DMIC_0 and DMIC_1, External logic required to support sampling on a

single Digital Mic pin channel on rising edge and second Digital Mic right channel on

falling edge of DMIC_CLK for those digital microphones that don’t support alternative

clock edge capability. Two ADC units are required to support this configuration

Table 16. Valid Digital Mic Configurations

Power State DMIC Widget

Enabled?

DMIC_CLK

Output DMIC_0,1 Notes

D0 Yes Clock Capable Input Capable DMIC_CLK Output is Enabled when either DMIC_0 or DMIC_1

Input Widget is Enabled. Otherwise, the DMIC_CLK remains Low

D1-D3 Yes Clock Disabled Input Disabled DMIC_CLK is HIGH-Z with Weak Pull-down

D0-D3 No Clock Disabled Input Disabled DMIC_CLK is HIGH-Z with Weak Pull-down

D4 - Clock Disabled Input Disabled DMIC_CLK is HIGH-Z with Weak Pull-down

D5 - Clock Disabled Input Disabled DMIC_CLK is HIGH-Z with Weak Pull-down

Table 17. DMIC_CLK and DMIC_0,1 Operation During Power States

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Figure 5. Single Digital Microphone (data is ported to both left and right channels

DMIC_0

DMIC_1

DMIC_CLK

Right

Channel

Left

Channel

Valid Data Valid Data Valid Data

DMIC_0

DMIC_1

DMIC_CLK

Single Line In

Pin On-Chip

Multiplexer

Digital

Microphone

On-ChipOff-Chip

MUX

Stereo Channels

Output

STEREO

ADC0 or 1

PCM

DMIC_0

DMIC_1

DMIC_CLK

Left & Right

Channel

Valid DataValid Data Valid Data Valid Data

Single “Left” Microphone, DMIC input set to mono input mode.

Single Microphone not supporting multiplexed output.

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Figure 6. Stereo Digital Microphone Configuration

Note: Some Digital Microphone Implementations support data on either edge, therefore, the

external mux may not be required.

DMIC_0

DMIC_1

DMIC_CLK

Right

Channel

Left

Channel

Valid

Data R

Valid

Data L

Valid

Data R

Valid

Data L

Valid

Data R

Digital

Microphones

DMIC_CLK

MUX

Stereo Channels

Output

External

Multiplexer

On-Chip

Multiplexer

On-ChipOff-Chip

STEREO

ADC0 or 1

PCM

MUX

DMIC_0

DMIC_1

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Figure 7. Quad Digital Microphone Configuration

Note: Some Digital Microphone Implementations support data on either edge, in this case the

external multiplexer is not required.

2.16. Analog PC-Beep

The codec supports automatic routing of the PC_Beep pin to Port A, Port B, and Port D outputs

when the HD-Link is in reset.

When the link is active (not held in reset) Analog PC-Beep may be enabled manually. Analog

PC_Beep is mixed at the port and only ports enabled as outputs will pass PC_Beep.

DMIC_1

DMIC_CLK

DMIC_0

Right

Channel

Left

Channel

Valid

Data R1

Valid

Data L1

Valid

Data R1

Valid

Data L1

Valid

Data R1

Valid

Data R0

Valid

Data L0

Valid

Data R0

Valid

Data L0

Valid

Data R0

Right

Channel

Left

Channel

MUX

Stereo Channels

Output For

DMIC_0 L&R

On-Chip

Multiplexer

STEREO

ADC0

PCM

MUX

Stereo Channels

Output For

DMIC_1 L&R

On-Chip

Multiplexer

STEREO

ADC1

PCM

Digital

Microphones

DMIC_CLK

External

Multiplexer

MUX

DMIC_0

On-ChipOff-Chip

Digital

Microphones

External

Multiplexer

MUX

DMIC_1

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Beep activity monitoring is provided when the analog beep path is enabled and the CODEC or ampli-

fier is in a low power state (D3).

The Analog PC Beep input is sampled for 500us every 1ms. If the beep input is high or low

(>200mVpp) for at least 37% of that time, it is considered active. If it is active for less than 7.5% of

that time, it is possibly inactive. If no activity is detected for 64ms (128ms, 256ms and 512ms also

selectable for the idle threshold), then beep is considered inactive.

Figure 8. Analog PC Beep Active

Phase 1: analog beep auto-routing phase in the period after application of DVDD, before the first ris-

ing edge of link reset.

Once Analog PCbeep is detected(BEEP_PRESENCE=1) after 64ms delays (after POR (power on

reset)), the Amplifier will be turned on(port_pwd=0, port_output_en=1, there is a timing between

these two signals) and analog_beep_en=1. If BEEP_PRESENCE=0 for longer than the threshold

time, the amplifiers will be turned off to save power and prevent unwanted system noise from being

heard.

Phase 2: When not in phase 1

A. If analog beep function is disabled by driver.

Analog beep auto-detect will also be disabled.

B. If analog beep function is enabled by driver.

Once analog PCbeep is detected(BEEP_PRESENCE=1), analog pc_beep will be enabled

If in D0-D2, enabled simply means muting or un-muting beep to avoid hearing system noise on the

beep input pin but it is acceptable to turn off port amplifiers if not currently used by DACs, mixer, or

beep to save power.

If in D3, enabled means that the necessary amplifiers are turned on so that the beep signal may be

heard on all ports configured as outputs (see analog pc-beep description section above)

All needed amplifiers are enabled until BEEP_PRESENCE=0 for longer than the idle threshold

A flow chart of Analog PC Beep is below.

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Figure 9. Analog PC Beep Flow chart

2.17. Digital PC-Beep

This block uses an 8-bit divider value to generate the PC beep from the 48kHz HD Audio Sync

pulse. The digital PC_Beep block generates the beep tone on all Pin Complexes that are currently

configured as outputs. The HD Audio spec states that the beep tone frequency = (48kHz HD Audio

POR

Wait

64mS

Activity on Pin?

Link Reset

Active?

Turn on

Amplifiers / Enable

Beep Path

Activity on Pin?

Analog

PC_Beep

Enabled?

YESYES

YES YES

Activity on Pin?

Inactivity over

threshold?

Disable Beep

Path / Turn off

Amplifiers

YES

IDLE

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SYNC rate) / (4*Divider), producing tones from 47 Hz to 12 kHz (logarithmic scale). Other audio

sources are disabled when digital PC_Beep is active.

It should be noted that digital PC Beep is disabled if the divider = 00h.

PC-Beep may be attenuated and distorted when the CODEC is in D3 depending on the load imped-

ance seen by the output amplifier since all ports are in a low power state while in D3. Load imped-

ances of 10K or larger can support full scale outputs but lower impedance loads will distort unless

the output amplitude is reduced. Digital PC_Beep requires a clock to operate and the CODEC will

prevent the system from stopping the bus clock while in D3 by setting the Clock_Stop_OK bit to 0 to

indicate that the part requires a clock.

2.18. Headphone Drivers

The codec implements both traditional and cap-less headphone outputs. The Microsoft Windows

Logo Program allows up to the equivalent of 100ohms in series. However, an output level of +3dBV

at the pin is required to support 300mV at the jack with a 32ohm load and 1V with a 320 ohm load.

Microsoft allows device and system manufactures to limit output voltages to address EU safety

requirements. (WLP 3.09 - please refer to the latest Windows Logo Program requirements from

Microsoft.) The codec does not support power limiting.

Headphone performance will degrade if more than one port is driving a 32 ohm load.

2.19. BTL Amplifier

An integrated class-D stereo BTL amplifier is provided to directly drive 4 ohm speakers (2W @

4.75V) or 8 ohm speakers (1W @ 4.75V). No external filter is needed for cable runs of 18” or less.

An internal DC blocking filter prevents distortion when the audio source has DC content, and pre-

vents unintentional power consumption when pausing audio playback. The amplifier may be con-

trolled using the EAPD pin (see EAPD section.)

Using a vendor specific verb, the BTL amplifier may be configured to support a mono speaker con-

nected to the L +/- pins. In this mode, the Left and Right audio is mixed and sent to the left output

only. The right channel is turned off to conserve power.

Maximum gain for the BTL amplifier is programmable. The following 4 gain settings relative to a

nominal line output are desired: +6.5dB, +9.5dB, +14.5dB, +16.5dB. Absolute gain may vary and the

suggested accuracy is +/-1.5dB.

This gain is exposed in a vendor specific widget and is intended to mimic the pin programmable gain

implemented in discrete BTL amplifiers commonly used in notebook computers.

The BTL amplifier includes thermal management circuitry. When the CODEC reaches a temperature

of about 140 degrees, the output amplitude of the BTL amp is gradually lowered until the tempera-

ture falls below 140. All other functions will remain active if the BTL amplifier is shut down due to die

temperature.

2.20. BTL Amplifier High-Pass Filter

For mobile applications, speakers are often incapable of reproducing low frequency audio and

unable to handle the maximum output power of the BTL amplifier. A high-pass filter is implemented

in the BTL output path to reduce the amount of low frequency energy reaching speakers attached to

the BTL amplifier. This can prevent speaker failure.

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2.20.1. Filter Description

The high-pass filter is derived from the common biquadratic filter and provides a 12dB/octave roll-off.

The filter may be programmed for a -3dB response at: 100Hz, 200Hz, 300Hz, 400Hz, 500Hz, 750Hz,

1KHz, or 2KHz. The high pass filter is enabled by default with a cut-off frequency of 300Hz. The filter

may be bypassed using the associated verb (processing state verb).

The analog PC_Beep input is not affected by the digital high-pass filter. To ensure that the speakers

attached to the BTL amplifier are not harmed by low frequency audio entering the PC_Beep input, an

external filter must be implemented. Fortunately, it is common practice to implement an attenuation

circuit and DC blocking capacitor at the PC_Beep input. This attenuator/filter is easily adjusted to

restrict low frequency audio. The easiest approach is to reduce the value of the DC blocking capaci-

tor but other approaches are equally effective.

2.21. EQ

There are 5 bands of parametric EQ (bi-quad) per channel. Due to the flexibility of the bi-quad imple-

mentation, each filter band may be configured as a high-pass, low-pass, band-pass, high shelving,

low shelving, or other function.

Each band has an independent set of coefficients. A bi-quad filter has 6 coefficients. One coefficient

is normalized to 1 and 5 are programmed into the core. Each band supports up to +15dB boost or up

to -36dB cut.

2.22. Combo Jack Detection

4 conductor (combo) jacks are becoming popular. In the most common implementation the 4 con-

ductor plug has the same mechanical dimensions as a 3 conductor 3.5mm plug but the sleeve por-

tion has been split into two segments:S1 and S2. When a 4-conductor plug (headset) is inserted into

the jack T (Tip) = Left headphone audio, R (Ring) = Right headphone audio, S1 (First half of sleeve)

= microphone input, and S2 (Second half of sleeve) = return (GND). When a 3-conductor plug

(headphones) is inserted into the jack; T=Left audio, R=Right audio, S1=GND, S2=GND. By moni-

toring the S1 connection to see if it is shorted to ground, we can distinguish between headsets and

headphones. Please note that analog microphone plugs (3-conductor-Lmic/Rmic/GND) and optical

SPDIF plugs can not be supported using this implementation.

Figure 10. Combo Jack

Plug insertion is reported on the headphone port using the switch integrated into the jack.

The internal circuit monitors the voltage at the jack to determine if a low impedance load is present.

GND

MIC

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Detection of a microphone is not reported unless plug insertion is also detected.

2.23. GPIO

2.23.1. GPIO Pin mapping and shared functions

2.23.2. SPDIF/Digital Microphone/GPIO Selection

3 functions are available on the DMIC_1/GPIO0/SPDIFOUT1 pin (pin 46). To determine which func-

tion is enabled, the order of precedence is followed:

1. If the GPIOs are enabled, they override both SPDIF_OUT and Digital Mics

2. If the GPIOs are not enabled through the AFG, then at reset, the pin is pulled low by an internal

pull-down resistor.

3. If the port is enabled as an input, the digital microphones will be used.

4. If the port is enabled as an output, the SPDIF output will be used.

5. In the event that the port is enabled as an input and an output, the port will be an output and the

Digital Mic path will be mute.

2.23.3. Digital Microphone/GPIO Selection

2 functions are available on the DMIC_CLK/GPIO1 (pin 2) and the DMIC_0/GPIO2 (pin 4) pins. To

determine which function is enabled, the order of precedence is followed:

1. If GPIOs are not enabled through the AFG, then at reset, pins 2 and 4 are pulled low by an inter-

nal pull-down resistor.

2. If the GPIO 1 is enabled, the 2 DMIC pins become mute (unless programmed for GPIO or SPDIF

use) and pin 2 becomes GPIO with an internal pull-down.

3. If GPIO2 is enabled through the AFG, pin 4 becomes a GPIO and is pulled low by an internal

pull-down resistor.

4. If the port is enabled as an input, the digital microphones will be used.

5. If the port is not enabled as an input or if the pin is configured as a GPIO, the digital microphone

path will be mute.

2.24. HD Audio HDA015-B support

The codec provides complete support for the HDA015-B specification (now DCN) building on the

support already present in previous products. HDA015-B features supported are:

1. Persistence of many configuration options through bus and function group reset.

2. The ability to support port presence detect in D3 even when the HD Audio bus is in a low power

state (no clock.)

GPIO

#Pin Supply SPDIF

SPDIF

Out GPI/O GPI GPO VrefOut DMIC VOL Pull

Pull

Down

0 46 DVDD YES YES IN 50K

1 2 DVDD YES CLK 50K

2 4 DVDD YES IN 50K

3 48 DVDD YES YES 50K

4 24 AVDD YES YES 50K

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3. Fast resume times from low power states: 1ms D1 to D0, 2ms D2 to D0, 10mS D3 to D0.

4. Notification if persistent register settings have been unexpectedly reset.

5. SPDIF active in D3 (required)

2.25. Digital Core Voltage Regulator

The digital core operates from a 1.8V (10%) supply voltage. Many systems require that the CODEC

use a single 3.3V digital supply, so an integrated regulator is included on die. The regulator uses pin

9, DVDD, as its voltage source. The output of the LDO is connected to pin 1 and the digital core. A

10uF capacitor must be placed on pin 1 for proper load regulation and regulator stability.

The digital core voltage regulator is only dependent on DVDD. DVDDIO may be either 3.3 or 1.5V

and may precede or follow DVDD in sequence. The CODEC digital logic and I/O (unless referenced

to AVDD) will operate in the absence of AVDD. DVDD and AVDD supply sequencing for the applica-

tion of power and the removal of power is neither defined nor guaranteed. It is common for desktop

systems to supply AVDD from the system standby supply and the CODEC will tolerate, indefinitely,

the condition where AVDD is active but DVDD and DVDDIO are inactive.

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2.26. Aux Audio Support

The CODEC supports an auxiliary audio mode where audio routing is supported by default after

power is supplied with the HD Audio bus disabled. In this mode, an I2S input is routed to one of sev-

eral output ports depending on jack presence detection, likewise seceral audio sources (analog, dig-

inal mic, I2S) are routed and converted to an I2S output.

In addition to shutting of the CODEC BTL and headphone amplifiers when the dock output jack is

used, the BTL amplifier will be disabled when the headphone jacks are used, and the headphone

amplifiers will be disabled when not in use.

2.26.1. General conditions in Aux Audio Mode:

HD Audio Link is off (RST# is 0, active, and BitClk is 0, inactive. CODEC does not need to monitor

BitClk to enter/exit this mode but must not depend on BitClk to operate.) (Part will enter Aux Audio

Mode immediately on application of power if Aux Audio Mode is enabled as default.)

HD Audio CODEC function group power state is set to D3cold and Aux Audio Mode is enabled.

(Device enters immediately on transition to D3cold and remains in Aux mode until a double AFG

reset event is received or until the next rising edge of RST#)

• HD Audio CODEC analog and digital supplies are active.

• Port A connects to the system microphone jack.

• Port B connects to the system headphone jack.

• Port C is not used

• Port D connects to the internal speakers.

• Port E is connected to the dock Line Out jack/AUX Audio out (it is an output port)

• Port F is connected to the dock Mic Input jack/AUX Audio In (it is an input port)

• The digital microphone clock is generated by the CODEC. The DMIC data is converted to PCM

and sent to the Aux Audio Module through the Aux Out port.

• The System microphone jack (Port A) is available to the auxiliary audio subsystem. Vref_Out will

be enabled when the system Mic is plugged in.

• EAPD is used to control the power state of the mixer, BTL amplifier, and headphone amplifiers.

The amplifiers are off if EAPD is held low.

• Internal circuitry will delay enabling (change power state, un-mute, etc.) the output amplifiers a

sufficient amount of time after the application of power or EAPD=1 to prevent pops.

• Internal circuitry will orchestrate power down (EAPD = 0) to prevent pops.

• EAPD must be forced low before removing power.

• No special Dock signal present for the CODEC. Only port presence detect for the dock Line Out

(port E) and MinIN (Poer F) are used.

• ECR15b operation does not presents a problem. The CODEC will not enter Aux Audio mode

unless the function group power state is set to D3cold prior to putting the HD Audio interface into

reset (controller D3.)To prevent undesirable behavior (pops, etc.) the bus must not be placed

into reset with the clock stopped unless EAPD is forced low or D3cold has been set. The Enable

bit in the Aux Audio vendor specific verb is provided so firmware or other software can disable

Aux Audio support. The default value of this bit is determined by a bond option and may be

determined by reading the device ID. This bit only returns to its default value when a power on

reset event is generated or when programmed to that value by software.

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2.26.2. Entering Aux Audio Mode

Enter AUX mode under two conditions, refer to figure below:

• When DVDD is powered-up, the value of AUX_enable register is “enabled” (one), and before

link reset is de-asserted (pull high).

• If AUX_enable is “enabled” (one) and the Power state is D3cold then chip will also enter AUX

mode but the Clock_Stop_OK flag is not required (set to 1 if convenient.). (Note that the part will

enter Aux mode immediately upon transition to D3cold. It is possible to return to normal opera-

tion by issuing a double AFG reset if the link is still active.)

Note: At that time, Force Portsense and BTL Amp on when we enter link reset if the AuxAudio bit

is set. If the AuxAudio bit is not set (by bond option or software) then we will not enter Aux Audio

Mode-Portsense and BTL Amp will remain off.

Port F (“dock microphone”) input is routed to Port D (“internal speakers”), Ports B (system head-

phone port), and Port E (“dock Line Out”) directly. The analog mixer is disabled to reduce power con-

sumption.

Figure 11. Switching between Normal and Aux Audio Modes

DVDD

Dig_POR

Link_reset

AUX_enable

(register)

AUX_mode

Operation

mode

Normal mode

Power state D0 D3

D3 with clock D3 clockless

D0 D3 cold

Normal mode AUX_mode

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2.26.3. “Playback Path” Port Behavior (AnaIog I/O)

Port F (“dock microphone”) input is routed to Port D (“internal speakers”), Ports B (system head-

phone port), and Port E (“dock Line Out”) directly. The analog mixer is disabled to reduce power con-

sumption.

2.26.4. When Port E presence detect = 0

• Presence detect for Port E = 0 (nothing plugged in)

• If Port B is in use (port presence detect = 1), Port D, internal speakers, will be inactive (off)

• The power supply (charge pump) for B will be inactive if B is not in use.

• If Port B is not in use (port presence detect = 0), Port D, internal speakers, will be active and port

B will be inactive.

• EAPD must not be forced low due to the dock being absent or high when a dock is present.

EAPD is used to indicate if AUX Audio Mode is in use.

2.26.5. When Port E presence detect = 1

• Presence detect for Port E = 1 (something plugged in)

• Port D is disabled

• If Port B is in use (port presence detect = 1), that port will be enabled and output the audio enter-

ing Port F

• The power supply for port B will be active if port B is in use.

• If Port B is not in use (port presence detect = 0), port B will be inactive and the audio on Aux_In

will be mixed with the audio from the Secondary Audio input and routed to Port E, the dock

headphone jack.

• EAPD must not be forced low due to the dock being absent or high when a dock is present.

EAPD is used to indicate if AUX Audio Mode is in use.

EAPD

(pin)

Aux

Support

Enable1

1.default value for Aux Audio Enable is determined by bond option.

Port E

detect

Port B

detect

Port A, C, F,

DMIC

detect

Port D

behavior

Port B

behavior

Port E

behavior

0 NA NA NA NA disabled disabled disabled (mute)

1 0 NA NA NA Widget controlled Widget controlled Widget controlled

11 00 NA enabled

(F to D) disabled disabled (mute)

1 1 0 1 NA disabled enabled

(F to B) disabled (mute)

1 1 1 0 NA disabled disabled enabled

Aux+Secondary

1 1 1 1 NA disabled enabled

(F to B) disabled (mute)

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2.26.6. “Record Path” Port Behavior (Analog I/O)

Digital Microphone input DMIC0 is used as an internal microphone port in normal mode. The Digital

Microphone clock pin is enabled in Aux Audio Mode and the digital microphone clock is provided by

an internal oscillator.

If Port F and Port A presence detect = 0, this indicates that nothing is plugged into the dock or sys-

tem; the digital microphone input is converted to analog and sent to the Aux Audio Module through

Port E. If Port A presence detect = 1, this indicates that an external microphone is plugged into the

system jack and port A is sent to the Auxiliary Audio Module through Port E. If Port F presence

detect = 1 (and Port A presence detect = 0), this indicates that an external microphone is plugged

into the dock. External circuitry routes the dock microphone to the Auxiliary Audio Module.

2.26.7. SYSTEM DIAGRAMS (Analog I/O)

Figure 12. Aux Audio Playback When Nothing Plugged In (or System is not Docked)

EAPD

(pin)

Aux

Support

Enable1

1.default value for Aux Audio Enable is determined by bond option.

D MIc0

detect

Port A

detect

Port F

detect

Ports B, C, E

detect Aux_Out behavior

0 X X X X NA disabled

1 0 X X X NA Widget controlled

1 1 000 NA Mute

1 1 100 NA DMIC converted to analog and routed to module

through port E. DMIC Clock provided by CODEC

11X01 NA Dock Mic routed to module (not through CODEC)

CODEC DMIC interface and Port A disabled

I2S

Routing

SPKR

MIC

D-MIC

HD Audio Interface

Dock

MIC

Beep

Filter

DAC

Playback Speaker

Aux Audio

Module

I2S

CODEC

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Figure 13. Aux Audio Playback When System Headphones are Plugged In

Figure 14. Aux Audio Playback when the System is Docked and Headphones are Plugged In

Figure 15. Aux Audio Record when Nothing is Plugged In (or The System is not Docked)

SPKR

MIC

D-MIC

HD Audio Interface

Beep

Filter

DAC

Playback Headphone

I2S

Routing

Dock

MIC

Aux Audio

Module

I2S

CODEC

SPKR

MIC

D-MIC

HD Audio Interface

Beep

Filter

DAC

Playback Dock Headphone

I2S

Routing

Dock

MIC

Aux Audio

Module

I2S

CODEC

SPKR

MIC

D-MIC

HD Audio Interface

Beep

Filter

DAC

Record Digital Mic

I2S

Routing

Dock

MIC

Aux Audio

Module

I2S

CODEC

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Figure 16. Aux Audio Record when the System is Docked with the System Microphone Plugged In

Figure 17. Aux Audio Record when the System is Docked with the Dock Microphone Plugged In

2.26.8. EAPD

Since the Aux Audio mode overrides the default behavior but not the actual port settings when in

reset, the logical state of the EAPD pin must be overridden as well. When Aux Audio mode is

enabled and the part is in reset as described above, the logical state of EAPD will be 1 (External

Amplifier Powered Up) unless held low by an external circuit. This ensures that audio pass-thru and

analog PC_Beep will be supported.

2.26.9. Analog PC_Beep

Analog PC_Beep is supported in Aux Audio mode. By default, analog PC_Beep is disabled but may

be enabled due to Beep pass-thru support in reset (see the PC_Beep section). If the CODEC is pro-

grammed to enable analog PC_Beep and Aux Audio mode is enabled, the next time reset is

asserted, the analog PC_Beep pin will be mixed at each of the active outputs.

SPKR

MIC

D-MIC

HD Audio Interface

Beep

Filter

DAC

Record Analog Mic

I2S

Routing

Dock

MIC

Aux Audio

Module

I2S

CODEC

SPKR

MIC

D-MIC

HD Audio Interface

Beep

Filter

DAC

Record Dock Mic

I2S

Routing

Dock

MIC

Aux Audio

Module

I2S

CODEC

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2.26.10. Class-D BTL Issues

While in Aux Audio mode the HD Audio bus clock (BitClk) is not available. The Class-D controller

requires a very high speed clock to operate and an internal clock must be provided. In Aux Audio

mode, the actual frequency used by the Class-D controller and its associated ADC will not be exact

since an external reference will not be available.The performance characteristics in Aux Audio Mode

will be degraded compared to the normal operating mode characteristics specified elsewhere in this

document.

2.26.11. Firmware/Software Requirements:

The reconfiguration outlined in this chapter is autonomous (without the help of firmware or OS

driver.)

This autonomous mode does not interfere with normal operation.

If it is desirable to stop the HD Audio bus while the CODEC is in D3 under OS control per DCN

HDA015-B, no action is required. The CODEC will not enter Aux Audio Mode unless placed in

D3cold.

2.27. Microphone Mute Input

Available on silicon revision WB and beyond.

The 92HD91 supports a microphone mute input. An external switch or other circuit may directly

mute the CODEC without relying on software control. This is a most helpful feature for allowing the

end user to conveniently enforce privacy since it bypasses the record gain/mute functions typically

controlled by software. While recording is muted, any active stream will receive digital silence.

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3. CHARACTERISTICS

3.1. Electrical Specifications

3.1.1. Absolute Maximum Ratings

Stresses above the ratings listed below can cause permanent damage to the 92HD91. These rat-

ings, which are standard values are stress ratings only. Functional operation of the device at these or

any other conditions above those indicated in the operational sections of the specifications is not

implied. Exposure to absolute maximum rating conditions for extended periods can affect product

reliability. Electrical parameters are guaranteed only over the recommended operating temperature

range.

3.1.2. Recommended Operating Conditions

Item Pin Maximum Rating

Analog maximum supply voltage AVdd 6 Volts

Digital maximum supply voltage

DVdd 5.5 Volts

PVdd 6 Volts

VREFOUT output current 5 mA

Voltage on any pin relative to ground Vss - 0.3 V to Vdd + 0.3 V

Operating temperature 0 oC to +70 oC

-40 oC to +85oC (INDUSTRIAL TEMP, see part number list)

Storage temperature -55 oC to +125 oC

Soldering temperature Soldering temperature information for all available in the package

section of this datasheet.

Table 18. Electrical Specification: Maximum Ratings

Parameter Min. Typ. Max. Units

Power Supplies DVDD_Core 1.6 1.8 1.98 V

DVDD_IO (3.3V signaling) 3.135 3.3 3.465 V

DVDD_IO (1.5V signaling) 1.418 1.5 1.583 V

Power Supply Voltage Digital - 3.3 V 3.135 3.3 3.465 V

Analog - 5 V 4.75 5 5.25 V

Ambient Operating Temperature 0 +70 C

Case Temperature Tcase +90 C

Tcase Industrial +110 C

Table 19. Recommended Operating Conditions

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3.2. 92HD91 Analog Performance Characteristics

(Tambient = 25 ºC, AVdd = 4.75V (4.5-5.25V) or 3.3V +/-5%, DVdd = 3.3V ± 5% or 1.8V± 10%, AVss=DVss=0V; 20Hz to

20KHz swept sinusoidal input; Sample Frequency = 48 kHz; 0dB FS = 1Vrms for AVdd = 4.75V and 0.71Vrms for AVdd

= 3.3V, 10KΩ//50pF load, Testbench Characterization BW: 20 Hz – 20 kHz, 0 dB settings on all gain stages)

ESD: The 92HD91 is an ESD (electrostatic discharge) sensitive device. The human body and test equipment can

accumulate and discharge electrostatic charges up to 4000 Volts without detection. Even though the 92HD91 implements

internal ESD protection circuitry, proper ESD precautions should be followed to avoid damaging the functionality or

performance.

Parameter Conditions Min Typ Max Unit

Digital to Analog Converters

Resolution 24 Bits

Dynamic Range1: PCM to All Analog

Outputs -60dB FS signal level, Analog Mixer disabled 98 dB

SNR2 - DAC to All Line-Out Ports Analog Mixer Disabled, PCM data 98 dB

THD+N3 - DAC to All Line-Out Ports Analog Mixer Disabled,-3dB FS Signal, PCM

data 89 dBr

SNR2 - DAC to All Headphone Ports Analog Mixer Disabled, 10K load, PCM data 98 dB

THD+N3 - DAC to All Headphone Ports Analog Mixer Disabled,-3dB FS Signal, 10K

load, PCM data 87 dBr

SNR2 - DAC to All Headphone Ports Analog Mixer Disabled, 32 load, PCM data 98 dB

THD+N3 - DAC to All Headphone Ports Analog Mixer Disabled, -3dB FS Signal, 32

load, PCM data 73 dBr

Any Analog Input (ADC) to DAC Crosstalk 10KHz Signal Frequency. 0dBV signal applied

to ADC, DACs idle, ports enabled as output. -65 - - dB

Any Analog Input (ADC) to DAC Crosstalk 1KHz Signal Frequency. see above -65 - - dB

DAC L/R crosstalk DAC to LO or HP 20-15KHz into 10K load 70 73 dB

DAC L/R crosstalk DAC to HP 20-15KHz into 32 load 65 68 dB

Gain Error Analog Mixer Disabled 0.5 dB

Interchannel Gain Mismatch Analog Mixer Disabled 0.5 dB

D/A Digital Filter Pass Band420 -21,000 Hz

D/A Digital Filter Pass Band Ripple50.125 +/- dB

D/A Digital Filter Transition Band 21,000 -31,000 Hz

D/A Digital Filter Stop Band 31,000 - - Hz

D/A Digital Filter Stop Band Rejection6-100 - - dB

D/A Out-of-Band Rejection7-55 - - dB

Group Delay (48KHz sample rate) - - 1 ms

Attenuation, Gain Step Size DIGITAL -0.75 -dB

Table 20. 92HD91 Analog Performance Characteristics

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DAC Offset Voltage -10 20 mV

Deviation from Linear Phase - 1 10 deg.

Analog Outputs

Full Scale All Mono/Line-Outs DAC PCM Data 1.00 - - Vrms

Full Scale All Mono/Line-Outs DAC PCM Data 2.83 - - Vp-p

All Headphone Capable Outputs 32load 40 60 -mW

(peak)

Amplifier output impedance Mono/Line Outputs

Headphone Outputs

150

0.1 Ohms

External load Capacitance Mono/Line Outputs

Headphone Outputs 220 pF

Analog inputs

Full Scale Input Voltage 0dB Boost @4.75V

(input voltage required for 0dB FS output) 1.05 - - Vrms

All Analog Inputs with boost 10dB Boost 0.320 - - Vrms

All Analog Inputs with boost 20dB Boost 0.105 - - Vrms

All Analog Inputs with boost 30dB Boost 0.032 - - Vrms

Boost Gain Accuracy -2 2dB

Input Impedance -50 - K

Input Capacitance -15 -pF

Analog Mixer

Dynamic Range: PCM to All Analog

Outputs

-60dB FS signal level Analog Beep enabled all

other mixer inputs mute 95 dB

SNR2 - All Line-Inputs to all Line Outputs All inputs unmuted, single line input driven by

ATE. 90 dB

THD+N3 - All Line-Inputs to all Line

Outputs

0dB Full Scale Input on one input, all others

silent. 83 dBr

SNR2 - DAC to All Ports Analog Mixer Enabled, PCM data, all others

inputs mute. 98 dB

THD+N3 - DAC to All Ports Analog Mixer Enabled, 0dB FS Signal, PCM

data, all others inputs unmute/silent 85 dBr

Attenuation, Gain Step Size ANALOG -1.5 -dB

Analog to Digital Converter

Resolution 24 Bits

Full Scale Input Voltage 0dB Boost (input voltage required to generate

0dBFS per AES 17) 1.05

Dynamic Range1, All Analog Inputs to A/D High Pass Filer Enabled, -60dB FS, No boost 94 dB

Full Scale Input Voltage 20dB Boost (input voltage required to

generate 0dBFS per AES 17) 0.105

Dynamic Range1, All Analog Inputs to A/D 20dB Boost

High Pass Filter Enabled, -60dB FS 90 dB

THD+N3 All Analog Inputs to A/D High Pass Filter enabled, -3dB FS signal level 83 dB

Parameter Conditions Min Typ Max Unit

Table 20. 92HD91 Analog Performance Characteristics

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THD+N3 All Analog Inputs to A/D 20dB Boost, High Pass Filter enabled, -3dB

FS signal level 80 dB

Analog Frequency Response810 -30,000 Hz

A/D Digital Filter Pass Band420 -21,000 Hz

A/D Digital Filter Pass Band Ripple50.1 +/- dB

A/D Digital Filter Transition Band 21,000 -31,000 Hz

A/D Digital Filter Stop Band 31,000 - - Hz

A/D Digital Filter Stop Band Rejection6-100 - - dB

Group Delay 48 KHz sample rate - - 1 ms

Any unselected analog Input to ADC

Crosstalk 10KHz Signal Frequency -65 - - dB

Any unselected analog Input to ADC

Crosstalk 1KHz Signal Frequency -65 - - dB

ADC L/R crosstalk Any selected input to ADC 20-15Khz -65 dB

DAC to ADC crosstalk DAC output 0dBFS. All outputs loaded. Input

to ADC open. 20-15Khz -65 dB

Spurious Tone Rejection9--100 -dB

Attenuation, Gain Step Size

(analog) -1.5 -dB

Interchannel Gain Mismatch ADC - - 0.5 dB

Power Supply

Power Supply Rejection Ratio 10kHz --60 -dB

Power Supply Rejection Ratio 1kHz --70 -dB

D0 Didd10 3.3V 25 mA

D0 Aidd10 5V 66 mA

D0 Didd11 3.3V 17 mA

D0 Aidd11 5V 54 mA

D1 Didd12 3.3V 10 mA

D1 Aidd12 5V 30 mA

D2 Didd 3.3V 8mA

D2 Aidd 5V 7mA

D3 (Beep enabled) Didd13 3.3V 2mA

D3 (Beep enabled) Aidd13 5V 6mA

D3 Didd13 3.3V 2mA

D3 Aidd13 5V 4mA

D3cold Didd13 3.3V 1.3 mA

D3cold Aidd13 5V 3.5 mA

Vendor D4 Didd 3.3V 1.1 mA

Vendor D4 Aidd 5V 3.5 mA

Parameter Conditions Min Typ Max Unit

Table 20. 92HD91 Analog Performance Characteristics

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Vendor D5 Didd 3.3V 1mA

Vendor D5 Aidd 5V 0.3 mA

Voltage Reference Outputs

VREFOut14 -0.5 X

AVdd - V

VREFOut Drive 1.6 mA

VREFILT (VAG) 0.45 X

AVdd V

Phased Locked Loop

PLL lock time 96 200 usec

PLL (or HD Audio Bit CLK) 24MHz clock

jitter 150 500 psec

ESD / Latchup

IEC1000-4-2 1Level

JESD22-A114-B 2Class

JESD22-C101 4Class

1.Dynamic Range is the ratio of the full scale signal to the noise output with a -60dBFS signal as defined in AES17 as SNR in

the presence of signal and outlined in AES6id, measured “A weighted” over 20 Hz to 20 kHz bandwidth

2.Ratio of Full Scale signal to idle channel noise output is measured “A weighted” over a 20 Hz to a 20 kHz bandwidth.

(AES17-1991 Idle Channel Noise or EIAJ CP-307 Signal-to-noise Ratio).

3.THD+N ratio as defined in AES17 and outlined in AES6id,non-weighted, over 20 Hz to 20 kHz bandwidth.Results at the jack

are dependent on external components and will likely be 1 - 2dB worse.

4.Peak-to-Peak Ripple over Passband meets ± 0.125dB limits, 48 kHz or 44.1 kHz Sample Frequency. 1dB limit.

5.Peak-to-Peak Ripple over Passband meets ± 0.125dB limits, 48 kHz or 44.1 kHz Sample Frequency. 1dB limit.

6.Stop Band rejection determines filter requirements. Out-of-Band rejection determines audible noise.

7.The integrated Out-of-Band noise generated by the DAC process, during normal PCM audio playback, over a bandwidth 28.8

to 100 kHz, with respect to a 1 Vrms DAC output.

8.± 1dB limits for Line Output & 0 dB gain, at -20dBV

9.Spurious tone rejection is tested with ADC dither enabled and compared to ADC performance without dither.

10.All functions/converters active, pin complexes enabled, two FDX streams, line (10Kohm) loads. Add 24mA analog current per

stereo 32 ohm headphone.

11.One stereo DAC and corresponding pin widgets enabled (playback mode)

12.Mixer enabled

13.Idle measurement D3 set for minimum clicks/pops (biases and min. amps. on)

14.Can be set to 0.5 or 0.8 AVdd.

Parameter Conditions Min Typ Max Unit

Table 20. 92HD91 Analog Performance Characteristics

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3.3. Class-D BTL Amplifier Performance

Table 21. Class-D BTL Amplifier Performance

Parameter Min Typ Max Unit

Output Power (BTL 4 ohm, 5V, <1% THD+N) 2 W

Output Power (BTL 4 ohm, 5V, <10% THD+N) 3 W

Amplifier Efficiency (4, 5V, 2W) 86 %

THD+N (BTL 4, 5V, FS) 1%

THD+N (BTL 4, 5V, -3dBFS) 0.3 %

Frequency Response 20 - 20K Hz

PWM frequency 352.8 KHz

Output voltage noise (4, 5V) 65 uV

Idle current 3.6 mA

Shutdown current .2 mA

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3.4. Capless Headphone Supply Characteristics

3.5. AC Timing Specs

3.5.1. HD Audio Bus Timing

Figure 18. HD Audio Bus Timing

Parameter Min Typ Max Unit

LDO idle current 1 2 mA

Capless Headphone Amp idle current 2 3 mA

Charge Pump idle current 4 6 mA

Charge Pump shutdown time 1 mS

Charge Pump start-up time 10 mS

Frequency 384 KHz

C1/C2 cap value 2.2 uF

Table 22. Capless Headphone Supply

Parameter Definition Symbol Min Typ Max Units

BCLK Frequency Average BCLK frequency 23.9976 24.0 24.0024 Mhz

BCLK Period Period of BCLK including jitter Tcyc 41.163 41.67 42.171 ns

BCLK High Phase High phase of BCLK T_high 17.5 24.16 ns

BCLK Low Phase Low phase of BCLK T_low 17.5 24.16 ns

BCLK jitter BCLK jitter 150 500 ps

SDI delay Time after rising edge of BCLK that

SDI becomes valid T_tco 3 11 ns

SDO setup Setup for SDO at both rising and

falling edges of BCLK T_su 5 ns

SDO hold Hold for SDO at both rising and

falling edges of BCLK T_h 5 ns

Table 23. HD Audio Bus Timing

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3.5.2. SPDIF Timing

3.5.3. Digital Microphone Timing

3.5.4. GPIO Characteristics

Parameter Definition Symbol Min Typ Max Units

SPDIF_OUT Frequency highest rate of encoded signal

64 times the sample rate 2.8224 3.072 12.288 MHz

SPDIF_OUT unit interval 1/(128 times the sample rate) UI 177.15 162.76 40.69 ns

SPDIF_OUT jitter SPDIF_OUT jitter 4.43 ns

SPDIF_OUT rise time T_rise 15 ns

SPDIF_OUT fall time T_fall 15 ns

Table 24. SPDIF Timing

Parameter Definition Symbol Min Typ Max Units

DMIC_CLK Frequency Average DMIC_CLK frequency 1.176 2.352 4.704 MHz

DMIC_CLK Period Period of DMIC_CLK Tdmic_cyc 850.34 425.17 212.59 ns

DMIC_CLK jitter DMIC_CLK jitter 5000 ps

DMIC Data setup Setup for the microphone data at both rising

and falling edges of DMIC_CLK Tdmic_su 5 ns

DMIC Data hold Hold for the microphone data at both rising and

falling edges of DMIC_CLK Tdmic_h 5 ns

Table 25. Digital Mic timing

Parameter Definition Symbol Min Typ Max Units

Input High Voltage1

1.High peak currents during dynamic switching of the Class-D PWM Outputs can result in Ground Rail Bounce. The amount of

Ground Bounce should be kept below 0.35 x VDD for all Inputs, including internal logic which is tied to DVDD_CORE.

input level at or above which a 1 is reliably

recorded Vih 0.6 x

VDD V

Input Low Voltage1input level at or below which a 0 is reliably

recorded. VDD may be DVDD or AVDD Vil 0.35 x

VDD V

Output High Voltage iout = 4mA

VDD may be DVDD or AVDD depending on pin Voh 0.9 x

VDD V

Output Low Voltage iout = -4mA

VDD may be DVDD or AVDD depending on pin Vol 0.1 x

VDD V

Input rise/fall time transition time between 10% and 90% of supply T_rise/T_fall 10 ns

Input/Tristate High

Leakage Current

Vin = VDD

VDD may be DVDD or AVDD depending on pin

(does not include pull-up or pull-down resistor if

present)

0.5 uA

Input/Tristate Low Leakage

Current

Vin = 0

VDD may be DVDD or AVDD depending on pin

(does not include pull-up or pull-down resistor if

present)

-50 uA

Table 26. GPIO Characteristics

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4. FUNCTIONAL BLOCK DIAGRAM

Figure 19. Functional Block Diagram

Stream &

Channel

Select

DAC 0

Stream &

Channel

Select

Stream &

Channel

Select

HD Audio LINK LOGIC

PCM to

SPDIF OUT

SPDIF OUT0

vol

DAC 1

Digital

Mute

Digital

Mute

MUX

ADC0

Pin 48

Pin 4

DMIC_0

MUX

ADC1

MUX

DMIC_1

(shared)

DMIC_1

Pin 46

Stream &

Channel

Select

volmute

vol

mute

volmute

Digital Microphone

volume and mute is

done after the ADC but

shown here and in

widget list as same as

analog path.

Stream &

Channel

Select

PCM to

SPDIF OUT

ADC0

MUX

ADC1

DAC0

DAC1

Mixer

Boost

+0/+10/+20/+30 dB

Boost

+0/+10/+20/+30 dB

DMIC

Pin 46

Pin Complex

Pins 19/20

PORT C

Mic Bias

PORT E

ADC0

Stream &

Channel

Select

vol

Gain

mute

SPDIF OUT1 (shared)

ADC1 vol

Gain

mute

-34.5 to +12 dB

In 1.5 dB steps

Boost

+0/+10/+20/+30 dB

Port C

PORT F

Boost

+0/+10/+20/+30 dB

Port F

Mono

Pin Complex

Pin 25

Pin Complex

Pins 17/18

Pin Complex

Pins 15/16

Port A

Port C

Port E

vol

Pin Complex

Pins 28/29

PORT A

Pin Complex

Pins 31/32

PORT B

Cap-less

MUX



Analog BeepDigital PC Beep

MUX



Analog BeepDigital PC Beep

MUX



Analog BeepDigital PC Beep

volmute DAC0

DAC1

Vol

-46.5 to 0 dB

In 1.5 dB steps

mute

MixerOutVol

MUX



Analog BeepDigital PC Beep

Boost

+0/+10/+20/+30 dB

Port A

DAC1

MixerOutVol

DAC0

MUX

DAC1

MixerOutVol

DAC0

MUX

DAC1

MixerOutVol

DAC0

MUX

DAC1

MixerOutVol

DAC0

MUX

Pin Complex

Pins 40/41/43/44

PORT D

BTL

Class-D

Digital

PWM

controller

MUX



Analog Beep_DigDigital PC Beep

DAC1_Dig

DAC0_Dig

MUX

MixerOutVol_Dig Highpass

Filter

5-band

Clocking

Bandpass

Filter

volmute Analog PC_BEEP

0,-6,-12,-18dB

volmute

0,-6,-12,-18dB

Detect/Convert

Analog Beep

Analog Beep_Dig

Beep_Active

DAC0_Dig

DAC1_Dig

ADC

MixerOutVol_Dig

DAC M



Stereo to

Mono mix

MUX



Analog Beep_DigDigital PC Beep

DAC1_Dig

DAC0_Dig

MUX

MixerOutVol_Dig

-16 to +30 dB

In 1 dB steps

-16 to +30 dB

In 1 dB steps

MUX



Analog BeepDigital PC Beep

DAC1

MixerOutVol

DAC0

MUX

Mic Bias

Mixer

Port F

DMIC0

DMIC1

Port C

Port A

MUX

Port E

Mixer

Port F

DMIC0

DMIC1

Port C

Port A

MUX

Port E

volmute Port F

Boost

+0/+10/+20/+30 dB

Port E

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5. WIDGET DIAGRAM

Figure 20. Widget Diagram

Vendor Specific Test

HDA

Link

SPDIF

OUT1

NID = 1Eh

NID = 20h

Dig1Pin

ADC0 MUX

ADC1 MUX

DAC0

Digital

ADC0

NID = 15h

DMIC0

NID = 11h

Port B

Port A

NID = 0Ah

Analog*

DAC0

NID = 13h

VOLUME

MUTE

Mixer

NID = 17h

ADC0

MUX

VOLUME

Mute

DMIC0

DMIC1

NID = 18h

VOL

DMIC1 VOL

(VSW)

NID = 12h

Digital

VOL

ADC1

NID = 16h

DAC1

MixerOutVol

NID = 0Bh

Port C

BIAS

NID = 0Ch

Port D

NID = 0Dh

Port E

NID = 0Eh

Port F

NID = 0Fh

DAC1

NID = 14h

VOLUME

MUTE

10/20/30

-16 to 30dB

1dB step

-95.25 to 0dB

0.75dB step

-95.25 to 0dB

0.75dB step

SPDIF

OUT0

NID = 1Dh

NID = 1Fh

Dig0Pin

ADC1 MUX

Digital

ADC0 MUX PC_BEEP

NID = 21h

Digital

ADC1 MUX

ADC0 MUX

BTL

PC_BEEP (Pin 12)

Mute Volume

NID = 1Bh



-34.5 to +12dB

in 1.5dB steps

DAC0

DAC1

IN VOL

10/20/30

IN VOL

10/20/30

Mixer

Port A

Port C

ADC1

MUX

VOLUME

Mute

-16 to 30dB

1dB step

Port F

Port C

0,-6,-12,-18dB

VSV

Mono

NID = 10h

DAC0

DAC1

MixerOutVol

DAC0

DAC1

MixerOutVol

DAC0

DAC1

MixerOutVol

DAC0

DAC1

MixerOutVol

DAC0

DAC1

MixerOutVol

DMIC0

DMIC1

Vendor Specific Test

D – Nodes are Digital Capable

DMIC0

Mixer

DMIC1

Port C

Port F

Port A

VSW

NID = 22h

Mute Volume

Port C

Mute Volume

DAC0

Port A

DAC1

To all ports enabled

as an output

To all

ports

enabled

as an

output

NID = 1Ch

MixerOutVol

Volume

-46.5 to 0dB

in 1.5dB steps

Mixer

MixerOutVol Mute

BIAS

IN VOL

10/20/30

NID = 1AhNID = 19h

Mono Mix

Mono Mux

DAC0

DAC1

MixerOutVol

Port E

Port F

IN VOL

10/20/30

Port E

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6. PORT AND PIN CONFIGURATIONS

6.1. Port Configurations

Figure 21. Port Configurations

Internal

SPDIF_OUT

*EAPD

HDMI/Display Port

External

BHP

Side

AMIC/HP FMIC

Dock

Mobile

Digital Mic

Array

HDMI/Display Port

ELO

Rear

CMIC,LI

SPDIF_OUT

Front

AMIC

Desktop 1

HDMI/Display Port

Rear

SPDIF_OUT

Front

CMIC

Desktop 2

EMIC,LI,HP

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6.2. Pin Configuration Default Register Settings

The following table shows the Pin Widget Configuration Default settings. Desktop implementation with 2 jacks in front

and 3 jacks in rear. The internal speaker is redirected from the front (green) headphone jack. An internal microphone is

present.

Pin Name Port Location Device Connection Color Misc Assoc. Seq

PortAPin Connect to

Jack

00b

Mainboard

Front

Mic In

1/8 inch Jack

Pink

Jack Detect

Override=0

2h 0h

PortBPin Connect to

Jack

00b

Mainboard

Front

HP Out

1/8 inch Jack

Green

Jack Detect

Override=0

1h Fh

PortCPin Connect to

Jack

00b

Mainboard

Rear 1h

Mic In

1/8 inch Jack

Pink

Jack Detect

Override=0

2h 1h

PortDPin Internal

10b

010000b

Speaker

Other Analog

Unknown

Jack Detect

Override=1

1h 0h

PortEPin Connect to

Jack

00b

Mainboard

Rear 1h

Line Out

1/8 inch Jack

Green

Jack Detect

Override=0

5h 0h

PortFPin Connect to

Jack

00b

Mainboard

Rear

Line In

1/8 inch Jack

Blue

Jack Detect

Override=0

2h Eh

MonoOutPin No Connect

01b

000000b

Other

Unknown

Jack Detect

Override=0

Fh 0h

DigOutPin0 Connect to

Jack

00b

Mainboard

Rear

000001b

SPDIF Out

optical

Black

Jack Detect

Override=1

6h 0h

DigOutPin1 Connect to

Jack

10b

Internal

011000b

Digital

Other Out

Other Digital

Unknown

Jack Detect

Override=1

7h 0h

DigMic0Pin Internal

10b

Internal

010000b

Mic In

ATAPI

Unknown

Jack Detect

Override=1

3h 0h

Table 27. Pin Configuration Default Settings

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7. WIDGET INFORMATION

There are two types of responses: Solicited and Unsolicited. Solicited responses are provided as a

direct response to an issued command and will be provided in the frame immediately following the

command. Unsolicited responses are provided by the CODEC independent of any command. Unso-

licited responses are the result of CODEC events such as a jack insertion detection. The formats for

Solicited Responses and Unsolicited Responses are shown in the tables below. The “Tag” field in

bits [31:28] of the Unsolicited Response identify the event.

Bits [39:32] Bits [31:28] BITS [27:20] BITS[19:16] BITS [15:0]

Reserved CODEC Address NID Verb ID (4-bit) Payload Data (16-bit)

Table 28. Command Format for Verb with 4-bit Identifier

Bits [39:32] Bits [31:28] BITS [27:20] BITS[19:8] BITS [7:0]

Reserved CODEC Address NID Verb ID (12-bit) Payload Data (8-bit)

Table 29. Command Format for Verb with 12-bit Identifier

Bit [35] Bit [34] BITS [33:32] BITS[31:0]

Valid (Valid = 1) UnSol = 0 Reserved Response

Table 30. Solicited Response Format

Bit [35] Bit [34] BITS [33:32] BITS[31:28] BITS [27:0]

Valid (Valid = 1) UnSol = 1 Reserved Tag Response

Table 31. Unsolicited Response Format

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7.1. Widget List

Table 32. Widget List

ID Widget Name Description

00h Root Root Node

01h AFG Audio Function Group

0Ah Port A Port A Pin Widget (Headphone, Line IN/OUT, MIC)

0Bh Port B Port B Pin Widget (Cap-less Headphone)

0Ch Port C Port C Pin Widget (Line IN/OUT, MIC)

0Dh Port D Port D Pin Widget (Class-D BTL output)

0Eh Port E Port E Pin Widget (Line IN/OUT, MIC)

0Fh Port F Port F Pin Widget (Line IN/OUT, MIC)

10h MonoOut MonoOut Pin Widget (Output Only)

11h DigMic0 Digital Microphone 0 Pin Widget

12h DigMic1 Vol Vendor Specific Widget - D-Mic1 volume (D pin to A mux connection)

13h DAC0 Stereo Output Converter to DAC

14h DAC1 Stereo Output Converter to DAC

15h ADC0 Stereo Input Converter to ADC

16h ADC1 Stereo Input Converter to ADC

17h ADC0Mux ADC0 Mux with volume and mute

18h ADC1Mux ADC1 Mux with volume and mute

19h Mono_Mux Mono output source select

1Ah Mono_Mix Stereo to mono conversion

1Bh Mixer Input Mixer (Input Ports, DACs, Analog PC_Beep)

1Ch MixerOutVol Volume control for analog mixer

1Dh SPDIFOut0 Stereo Output for SPDIF_Out

1Eh SPDIFOut1 Second Stereo Output for SPDIF_Out

1Fh Dig0Pin First Digital Output Pin (pin48)

20h Dig1Pin Second Digital Output Pin / DMIC Input Pin (pin 46)

21h PCBeep Digital PC Beep

22h VSW Vendor Defined Widget

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7.2. Reset Key

Abbreviation Description

POR Power On Reset.

SAFG Single AFG Reset - One single write to the Reset Verb in the AFG Node.

DAFG Double AFG Reset - Two consecutive Single AFG Resets with only idle frames (if

any) and no Link Resets between.

S&DAFG Single And Double AFG Reset - Either one will cause reset.

LR Link Reset - Level sensitive reset anytime the HDA Reset is set low.

ELR Exiting Link Reset - Edge sensitive reset any time the HDA Reset transitions from

low to high.

ULR Unexpected Link Reset - Level sensitive reset anytime the HDA Reset is set low

when the ClkStopOK indicator is currently set to 0.

PS Power State Change - Reset anytime the Actual Power State changes for the Widget

in question.

7.3. Root (NID = 00h): VendorID

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set

Get F0000h

Field Name Bits R/W Default Reset

Vendor 31:16 R111Dh N/A

Vendor ID.

DeviceFix 15:8 Rsee below N/A

Device ID.

DeviceProg 7:0 Rsee below N/A

Device ID.

Device 92HD91

Device ID 76E0h

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7.3.1. Root (NID = 00h): RevID

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set

Get F0002h

Field Name Bits R/W Default Reset

Rsvd 31:24 R00h N/A (Hard-coded)

Reserved.

Major 23:20 R1h N/A (Hard-coded)

Major rev number of compliant HD Audio spec.

Minor 19:16 R0h N/A (Hard-coded)

Minor rev number of compliant HD Audio spec.

RevisionFix 15:12 R xh N/A (Hard-coded)

Vendor's rev number for this device.

RevisionProg 11:8 R xh N/A (Hard-coded)

Vendor's rev number for this device.

SteppingFix 7:4 R xh N/A (Hard-coded)

Vendor stepping number within the Vendor RevID.

SteppingProg 3:0 R xh N/A (Hard-coded)

Vendor stepping number within the Vendor RevID.

7.3.2. Root (NID = 00h): NodeInfo

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set

Get F0004h

Field Name Bits R/W Default Reset

Rsvd2 31:24 R00h N/A (Hard-coded)

Reserved.

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StartNID 23:16 R01h N/A (Hard-coded)

Starting node number (NID) of first function group

Rsvd1 15:8 R00h N/A (Hard-coded)

Reserved.

TotalNodes 7:0 R01h N/A (Hard-coded)

Total number of nodes

7.4. AFG (NID = 01h): NodeInfo

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set

Get F0004h

Field Name Bits R/W Default Reset

Rsvd2 31:24 R00h N/A (Hard-coded)

Reserved.

StartNID 23:16 R0Ah N/A (Hard-coded)

Starting node number for function group subordinate nodes.

Rsvd1 15:8 R00h N/A (Hard-coded)

Reserved.

TotalNodes 7:0 R19h N/A (Hard-coded)

Total number of nodes.

7.4.1. AFG (NID = 01h): FGType

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set

Get F0005h

Field Name Bits R/W Default Reset

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Field Name Bits R/W Default Reset

Rsvd 31:9 R000000h N/A (Hard-coded)

Reserved.

UnSol 8 R 1h N/A (Hard-coded)

Unsolicited response supported: 1 = yes, 0 = no.

NodeType 7:0 R1h N/A (Hard-coded)

Function group type:

00h = Reserved

01h = Audio Function Group

02h = Vendor Defined Modem Function Group

03h-7Fh = Reserved

80h-FFh = Vendor Defined Function Group

7.4.2. AFG (NID = 01h): AFGCap

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set

Get F0008h

Field Name Bits R/W Default Reset

Rsvd3 31:17 R00h N/A (Hard-coded)

Reserved.

BeepGen 16 R1h N/A (Hard-coded)

Beep generator present: 1 = yes, 0 = no.

Rsvd2 15:12 R0h N/A (Hard-coded)

Reserved.

InputDelay 11:8 RDh N/A (Hard-coded)

Typical latency in frames. Number of samples between when the sample is re-

ceived as an analog signal at the pin and when the digital representation is

transmitted on the HD Audio link.

Rsvd1 7:4 R0h N/A (Hard-coded)

Reserved.

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OutputDelay 3:0 RDh N/A (Hard-coded)

Typical latency in frames. Number of samples between when the signal is re-

ceived from the HD Audio link and when it appears as an analog signal at the

pin.

7.4.3. AFG (NID = 01h): PCMCap

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set

Get F000Ah

Field Name Bits R/W Default Reset

Rsvd2 31:21 R000h N/A (Hard-coded)

Reserved.

B32 20 R0h N/A (Hard-coded)

32 bit audio format support: 1 = yes, 0 = no.

B24 19 R1h N/A (Hard-coded)

24 bit audio format support: 1 = yes, 0 = no.

B20 18 R1h N/A (Hard-coded)

20 bit audio format support: 1 = yes, 0 = no.

B16 17 R1h N/A (Hard-coded)

16 bit audio format support: 1 = yes, 0 = no.

B8 16 R0h N/A (Hard-coded)

8 bit audio format support: 1 = yes, 0 = no.

Rsvd1 15:12 R0h N/A (Hard-coded)

Reserved.

R12 11 R0h N/A (Hard-coded)

384kHz rate support: 1 = yes, 0 = no.

R11 10 R1h N/A (Hard-coded)

192kHz rate support: 1 = yes, 0 = no.

Field Name Bits R/W Default Reset

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R10 9 R 0h N/A (Hard-coded)

176.4kHz rate support: 1 = yes, 0 = no.

R9 8 R 1h N/A (Hard-coded)

96kHz rate support: 1 = yes, 0 = no.

R8 7 R 1h N/A (Hard-coded)

88.2kHz rate support: 1 = yes, 0 = no.

R7 6 R 1h N/A (Hard-coded)

48kHz rate support: 1 = yes, 0 = no.

R6 5 R 1h N/A (Hard-coded)

44.1kHz rate support: 1 = yes, 0 = no.

R5 4 R 0h N/A (Hard-coded)

32kHz rate support: 1 = yes, 0 = no.

R4 3 R 0h N/A (Hard-coded)

22.05kHz rate support: 1 = yes, 0 = no.

R3 2 R 0h N/A (Hard-coded)

16kHz rate support: 1 = yes, 0 = no.

R2 1 R 0h N/A (Hard-coded)

11.025kHz rate support: 1 = yes, 0 = no.

R1 0 R 0h N/A (Hard-coded)

8kHz rate support: 1 = yes, 0 = no.

7.4.4. AFG (NID = 01h): StreamCap

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set

Get F000Bh

Field Name Bits R/W Default Reset

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Field Name Bits R/W Default Reset

Rsvd 31:3 R00000000h N/A (Hard-coded)

Reserved.

AC3 2 R 0h N/A (Hard-coded)

AC-3 formatted data support: 1 = yes, 0 = no.

Float32 1 R 0h N/A (Hard-coded)

Float32 formatted data support: 1 = yes, 0 = no.

PCM 0 R 1h N/A (Hard-coded)

PCM-formatted data support: 1 = yes, 0 = no.

7.4.5. AFG (NID = 01h): InAmpCap

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set

Get F000Dh

Field Name Bits R/W Default Reset

Mute 31 R0h N/A (Hard-coded)

Mute support: 1 = yes, 0 = no.

Rsvd3 30:23 R00h N/A (Hard-coded)

Reserved.

StepSize 22:16 R27h N/A (Hard-coded)

Size of each step in the gain range: 0 to 127 = .25dB to 32dB, in .25dB steps.

Rsvd2 15 R0h N/A (Hard-coded)

Reserved.

NumSteps 14:8 R03h N/A (Hard-coded)

Number of gains steps (number of possible settings - 1).

Rsvd1 7 R 0h N/A (Hard-coded)

Reserved.

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Offset 6:0 R00h N/A (Hard-coded)

Indicates which step is 0dB

7.4.6. AFG (NID = 01h): PwrStateCap

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set

Get F000Fh

Field Name Bits R/W Default Reset

EPSS 31 R1h N/A (Hard-coded)

Extended power states support: 1 = yes, 0 = no.

ClkStop 30 R1h N/A (Hard-coded)

D3 clock stop support: 1 = yes, 0 = no.

S3D3ColdSup 29 R1h N/A (Hard-coded)

Codec state intended during system S3 state: 1 = D3Hot, 0 = D3Cold.

Rsvd 28:5 R000000h N/A (Hard-coded)

Reserved.

D3ColdSup 4 R 1h N/A (Hard-coded)

D3Cold power state support: 1 = yes, 0 = no.

D3Sup 3 R 1h N/A (Hard-coded)

D3 power state support: 1 = yes, 0 = no.

D2Sup 2 R 1h N/A (Hard-coded)

D2 power state support: 1 = yes, 0 = no.

D1Sup 1 R 1h N/A (Hard-coded)

D1 power state support: 1 = yes, 0 = no.

D0Sup 0 R 1h N/A (Hard-coded)

D0 power state support: 1 = yes, 0 = no.

Field Name Bits R/W Default Reset

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7.4.7. AFG (NID = 01h): GPIOCnt

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set

Get F0011h

Field Name Bits R/W Default Reset

GPIWake 31 R1h N/A (Hard-coded)

Wake capability. Assuming the Wake Enable Mask controls are enabled,

GPIO's configured as inputs can cause a wake (generate a Status Change

event on the link) when there is a change in level on the pin.

GPIUnsol 30 R1h N/A (Hard-coded)

GPIO unsolicited response support: 1 = yes, 0 = no.

Rsvd 29:24 R00h N/A (Hard-coded)

Reserved.

NumGPIs 23:16 R00h N/A (Hard-coded)

Number of GPI pins supported by function group.

NumGPOs 15:8 R00h N/A (Hard-coded)

Number of GPO pins supported by function group.

NumGPIOs 7:0 R05h N/A (Hard-coded)

Number of GPIO pins supported by function group.

7.4.8. AFG (NID = 01h): OutAmpCap

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set

Get F0012h

Field Name Bits R/W Default Reset

Mute 31 R1h N/A (Hard-coded)

Mute support: 1 = yes, 0 = no.

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Rsvd3 30:23 R00h N/A (Hard-coded)

Reserved.

StepSize 22:16 R02h N/A (Hard-coded)

Size of each step in the gain range: 0 to 127 = .25dB to 32dB, in .25dB steps.

Rsvd2 15 R0h N/A (Hard-coded)

Reserved.

NumSteps 14:8 R7Fh N/A (Hard-coded)

Number of gains steps (number of possible settings - 1).

Rsvd1 7 R 0h N/A (Hard-coded)

Reserved.

Offset 6:0 R7Fh N/A (Hard-coded)

Indicates which step is 0dB

7.4.9. AFG (NID = 01h): PwrState

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 705h

Get F0500h

Field Name Bits R/W Default Reset

Rsvd3 31:11 R000000h N/A (Hard-coded)

Reserved.

SettingsReset 10 R1h POR - DAFG - ULR

Indicates if any persistent settings in this Function Group have been reset.

Cleared by PwrState 'Get' to this Widget.

ClkStopOK 9 R 1h POR - DAFG - ULR

Bit clock can currently be removed: 1 = yes, 0 = no.

Error 8 R 0h POR - DAFG - ULR

Error indicator: 1 = cannot enter requested power state, 0 = no problem with

requested power state.

Field Name Bits R/W Default Reset

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Rsvd2 7 R 0h N/A (Hard-coded)

Reserved.

Act 6:4 R3h POR - DAFG - LR

Actual power state of this widget.

Rsvd1 3 R 0h N/A (Hard-coded)

Reserved.

Set 2:0 RW 3h POR - DAFG - LR

Current power state setting for this widget.

7.4.10. AFG (NID = 01h): UnsolResp

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 708h

Get F0800h

Field Name Bits R/W Default Reset

Rsvd2 31:8 R000000h N/A (Hard-coded)

Reserved.

En 7RW 0h POR - DAFG - ULR

Unsolicited response enable: 1 = enabled, 0 = disabled.

Rsvd1 6 R 0h N/A (Hard-coded)

Reserved.

Tag 5:0 RW 00h POR - DAFG - ULR

Software programmable field returned in top six bits (31:26) of every Unsolicit-

ed Response generated by this node.

7.4.11. AFG (NID = 01h): GPIO

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 715h

Get F1500h

Field Name Bits R/W Default Reset

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Field Name Bits R/W Default Reset

Rsvd 31:5 R00000000h N/A (Hard-coded)

Reserved.

Data4 4RW 0h POR - DAFG - ULR

Data for GPIO4. If this GPIO bit is configured as Sticky (edge-sensitive) input,

it can be cleared by writing "0". For details of read back value, refer to HD Audio

spec. section 7.3.3.22

Data3 3RW 0h POR - DAFG - ULR

Data for GPIO3. If this GPIO bit is configured as Sticky (edge-sensitive) input,

it can be cleared by writing "0". For details of read back value, refer to HD Audio

spec. section 7.3.3.22

Data2 2RW 0h POR - DAFG - ULR

Data for GPIO2. If this GPIO bit is configured as Sticky (edge-sensitive) input,

it can be cleared by writing "0". For details of read back value, refer to HD Audio

spec. section 7.3.3.22

Data1 1RW 0h POR - DAFG - ULR

Data for GPIO1. If this GPIO bit is configured as Sticky (edge-sensitive) input,

it can be cleared by writing "0". For details of read back value, refer to HD Audio

spec. section 7.3.3.22

Data0 0RW 0h POR - DAFG - ULR

Data for GPIO0. If this GPIO bit is configured as Sticky (edge-sensitive) input,

it can be cleared by writing "0". For details of read back value, refer to HD Audio

spec. section 7.3.3.22

7.4.12. AFG (NID = 01h): GPIOEn

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 716h

Get F1600h

Field Name Bits R/W Default Reset

Rsvd 31:5 R00000000h N/A (Hard-coded)

Reserved.

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Mask4 4RW 0h POR - DAFG - ULR

Enable for GPIO4: 0 = pin is disabled (Hi-Z state); 1 = pin is enabled; behavior

determined by GPIO Direction control

Mask3 3RW 0h POR - DAFG - ULR

Enable for GPIO3: 0 = pin is disabled (Hi-Z state); 1 = pin is enabled; behavior

determined by GPIO Direction control

Mask2 2RW 0h POR - DAFG - ULR

Enable for GPIO2: 0 = pin is disabled (Hi-Z state); 1 = pin is enabled; behavior

determined by GPIO Direction control

Mask1 1RW 0h POR - DAFG - ULR

Enable for GPIO1: 0 = pin is disabled (Hi-Z state); 1 = pin is enabled; behavior

determined by GPIO Direction control

Mask0 0RW 0h POR - DAFG - ULR

Enable for GPIO0: 0 = pin is disabled (Hi-Z state); 1 = pin is enabled; behavior

determined by GPIO Direction control

7.4.13. AFG (NID = 01h): GPIODir

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 717h

Get F1700h

Field Name Bits R/W Default Reset

Rsvd 31:5 R00000000h N/A (Hard-coded)

Reserved.

Control4 4RW 0h POR - DAFG - ULR

Direction control for GPIO4: 0 = GPIO is configured as input; 1 = GPIO is con-

figured as output

Control3 3RW 0h POR - DAFG - ULR

Direction control for GPIO3: 0 = GPIO is configured as input; 1 = GPIO is con-

figured as output

Field Name Bits R/W Default Reset

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Control2 2RW 0h POR - DAFG - ULR

Direction control for GPIO2: 0 = GPIO is configured as input; 1 = GPIO is con-

figured as output

Control1 1RW 0h POR - DAFG - ULR

Direction control for GPIO1: 0 = GPIO is configured as input; 1 = GPIO is con-

figured as output

Control0 0RW 0h POR - DAFG - ULR

Direction control for GPIO0: 0 = GPIO is configured as input; 1 = GPIO is con-

figured as output

7.4.14. AFG (NID = 01h): GPIOWakeEn

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 718h

Get F1800h

Field Name Bits R/W Default Reset

Rsvd 31:5 R00000000h N/A (Hard-coded)

Reserved.

W4 4RW 0h POR - DAFG - ULR

Wake enable for GPIO4: 0 = wake-up event is disabled; 1 = When HD Audio

link is powered down (RST# is asserted), a wake-up event will trigger a Status

Change Request event on the link.

W3 3RW 0h POR - DAFG - ULR

Wake enable for GPIO3: 0 = wake-up event is disabled; 1 = When HD Audio

link is powered down (RST# is asserted), a wake-up event will trigger a Status

Change Request event on the link.

W2 2RW 0h POR - DAFG - ULR

Wake enable for GPIO2: 0 = wake-up event is disabled; 1 = When HD Audio

link is powered down (RST# is asserted), a wake-up event will trigger a Status

Change Request event on the link.

Field Name Bits R/W Default Reset

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W1 1RW 0h POR - DAFG - ULR

Wake enable for GPIO1: 0 = wake-up event is disabled; 1 = When HD Audio

link is powered down (RST# is asserted), a wake-up event will trigger a Status

Change Request event on the link.

W0 0RW 0h POR - DAFG - ULR

Wake enable for GPIO0: 0 = wake-up event is disabled; 1 = When HD Audio

link is powered down (RST# is asserted), a wake-up event will trigger a Status

Change Request event on the link.

7.4.15. AFG (NID = 01h): GPIOUnsol

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 719h

Get F1900h

Field Name Bits R/W Default Reset

Rsvd 31:5 R00000000h N/A (Hard-coded)

Reserved.

EnMask4 4RW 0h POR - DAFG - ULR

Unsolicited enable mask for GPIO4. If set, and the Unsolicited Response con-

trol for this widget has been enabled, an unsolicited response will be sent when

GPIO2 is configured as input and changes state.

EnMask3 3RW 0h POR - DAFG - ULR

Unsolicited enable mask for GPIO3. If set, and the Unsolicited Response con-

trol for this widget has been enabled, an unsolicited response will be sent when

GPIO2 is configured as input and changes state.

EnMask2 2RW 0h POR - DAFG - ULR

Unsolicited enable mask for GPIO2. If set, and the Unsolicited Response con-

trol for this widget has been enabled, an unsolicited response will be sent when

GPIO2 is configured as input and changes state.

EnMask1 1RW 0h POR - DAFG - ULR

Unsolicited enable mask for GPIO1. If set, and the Unsolicited Response con-

trol for this widget has been enabled, an unsolicited response will be sent when

GPIO1 is configured as input and changes state.

Field Name Bits R/W Default Reset

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EnMask0 0RW 0h POR - DAFG - ULR

Unsolicited enable mask for GPIO0. If set, and the Unsolicited Response con-

trol for this widget has been enabled, an unsolicited response will be sent when

GPIO0 is configured as input and changes state.

7.4.16. AFG (NID = 01h): GPIOSticky

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 71Ah

Get F1A00h

Field Name Bits R/W Default Reset

Rsvd 31:5 R00000000h N/A (Hard-coded)

Reserved.

Mask4 4RW 0h POR - DAFG - ULR

GPIO4 input type (when configured as input): 0 = Non-Sticky (level-sensitive);

1 = Sticky (edge-sensitive).

Mask3 3RW 0h POR - DAFG - ULR

GPIO3 input type (when configured as input): 0 = Non-Sticky (level-sensitive);

1 = Sticky (edge-sensitive).

Mask2 2RW 0h POR - DAFG - ULR

GPIO2 input type (when configured as input): 0 = Non-Sticky (level-sensitive);

1 = Sticky (edge-sensitive).

Mask1 1RW 0h POR - DAFG - ULR

GPIO1 input type (when configured as input): 0 = Non-Sticky (level-sensitive);

1 = Sticky (edge-sensitive).

Mask0 0RW 0h POR - DAFG - ULR

GPIO0 input type (when configured as input): 0 = Non-Sticky (level-sensitive);

1 = Sticky (edge-sensitive).

7.4.17. AFG (NID = 01h): SubID

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 723h 722h 721h 720h

Field Name Bits R/W Default Reset

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Get F2300h / F2200h / F2100h / F2000h

Field Name Bits R/W Default Reset

Subsys3 31:24 RW 00h POR

Subsystem ID (byte 3)

Subsys2 23:16 RW 00h POR

Subsystem ID (byte 2)

Subsys1 15:8 RW 01h POR

Subsystem ID (byte 1)

Assembly 7:0 RW 00h POR

Assembly ID (Not applicable to codec vendors).

7.4.18. AFG (NID = 01h): GPIOPlrty

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 770h

Get F7000h

Field Name Bits R/W Default Reset

Rsvd 31:5 R00000000h N/A (Hard-coded)

Reserved.

GP4 4RW 1h POR - DAFG - ULR

GPIO4 Polarity:

If configured as output or non-sticky input:

0 = inverting

1 = non-inverting

If configured as sticky input:

0 = falling edges will be detected

1 = rising edges will be detected

7.4.17. AFG (NID = 01h): SubID

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

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GP3 3RW 1h POR - DAFG - ULR

GPIO3 Polarity:

If configured as output or non-sticky input:

0 = inverting

1 = non-inverting

If configured as sticky input:

0 = falling edges will be detected

1 = rising edges will be detected

GP2 2RW 1h POR - DAFG - ULR

GPIO2 Polarity:

If configured as output or non-sticky input:

0 = inverting

1 = non-inverting

If configured as sticky input:

0 = falling edges will be detected

1 = rising edges will be detected

GP1 1RW 1h POR - DAFG - ULR

GPIO1 Polarity:

If configured as output or non-sticky input:

0 = inverting

1 = non-inverting

If configured as sticky input:

0 = falling edges will be detected

1 = rising edges will be detected

GP0 0RW 1h POR - DAFG - ULR

GPIO0 Polarity:

If configured as output or non-sticky input:

0 = inverting

1 = non-inverting

If configured as sticky input:

0 = falling edges will be detected

1 = rising edges will be detected

7.4.19. AFG (NID = 01h): GPIODrive

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 771h

Get F7100h

Field Name Bits R/W Default Reset

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Field Name Bits R/W Default Reset

Rsvd 31:5 R00000000h N/A (Hard-coded)

Reserved.

OD4 4RW 0h POR - DAFG - ULR

GPIO4 Drive Mode: 0 = push-pull (drive 0 and 1); 1 = open drain (drive 0, float

for 1).

OD3 3RW 0h POR - DAFG - ULR

GPIO3 Drive Mode: 0 = push-pull (drive 0 and 1); 1 = open drain (drive 0, float

for 1).

OD2 2RW 0h POR - DAFG - ULR

GPIO2 Drive Mode: 0 = push-pull (drive 0 and 1); 1 = open drain (drive 0, float

for 1).

OD1 1RW 0h POR - DAFG - ULR

GPIO1 Drive Mode: 0 = push-pull (drive 0 and 1); 1 = open drain (drive 0, float

for 1).

OD0 0RW 0h POR - DAFG - ULR

GPIO0 Drive Mode: 0 = push-pull (drive 0 and 1); 1 = open-drain (drive 0, float

for 1).

7.4.20. AFG (NID = 01h): DMic

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 778h

Get F7800h

Field Name Bits R/W Default Reset

Rsvd 31:6 R0000000h N/A (Hard-coded)

Reserved.

Mono1 5RW 0h POR

DMic1 mono select: 0 = stereo operation, 1 = mono operation (left channel du-

plicated to the right channel).

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Mono0 4RW 0h POR

DMic0 mono select: 0 = stereo operation, 1 = mono operation (left channel du-

plicated to the right channel).

PhAdj 3:2 RW 0h POR

Selects what phase of the DMic clock the data should be latched:

0h = left data rising edge/right data falling edge

1h = left data center of high/right data center of low

2h = left data falling edge/right data rising edge

3h = left data center of low/right data center of high

Rate 1:0 RW 2h POR

Selects the DMic clock rate:

0h = 4.704MHz

1h = 3.528MHz

2h = 2.352MHz

3h = 1.176MHz.

7.4.21. AFG (NID = 01h): DACMode

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 780h

Get F8000h

Field Name Bits R/W Default Reset

Rsvd 31:8 R000000h N/A (Hard-coded)

Reserved.

SwapEn 8RW 0h POR

Internal DAC left channel and right channel swap. 0h = not swap, 1h =

swap.

SDMSettleDisable 7RW 0h POR

SDM wait-to-settle disable:

1 = at mute, the SDM switches to the mute pattern immediately

0 = at mute, the SDM switches to the mute pattern after settling (can take up to

~45ms)

Field Name Bits R/W Default Reset

TSI™ CONFIDENTIAL

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SINGLE CHIP PC AUDIO SYSTEM, CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO

SDMCoeffSel 6RW 0h POR

DAC SDM coefficient select (stages 1, 2, 3):

1 = 1/16, 1/2, 1/4

0 = 1/16, 1/4, 1/2

SDMLFHalf 5RW 0h POR

DAC SDM local feedback coefficient select: 1 = 1/4096, 0 = 1/2048.

SDMLFDisable 4RW 0h POR

DAC SDM local feedback disable: 1 = local feedback disabled, 0 = local feed-

back enabled.

InvertValid 3RW 0h POR

DAC Valid Invert: 1 = 7.056MHz valid strobe is inverted, 0 = 7.056MHz valid

strobe is not inverted.

InvertData 2RW 0h POR

DAC Data Invert: 1 = 1-bit outputs are inverted, 0 = 1-bit outputs are not invert-

ed.

Atten6dBDisable 1RW 1h POR

Disable built-in -6dB digital attenuation: 1 = -6dB disabled, 0 = -6dB enabled.

Fade 0RW 1h POR

DAC Gain Fade Enable:

1 = gain will be slowly faded from old value to new value (~10ms)

0 = gain will jump immediately to new value.

7.4.22. AFG (NID = 01h): ADCMode

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 784h

Get F8400h

Field Name Bits R/W Default Reset

Rsvd2 31:4 R0000000h N/A (Hard-coded)

Reserved.

Field Name Bits R/W Default Reset

TSI™ CONFIDENTIAL

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SINGLE CHIP PC AUDIO SYSTEM, CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO

InvertValid 3RW 0h POR

ADC Valid Invert: 1 = 14.112MHz valid strobe is inverted, 0 = 14.112MHz valid

strobe is not inverted.

InvertData 2RW 0h POR

ADC Data Invert: 1 = 1-bit inputs are inverted, 0 = 1-bit inputs are not inverted.

ADCClkDelay 1RW 0h POR

Delay ADC clock.

DACClkDelay 0RW 0h POR

Delay DAC clock.

7.4.23. AFG (NID = 01h): PortUse

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 7C0h

Get FC000h

Field Name Bits R/W Default Reset

Rsvd 31:7 R0000000h N/A (Hard-coded)

Reserved.

Mono 6RW 1h POR

1=power down port if not input or output enabled, 0=do not force power down

based on input or output enable

PortF 5RW 1h POR

1=power down port if not input or output enabled, 0=do not force power down

based on input or output enable

PortE 4RW 1h POR

1=power down port if not input or output enabled, 0=do not force power down

based on input or output enable

PortD 3RW 1h POR

1=power down port if not input or output enabled, 0=do not force power down

based on input or output enable.

Field Name Bits R/W Default Reset

TSI™ CONFIDENTIAL

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SINGLE CHIP PC AUDIO SYSTEM, CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO

PortC 2RW 1h POR

1=power down port if not input or output enabled, 0=do not force power down

based on input or output enable

PortB 1RW 1h POR

1=power down port if not input or output enabled, 0=do not force power down

based on input or output enable

PortA 0RW 1h POR

1=power down port if not input or output enabled, 0=do not force power down

based on input or output enable.

7.4.24. AFG (NID = 01h): ComJack

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 7C7h 7C6h

Get FC700h/FC600h

Field Name Bits R/W Default Reset

Rsvd3 31:14 R00000000h N/A (Hard-coded)

Reserved.

DebounceTime 13:12 RW 1h POR

Combo Jack debounce time set.

2'h0 = 0.1ms; 2'h1 = 125ms; 2'h2 = 500ms; 2'h3 = 1s."

Rsvd2 11 Roh N/A (Hard-coded)

Reserved.

RbCon 10:8 RW 4h POR

Combo jack detection reference voltage

000 = 0.18*AVDD

001 = 0.16*AVDD

010 = 0.14*AVDD

011 = 0.12*AVDD

100 = 0.10*AVDD

101 = 0.08*AVDD

110 = 0.06*AVDD

111 = 0.04*AVDD

Field Name Bits R/W Default Reset

TSI™ CONFIDENTIAL

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SINGLE CHIP PC AUDIO SYSTEM, CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO

MasterPort 7:5 RW 0h POR

Port tied to the jack presence detection switch

000 = Port A

001 = Port B

010 = Port C

011 = Port D

100 = Port E

101 = Port F

Rsvd1 4 R 0h N/A (Hard-coded)

Reserved.

SlavePort 3:1 RW 0h POR

Port used as microphone input

When combo jack detection is enabled, Port presence detection as shown in

the pin complex is not sensed directly by the sense input but is inferred by the

load placed on the Vref_Output associated with the port

000 = Port A

001 = Port B

010 = Port C

011 = Port D;100 = Port E

101 = Port F

Det-en 0 R 0h POR

0h = disable combo jact detection 1h = enable combo jact detection

7.4.25. AFG (NID = 01h): VSPwrState

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 7D8h

Get FD800h

Field Name Bits R/W Default Reset

Rsvd 31:2 R00000000h N/A (Hard-coded)

Reserved.

Field Name Bits R/W Default Reset

TSI™ CONFIDENTIAL

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SINGLE CHIP PC AUDIO SYSTEM, CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO

D5 1RW 0h POR - ELR

Vendor specific D5 power state, only entered once the part is already in D3cold

(this bit must be set before the command to enter D3cold). If set, this bit over-

rides the D4 bit (bit 0). Includes the power savings of D4, but additionally pow-

ers down GPIO pins, the VAG amp, and the HP amps. Exits this power state

via POR or rising edge of Link Reset.

D4 0RW 0h POR - ELR

Vendor specific D4 power state, only entered once the part is already in D3cold

(this bit must be set before the command to enter D3cold). If the D5 bit (bit 1)

is set, this bit is overridden. Includes the power savings of D3cold, but addi-

tionally powers down the HDA interface (no responses). Exit this power state

via POR or rising edge of Link Reset.

7.4.26. AFG (NID = 01h): AnaPort

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 7EDh 7ECh

Get FEC00h

Field Name Bits R/W Default Reset

Rsvd2 31:7 R0000000h N/A (Hard-coded)

Reserved.

MonoPwd 6RW 0h POR

Power down Mono Output.

FPwd 5RW 0h POR

Power down Port F.

EPwd 4RW 0h POR

Power down Port E.

DPwd 3RW 0h POR

Power down Port D.

CPwd 2RW 0h POR

Power down Port C.

Field Name Bits R/W Default Reset

TSI™ CONFIDENTIAL

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SINGLE CHIP PC AUDIO SYSTEM, CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO

BPwd 1RW 0h POR

Power down Port B.

APwd 0RW 0h POR

Power down Port A.

7.4.27. AFG (NID = 01h): AnaBTL

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 7F6h 7F5h 7F4h

Get FF400h

Field Name Bits R/W Default Reset

Rsvd6 31:22 R0h N/A (Hard-coded)

Reserved.

SCStableTimeSel 21:22 RW 0h POR

The programmed time window for short circuit detect.

This is available on WB silicon revisions and beyond. Prior silicon revi-

sions, these bits are reserved.

TSOverrideHiz 19 RW 0h POR

Override Hiz for the BTL amplifier power stage circuit: set to 1 to Hiz, set back

to 0 to normal mode

TSTestMode 18 RW 0h POR

Temp sense test mode select, 0=normal operation, 1=sensor will trip at ambi-

ent temperature.

TSForcePwd 17 RW 1h POR

Temp sense force powerdown select

0=BTL will not be muted and powered down even if it is still overheating when

the volume is 0h

1=BTL will be muted and powered down even if it is still overheating when the

volume is 0h

TSInstantCutMode 16 RW 0h POR

Temp sense instant cut mode

0=Two trip points used to smoothly adjust the volume

1=One single trip point used to set volume to wither 0 or max value (TI mode)

Field Name Bits R/W Default Reset

TSI™ CONFIDENTIAL

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SINGLE CHIP PC AUDIO SYSTEM, CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO

TSWait 15:12 RW 3h POR

Temperature sensing wait time between volume increments

0h = 2ms (polling at 2ms)

1h = 4ms (polling at 4ms)

2h = 8ms (polling at 8ms)

3h = 16ms (polling at 16ms)

4h = 32ms (polling at 16ms)

5h = 64ms (polling at 16ms)

6h = 128ms (polling at 16ms)

7h = 256ms (polling at 16ms)

8h = 512ms (polling at 16ms)

9h = 1.024s (polling at 16ms)

Ah = 2.048s (polling at 16ms)

Bh = 4.096s (polling at 16ms)

Ch = 8.192s (polling at 16ms)

Dh = 16.384s (polling at 16ms)

Eh = 32.768s (polling at 16ms)

Fh = 65.536s (polling at 16ms).

TSTripHish 11:9 RW 3h POR

Temp sense high trip point setting:

0h = 125 Degrees C

1h =140 Degrees C

2h = 155 Degrees C

3h = 170 Degrees C

4h = 185 C

5h = 200 C

6h = 215 C

7h = Reserved

TSOverrideRest 8RW 0h POR

Override reset for the BTL amplifier Temp sense circuit: set to 1 to recalculate, set

back to 0 to latch the value

TSTripLow 7:5 RW 2h POR

Temp sense low trip point setting:

0h = 110 Degrees C

1h = 125 Degrees C

2h = 140 Degrees C

3h = 155 Degrees C

4h = 170 C

5h = 185 C

6h = 200 C

7h = 215 C

Rsvd1 4:0 R0h NA

Reserved

Field Name Bits R/W Default Reset

TSI™ CONFIDENTIAL

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SINGLE CHIP PC AUDIO SYSTEM, CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO

7.4.28. AFG (NID = 01h): AnaBTLStatus

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set

Get FF700h

Field Name Bits R/W Default Reset

Rsvd 31:20 R00h N/A (Hard-coded)

Reserved.

TSTripHigh 19 R0h POR

Temp sense high trip point status

TSTripLow 18 R0h POR

Temp sense low trip point status

TSMute 17 R0h POR

Temp sense forced mute status for BTL amplifier

TSPwd 16 R0h POR

Temp sense forced powerdown status for BTL amplifier

TSLeftVol 15:8 R0h POR

Temp sense volume status for the BTL amplifier: 00000000b..11111111b =

Range specified for SPKVol field.

TSRightVol 7:0 R0h POR

Temp sense volume status for the BTL amplifier: 00000000b..11111111b =

Range specified for SPKVol field.

7.4.29. AFG (NID = 01h): AnaCapless

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 7FAh 7F9h 7F8h

Get FF800h

TSI™ CONFIDENTIAL

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Field Name Bits R/W Default Reset

Rsvd2 31:26 R00h N/A (Hard-coded)

Reserved.

VRegSCDet 25 R0h POR

Capless regulator short circuit detect indicator.

ChargePumpSCDet 24 R0h POR

Capless charge pump short circuit detect indicator.

VRegSel 23:20 RW 5h POR

Capless regulator output voltage multiply ratio

Bits [3..2] Reserved

Bits [1..0]:

00b = 2*Vbg

01b = 2.1*Vbg

10b = 2.2*Vbg

11b = 2.3*Vbg

VRegSCRstB 19 RW 0h POR

Capless regulator short circuit detect reset: 0 = short circuit detect disabled, 1

= short circuit detect enabled.

VRegGndShort 18 RW 0h POR

Ground the capless regulator output.

VRegPwd 17 RW 0h POR

Capless regulator powerdown.

ChargePumpSCRstB 16 RW 0h POR

Capless charge pump short circuit detect reset: 0 = short circuit detect dis-

abled, 1 = short circuit detect enabled.

ChargePumpHiZ 15 RW 0h POR

Hi-Z the capless charge pump outputs.

ChargePumpPwd 14 RW 0h POR

Capless charge pump powerdown.

ChargePumpSplyDetOver-

ride

13 RW 0h POR

Capless charge pump supply detect override.

TSI™ CONFIDENTIAL

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ChargePumpFreqBypass 12 RW 1h POR

Capless charge pump frequency reg bypass.

ChargePumpClkRate 11:8 RW 8h POR

Capless charge pump clock rate:

0000b = 800.0kHz (24MHz/30)

0001b = 750.0kHz (24MHz/32)

0010b = 706.9kHz (24MHz/34)

0011b = 666.7kHz (24MHz/36)

0100b = 631.6kHz (24MHz/38)

0101b = 600.0kHz (24MHz/40)

0110b = 571.4kHz (24MHz/42)

0111b = 545.5kHz (24MHz/44)

1000b = 800.0kHz (24MHz/30)

1001b = 857.1kHz (24MHz/28)

1010b = 923.1kHz (24MHz/26)

1011b = 1.000MHz (24MHz/24)

1100b = 1.091MHz (24MHz/22)

1101b = 1.200MHz (24MHz/20)

1110b = 1.333MHz (24MHz/18)

1111b = 1.500MHz (24MHz/16)

ChargePumpClkDiv 7:5 RW 4h POR

Capless charge pump analog clock divider:

001b = No divide

010b = Divide by 2, 50% duty cycle

100b = Divide by 4, 50% duty cycle

110b = Divide by 2, 75% duty cycle

011b = Divide by 4, 75% duty cycle

111b = Divide by 4, 87.5% duty cycle

Other values undefined

ChargePumpClkSel 4RW 0h POR

Capless charge pump clock select: 0 = ring oscillator, 1 = charge pump clock

defined by AFGCaplessChargePumpClkRate[3:0] field below.

PadGnd 3RW 0h POR

Ground the output pad of the capless amplifiers.

InputGnd 2RW 0h POR

Ground the input to the capless output amplifiers.

Rsvd1 1 R 0h NA

Reserved

Field Name Bits R/W Default Reset

TSI™ CONFIDENTIAL

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SINGLE CHIP PC AUDIO SYSTEM, CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO

AntiPopBypass 0RW 0h POR

0 = Enable anti-pop on the capless headphone; 1 = bypass anti-pop on the ca-

pless headphone.

7.4.30. AFG (NID = 01h): Reset

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 7FFh

Get FFF00h

Field Name Bits R/W Default Reset

Rsvd1 31:8 R000000h N/A (Hard-coded)

Reserved.

Execute 7:0 W00h N/A (Hard-coded)

Function Reset. Function Group reset is executed when the Set verb 7FF is

written with 8-bit payload of 00h. The codec should issue a response to ac-

knowledge receipt of the verb, and then reset the affected Function Group and

all associated widgets to their power-on reset values. Some controls such as

Configuration Default controls should not be reset. Overlaps Response.

Field Name Bits R/W Default Reset

TSI™ CONFIDENTIAL

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7.4.31. AFG (NID = 01h): DAC3OutAmp (Mono Out Volume)

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 7B6hh

Get FB600h

Field Name Bits R/W Default Reset

Rsvd 31:8 R0000000h N/A (Hard-coded)

Reserved.

Mute 7RW 0h POR - DAFG - ULR

Amp mute: 1 = muted, 0 = not muted

Gain 6:0 RW 7Fh POR - DAFG - ULR

Amp gain step number (see OutAmpCap parameter of AFG)

TSI™ CONFIDENTIAL

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7.4.32. AFG (NID = 01h): AnaBeep

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 7EFh 7EEh

Get FEE00h / FEE00h

Field Name Bits R/W Default Reset

Rsvd2 31:14 R00000h N/A (Hard-coded)

Reserved.

Detect 13 R0h POR - DAFG - ULR

0: no beep present; 1: beep present.

GainAdj 12:10 RW 3h POR

Analog PC Beep Gain in digital side 7h = -6dB, 6h = -12dB, 5h = -18dB, 4h = -24dB, 3h

= -30dB, 2h = -36dB, 1h = -42dB, 0h = -48dB.

ConvertEn 9RW 1h POR

Analog pc beep quantization enable (enabled only when both

""d2a_ana_pc_beep_det_en"" and ""d2a_ana_pc_beep_convert_en"" are 1).

DetectEn 8RW 1h POR

Analog pc beep detection enable 0h = disable 1h = enable.

Rsvd1 7:6 R0h N/A (Hard-coded)

Gain 5:4 RW 3h POR

Analog PC Beep Gain: 0h = -24dB, 1h = -18dB, 2h = -12dB, 3h = -6dB.

CntSel 3:2 RW 0h POR

Select counter delay.0h=64ms,1h = 128ms, 2h = 256ms, 3h = 512ms.

Mode 1:0 RW 2h POR

Analog PC Beep Mode:

00b = Always disabled

01b = Always enabled

1Xb = Enabled during HDA Link Reset only

TSI™ CONFIDENTIAL

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7.4.33. AFG (NID = 01h): EAPD

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 788h

Get F8800h

Field Name Bits R/W Default Reset

Rsvd7 31:19 R00000h N/A (Hard-coded)

Reserved.

HPESDInv 18 RW 0h POR

YA silicon: called AuxSDInv

Port E HP Amp Shutdown Invert:

0 = Amp will power down (or mute) when EAPD pin is low

1 = Amp will power down (or mute) when EAPD pin is high

HPESDMode 17 RW 1h POR

YA silicon and before: Reserved

Port E HP Amp Shutdown Mode:

0 = Amp will mute when disabled

1 = Amp will enter a low power state when disabled

HPESD 16 RW 0h POR

YA silicon and before: Reserved

Port E HP Amp Shutdown Control Select:

0 = Amp controlled by EAPD pin only

1 = Amp controlled by power state only

Rsvd4 15 R 0 N/A (Hard-coded)

Reserved.

HPBSDInv 14 RW 0h POR

Port B HP Amp Shutdown Invert:

0 = Amp will power down (or mute) when EAPD pin is low

1 = Amp will power down (or mute) when EAPD pin is high

HPBSDMode 13 RW 1h POR

Port B HP Amp Shutdown Mode:

0 = Amp will mute when disabled

1 = Amp will enter a low power state when disabled

TSI™ CONFIDENTIAL

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HPBSD 12 RW 0h POR

Port B HP Amp Shutdown Control Select:

0 = Amp controlled by EAPD pin only

1 = Amp controlled by power state only

Rsvd3 11 R0h N/A (Hard-coded)

Reserved.

HPASDInv 10 RW 0h POR

Port A HP Amp Shutdown Invert:

0 = Amp will power down (or mute) when EAPD pin is low

1 = Amp will power down (or mute) when EAPD pin is high

HPASDMode 9RW 1h POR

Port A HP Amp Shutdown Mode:

0 = Amp will mute when disabled

1 = Amp will enter a low power state when disabled

HPASD 8RW 0h POR

Port A HP Amp Shutdown Control Select:

0 = Amp controlled by EAPD pin only

1 = Amp controlled by power state only

Rsvd2 7 R 0h N/A (Hard-coded)

Reserved.

BTLSDInv 6RW 0h POR

BTL Amp Shutdown Invert:

0 = Amp will power down (or mute) when EAPD pin is low

1 = Amp will power down (or mute) when EAPD pin is high

BTLSDMode 5RW 1h POR

BTL Amp Shutdown Mode:

0 = Amp will mute when disabled

1 = Amp will enter a low power state when disabled

BTLSD 4RW 0h POR

BTL Amp Shutdown Control Select:

0 = Amp controlled by EAPD pin only

1 = Amp controlled by power state only

Rsvd1 3:2 R0h N/A (Hard-coded)

Reserved.

Field Name Bits R/W Default Reset

TSI™ CONFIDENTIAL

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PinMode 1:0 RW 0h POR

EAPD Pin Mode:

00b = Open Drain I/O (Value at pin is wired-AND of EAPD bit & external signal)

01b = CMOS Output (Value of EAPD bit is forced at pin)

1xb = CMOS Input (External signal controls internal amps, EAPD bit ignored)

Field Name Bits R/W Default Reset

TSI™ CONFIDENTIAL

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SINGLE CHIP PC AUDIO SYSTEM, CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO

7.4.34. AFG (NID = 01h): ComboJackTime (Available only on WB revision and beyond)

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 7CAh 7C9h

Get FCA00h/FC900h

Field Name Bits R/W Default Reset

Rsvd3 31:16 R0000000h N/A (Hard-coded)

Reserved.

bouncertimer_bypass 15 RW 0h POR

0 = all the combjack debounce time in normal;

1= all the comjack debounce time in simulation mode(debounce time is short).

t_delay_slave_port_usr 14:12 RW 3h POR

000 = 2frame

001 =4frame

010 =8frame

011 =16frame

100 = 32frame

101 =64frame

110 = 128frame

111 = 256frame

t_stable 11:8 RW 7h POR

0000 = 0.1ms

0001 =0.5ms

0010 =1ms

0011 =2ms

0100 = 4ms

0101 =8ms

0110 = 16ms

0111 = 32ms

1000 = 64ms

1001 =128ms;1010 =256ms;1011 =512ms

1100 = 1024ms

1101 =1024ms

1110 = 1024ms

1111 = 1024ms

RSVD2 7R0h N/A (Hard-coded)

Reserved

TSI™ CONFIDENTIAL

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t_long_realtime_detect 6:4 RW 5h POR

000 = 2s

001 =4s

010 =8s

011 =16s

100 = 32s

101 =64s

110 = 128s

111 = infinite

RSVD1 3R0h N/A (Hard-coded)

Reserved

t_delay_verfout 2:0 RW 3h POR

000 = 0.1ms

001 =50ms

010 = 125ms

011 =250ms

100 = 500ms

101 = 1s

110 = 2s

111 = 4s

Field Name Bits R/W Default Reset

TSI™ CONFIDENTIAL

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7.5. PortA (NID = 0Ah): WCap

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set

Get F0009h

Field Name Bits R/W Default Reset

Rsvd2 31:24 R00h N/A (Hard-coded)

Reserved.

Type 23:20 R4h N/A (Hard-coded)

Widget type:

0h = Out Converter

1h = In Converter

2h = Summing (Mixer)

3h = Selector (Mux)

4h = Pin Complex

5h = Power

6h = Volume Knob

7h = Beep Generator

8h-Eh = Reserved

Fh = Vendor Defined

Delay 19:16 R0h N/A (Hard-coded)

Number of sample delays through widget.

Rsvd1 15:12 R0h N/A (Hard-coded)

Reserved.

SwapCap 11 R0h N/A (Hard-coded)

Left/right swap support: 1 = yes, 0 = no.

PwrCntrl 10 R1h N/A (Hard-coded)

Power state support: 1 = yes, 0 = no.

Dig 9 R 0h N/A (Hard-coded)

Digital stream support: 1 = yes (digital), 0 = no (analog).

ConnList 8 R 1h N/A (Hard-coded)

Connection list present: 1 = yes, 0 = no.

UnSolCap 7 R 1h N/A (Hard-coded)

Unsolicited response support: 1 = yes, 0 = no.

TSI™ CONFIDENTIAL

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ProcWidget 6 R 0h N/A (Hard-coded)

Processing state support: 1 = yes, 0 = no.

Stripe 5 R 0h N/A (Hard-coded)

Striping support: 1 = yes, 0 = no.

FormatOvrd 4 R 0h N/A (Hard-coded)

Stream format override: 1 = yes, 0 = no.

AmpParOvrd 3 R 0h N/A (Hard-coded)

Amplifier capabilities override: 1 = yes, no.

OutAmpPrsnt 2 R 0h N/A (Hard-coded)

Output amp present: 1 = yes, 0 = no.

InAmpPrsnt 1 R 1h N/A (Hard-coded)

Input amp present: 1 = yes, 0 = no.

Stereo 0 R 1h N/A (Hard-coded)

Stereo stream support: 1 = yes (stereo), 0 = no (mono).

7.5.1. PortA (NID = 0Ah): PinCap

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set

Get F000Ch

Field Name Bits R/W Default Reset

Rsvd2 31:17 R0000h N/A (Hard-coded)

Reserved.

EapdCap 16 R1h N/A (Hard-coded)

EAPD support: 1 = yes, 0 = no.

Field Name Bits R/W Default Reset

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VrefCntrl 15:8 R17h N/A (Hard-coded)

Vref support:

bit 7 = Reserved

bit 6 = Reserved

bit 5 = 100% support (1 = yes, 0 = no)

bit 4 = 80% support (1 = yes, 0 = no)

bit 3 = Reserved

bit 2 = GND support (1 = yes, 0 = no)

bit 1 = 50% support (1 = yes, 0 = no)

bit 0 = Hi-Z support (1 = yes, 0 = no)

Rsvd1 7 R 0h N/A (Hard-coded)

Reserved.

BalancedIO 6 R 0h N/A (Hard-coded)

Balanced I/O support: 1 = yes, 0 = no.

InCap 5 R 1h N/A (Hard-coded)

Input support: 1 = yes, 0 = no.

OutCap 4 R 1h N/A (Hard-coded)

Output support: 1 = yes, 0 = no.

HdphDrvCap 3 R 1h N/A (Hard-coded)

Headphone amp present: 1 = yes, 0 = no.

PresDtctCap 2 R 1h N/A (Hard-coded)

Presence detection support: 1 = yes, 0 = no.

TrigRqd 1 R 0h N/A (Hard-coded)

Trigger required for impedance sense: 1 = yes, 0 = no.

ImpSenseCap 0 R 0h N/A (Hard-coded)

Impedance sense support: 1 = yes, 0 = no.

7.5.2. PortA (NID = 0Ah): ConLst

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set

Get F000Eh

Field Name Bits R/W Default Reset

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Field Name Bits R/W Default Reset

Rsvd 31:8 R000000h N/A (Hard-coded)

Reserved.

LForm 7 R 0h N/A (Hard-coded)

Connection list format: 1 = long-form (15-bit) NID entries, 0 = short-form (7-bit)

NID entries.

ConL 6:0 R03h N/A (Hard-coded)

Number of NID entries in connection list.

7.5.3. PortA (NID = 0Ah): ConLstEntry0

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set

Get F0200h

Field Name Bits R/W Default Reset

ConL3 31:24 R00h N/A (Hard-coded)

DAC2 Converter widget (0x22)

ConL2 23:16 R1Ch N/A (Hard-coded)

MixerOutVol Selector widget (0x1C)

ConL1 15:8 R14h N/A (Hard-coded)

DAC1 Converter widget (0x14)

ConL0 7:0 R13h N/A (Hard-coded)

DAC0 Converter widget (0x13)

7.5.4. PortA (NID = 0Ah): InAmpLeft

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 360h

Get B2000h

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Field Name Bits R/W Default Reset

Rsvd1 31:2 R00000000h N/A (Hard-coded)

Reserved.

Gain 1:0 RW 0h POR - DAFG - ULR

Amp gain step number (see InAmpCap parameter pertaining to this widget).

7.5.5. PortA (NID = 0Ah): InAmpRight

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 350h

Get B0000h

Field Name Bits R/W Default Reset

Rsvd1 31:2 R00000000h N/A (Hard-coded)

Reserved.

Gain 1:0 RW 0h POR - DAFG - ULR

Amp gain step number (see InAmpCap parameter pertaining to this widget).

7.5.6. PortA (NID = 0Ah): ConSelectCtrl

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 701h

Get F0100h

Field Name Bits R/W Default Reset

Rsvd 31:2 R00000000h N/A (Hard-coded)

Reserved.

Index 1:0 RW 0h POR - DAFG - ULR

Connection select control index.

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7.5.7. PortA (NID = 0Ah): PwrState

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 705h

Get F0500h

Field Name Bits R/W Default Reset

Rsvd4 31:11 R000000h N/A (Hard-coded)

Reserved.

SettingsReset 10 R1h POR - DAFG - ULR

Indicates if any persistent settings in this Widget have been reset. Cleared by

PwrState 'Get', or a 'Set' to any Verb in this Widget.

Rsvd3 9 R 0h N/A (Hard-coded)

Reserved.

Error 8 R 0h POR - DAFG - ULR

Error indicator: 1 = cannot enter requested power state, 0 = no problem with

requested power state.

Rsvd2 7:6 R0h N/A (Hard-coded)

Reserved.

Act 5:4 R3h POR - DAFG - LR

Actual power state of this widget.

Rsvd1 3:2 R0h N/A (Hard-coded)

Reserved.

Set 1:0 RW 0h POR - DAFG - LR

Current power state setting for this widget.

7.5.8. PortA (NID = 0Ah): PinWCntrl

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 707h

Get F0700h

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Field Name Bits R/W Default Reset

Rsvd2 31:8 R000000h N/A (Hard-coded)

Reserved.

HPhnEn 7RW 0h POR - DAFG - ULR

Headphone amp enable: 1 = enabled, 0 = disabled.

OutEn 6RW 0h POR - DAFG - ULR

Output enable: 1 = enabled, 0 = disabled.

InEn 5RW 0h POR - DAFG - ULR

Input enable: 1 = enabled, 0 = disabled.

Rsvd1 4:3 R0h N/A (Hard-coded)

Reserved.

VRefEn 2:0 RW 0h POR - DAFG - ULR

Vref selection (See VrefCntrl field of PinCap parameter for supported selec-

tions):

000b= HI-Z

001b= 50%

010b= GND

011b= Reserved

100b= 80%

101b= 100%

110b= Reserved

111b= Reserved

7.5.9. PortA (NID = 0Ah): UnsolResp

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 708h

Get F0800h

Field Name Bits R/W Default Reset

Rsvd2 31:8 R000000h N/A (Hard-coded)

Reserved.

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En 7RW 0h POR - DAFG - ULR

Unsolicited response enable (also enables Wake events for this Widget): 1 =

enabled, 0 = disabled.

Rsvd1 6 R 0h N/A (Hard-coded)

Reserved.

Tag 5:0 RW 00h POR - DAFG - ULR

Software programmable field returned in top six bits (31:26) of every Unsolicit-

ed Response generated by this node.

7.5.10. PortA (NID = 0Ah): ChSense

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 709h

Get F0900h

Field Name Bits R/W Default Reset

PresDtct 31 R0h POR

Presence detection indicator: 1 = presence detected; 0 = presence not detect-

ed.

Rsvd 30:0 R00000000h N/A (Hard-coded)

Reserved.

7.5.11. PortA (NID = 0Ah): EAPDBTLLR

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 70Ch

Get F0C00h

Field Name Bits R/W Default Reset

Rsvd2 31:2 R00000000h N/A (Hard-coded)

Reserved.

Field Name Bits R/W Default Reset

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EAPD 1RW 1h POR - DAFG - ULR

EAPD control: 1 = set EAPD pin to 1 (powered) up if this pin is powered up, 0

= set EAPD pin to 0.

Rsvd1 0 R 0h N/A (Hard-coded)

Reserved.

7.5.12. PortA (NID = 0Ah): ConfigDefault

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 71Fh 71Eh 71Dh 71Ch

Get F1F00h / F1E00h / F1D00h / F1C00h

Field Name Bits R/W Default Reset

PortConnectivity 31:30 RW 0h POR

Port connectivity:

0h = Port complex is connected to a jack

1h = No physical connection for port

2h = Fixed function device is attached

3h = Both jack and internal device attached (info in all other fields refers to in-

tegrated device, any presence detection refers to jack)

Location 29:24 RW 02h POR

Location

Bits [5..4]:

0h = External on primary chassis

1h = Internal

2h = Separate chassis

3h = Other

Bits [3..0]:

0h = N/A

1h = Rear

2h = Front

3h = Left

4h = Right

5h = Top

6h = Bottom

7h-9h = Special

Ah-Fh = Reserved

Field Name Bits R/W Default Reset

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Device 23:20 RW Ah POR

Default device:

0h = Line out

1h = Speaker

2h = HP out

3h = CD

4h = SPDIF Out

5h = Digital other out

6h = Modem line side

7h = Modem handset side

8h = Line in

9h = Aux

Ah = Mic in

Bh = Telephony

Ch = SPDIF In

Dh = Digital other in

Eh = Reserved

Fh = Other

ConnectionType 19:16 RW 1h POR

Connection type:

0h = Unknown

1h = 1/8" stereo/mono

2h = 1/4" stereo/mono

3h = ATAPI internal

4h = RCA

5h = Optical

6h = Other digital

7h = Other analog

8h = Multichannel analog (DIN)

9h = XLR/Professional

Ah = RJ-11 (modem)

Bh = Combination

Ch-Eh = Reserved

Fh = Other

Field Name Bits R/W Default Reset

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Color 15:12 RW 9h POR

Color:

0h = Unknown

1h = Black

2h = Grey

3h = Blue

4h = Green

5h = Red

6h = Orange

7h = Yellow

8h = Purple

9h = Pink

Ah-Dh = Reserved

Eh = White

Fh = Other

Misc 11:8 RW 0h POR

Miscellaneous:

Bits [3..1] = Reserved

Bit 0 = Jack detect override

Association 7:4 RW 2h POR

Default assocation.

Sequence 3:0 RW Fh POR

Sequence.

7.6. PortB (NID = 0Bh): WCap

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set

Get F0009h

Field Name Bits R/W Default Reset

Rsvd2 31:24 R00h N/A (Hard-coded)

Reserved.

Field Name Bits R/W Default Reset

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Type 23:20 R4h N/A (Hard-coded)

Widget type:

0h = Out Converter

1h = In Converter

2h = Summing (Mixer)

3h = Selector (Mux)

4h = Pin Complex

5h = Power

6h = Volume Knob

7h = Beep Generator

8h-Eh = Reserved

Fh = Vendor Defined

Delay 19:16 R0h N/A (Hard-coded)

Number of sample delays through widget.

Rsvd1 15:12 R0h N/A (Hard-coded)

Reserved.

SwapCap 11 R0h N/A (Hard-coded)

Left/right swap support: 1 = yes, 0 = no.

PwrCntrl 10 R1h N/A (Hard-coded)

Power state support: 1 = yes, 0 = no.

Dig 9 R 0h N/A (Hard-coded)

Digital stream support: 1 = yes (digital), 0 = no (analog).

ConnList 8 R 1h N/A (Hard-coded)

Connection list present: 1 = yes, 0 = no.

UnSolCap 7 R 1h N/A (Hard-coded)

Unsolicited response support: 1 = yes, 0 = no.

ProcWidget 6 R 0h N/A (Hard-coded)

Processing state support: 1 = yes, 0 = no.

Stripe 5 R 0h N/A (Hard-coded)

Striping support: 1 = yes, 0 = no.

FormatOvrd 4 R 0h N/A (Hard-coded)

Stream format override: 1 = yes, 0 = no.

Field Name Bits R/W Default Reset

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AmpParOvrd 3 R 0h N/A (Hard-coded)

Amplifier capabilities override: 1 = yes, no.

OutAmpPrsnt 2 R 0h N/A (Hard-coded)

Output amp present: 1 = yes, 0 = no.

InAmpPrsnt 1 R 0h N/A (Hard-coded)

Input amp present: 1 = yes, 0 = no.

Stereo 0 R 1h N/A (Hard-coded)

Stereo stream support: 1 = yes (stereo), 0 = no (mono).

7.6.1. PortB (NID = 0Bh): PinCap

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set

Get F000Ch

Field Name Bits R/W Default Reset

Rsvd2 31:17 R0000h N/A (Hard-coded)

Reserved.

EapdCap 16 R1h N/A (Hard-coded)

EAPD support: 1 = yes, 0 = no.

VrefCntrl 15:8 R00h N/A (Hard-coded)

Vref support:

bit 7 = Reserved

bit 6 = Reserved

bit 5 = 100% support (1 = yes, 0 = no)

bit 4 = 80% support (1 = yes, 0 = no)

bit 3 = Reserved

bit 2 = GND support (1 = yes, 0 = no)

bit 1 = 50% support (1 = yes, 0 = no)

bit 0 = Hi-Z support (1 = yes, 0 = no)

Rsvd1 7 R 0h N/A (Hard-coded)

Reserved.

Field Name Bits R/W Default Reset

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BalancedIO 6 R 0h N/A (Hard-coded)

Balanced I/O support: 1 = yes, 0 = no.

InCap 5 R 0h N/A (Hard-coded)

Input support: 1 = yes, 0 = no.

OutCap 4 R 1h N/A (Hard-coded)

Output support: 1 = yes, 0 = no.

HdphDrvCap 3 R 1h N/A (Hard-coded)

Headphone amp present: 1 = yes, 0 = no.

PresDtctCap 2 R 1h N/A (Hard-coded)

Presence detection support: 1 = yes, 0 = no.

TrigRqd 1 R 0h N/A (Hard-coded)

Trigger required for impedance sense: 1 = yes, 0 = no.

ImpSenseCap 0 R 0h N/A (Hard-coded)

Impedance sense support: 1 = yes, 0 = no.

7.6.2. PortB (NID = 0Bh): ConLst

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set

Get F000Eh

Field Name Bits R/W Default Reset

Rsvd 31:8 R000000h N/A (Hard-coded)

Reserved.

LForm 7 R 0h N/A (Hard-coded)

Connection list format: 1 = long-form (15-bit) NID entries, 0 = short-form (7-bit)

NID entries.

ConL 6:0 R03h N/A (Hard-coded)

Number of NID entries in connection list.

Field Name Bits R/W Default Reset

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7.6.3. PortB (NID = 0Bh): ConLstEntry0

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set

Get F0200h

Field Name Bits R/W Default Reset

ConL3 31:24 R00h N/A (Hard-coded)

DAC2 Converter widget (0x22)

ConL2 23:16 R1Ch N/A (Hard-coded)

MixerOutVol Selector widget (0x1C)

ConL1 15:8 R14h N/A (Hard-coded)

DAC1 Converter widget (0x14)

ConL0 7:0 R13h N/A (Hard-coded)

DAC0 Converter widget (0x13)

7.6.4. PortB (NID = 0Bh): ConSelectCtrl

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 701h

Get F0100h

Field Name Bits R/W Default Reset

Rsvd 31:2 R00000000h N/A (Hard-coded)

Reserved.

Index 1:0 RW 0h POR - DAFG - ULR

Connection select control index.

7.6.5. PortB (NID = 0Bh): PwrState

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 705h

Get F0500h

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Field Name Bits R/W Default Reset

Rsvd4 31:11 R000000h N/A (Hard-coded)

Reserved.

SettingsReset 10 R1h POR - DAFG - ULR

Indicates if any persistent settings in this Widget have been reset. Cleared by

PwrState 'Get', or a 'Set' to any Verb in this Widget.

Rsvd3 9 R 0h N/A (Hard-coded)

Reserved.

Error 8 R 0h POR - DAFG - ULR

Error indicator: 1 = cannot enter requested power state, 0 = no problem with

requested power state.

Rsvd2 7:6 R0h N/A (Hard-coded)

Reserved.

Act 5:4 R3h POR - DAFG - LR

Actual power state of this widget.

Rsvd1 3:2 R0h N/A (Hard-coded)

Reserved.

Set 1:0 RW 0h POR - DAFG - LR

Current power state setting for this widget.

7.6.6. PortB (NID = 0Bh): PinWCntrl

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 707h

Get F0700h

Field Name Bits R/W Default Reset

Rsvd2 31:8 R000000h N/A (Hard-coded)

Reserved.

HPhnEn 7RW 0h POR - DAFG - ULR

Headphone amp enable: 1 = enabled, 0 = disabled.

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OutEn 6RW 0h POR - DAFG - ULR

Output enable: 1 = enabled, 0 = disabled.

Rsvd1 5:0 RW 00h N/A (Hard-coded)

Reserved.

7.6.7. PortB (NID = 0Bh): UnsolResp

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 708h

Get F0800h

Field Name Bits R/W Default Reset

Rsvd2 31:8 R000000h N/A (Hard-coded)

Reserved.

En 7RW 0h POR - DAFG - ULR

Unsolicited response enable (also enables Wake events for this Widget): 1 =

enabled, 0 = disabled.

Rsvd1 6 R 0h N/A (Hard-coded)

Reserved.

Tag 5:0 RW 00h POR - DAFG - ULR

Software programmable field returned in top six bits (31:26) of every Unsolicit-

ed Response generated by this node.

7.6.8. PortB (NID = 0Bh): ChSense

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 709h

Get F0900h

Field Name Bits R/W Default Reset

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Field Name Bits R/W Default Reset

PresDtct 31 R0h POR

Presence detection indicator: 1 = presence detected; 0 = presence not detect-

ed.

Rsvd 30:0 R00000000h N/A (Hard-coded)

Reserved.

7.6.9. PortB (NID = 0Bh): EAPDBTLLR

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 70Ch

Get F0C00h

Field Name Bits R/W Default Reset

Rsvd2 31:2 R00000000h N/A (Hard-coded)

Reserved.

EAPD 1RW 1h POR - DAFG - ULR

EAPD control: 1 = set EAPD pin to 1 (powered) up if this pin is powered up, 0

= set EAPD pin to 0.

Rsvd1 0 R 0h N/A (Hard-coded)

Reserved.

7.6.10. PortB (NID = 0Bh): ConfigDefault

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 71Fh 71Eh 71Dh 71Ch

Get F1F00h / F1E00h / F1D00h / F1C00h

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Field Name Bits R/W Default Reset

PortConnectivity 31:30 RW 0h POR

Port connectivity:

0h = Port complex is connected to a jack

1h = No physical connection for port

2h = Fixed function device is attached

3h = Both jack and internal device attached (info in all other fields refers to in-

tegrated device, any presence detection refers to jack)

Location 29:24 RW 02h POR

Location

Bits [5..4]:

0h = External on primary chassis

1h = Internal

2h = Separate chassis

3h = Other

Bits [3..0]:

0h = N/A

1h = Rear

2h = Front

3h = Left

4h = Right

5h = Top

6h = Bottom

7h-9h = Special

Ah-Fh = Reserved

Device 23:20 RW 2h POR

Default device:

0h = Line out

1h = Speaker

2h = HP out

3h = CD

4h = SPDIF Out

5h = Digital other out

6h = Modem line side

7h = Modem handset side

8h = Line in

9h = Aux

Ah = Mic in

Bh = Telephony

Ch = SPDIF In

Dh = Digital other in

Eh = Reserved

Fh = Other

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ConnectionType 19:16 RW 1h POR

Connection type:

0h = Unknown

1h = 1/8" stereo/mono

2h = 1/4" stereo/mono

3h = ATAPI internal

4h = RCA

5h = Optical

6h = Other digital

7h = Other analog

8h = Multichannel analog (DIN)

9h = XLR/Professional

Ah = RJ-11 (modem)

Bh = Combination

Ch-Eh = Reserved

Fh = Other

Color 15:12 RW 4h POR

Color:

0h = Unknown

1h = Black

2h = Grey

3h = Blue

4h = Green

5h = Red

6h = Orange

7h = Yellow

8h = Purple

9h = Pink

Ah-Dh = Reserved

Eh = White

Fh = Other

Misc 11:8 RW 0h POR

Miscellaneous:

Bits [3..1] = Reserved

Bit 0 = Jack detect override

Association 7:4 RW 1h POR

Default assocation.

Sequence 3:0 RW Fh POR

Sequence.

Field Name Bits R/W Default Reset

TSI™ CONFIDENTIAL

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SINGLE CHIP PC AUDIO SYSTEM, CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO

7.7. PortC (NID = 0Ch): WCap

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set

Get F0009h

Field Name Bits R/W Default Reset

Rsvd2 31:24 R00h N/A (Hard-coded)

Reserved.

Type 23:20 R4h N/A (Hard-coded)

Widget type:

0h = Out Converter

1h = In Converter

2h = Summing (Mixer)

3h = Selector (Mux)

4h = Pin Complex

5h = Power

6h = Volume Knob

7h = Beep Generator

8h-Eh = Reserved

Fh = Vendor Defined

Delay 19:16 R0h N/A (Hard-coded)

Number of sample delays through widget.

Rsvd1 15:12 R0h N/A (Hard-coded)

Reserved.

SwapCap 11 R0h N/A (Hard-coded)

Left/right swap support: 1 = yes, 0 = no.

PwrCntrl 10 R1h N/A (Hard-coded)

Power state support: 1 = yes, 0 = no.

Dig 9 R 0h N/A (Hard-coded)

Digital stream support: 1 = yes (digital), 0 = no (analog).

ConnList 8 R 1h N/A (Hard-coded)

Connection list present: 1 = yes, 0 = no.

UnSolCap 7 R 1h N/A (Hard-coded)

Unsolicited response support: 1 = yes, 0 = no.

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ProcWidget 6 R 0h N/A (Hard-coded)

Processing state support: 1 = yes, 0 = no.

Stripe 5 R 0h N/A (Hard-coded)

Striping support: 1 = yes, 0 = no.

FormatOvrd 4 R 0h N/A (Hard-coded)

Stream format override: 1 = yes, 0 = no.

AmpParOvrd 3 R 0h N/A (Hard-coded)

Amplifier capabilities override: 1 = yes, no.

OutAmpPrsnt 2 R 0h N/A (Hard-coded)

Output amp present: 1 = yes, 0 = no.

InAmpPrsnt 1 R 1h N/A (Hard-coded)

Input amp present: 1 = yes, 0 = no.

Stereo 0 R 1h N/A (Hard-coded)

Stereo stream support: 1 = yes (stereo), 0 = no (mono).

7.7.1. PortC (NID = 0Ch): PinCap

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set

Get F000Ch

Field Name Bits R/W Default Reset

Rsvd2 31:17 R0000h N/A (Hard-coded)

Reserved.

EapdCap 16 R1h N/A (Hard-coded)

EAPD support: 1 = yes, 0 = no.

Field Name Bits R/W Default Reset

TSI™ CONFIDENTIAL

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SINGLE CHIP PC AUDIO SYSTEM, CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO

VrefCntrl 15:8 R17h N/A (Hard-coded)

Vref support:

bit 7 = Reserved

bit 6 = Reserved

bit 5 = 100% support (1 = yes, 0 = no)

bit 4 = 80% support (1 = yes, 0 = no)

bit 3 = Reserved

bit 2 = GND support (1 = yes, 0 = no)

bit 1 = 50% support (1 = yes, 0 = no)

bit 0 = Hi-Z support (1 = yes, 0 = no)

Rsvd1 7 R 0h N/A (Hard-coded)

Reserved.

BalancedIO 6 R 0h N/A (Hard-coded)

Balanced I/O support: 1 = yes, 0 = no.

InCap 5 R 1h N/A (Hard-coded)

Input support: 1 = yes, 0 = no.

OutCap 4 R 1h N/A (Hard-coded)

Output support: 1 = yes, 0 = no.

HdphDrvCap 3 R 0h N/A (Hard-coded)

Headphone amp present: 1 = yes, 0 = no.

PresDtctCap 2 R 1h N/A (Hard-coded)

Presence detection support: 1 = yes, 0 = no.

TrigRqd 1 R 0h N/A (Hard-coded)

Trigger required for impedance sense: 1 = yes, 0 = no.

ImpSenseCap 0 R 0h N/A (Hard-coded)

Impedance sense support: 1 = yes, 0 = no.

7.7.2. PortC (NID = 0Ch): ConLst

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set

Get F000Eh

Field Name Bits R/W Default Reset

TSI™ CONFIDENTIAL

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SINGLE CHIP PC AUDIO SYSTEM, CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO

Field Name Bits R/W Default Reset

Rsvd 31:8 R000000h N/A (Hard-coded)

Reserved.

LForm 7 R 0h N/A (Hard-coded)

Connection list format: 1 = long-form (15-bit) NID entries, 0 = short-form (7-bit)

NID entries.

ConL 6:0 R03h N/A (Hard-coded)

Number of NID entries in connection list.

7.7.3. PortC (NID = 0Ch): ConLstEntry0

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set

Get F0200h

Field Name Bits R/W Default Reset

ConL3 31:24 R00h N/A (Hard-coded)

Reserved

ConL2 23:16 R1Ch N/A (Hard-coded)

MixerOutVol Selector widget (0x1C)

ConL1 15:8 R14h N/A (Hard-coded)

DAC1 Converter widget (0x14)

ConL0 7:0 R13h N/A (Hard-coded)

DAC0 Converter widget (0x13)

7.7.4. PortC (NID = 0Ch): InAmpLeft

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 360h

Get B2000h

TSI™ CONFIDENTIAL

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SINGLE CHIP PC AUDIO SYSTEM, CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO

Field Name Bits R/W Default Reset

Rsvd1 31:2 R00000000h N/A (Hard-coded)

Reserved.

Gain 1:0 RW 0h POR - DAFG - ULR

Amp gain step number (see InAmpCap parameter pertaining to this widget).

7.7.5. PortC (NID = 0Ch): InAmpRight

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 350h

Get B0000h

Field Name Bits R/W Default Reset

Rsvd1 31:2 R00000000h N/A (Hard-coded)

Reserved.

Gain 1:0 RW 0h POR - DAFG - ULR

Amp gain step number (see InAmpCap parameter pertaining to this widget).

7.7.6. PortC (NID = 0Ch): ConSelectCtrl

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 701h

Get F0100h

Field Name Bits R/W Default Reset

Rsvd 31:2 R00000000h N/A (Hard-coded)

Reserved.

Index 1:0 RW 0h POR - DAFG - ULR

Connection select control index.

TSI™ CONFIDENTIAL

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7.7.7. PortC (NID = 0Ch): PwrState

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 705h

Get F0500h

Field Name Bits R/W Default Reset

Rsvd4 31:11 R000000h N/A (Hard-coded)

Reserved.

SettingsReset 10 R1h POR - DAFG - ULR

Indicates if any persistent settings in this Widget have been reset. Cleared by

PwrState 'Get', or a 'Set' to any Verb in this Widget.

Rsvd3 9 R 0h N/A (Hard-coded)

Reserved.

Error 8 R 0h POR - DAFG - ULR

Error indicator: 1 = cannot enter requested power state, 0 = no problem with

requested power state.

Rsvd2 7:6 R0h N/A (Hard-coded)

Reserved.

Act 5:4 R3h POR - DAFG - LR

Actual power state of this widget.

Rsvd1 3:2 R0h N/A (Hard-coded)

Reserved.

Set 1:0 RW 0h POR - DAFG - LR

Current power state setting for this widget.

7.7.8. PortC (NID = 0Ch): PinWCntrl

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 707h

Get F0700h

TSI™ CONFIDENTIAL

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SINGLE CHIP PC AUDIO SYSTEM, CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO

Field Name Bits R/W Default Reset

Rsvd2 31:7 R000000h N/A (Hard-coded)

Reserved.

OutEn 6RW 0h POR - DAFG - ULR

Output enable: 1 = enabled, 0 = disabled.

InEn 5RW 0h POR - DAFG - ULR

Input enable: 1 = enabled, 0 = disabled.

Rsvd1 4:3 R0h N/A (Hard-coded)

Reserved.

VRefEn 2:0 RW 0h POR - DAFG - ULR

Vref selection (See VrefCntrl field of PinCap parameter for supported selec-

tions):

000b= HI-Z

001b= 50%

010b= GND

011b= Reserved

100b= 80%

101b= 100%

110b= Reserved

111b= Reserved

7.7.9. PortC (NID = 0Ch): UnsolResp

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 708h

Get F0800h

Field Name Bits R/W Default Reset

Rsvd2 31:8 R000000h N/A (Hard-coded)

Reserved.

En 7RW 0h POR - DAFG - ULR

Unsolicited response enable (also enables Wake events for this Widget): 1 =

enabled, 0 = disabled.

TSI™ CONFIDENTIAL

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SINGLE CHIP PC AUDIO SYSTEM, CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO

Rsvd1 6 R 0h N/A (Hard-coded)

Reserved.

Tag 5:0 RW 00h POR - DAFG - ULR

Software programmable field returned in top six bits (31:26) of every Unsolicit-

ed Response generated by this node.

7.7.10. PortC (NID = 0Ch): ChSense

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 709h

Get F0900h

Field Name Bits R/W Default Reset

PresDtct 31 R0h POR

Presence detection indicator: 1 = presence detected; 0 = presence not detect-

ed.

Rsvd 30:0 R00000000h N/A (Hard-coded)

Reserved.

7.7.11. PortC (NID = 0Ch): EAPDBTLLR

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 70Ch

Get F0C00h

Field Name Bits R/W Default Reset

Rsvd2 31:2 R00000000h N/A (Hard-coded)

Reserved.

EAPD 1RW 1h POR - DAFG - ULR

EAPD control: 1 = set EAPD pin to 1 (powered) up if this pin is powered up, 0

= set EAPD pin to 0.

Field Name Bits R/W Default Reset

TSI™ CONFIDENTIAL

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SINGLE CHIP PC AUDIO SYSTEM, CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO

Rsvd1 0 R 0h N/A (Hard-coded)

Reserved.

7.7.12. PortC (NID = 0Ch): ConfigDefault

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 71Fh 71Eh 71Dh 71Ch

Get F1F00h / F1E00h / F1D00h / F1C00h

Field Name Bits R/W Default Reset

PortConnectivity 31:30 RW 0h POR

Port connectivity:

0h = Port complex is connected to a jack

1h = No physical connection for port

2h = Fixed function device is attached

3h = Both jack and internal device attached (info in all other fields refers to in-

tegrated device, any presence detection refers to jack)

Location 29:24 RW 01h POR

Location

Bits [5..4]:

0h = External on primary chassis

1h = Internal

2h = Separate chassis

3h = Other

Bits [3..0]:

0h = N/A

1h = Rear

2h = Front

3h = Left

4h = Right

5h = Top

6h = Bottom

7h-9h = Special

Ah-Fh = Reserved

Field Name Bits R/W Default Reset

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Device 23:20 RW Ah POR

Default device:

0h = Line out

1h = Speaker

2h = HP out

3h = CD

4h = SPDIF Out

5h = Digital other out

6h = Modem line side

7h = Modem handset side

8h = Line in

9h = Aux

Ah = Mic in

Bh = Telephony

Ch = SPDIF In

Dh = Digital other in

Eh = Reserved

Fh = Other

ConnectionType 19:16 RW 1h POR

Connection type:

0h = Unknown

1h = 1/8" stereo/mono

2h = 1/4" stereo/mono

3h = ATAPI internal

4h = RCA

5h = Optical

6h = Other digital

7h = Other analog

8h = Multichannel analog (DIN)

9h = XLR/Professional

Ah = RJ-11 (modem)

Bh = Combination

Ch-Eh = Reserved

Fh = Other

Field Name Bits R/W Default Reset

TSI™ CONFIDENTIAL

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SINGLE CHIP PC AUDIO SYSTEM, CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO

Color 15:12 RW 9h POR

Color:

0h = Unknown

1h = Black

2h = Grey

3h = Blue

4h = Green

5h = Red

6h = Orange

7h = Yellow

8h = Purple

9h = Pink

Ah-Dh = Reserved

Eh = White

Fh = Other

Misc 11:8 RW 0h POR

Miscellaneous:

Bits [3..1] = Reserved

Bit 0 = Jack detect override

Association 7:4 RW 2h POR

Default assocation.

Sequence 3:0 RW 1h POR

Sequence.

Field Name Bits R/W Default Reset

TSI™ CONFIDENTIAL

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SINGLE CHIP PC AUDIO SYSTEM, CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO

7.8. PortD (NID = 0Dh): WCap

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set

Get F0009h

Field Name Bits R/W Default Reset

Rsvd2 31:24 R00h N/A (Hard-coded)

Reserved.

Type 23:20 R4h N/A (Hard-coded)

Widget type:

0h = Out Converter

1h = In Converter

2h = Summing (Mixer)

3h = Selector (Mux)

4h = Pin Complex

5h = Power

6h = Volume Knob

7h = Beep Generator

8h-Eh = Reserved

Fh = Vendor Defined

Delay 19:16 R0h N/A (Hard-coded)

Number of sample delays through widget.

Rsvd1 15:12 R0h N/A (Hard-coded)

Reserved.

SwapCap 11 R0h N/A (Hard-coded)

Left/right swap support: 1 = yes, 0 = no.

PwrCntrl 10 R1h N/A (Hard-coded)

Power state support: 1 = yes, 0 = no.

Dig 9 R 0h N/A (Hard-coded)

Digital stream support: 1 = yes (digital), 0 = no (analog).

ConnList 8 R 1h N/A (Hard-coded)

Connection list present: 1 = yes, 0 = no.

UnSolCap 7 R 0h N/A (Hard-coded)

Unsolicited response support: 1 = yes, 0 = no.

TSI™ CONFIDENTIAL

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ProcWidget 6 R 0h N/A (Hard-coded)

Processing state support: 1 = yes, 0 = no.

Stripe 5 R 0h N/A (Hard-coded)

Striping support: 1 = yes, 0 = no.

FormatOvrd 4 R 0h N/A (Hard-coded)

Stream format override: 1 = yes, 0 = no.

AmpParOvrd 3 R 0h N/A (Hard-coded)

Amplifier capabilities override: 1 = yes, no.

OutAmpPrsnt 2 R 0h N/A (Hard-coded)

Output amp present: 1 = yes, 0 = no.

InAmpPrsnt 1 R 0h N/A (Hard-coded)

Input amp present: 1 = yes, 0 = no.

Stereo 0 R 1h N/A (Hard-coded)

Stereo stream support: 1 = yes (stereo), 0 = no (mono).

7.8.1. PortD (NID = 0Dh): PinCap

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set

Get F000Ch

Field Name Bits R/W Default Reset

Rsvd2 31:17 R0000h N/A (Hard-coded)

Reserved.

EapdCap 16 R1h N/A (Hard-coded)

EAPD support: 1 = yes, 0 = no.

Field Name Bits R/W Default Reset

TSI™ CONFIDENTIAL

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SINGLE CHIP PC AUDIO SYSTEM, CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO

VrefCntrl 15:8 R00h N/A (Hard-coded)

Vref support:

bit 7 = Reserved

bit 6 = Reserved

bit 5 = 100% support (1 = yes, 0 = no)

bit 4 = 80% support (1 = yes, 0 = no)

bit 3 = Reserved

bit 2 = GND support (1 = yes, 0 = no)

bit 1 = 50% support (1 = yes, 0 = no)

bit 0 = Hi-Z support (1 = yes, 0 = no)

Rsvd1 7 R 0h N/A (Hard-coded)

Reserved.

BalancedIO 6 R 1h N/A (Hard-coded)

Balanced I/O support: 1 = yes, 0 = no.

InCap 5 R 0h N/A (Hard-coded)

Input support: 1 = yes, 0 = no.

OutCap 4 R 1h N/A (Hard-coded)

Output support: 1 = yes, 0 = no.

HdphDrvCap 3 R 0h N/A (Hard-coded)

Headphone amp present: 1 = yes, 0 = no.

PresDtctCap 2 R 0h N/A (Hard-coded)

Presence detection support: 1 = yes, 0 = no.

TrigRqd 1 R 0h N/A (Hard-coded)

Trigger required for impedance sense: 1 = yes, 0 = no.

ImpSenseCap 0 R 0h N/A (Hard-coded)

Impedance sense support: 1 = yes, 0 = no.

7.8.2. PortD (NID = 0Dh): ConLst

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set

Get F000Eh

Field Name Bits R/W Default Reset

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SINGLE CHIP PC AUDIO SYSTEM, CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO

Field Name Bits R/W Default Reset

Rsvd 31:8 R000000h N/A (Hard-coded)

Reserved.

LForm 7 R 0h N/A (Hard-coded)

Connection list format: 1 = long-form (15-bit) NID entries, 0 = short-form (7-bit)

NID entries.

ConL 6:0 R03h N/A (Hard-coded)

Number of NID entries in connection list.

7.8.3. PortD (NID = 0Dh): ConLstEntry0

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set

Get F0200h

Field Name Bits R/W Default Reset

ConL3 31:24 R00h N/A (Hard-coded)

Reserved

ConL2 23:16 R1Ch N/A (Hard-coded)

MixerOutVol Selector widget (0x1C)

ConL1 15:8 R14h N/A (Hard-coded)

DAC1 Converter widget (0x14)

ConL0 7:0 R13h N/A (Hard-coded)

DAC0 Converter widget (0x13)

7.8.4. PortD (NID = 0Dh): ConSelectCtrl

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 701h

Get F0100h

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Field Name Bits R/W Default Reset

Rsvd 31:2 R00000000h N/A (Hard-coded)

Reserved.

Index 1:0 RW 0h POR - DAFG - ULR

Connection select control index.

7.8.5. PortD (NID = 0Dh): PwrState

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 705h

Get F0500h

Field Name Bits R/W Default Reset

Rsvd4 31:11 R000000h N/A (Hard-coded)

Reserved.

SettingsReset 10 R1h POR - DAFG - ULR

Indicates if any persistent settings in this Widget have been reset. Cleared by

PwrState 'Get', or a 'Set' to any Verb in this Widget.

Rsvd3 9 R 0h N/A (Hard-coded)

Reserved.

Error 8 R 0h POR - DAFG - ULR

Error indicator: 1 = cannot enter requested power state, 0 = no problem with

requested power state.

Rsvd2 7:6 R0h N/A (Hard-coded)

Reserved.

Act 5:4 R3h POR - DAFG - LR

Actual power state of this widget.

Rsvd1 3:2 R0h N/A (Hard-coded)

Reserved.

Set 1:0 RW 0h POR - DAFG - LR

Current power state setting for this widget.

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7.8.6. PortD (NID = 0Dh): PinWCntrl

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 707h

Get F0700h

Field Name Bits R/W Default Reset

Rsvd2 31:7 R000000h N/A (Hard-coded)

Reserved.

OutEn 6RW 0h POR - DAFG - ULR

Output enable: 1 = enabled, 0 = disabled.

Rsvd1 5:0 R0h N/A (Hard-coded)

Reserved.

7.8.7. PortD (NID = 0Dh): EAPDBTLLR

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 70Ch

Get F0C00h

Field Name Bits R/W Default Reset

Rsvd2 31:2 R00000000h N/A (Hard-coded)

Reserved.

EAPD 1RW 1h POR - DAFG - ULR

EAPD control: 1 = set EAPD pin to 1 (powered) up if this pin is powered up, 0

= set EAPD pin to 0.

Rsvd1 0 R 0h N/A (Hard-coded)

Reserved.

7.8.8. PortD (NID = 0Dh): ConfigDefault

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 71Fh 71Eh 71Dh 71Ch

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Get F1F00h / F1E00h / F1D00h / F1C00h

Field Name Bits R/W Default Reset

PortConnectivity 31:30 RW 2h POR

Port connectivity:

0h = Port complex is connected to a jack

1h = No physical connection for port

2h = Fixed function device is attached

3h = Both jack and internal device attached (info in all other fields refers to in-

tegrated device, any presence detection refers to jack)

Location 29:24 RW 10h POR

Location

Bits [5..4]:

0h = External on primary chassis

1h = Internal

2h = Separate chassis

3h = Other

Bits [3..0]:

0h = N/A

1h = Rear

2h = Front

3h = Left

4h = Right

5h = Top

6h = Bottom

7h-9h = Special

Ah-Fh = Reserved

7.8.8. PortD (NID = 0Dh): ConfigDefault

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

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Device 23:20 RW 1h POR

Default device:

0h = Line out

1h = Speaker

2h = HP out

3h = CD

4h = SPDIF Out

5h = Digital other out

6h = Modem line side

7h = Modem handset side

8h = Line in

9h = Aux

Ah = Mic in

Bh = Telephony

Ch = SPDIF In

Dh = Digital other in

Eh = Reserved

Fh = Other

ConnectionType 19:16 RW 7h POR

Connection type:

0h = Unknown

1h = 1/8" stereo/mono

2h = 1/4" stereo/mono

3h = ATAPI internal

4h = RCA

5h = Optical

6h = Other digital

7h = Other analog

8h = Multichannel analog (DIN)

9h = XLR/Professional

Ah = RJ-11 (modem)

Bh = Combination

Ch-Eh = Reserved

Fh = Other

Field Name Bits R/W Default Reset

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Color 15:12 RW 0h POR

Color:

0h = Unknown

1h = Black

2h = Grey

3h = Blue

4h = Green

5h = Red

6h = Orange

7h = Yellow

8h = Purple

9h = Pink

Ah-Dh = Reserved

Eh = White

Fh = Other

Misc 11:8 RW 1h POR

Miscellaneous:

Bits [3..1] = Reserved

Bit 0 = Jack detect override

Association 7:4 RW 1h POR

Default assocation.

Sequence 3:0 RW 0h POR

Sequence.

Field Name Bits R/W Default Reset

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7.9. PortE (NID = 0Eh): WCap

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set

Get F0009h

Field Name Bits R/W Default Reset

Rsvd2 31:24 R00h N/A (Hard-coded)

Reserved.

Type 23:20 R4h N/A (Hard-coded)

Widget type:

0h = Out Converter

1h = In Converter

2h = Summing (Mixer)

3h = Selector (Mux)

4h = Pin Complex

5h = Power

6h = Volume Knob

7h = Beep Generator

8h-Eh = Reserved

Fh = Vendor Defined

Delay 19:16 R0h N/A (Hard-coded)

Number of sample delays through widget.

Rsvd1 15:12 R0h N/A (Hard-coded)

Reserved.

SwapCap 11 R0h N/A (Hard-coded)

Left/right swap support: 1 = yes, 0 = no.

PwrCntrl 10 R1h N/A (Hard-coded)

Power state support: 1 = yes, 0 = no.

Dig 9 R 0h N/A (Hard-coded)

Digital stream support: 1 = yes (digital), 0 = no (analog).

ConnList 8 R 1h N/A (Hard-coded)

Connection list present: 1 = yes, 0 = no.

UnSolCap 7 R 1h N/A (Hard-coded)

Unsolicited response support: 1 = yes, 0 = no.

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ProcWidget 6 R 0h N/A (Hard-coded)

Processing state support: 1 = yes, 0 = no.

Stripe 5 R 0h N/A (Hard-coded)

Striping support: 1 = yes, 0 = no.

FormatOvrd 4 R 0h N/A (Hard-coded)

Stream format override: 1 = yes, 0 = no.

AmpParOvrd 3 R 0h N/A (Hard-coded)

Amplifier capabilities override: 1 = yes, no.

OutAmpPrsnt 2 R 0h N/A (Hard-coded)

Output amp present: 1 = yes, 0 = no.

InAmpPrsnt 1 R 1h N/A (Hard-coded)

Input amp present: 1 = yes, 0 = no.

Stereo 0 R 1h N/A (Hard-coded)

Stereo stream support: 1 = yes (stereo), 0 = no (mono).

7.9.1. PortE (NID = 0Eh): PinCap

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set

Get F000Ch

Field Name Bits R/W Default Reset

Rsvd2 31:17 R0000h N/A (Hard-coded)

Reserved.

EapdCap 16 R1h N/A (Hard-coded)

EAPD support: 1 = yes, 0 = no.

Field Name Bits R/W Default Reset

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VrefCntrl 15:8 R00h N/A (Hard-coded)

Vref support:

bit 7 = Reserved

bit 6 = Reserved

bit 5 = 100% support (1 = yes, 0 = no)

bit 4 = 80% support (1 = yes, 0 = no)

bit 3 = Reserved

bit 2 = GND support (1 = yes, 0 = no)

bit 1 = 50% support (1 = yes, 0 = no)

bit 0 = Hi-Z support (1 = yes, 0 = no)

Rsvd1 7 R 0h N/A (Hard-coded)

Reserved.

BalancedIO 6 R 0h N/A (Hard-coded)

Balanced I/O support: 1 = yes, 0 = no.

InCap 5 R 1h N/A (Hard-coded)

Input support: 1 = yes, 0 = no.

OutCap 4 R 1h N/A (Hard-coded)

Output support: 1 = yes, 0 = no.

HdphDrvCap 3 R 1h N/A (Hard-coded)

Headphone amp present: 1 = yes, 0 = no.

HdphDrvCap 3 R 0h N/A (Hard-coded)

Headphone amp present: 1 = yes, 0 = no.

PresDtctCap 2 R 1h N/A (Hard-coded)

Presence detection support: 1 = yes, 0 = no.

TrigRqd 1 R 0h N/A (Hard-coded)

Trigger required for impedance sense: 1 = yes, 0 = no.

ImpSenseCap 0 R 0h N/A (Hard-coded)

Impedance sense support: 1 = yes, 0 = no.

7.9.2. PortE (NID = 0Eh): ConLst

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set

Get F000Eh

Field Name Bits R/W Default Reset

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Field Name Bits R/W Default Reset

Rsvd 31:8 R000000h N/A (Hard-coded)

Reserved.

LForm 7 R 0h N/A (Hard-coded)

Connection list format: 1 = long-form (15-bit) NID entries, 0 = short-form (7-bit)

NID entries.

ConL 6:0 R03h N/A (Hard-coded)

Number of NID entries in connection list.

7.9.3. PortE (NID = 0Eh): ConLstEntry0

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set

Get F0200h

Field Name Bits R/W Default Reset

ConL3 31:24 R00h N/A (Hard-coded)

DAC2 Converter widget (0x22)

ConL2 23:16 R1Ch N/A (Hard-coded)

MixerOutVol Selector widget (0x1C)

ConL1 15:8 R14h N/A (Hard-coded)

DAC1 Converter widget (0x14)

ConL0 7:0 R13h N/A (Hard-coded)

DAC0 Converter widget (0x13)

7.9.4. PortE (NID = 0Eh): InAmpLeft

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 360h

Get B2000h

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Field Name Bits R/W Default Reset

Rsvd1 31:2 R00000000h N/A (Hard-coded)

Reserved.

Gain 1:0 RW 0h POR - DAFG - ULR

Amp gain step number (see InAmpCap parameter pertaining to this widget).

7.9.5. PortE (NID = 0Eh): InAmpRight

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 350h

Get B0000h

Field Name Bits R/W Default Reset

Rsvd1 31:2 R00000000h N/A (Hard-coded)

Reserved.

Gain 1:0 RW 0h POR - DAFG - ULR

Amp gain step number (see InAmpCap parameter pertaining to this widget).

7.9.6. PortE (NID = 0Eh): ConSelectCtrl

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 701h

Get F0100h

Field Name Bits R/W Default Reset

Rsvd 31:2 R00000000h N/A (Hard-coded)

Reserved.

Index 1:0 RW 0h POR - DAFG - ULR

Connection select control index.

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7.9.7. PortE (NID = 0Eh): PwrState

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 705h

Get F0500h

Field Name Bits R/W Default Reset

Rsvd4 31:11 R000000h N/A (Hard-coded)

Reserved.

SettingsReset 10 R1h POR - DAFG - ULR

Indicates if any persistent settings in this Widget have been reset. Cleared by

PwrState 'Get', or a 'Set' to any Verb in this Widget.

Rsvd3 9 R 0h N/A (Hard-coded)

Reserved.

Error 8 R 0h POR - DAFG - ULR

Error indicator: 1 = cannot enter requested power state, 0 = no problem with

requested power state.

Rsvd2 7:6 R0h N/A (Hard-coded)

Reserved.

Act 5:4 R3h POR - DAFG - LR

Actual power state of this widget.

Rsvd1 3:2 R0h N/A (Hard-coded)

Reserved.

Set 1:0 RW 0h POR - DAFG - LR

Current power state setting for this widget.

7.9.8. PortE (NID = 0Eh): PinWCntrl

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 707h

Get F0700h

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Field Name Bits R/W Default Reset

Rsvd2 31:7 R000000h N/A (Hard-coded)

Reserved.

OutEn 6RW 0h POR - DAFG - ULR

Output enable: 1 = enabled, 0 = disabled.

InEn 5 R 0h N/A (Hard-coded)

Input enable: 1 = enabled, 0 = disabled.

Rsvd1 4:0 R0h N/A (Hard-coded)

Reserved.

7.9.9. PortE (NID = 0Eh): UnsolResp

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 708h

Get F0800h

Field Name Bits R/W Default Reset

Rsvd2 31:8 R000000h N/A (Hard-coded)

Reserved.

En 7RW 0h POR - DAFG - ULR

Unsolicited response enable (also enables Wake events for this Widget): 1 =

enabled, 0 = disabled.

Rsvd1 6 R 0h N/A (Hard-coded)

Reserved.

Tag 5:0 RW 00h POR - DAFG - ULR

Software programmable field returned in top six bits (31:26) of every Unsolicit-

ed Response generated by this node.

7.9.10. PortE (NID = 0Eh): ChSense

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 709h

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Get F0900h

Field Name Bits R/W Default Reset

PresDtct 31 R0h POR

Presence detection indicator: 1 = presence detected; 0 = presence not detect-

ed.

Rsvd 30:0 R00000000h N/A (Hard-coded)

Reserved.

7.9.11. PortE (NID = 0Eh): EAPDBTLLR

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 70Ch

Get F0C00h

Field Name Bits R/W Default Reset

Rsvd2 31:2 R00000000h N/A (Hard-coded)

Reserved.

EAPD 1RW 1h POR - DAFG - ULR

EAPD control: 1 = set EAPD pin to 1 (powered) up if this pin is powered up, 0

= set EAPD pin to 0.

Rsvd1 0 R 0h N/A (Hard-coded)

Reserved.

7.9.12. PortE (NID = 0Eh): ConfigDefault

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 71Fh 71Eh 71Dh 71Ch

Get F1F00h / F1E00h / F1D00h / F1C00h

7.9.10. PortE (NID = 0Eh): ChSense

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

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Field Name Bits R/W Default Reset

PortConnectivity 31:30 RW 0h POR

Port connectivity:

0h = Port complex is connected to a jack

1h = No physical connection for port

2h = Fixed function device is attached

3h = Both jack and internal device attached (info in all other fields refers to in-

tegrated device, any presence detection refers to jack)

Location 29:24 RW 01h POR

Location

Bits [5..4]:

0h = External on primary chassis

1h = Internal

2h = Separate chassis

3h = Other

Bits [3..0]:

0h = N/A

1h = Rear

2h = Front

3h = Left

4h = Right

5h = Top

6h = Bottom

7h-9h = Special

Ah-Fh = Reserved

Device 23:20 RW 0h POR

Default device:

0h = Line out

1h = Speaker

2h = HP out

3h = CD

4h = SPDIF Out

5h = Digital other out

6h = Modem line side

7h = Modem handset side

8h = Line in

9h = Aux

Ah = Mic in

Bh = Telephony

Ch = SPDIF In

Dh = Digital other in

Eh = Reserved

Fh = Other

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ConnectionType 19:16 RW 1h POR

Connection type:

0h = Unknown

1h = 1/8" stereo/mono

2h = 1/4" stereo/mono

3h = ATAPI internal

4h = RCA

5h = Optical

6h = Other digital

7h = Other analog

8h = Multichannel analog (DIN)

9h = XLR/Professional

Ah = RJ-11 (modem)

Bh = Combination

Ch-Eh = Reserved

Fh = Other

Color 15:12 RW 4h POR

Color:

0h = Unknown

1h = Black

2h = Grey

3h = Blue

4h = Green

5h = Red

6h = Orange

7h = Yellow

8h = Purple

9h = Pink

Ah-Dh = Reserved

Eh = White

Fh = Other

Misc 11:8 RW 0h POR

Miscellaneous:

Bits [3..1] = Reserved

Bit 0 = Jack detect override

Association 7:4 RW 5h POR

Default assocation.

Sequence 3:0 RW 0h POR

Sequence.

Field Name Bits R/W Default Reset

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7.10. PortF (NID = 0Fh): WCap

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set

Get F0009h

Field Name Bits R/W Default Reset

Rsvd2 31:24 R00h N/A (Hard-coded)

Reserved.

Type 23:20 R4h N/A (Hard-coded)

Widget type:

0h = Out Converter

1h = In Converter

2h = Summing (Mixer)

3h = Selector (Mux)

4h = Pin Complex

5h = Power

6h = Volume Knob

7h = Beep Generator

8h-Eh = Reserved

Fh = Vendor Defined

Delay 19:16 R0h N/A (Hard-coded)

Number of sample delays through widget.

Rsvd1 15:12 R0h N/A (Hard-coded)

Reserved.

SwapCap 11 R0h N/A (Hard-coded)

Left/right swap support: 1 = yes, 0 = no.

PwrCntrl 10 R1h N/A (Hard-coded)

Power state support: 1 = yes, 0 = no.

Dig 9 R 0h N/A (Hard-coded)

Digital stream support: 1 = yes (digital), 0 = no (analog).

ConnList 8 R 1h N/A (Hard-coded)

Connection list present: 1 = yes, 0 = no.

UnSolCap 7 R 1h N/A (Hard-coded)

Unsolicited response support: 1 = yes, 0 = no.

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ProcWidget 6 R 0h N/A (Hard-coded)

Processing state support: 1 = yes, 0 = no.

Stripe 5 R 0h N/A (Hard-coded)

Striping support: 1 = yes, 0 = no.

FormatOvrd 4 R 0h N/A (Hard-coded)

Stream format override: 1 = yes, 0 = no.

AmpParOvrd 3 R 0h N/A (Hard-coded)

Amplifier capabilities override: 1 = yes, no.

OutAmpPrsnt 2 R 0h N/A (Hard-coded)

Output amp present: 1 = yes, 0 = no.

InAmpPrsnt 1 R 1h N/A (Hard-coded)

Input amp present: 1 = yes, 0 = no.

Stereo 0 R 1h N/A (Hard-coded)

Stereo stream support: 1 = yes (stereo), 0 = no (mono).

7.10.1. PortF (NID = 0Fh): PinCap

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set

Get F000Ch

Field Name Bits R/W Default Reset

Rsvd2 31:17 R0000h N/A (Hard-coded)

Reserved.

EapdCap 16 R1h N/A (Hard-coded)

EAPD support: 1 = yes, 0 = no.

Field Name Bits R/W Default Reset

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VrefCntrl 15:8 R00h N/A (Hard-coded)

Vref support:

bit 7 = Reserved

bit 6 = Reserved

bit 5 = 100% support (1 = yes, 0 = no)

bit 4 = 80% support (1 = yes, 0 = no)

bit 3 = Reserved

bit 2 = GND support (1 = yes, 0 = no)

bit 1 = 50% support (1 = yes, 0 = no)

bit 0 = Hi-Z support (1 = yes, 0 = no)

Rsvd1 7 R 0h N/A (Hard-coded)

Reserved.

BalancedIO 6 R 0h N/A (Hard-coded)

Balanced I/O support: 1 = yes, 0 = no.

InCap 5 R 1h N/A (Hard-coded)

Input support: 1 = yes, 0 = no.

OutCap 4 R 0h N/A (Hard-coded)

Output support: 1 = yes, 0 = no.

HdphDrvCap 3 R 0h N/A (Hard-coded)

Headphone amp present: 1 = yes, 0 = no.

PresDtctCap 2 R 1h N/A (Hard-coded)

Presence detection support: 1 = yes, 0 = no.

TrigRqd 1 R 0h N/A (Hard-coded)

Trigger required for impedance sense: 1 = yes, 0 = no.

ImpSenseCap 0 R 0h N/A (Hard-coded)

Impedance sense support: 1 = yes, 0 = no.

7.10.2. PortF (NID = 0Fh): ConLst

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set

Get F000Eh

Field Name Bits R/W Default Reset

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Field Name Bits R/W Default Reset

Rsvd 31:8 R000000h N/A (Hard-coded)

Reserved.

LForm 7 R 0h N/A (Hard-coded)

Connection list format: 1 = long-form (15-bit) NID entries, 0 = short-form (7-bit)

NID entries.

ConL 6:0 R03h N/A (Hard-coded)

Number of NID entries in connection list.

7.10.3. PortF (NID = 0Fh): ConLstEntry0

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set

Get F0200h

Field Name Bits R/W Default Reset

ConL3 31:24 R00h N/A (Hard-coded)

Reserved

ConL2 23:16 R1Ch N/A (Hard-coded)

MixerOutVol Selector widget (0x1C)

ConL1 15:8 R14h N/A (Hard-coded)

DAC1 Converter widget (0x14)

ConL0 7:0 R13h N/A (Hard-coded)

DAC0 Converter widget (0x13)

7.10.4. PortF (NID = 0Fh): InAmpLeft

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 360h

Get B2000h

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Field Name Bits R/W Default Reset

Rsvd1 31:2 R00000000h N/A (Hard-coded)

Reserved.

Gain 1:0 RW 0h POR - DAFG - ULR

Amp gain step number (see InAmpCap parameter pertaining to this widget).

7.10.5. PortF (NID = 0Fh): InAmpRight

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 350h

Get B0000h

Field Name Bits R/W Default Reset

Rsvd1 31:2 R00000000h N/A (Hard-coded)

Reserved.

Gain 1:0 RW 0h POR - DAFG - ULR

Amp gain step number (see InAmpCap parameter pertaining to this widget).

7.10.6. PortF (NID = 0Fh): ConSelectCtrl

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 701h

Get F0100h

Field Name Bits R/W Default Reset

Rsvd 31:2 R00000000h N/A (Hard-coded)

Reserved.

Index 1:0 RW 0h POR - DAFG - ULR

Connection select control index.

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7.10.7. PortF (NID = 0Fh): PwrState

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 705h

Get F0500h

Field Name Bits R/W Default Reset

Rsvd4 31:11 R000000h N/A (Hard-coded)

Reserved.

SettingsReset 10 R1h POR - DAFG - ULR

Indicates if any persistent settings in this Widget have been reset. Cleared by

PwrState 'Get', or a 'Set' to any Verb in this Widget.

Rsvd3 9 R 0h N/A (Hard-coded)

Reserved.

Error 8 R 0h POR - DAFG - ULR

Error indicator: 1 = cannot enter requested power state, 0 = no problem with

requested power state.

Rsvd2 7:6 R0h N/A (Hard-coded)

Reserved.

Act 5:4 R3h POR - DAFG - LR

Actual power state of this widget.

Rsvd1 3:2 R0h N/A (Hard-coded)

Reserved.

Set 1:0 RW 0h POR - DAFG - LR

Current power state setting for this widget.

7.10.8. PortF (NID = 0Fh): PinWCntrl

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 707h

Get F0700h

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Field Name Bits R/W Default Reset

Rsvd2 31:7 R000000h N/A (Hard-coded)

Reserved.

OutEn 6RW 0h POR - DAFG - ULR

Output enable: 1 = enabled, 0 = disabled.

InEn 5RW 0h POR - DAFG - ULR

Input enable: 1 = enabled, 0 = disabled.

Rsvd1 4:3 R0h N/A (Hard-coded)

Reserved.

VRefEn 2:0 RW 0h POR - DAFG - ULR

Vref selection (See VrefCntrl field of PinCap parameter for supported selec-

tions):

000b= HI-Z

001b= 50%

010b= GND

011b= Reserved

100b= 80%

101b= 100%

110b= Reserved

111b= Reserved

7.10.9. PortF (NID = 0Fh): UnsolResp

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 708h

Get F0800h

Field Name Bits R/W Default Reset

Rsvd2 31:8 R000000h N/A (Hard-coded)

Reserved.

En 7RW 0h POR - DAFG - ULR

Unsolicited response enable (also enables Wake events for this Widget): 1 =

enabled, 0 = disabled.

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Rsvd1 6 R 0h N/A (Hard-coded)

Reserved.

Tag 5:0 RW 00h POR - DAFG - ULR

Software programmable field returned in top six bits (31:26) of every Unsolicit-

ed Response generated by this node.

7.10.10. PortF (NID = 0Fh): ChSense

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 709h

Get F0900h

Field Name Bits R/W Default Reset

PresDtct 31 R0h POR

Presence detection indicator: 1 = presence detected; 0 = presence not detect-

ed.

Rsvd 30:0 R00000000h N/A (Hard-coded)

Reserved.

7.10.11. PortF (NID = 0Fh): EAPDBTLLR

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 70Ch

Get F0C00h

Field Name Bits R/W Default Reset

Rsvd2 31:2 R00000000h N/A (Hard-coded)

Reserved.

EAPD 1RW 1h POR - DAFG - ULR

EAPD control: 1 = set EAPD pin to 1 (powered) up if this pin is powered up, 0

= set EAPD pin to 0.

Field Name Bits R/W Default Reset

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Rsvd1 0 R 0h N/A (Hard-coded)

Reserved.

7.10.12. PortF (NID = 0Fh): ConfigDefault

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 71Fh 71Eh 71Dh 71Ch

Get F1F00h / F1E00h / F1D00h / F1C00h

Field Name Bits R/W Default Reset

PortConnectivity 31:30 RW 0h POR

Port connectivity:

0h = Port complex is connected to a jack

1h = No physical connection for port

2h = Fixed function device is attached

3h = Both jack and internal device attached (info in all other fields refers to in-

tegrated device, any presence detection refers to jack)

Location 29:24 RW 01h POR

Location

Bits [5..4]:

0h = External on primary chassis

1h = Internal

2h = Separate chassis

3h = Other

Bits [3..0]:

0h = N/A

1h = Rear

2h = Front

3h = Left

4h = Right

5h = Top

6h = Bottom

7h-9h = Special

Ah-Fh = Reserved

Field Name Bits R/W Default Reset

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Device 23:20 RW 8h POR

Default device:

0h = Line out

1h = Speaker

2h = HP out

3h = CD

4h = SPDIF Out

5h = Digital other out

6h = Modem line side

7h = Modem handset side

8h = Line in

9h = Aux

Ah = Mic in

Bh = Telephony

Ch = SPDIF In

Dh = Digital other in

Eh = Reserved

Fh = Other

ConnectionType 19:16 RW 1h POR

Connection type:

0h = Unknown

1h = 1/8" stereo/mono

2h = 1/4" stereo/mono

3h = ATAPI internal

4h = RCA

5h = Optical

6h = Other digital

7h = Other analog

8h = Multichannel analog (DIN)

9h = XLR/Professional

Ah = RJ-11 (modem)

Bh = Combination

Ch-Eh = Reserved

Fh = Other

Field Name Bits R/W Default Reset

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Color 15:12 RW 3h POR

Color:

0h = Unknown

1h = Black

2h = Grey

3h = Blue

4h = Green

5h = Red

6h = Orange

7h = Yellow

8h = Purple

9h = Pink

Ah-Dh = Reserved

Eh = White

Fh = Other

Misc 11:8 RW 0h POR

Miscellaneous:

Bits [3..1] = Reserved

Bit 0 = Jack detect override

Association 7:4 RW 2h POR

Default assocation.

Sequence 3:0 RW Eh POR

Sequence.

Field Name Bits R/W Default Reset

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7.11. MonoOut (NID = 10h): WCap

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set

Get F0009h

Field Name Bits R/W Default Reset

Rsvd2 31:24 R00h N/A (Hard-coded)

Reserved.

Type 23:20 R4h N/A (Hard-coded)

Widget type:

0h = Out Converter

1h = In Converter

2h = Summing (Mixer)

3h = Selector (Mux)

4h = Pin Complex

5h = Power

6h = Volume Knob

7h = Beep Generator

8h-Eh = Reserved

Fh = Vendor Defined

Delay 19:16 R0h N/A (Hard-coded)

Number of sample delays through widget.

Rsvd1 15:12 R0h N/A (Hard-coded)

Reserved.

SwapCap 11 R0h N/A (Hard-coded)

Left/right swap support: 1 = yes, 0 = no.

PwrCntrl 10 R1h N/A (Hard-coded)

Power state support: 1 = yes, 0 = no.

Dig 9 R 0h N/A (Hard-coded)

Digital stream support: 1 = yes (digital), 0 = no (analog).

ConnList 8 R 1h N/A (Hard-coded)

Connection list present: 1 = yes, 0 = no.

UnSolCap 7 R 0h N/A (Hard-coded)

Unsolicited response support: 1 = yes, 0 = no.

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ProcWidget 6 R 0h N/A (Hard-coded)

Processing state support: 1 = yes, 0 = no.

Stripe 5 R 0h N/A (Hard-coded)

Striping support: 1 = yes, 0 = no.

FormatOvrd 4 R 0h N/A (Hard-coded)

Stream format override: 1 = yes, 0 = no.

AmpParOvrd 3 R 0h N/A (Hard-coded)

Amplifier capabilities override: 1 = yes, no.

OutAmpPrsnt 2 R 0h N/A (Hard-coded)

Output amp present: 1 = yes, 0 = no.

InAmpPrsnt 1 R 0h N/A (Hard-coded)

Input amp present: 1 = yes, 0 = no.

Stereo 0 R 0h N/A (Hard-coded)

Stereo stream support: 1 = yes (stereo), 0 = no (mono).

7.11.1. MonoOut (NID = 10h): PinCap

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set

Get F000Ch

Field Name Bits R/W Default Reset

Rsvd2 31:17 R0000h N/A (Hard-coded)

Reserved.

EapdCap 16 R0h N/A (Hard-coded)

EAPD support: 1 = yes, 0 = no.

Field Name Bits R/W Default Reset

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VrefCntrl 15:8 R00h N/A (Hard-coded)

Vref support:

bit 7 = Reserved

bit 6 = Reserved

bit 5 = 100% support (1 = yes, 0 = no)

bit 4 = 80% support (1 = yes, 0 = no)

bit 3 = Reserved

bit 2 = GND support (1 = yes, 0 = no)

bit 1 = 50% support (1 = yes, 0 = no)

bit 0 = Hi-Z support (1 = yes, 0 = no)

Rsvd1 7 R 0h N/A (Hard-coded)

Reserved.

BalancedIO 6 R 0h N/A (Hard-coded)

Balanced I/O support: 1 = yes, 0 = no.

InCap 5 R 0h N/A (Hard-coded)

Input support: 1 = yes, 0 = no.

OutCap 4 R 1h N/A (Hard-coded)

Output support: 1 = yes, 0 = no.

HdphDrvCap 3 R 0h N/A (Hard-coded)

Headphone amp present: 1 = yes, 0 = no.

PresDtctCap 2 R 0h N/A (Hard-coded)

Presence detection support: 1 = yes, 0 = no.

TrigRqd 1 R 0h N/A (Hard-coded)

Trigger required for impedance sense: 1 = yes, 0 = no.

ImpSenseCap 0 R 0h N/A (Hard-coded)

Impedance sense support: 1 = yes, 0 = no.

7.11.2. MonoOut (NID = 10h): ConLst

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set

Get F000Eh

Field Name Bits R/W Default Reset

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Field Name Bits R/W Default Reset

Rsvd 31:8 R000000h N/A (Hard-coded)

Reserved.

LForm 7 R 0h N/A (Hard-coded)

Connection list format: 1 = long-form (15-bit) NID entries, 0 = short-form (7-bit)

NID entries.

ConL 6:0 R01h N/A (Hard-coded)

Number of NID entries in connection list.

7.11.3. MonoOut (NID = 10h): ConLstEntry0

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set

Get F0200h

Field Name Bits R/W Default Reset

ConL3 31:24 R00h N/A (Hard-coded)

Unused list entry.

ConL2 23:16 R00h N/A (Hard-coded)

Unused list entry.

ConL1 15:8 R00h N/A (Hard-coded)

Unused list entry.

ConL0 7:0 R1Ah N/A (Hard-coded)

MonoMix Summing widget (0x1A)

7.11.4. MonoOut (NID = 10h): PwrState

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 705h

Get F0500h

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Field Name Bits R/W Default Reset

Rsvd4 31:11 R000000h N/A (Hard-coded)

Reserved.

SettingsReset 10 R1h POR - DAFG - ULR

Indicates if any persistent settings in this Widget have been reset. Cleared by

PwrState 'Get', or a 'Set' to any Verb in this Widget.

Rsvd3 9 R 0h N/A (Hard-coded)

Reserved.

Error 8 R 0h POR - DAFG - ULR

Error indicator: 1 = cannot enter requested power state, 0 = no problem with

requested power state.

Rsvd2 7:6 R0h N/A (Hard-coded)

Reserved.

Act 5:4 R3h POR - DAFG - LR

Actual power state of this widget.

Rsvd1 3:2 R0h N/A (Hard-coded)

Reserved.

Set 1:0 RW 0h POR - DAFG - LR

Current power state setting for this widget.

7.11.5. MonoOut (NID = 10h): PinWCntrl

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 707h

Get F0700h

Field Name Bits R/W Default Reset

Rsvd2 31:7 R000000h N/A (Hard-coded)

Reserved.

OutEn 6RW 0h POR - DAFG - ULR

Output enable: 1 = enabled, 0 = disabled.

TSI™ CONFIDENTIAL

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Rsvd1 5:0 R0h N/A (Hard-coded)

Reserved.

7.11.6. MonoOut (NID = 10h): ConfigDefault

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 71Fh 71Eh 71Dh 71Ch

Get F1F00h / F1E00h / F1D00h / F1C00h

Field Name Bits R/W Default Reset

PortConnectivity 31:30 RW 1h POR

Port connectivity:

0h = Port complex is connected to a jack

1h = No physical connection for port

2h = Fixed function device is attached

3h = Both jack and internal device attached (info in all other fields refers to in-

tegrated device, any presence detection refers to jack)

Location 29:24 RW 00h POR

Location

Bits [5..4]:

0h = External on primary chassis

1h = Internal

2h = Separate chassis

3h = Other

Bits [3..0]:

0h = N/A

1h = Rear

2h = Front

3h = Left

4h = Right

5h = Top

6h = Bottom

7h-9h = Special

Ah-Fh = Reserved

Field Name Bits R/W Default Reset

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Device 23:20 RW Fh POR

Default device:

0h = Line out

1h = Speaker

2h = HP out

3h = CD

4h = SPDIF Out

5h = Digital other out

6h = Modem line side

7h = Modem handset side

8h = Line in

9h = Aux

Ah = Mic in

Bh = Telephony

Ch = SPDIF In

Dh = Digital other in

Eh = Reserved

Fh = Other

ConnectionType 19:16 RW 0h POR

Connection type:

0h = Unknown

1h = 1/8" stereo/mono

2h = 1/4" stereo/mono

3h = ATAPI internal

4h = RCA

5h = Optical

6h = Other digital

7h = Other analog

8h = Multichannel analog (DIN)

9h = XLR/Professional

Ah = RJ-11 (modem)

Bh = Combination

Ch-Eh = Reserved

Fh = Other

Field Name Bits R/W Default Reset

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Color 15:12 RW 0h POR

Color:

0h = Unknown

1h = Black

2h = Grey

3h = Blue

4h = Green

5h = Red

6h = Orange

7h = Yellow

8h = Purple

9h = Pink

Ah-Dh = Reserved

Eh = White

Fh = Other

Misc 11:8 RW 0h POR

Miscellaneous:

Bits [3..1] = Reserved

Bit 0 = Jack detect override

Association 7:4 RW Fh POR

Default assocation.

Sequence 3:0 RW 0h POR

Sequence.

Field Name Bits R/W Default Reset

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7.12. DMic0 (NID = 11h): WCap

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set

Get F0009h

Field Name Bits R/W Default Reset

Rsvd2 31:24 R00h N/A (Hard-coded)

Reserved.

Type 23:20 R4h N/A (Hard-coded)

Widget type:

0h = Out Converter

1h = In Converter

2h = Summing (Mixer)

3h = Selector (Mux)

4h = Pin Complex

5h = Power

6h = Volume Knob

7h = Beep Generator

8h-Eh = Reserved

Fh = Vendor Defined

Delay 19:16 R0h N/A (Hard-coded)

Number of sample delays through widget.

Rsvd1 15:12 R0h N/A (Hard-coded)

Reserved.

SwapCap 11 R0h N/A (Hard-coded)

Left/right swap support: 1 = yes, 0 = no.

PwrCntrl 10 R1h N/A (Hard-coded)

Power state support: 1 = yes, 0 = no.

DigitalStrm 9 R 0h N/A (Hard-coded)

Digital stream support: 1 = yes (digital), 0 = no (analog).

ConnList 8 R 0h N/A (Hard-coded)

Connection list present: 1 = yes, 0 = no.

UnsolCap 7 R 1h N/A (Hard-coded)

Unsolicited response support: 1 = yes, 0 = no.

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ProcWidget 6 R 0h N/A (Hard-coded)

Processing state support: 1 = yes, 0 = no.

Stripe 5 R 0h N/A (Hard-coded)

Striping support: 1 = yes, 0 = no.

FormatOvrd 4 R 0h N/A (Hard-coded)

Stream format override: 1 = yes, 0 = no.

AmpParOvrd 3 R 0h N/A (Hard-coded)

Amplifier capabilities override: 1 = yes, no.

OutAmpPrsnt 2 R 0h N/A (Hard-coded)

Output amp present: 1 = yes, 0 = no.

InAmpPrsnt 1 R 1h N/A (Hard-coded)

Input amp present: 1 = yes, 0 = no.

Stereo 0 R 1h N/A (Hard-coded)

Stereo stream support: 1 = yes (stereo), 0 = no (mono).

7.12.1. DMic0 (NID = 11h): PinCap

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set

Get F000Ch

Field Name Bits R/W Default Reset

Rsvd2 31:17 R0000h N/A (Hard-coded)

Reserved.

EapdCap 16 R0h N/A (Hard-coded)

EAPD support: 1 = yes, 0 = no.

Field Name Bits R/W Default Reset

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VRefCntrl 15:8 R00h N/A (Hard-coded)

Vref support:

bit 7 = Reserved

bit 6 = Reserved

bit 5 = 100% support (1 = yes, 0 = no)

bit 4 = 80% support (1 = yes, 0 = no)

bit 3 = Reserved

bit 2 = GND support (1 = yes, 0 = no)

bit 1 = 50% support (1 = yes, 0 = no)

bit 0 = Hi-Z support (1 = yes, 0 = no)

Rsvd1 7 R 0h N/A (Hard-coded)

Reserved.

BalancedIO 6 R 0h N/A (Hard-coded)

Balanced I/O support: 1 = yes, 0 = no.

InCap 5 R 1h N/A (Hard-coded)

Input support: 1 = yes, 0 = no.

OutCap 4 R 0h N/A (Hard-coded)

Output support: 1 = yes, 0 = no.

HPhnDrvCap 3 R 0h N/A (Hard-coded)

Headphone amp present: 1 = yes, 0 = no.

PresDtctCap 2 R 1h N/A (Hard-coded)

Presence detection support: 1 = yes, 0 = no.

TrigRqd 1 R 0h N/A (Hard-coded)

Trigger required for impedance sense: 1 = yes, 0 = no.

ImpSenseCap 0 R 0h N/A (Hard-coded)

Impedance sense support: 1 = yes, 0 = no.

7.12.2. DMic0 (NID = 11h): InAmpLeft

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 360h

Get B2000h

Field Name Bits R/W Default Reset

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Field Name Bits R/W Default Reset

Rsvd1 31:2 R00000000h N/A (Hard-coded)

Reserved.

Gain 1:0 RW 0h POR - DAFG - ULR

Amp gain step number (see InAmpCap parameter pertaining to this widget).

7.12.3. DMic0 (NID = 11h): InAmpRight

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 350h

Get B0000h

Field Name Bits R/W Default Reset

Rsvd1 31:2 R00000000h N/A (Hard-coded)

Reserved.

Gain 1:0 RW 0h POR - DAFG - ULR

Amp gain step number (see InAmpCap parameter pertaining to this widget).

7.12.4. DMic0 (NID = 11h): PwrState

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 705h

Get F0500h

Field Name Bits R/W Default Reset

Rsvd4 31:11 R000000h N/A (Hard-coded)

Reserved.

SettingsReset 10 R1h POR - DAFG - ULR

Indicates if any persistent settings in this Widget have been reset. Cleared by

PwrState 'Get', or a 'Set' to any Verb in this Widget.

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Rsvd3 9 R 0h N/A (Hard-coded)

Reserved.

Error 8 R 0h POR - DAFG - ULR

Error indicator: 1 = cannot enter requested power state, 0 = no problem with

requested power state.

Rsvd2 7:6 R0h N/A (Hard-coded)

Reserved.

Act 5:4 R3h POR - DAFG - LR

Actual power state of this widget.

Rsvd1 3:2 R0h N/A (Hard-coded)

Reserved.

Set 1:0 RW 0h POR - DAFG - LR

Current power state setting for this widget.

7.12.5. DMic0 (NID = 11h): PinWCntrl

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 707h

Get F0700h

Field Name Bits R/W Default Reset

Rsvd2 31:6 R0000000h N/A (Hard-coded)

Reserved.

InEn 5RW 0h POR - DAFG - ULR

Input enable: 1 = enabled, 0 = disabled.

Rsvd1 4:0 R00h N/A (Hard-coded)

Reserved.

Field Name Bits R/W Default Reset

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7.12.6. DMic0 (NID = 11h): UnsolResp

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 708h

Get F0800h

Field Name Bits R/W Default Reset

Rsvd2 31:8 R000000h N/A (Hard-coded)

Reserved.

En 7RW 0h POR - DAFG - ULR

Unsolicited response enable (also enables Wake events for this Widget): 1 =

enabled, 0 = disabled.

Rsvd1 6 R 0h N/A (Hard-coded)

Reserved.

Tag 5:0 RW 00h POR - DAFG - ULR

Software programmable field returned in top six bits (31:26) of every Unsolicit-

ed Response generated by this node.

7.12.7. DMic0 (NID = 11h): ChSense

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 709h

Get F0900h

Field Name Bits R/W Default Reset

PresDtct 31 R0h POR

Presence detection indicator: 1 = presence detected; 0 = presence not detect-

ed.

Rsvd 30:0 R00000000h N/A (Hard-coded)

Reserved.

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7.12.8. DMic0 (NID = 11h): ConfigDefault

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 71Fh 71Eh 71Dh 71Ch

Get F1F00h / F1E00h / F1D00h / F1C00h

Field Name Bits R/W Default Reset

PortConnectivity 31:30 RW 2h POR

Port connectivity:

0h = Port complex is connected to a jack

1h = No physical connection for port

2h = Fixed function device is attached

3h = Both jack and internal device attached (info in all other fields refers to in-

tegrated device, any presence detection refers to jack)

Location 29:24 RW 10h POR

Location

Bits [5..4]:

0h = External on primary chassis

1h = Internal

2h = Separate chassis

3h = Other

Bits [3..0]:

0h = N/A

1h = Rear

2h = Front

3h = Left

4h = Right

5h = Top

6h = Bottom

7h-9h = Special

Ah-Fh = Reserved

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Device 23:20 RW Ah POR

Default device:

0h = Line out

1h = Speaker

2h = HP out

3h = CD

4h = SPDIF Out

5h = Digital other out

6h = Modem line side

7h = Modem handset side

8h = Line in

9h = Aux

Ah = Mic in

Bh = Telephony

Ch = SPDIF In

Dh = Digital other in

Eh = Reserved

Fh = Other

ConnectionType 19:16 RW 3h POR

Connection type:

0h = Unknown

1h = 1/8" stereo/mono

2h = 1/4" stereo/mono

3h = ATAPI internal

4h = RCA

5h = Optical

6h = Other digital

7h = Other analog

8h = Multichannel analog (DIN)

9h = XLR/Professional

Ah = RJ-11 (modem)

Bh = Combination

Ch-Eh = Reserved

Fh = Other

Field Name Bits R/W Default Reset

TSI™ CONFIDENTIAL

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Color 15:12 RW 0h POR

Color:

0h = Unknown

1h = Black

2h = Grey

3h = Blue

4h = Green

5h = Red

6h = Orange

7h = Yellow

8h = Purple

9h = Pink

Ah-Dh = Reserved

Eh = White

Fh = Other

Misc 11:8 RW 1h POR

Miscellaneous:

Bits [3..1] = Reserved

Bit 0 = Jack detect override

Association 7:4 RW 3h POR

Default assocation.

Sequence 3:0 RW 0h POR

Sequence.

Field Name Bits R/W Default Reset

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7.13. DMic1Vol (NID = 12h): WCap

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set

Get F0009h

Field Name Bits R/W Default Reset

Rsvd2 31:24 R00h N/A (Hard-coded)

Reserved.

Type 23:20 RFh N/A (Hard-coded)

Widget type:

0h = Out Converter

1h = In Converter

2h = Summing (Mixer)

3h = Selector (Mux)

4h = Pin Complex

5h = Power

6h = Volume Knob

7h = Beep Generator

8h-Eh = Reserved

Fh = Vendor Defined

Delay 19:16 R0h N/A (Hard-coded)

Number of sample delays through widget.

Rsvd1 15:12 R0h N/A (Hard-coded)

Reserved.

SwapCap 11 R0h N/A (Hard-coded)

Left/right swap support: 1 = yes, 0 = no.

PwrCntrl 10 R1h N/A (Hard-coded)

Power state support: 1 = yes, 0 = no.

DigitalStrm 9 R 0h N/A (Hard-coded)

Digital stream support: 1 = yes (digital), 0 = no (analog).

ConnList 8 R 1h N/A (Hard-coded)

Connection list present: 1 = yes, 0 = no.

UnsolCap 7 R 0h N/A (Hard-coded)

Unsolicited response support: 1 = yes, 0 = no.

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ProcWidget 6 R 0h N/A (Hard-coded)

Processing state support: 1 = yes, 0 = no.

Stripe 5 R 0h N/A (Hard-coded)

Striping support: 1 = yes, 0 = no.

FormatOvrd 4 R 0h N/A (Hard-coded)

Stream format override: 1 = yes, 0 = no.

AmpParOvrd 3 R 0h N/A (Hard-coded)

Amplifier capabilities override: 1 = yes, no.

OutAmpPrsnt 2 R 0h N/A (Hard-coded)

Output amp present: 1 = yes, 0 = no.

InAmpPrsnt 1 R 1h N/A (Hard-coded)

Input amp present: 1 = yes, 0 = no.

Stereo 0 R 1h N/A (Hard-coded)

Stereo stream support: 1 = yes (stereo), 0 = no (mono).

7.13.1. DMic1Vol (NID = 12h): ConLst

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set

Get F000Eh

Field Name Bits R/W Default Reset

Rsvd 31:8 R000000h N/A (Hard-coded)

Reserved.

LForm 7 R 0h N/A (Hard-coded)

Connection list format: 1 = long-form (15-bit) NID entries, 0 = short-form (7-bit)

NID entries.

ConL 6:0 R01h N/A (Hard-coded)

Number of NID entries in connection list.

Field Name Bits R/W Default Reset

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7.13.2. DMic1Vol (NID = 12h): ConLstEntry0

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set

Get F0200h

Field Name Bits R/W Default Reset

ConL3 31:24 R00h N/A (Hard-coded)

Unused list entry.

ConL2 23:16 R00h N/A (Hard-coded)

Unused list entry.

ConL1 15:8 R00h N/A (Hard-coded)

Unused list entry.

ConL0 7:0 R20h N/A (Hard-coded)

Dig1Pin Pin widget (0x20)

7.13.3. DMic1Vol (NID = 12h): InAmpLeft

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 360h

Get B2000h

Field Name Bits R/W Default Reset

Rsvd1 31:2 R00000000h N/A (Hard-coded)

Reserved.

Gain 1:0 RW 0h POR - DAFG - ULR

Amp gain step number (see InAmpCap parameter pertaining to this widget).

7.13.4. DMic1Vol (NID = 12h): InAmpRight

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 350h

Get B0000h

TSI™ CONFIDENTIAL

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Field Name Bits R/W Default Reset

Rsvd1 31:2 R00000000h N/A (Hard-coded)

Reserved.

Gain 1:0 RW 0h POR - DAFG - ULR

Amp gain step number (see InAmpCap parameter pertaining to this widget).

7.13.5. DMic1Vol (NID = 12h): PwrState

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 705h

Get F0500h

Field Name Bits R/W Default Reset

Rsvd4 31:11 R000000h N/A (Hard-coded)

Reserved.

SettingsReset 10 R1h POR - DAFG - ULR

Indicates if any persistent settings in this Widget have been reset. Cleared by

PwrState 'Get', or a 'Set' to any Verb in this Widget.

Rsvd3 9 R 0h N/A (Hard-coded)

Reserved.

Error 8 R 0h POR - DAFG - ULR

Error indicator: 1 = cannot enter requested power state, 0 = no problem with

requested power state.

Rsvd2 7:6 R0h N/A (Hard-coded)

Reserved.

Act 5:4 R3h POR - DAFG - LR

Actual power state of this widget.

Rsvd1 3:2 R0h N/A (Hard-coded)

Reserved.

Set 1:0 RW 0h POR - DAFG - LR

Current power state setting for this widget.

TSI™ CONFIDENTIAL

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7.14. DAC0 (NID = 13h): WCap

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set

Get F0009h

Field Name Bits R/W Default Reset

Rsvd2 31:24 R00h N/A (Hard-coded)

Reserved.

Type 23:20 R0h N/A (Hard-coded)

Widget type:

0h = Out Converter

1h = In Converter

2h = Summing (Mixer)

3h = Selector (Mux)

4h = Pin Complex

5h = Power

6h = Volume Knob

7h = Beep Generator

8h-Eh = Reserved

Fh = Vendor Defined

Delay 19:16 RDh N/A (Hard-coded)

Number of sample delays through widget.

Rsvd1 15:12 R0h N/A (Hard-coded)

Reserved.

SwapCap 11 R1h N/A (Hard-coded)

Left/right swap support: 1 = yes, 0 = no.

PwrCntrl 10 R1h N/A (Hard-coded)

Power state support: 1 = yes, 0 = no.

Dig 9 R 0h N/A (Hard-coded)

Digital stream support: 1 = yes (digital), 0 = no (analog).

ConnList 8 R 0h N/A (Hard-coded)

Connection list present: 1 = yes, 0 = no.

UnSolCap 7 R 0h N/A (Hard-coded)

Unsolicited response support: 1 = yes, 0 = no.

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ProcWidget 6 R 0h N/A (Hard-coded)

Processing state support: 1 = yes, 0 = no.

Stripe 5 R 0h N/A (Hard-coded)

Striping support: 1 = yes, 0 = no.

FormatOvrd 4 R 0h N/A (Hard-coded)

Stream format override: 1 = yes, 0 = no.

AmpParOvrd 3 R 0h N/A (Hard-coded)

Amplifier capabilities override: 1 = yes, no.

OutAmpPrsnt 2 R 1h N/A (Hard-coded)

Output amp present: 1 = yes, 0 = no.

InAmpPrsnt 1 R 0h N/A (Hard-coded)

Input amp present: 1 = yes, 0 = no.

Stereo 0 R 1h N/A (Hard-coded)

Stereo stream support: 1 = yes (stereo), 0 = no (mono).

7.14.1. DAC0 (NID = 13h): Cnvtr

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 2h

Get A0000h

Field Name Bits R/W Default Reset

Rsvd2 31:16 R0000h N/A (Hard-coded)

Reserved.

StrmType 15 R0h N/A (Hard-coded)

Stream type: 1 = Non-PCM, 0 = PCM.

FrmtSmplRate 14 RW 0h POR - DAFG - ULR

Sample base rate: 1 = 44.1kHz, 0 = 48kHz.

Field Name Bits R/W Default Reset

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SmplRateMultp 13:11 RW 0h POR - DAFG - ULR

Sample base rate multiple:

000b= x1 (48kHz/44.1kHz or less)

001b= x2 (96kHz/88.2kHz/32kHz)

010b= x3 (144kHz)

011b= x4 (192kHz/176.4kHz)

100b-111b Reserved

SmplRateDiv 10:8 RW 0h POR - DAFG - ULR

Sample base rate divider:

000b= Divide by 1 (48kHz/44.1kHz)

001b= Divide by 2 (24kHz/20.05kHz)

010b= Divide by 3 (16kHz/32kHz)

011b= Divide by 4 (11.025kHz)

100b= Divide by 5 (9.6kHz)

101b= Divide by 6 (8kHz)

110b= Divide by 7

111b= Divide by 8 (6kHz)

Rsvd1 7 R 0h N/A (Hard-coded)

Reserved.

BitsPerSmpl 6:4 RW 3h POR - DAFG - ULR

Bits per sample:

000b= 8 bits

001b= 16 bits

010b= 20 bits

011b= 24 bits

100b= 32 bits

101b-111b= Reserved

NmbrChan 3:0 RW 1h POR - DAFG - ULR

Total number of channels in the stream assigned to this converter:

0000b-1111b= 1-16 channels.

7.14.2. DAC0 (NID = 13h): OutAmpLeft

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 3A0h

Get BA000h

Field Name Bits R/W Default Reset

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Field Name Bits R/W Default Reset

Rsvd 31:8 R000000h N/A (Hard-coded)

Reserved.

Mute 7RW 1h POR - DAFG - ULR

Amp mute: 1 = muted, 0 = not muted.

Gain 6:0 RW 7Fh POR - DAFG - ULR

Amp gain step number (see OutAmpCap parameter pertaining to this widget).

7.14.3. DAC0 (NID = 13h): OutAmpRight

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 390h

Get B8000h

Field Name Bits R/W Default Reset

Rsvd 31:8 R000000h N/A (Hard-coded)

Reserved.

Mute 7RW 1h POR - DAFG - ULR

Amp mute: 1 = muted, 0 = not muted.

Gain 6:0 RW 7Fh POR - DAFG - ULR

Amp gain step number (see OutAmpCap parameter pertaining to this widget).

7.14.4. DAC0 (NID = 13h): PwrState

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 705h

Get F0500h

Field Name Bits R/W Default Reset

Rsvd4 31:11 R000000h N/A (Hard-coded)

Reserved.

TSI™ CONFIDENTIAL

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SettingsReset 10 R1h POR - DAFG - ULR

Indicates if any persistent settings in this Widget have been reset. Cleared by

PwrState 'Get', or a 'Set' to any Verb in this Widget.

Rsvd3 9 R 0h N/A (Hard-coded)

Reserved.

Error 8 R 0h POR - DAFG - ULR

Error indicator: 1 = cannot enter requested power state, 0 = no problem with

requested power state.

Rsvd2 7:6 R0h N/A (Hard-coded)

Reserved.

Act 5:4 R3h POR - DAFG - LR

Actual power state of this widget.

Rsvd1 3:2 R0h N/A (Hard-coded)

Reserved.

Set 1:0 RW 3h POR - DAFG - LR

Current power state setting for this widget.

7.14.5. DAC0 (NID = 13h): CnvtrID

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 706h

Get F0600h

Field Name Bits R/W Default Reset

Rsvd 31:8 R000000h N/A (Hard-coded)

Reserved.

Strm 7:4 RW 0h POR - S&DAFG - LR - PS

Stream ID: 0h = Converter "off", 1h-Fh = valid ID's.

Ch 3:0 RW 0h POR - S&DAFG - LR - PS

Channel assignment ("Ch" and "Ch+1" assigned as a pair, for a stereo convert-

er).

Field Name Bits R/W Default Reset

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7.14.6. DAC0 (NID = 13h): EAPDBTLLR

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 70Ch

Get F0C00h

Field Name Bits R/W Default Reset

Rsvd2 31:3 R00000000h N/A (Hard-coded)

Reserved.

SwapEn 2RW 0h POR - DAFG - ULR

Swap enable: 1 = L/R swap enabled, 0 = L/R swap disabled.

Rsvd1 1:0 R0h N/A (Hard-coded)

Reserved.

7.15. DAC1 (NID = 14h): WCap

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set

Get F0009h

Field Name Bits R/W Default Reset

Rsvd2 31:24 R00h N/A (Hard-coded)

Reserved.

Type 23:20 R0h N/A (Hard-coded)

Widget type:

0h = Out Converter

1h = In Converter

2h = Summing (Mixer)

3h = Selector (Mux)

4h = Pin Complex

5h = Power

6h = Volume Knob

7h = Beep Generator

8h-Eh = Reserved

Fh = Vendor Defined

TSI™ CONFIDENTIAL

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Delay 19:16 RDh N/A (Hard-coded)

Number of sample delays through widget.

Rsvd1 15:12 R0h N/A (Hard-coded)

Reserved.

SwapCap 11 R1h N/A (Hard-coded)

Left/right swap support: 1 = yes, 0 = no.

PwrCntrl 10 R1h N/A (Hard-coded)

Power state support: 1 = yes, 0 = no.

Dig 9 R 0h N/A (Hard-coded)

Digital stream support: 1 = yes (digital), 0 = no (analog).

ConnList 8 R 0h N/A (Hard-coded)

Connection list present: 1 = yes, 0 = no.

UnSolCap 7 R 0h N/A (Hard-coded)

Unsolicited response support: 1 = yes, 0 = no.

ProcWidget 6 R 0h N/A (Hard-coded)

Processing state support: 1 = yes, 0 = no.

Stripe 5 R 0h N/A (Hard-coded)

Striping support: 1 = yes, 0 = no.

FormatOvrd 4 R 0h N/A (Hard-coded)

Stream format override: 1 = yes, 0 = no.

AmpParOvrd 3 R 0h N/A (Hard-coded)

Amplifier capabilities override: 1 = yes, no.

OutAmpPrsnt 2 R 1h N/A (Hard-coded)

Output amp present: 1 = yes, 0 = no.

InAmpPrsnt 1 R 0h N/A (Hard-coded)

Input amp present: 1 = yes, 0 = no.

Stereo 0 R 1h N/A (Hard-coded)

Stereo stream support: 1 = yes (stereo), 0 = no (mono).

Field Name Bits R/W Default Reset

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7.15.1. DAC1 (NID = 14h): Cnvtr

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 2h

Get A0000h

Field Name Bits R/W Default Reset

Rsvd2 31:16 R0000h N/A (Hard-coded)

Reserved.

StrmType 15 R0h N/A (Hard-coded)

Stream type: 1 = Non-PCM, 0 = PCM.

FrmtSmplRate 14 RW 0h POR - DAFG - ULR

Sample base rate: 1 = 44.1kHz, 0 = 48kHz.

SmplRateMultp 13:11 RW 0h POR - DAFG - ULR

Sample base rate multiple:

000b= x1 (48kHz/44.1kHz or less)

001b= x2 (96kHz/88.2kHz/32kHz)

010b= x3 (144kHz)

011b= x4 (192kHz/176.4kHz)

100b-111b Reserved

SmplRateDiv 10:8 RW 0h POR - DAFG - ULR

Sample base rate divider:

000b= Divide by 1 (48kHz/44.1kHz)

001b= Divide by 2 (24kHz/20.05kHz)

010b= Divide by 3 (16kHz/32kHz)

011b= Divide by 4 (11.025kHz)

100b= Divide by 5 (9.6kHz)

101b= Divide by 6 (8kHz)

110b= Divide by 7

111b= Divide by 8 (6kHz)

Rsvd1 7 R 0h N/A (Hard-coded)

Reserved.

TSI™ CONFIDENTIAL

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BitsPerSmpl 6:4 RW 3h POR - DAFG - ULR

Bits per sample:

000b= 8 bits

001b= 16 bits

010b= 20 bits

011b= 24 bits

100b= 32 bits

101b-111b= Reserved

NmbrChan 3:0 RW 1h POR - DAFG - ULR

Total number of channels in the stream assigned to this converter:

0000b-1111b= 1-16 channels.

7.15.2. DAC1 (NID = 14h): OutAmpLeft

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 3A0h

Get BA000h

Field Name Bits R/W Default Reset

Rsvd 31:8 R000000h N/A (Hard-coded)

Reserved.

Mute 7RW 1h POR - DAFG - ULR

Amp mute: 1 = muted, 0 = not muted.

Gain 6:0 RW 7Fh POR - DAFG - ULR

Amp gain step number (see OutAmpCap parameter pertaining to this widget).

7.15.3. DAC1 (NID = 14h): OutAmpRight

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 390h

Get B8000h

Field Name Bits R/W Default Reset

TSI™ CONFIDENTIAL

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Field Name Bits R/W Default Reset

Rsvd 31:8 R000000h N/A (Hard-coded)

Reserved.

Mute 7RW 1h POR - DAFG - ULR

Amp mute: 1 = muted, 0 = not muted.

Gain 6:0 RW 7Fh POR - DAFG - ULR

Amp gain step number (see OutAmpCap parameter pertaining to this widget).

7.15.4. DAC1 (NID = 14h): PwrState

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 705h

Get F0500h

Field Name Bits R/W Default Reset

Rsvd4 31:11 R000000h N/A (Hard-coded)

Reserved.

SettingsReset 10 R1h POR - DAFG - ULR

Indicates if any persistent settings in this Widget have been reset. Cleared by

PwrState 'Get', or a 'Set' to any Verb in this Widget.

Rsvd3 9 R 0h N/A (Hard-coded)

Reserved.

Error 8 R 0h POR - DAFG - ULR

Error indicator: 1 = cannot enter requested power state, 0 = no problem with

requested power state.

Rsvd2 7:6 R0h N/A (Hard-coded)

Reserved.

Act 5:4 R3h POR - DAFG - LR

Actual power state of this widget.

Rsvd1 3:2 R0h N/A (Hard-coded)

Reserved.

TSI™ CONFIDENTIAL

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Set 1:0 RW 3h POR - DAFG - LR

Current power state setting for this widget.

7.15.5. DAC1 (NID = 14h): CnvtrID

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 706h

Get F0600h

Field Name Bits R/W Default Reset

Rsvd 31:8 R000000h N/A (Hard-coded)

Reserved.

Strm 7:4 RW 0h POR - S&DAFG - LR - PS

Stream ID: 0h = Converter "off", 1h-Fh = valid ID's.

Ch 3:0 RW 0h POR - S&DAFG - LR - PS

Channel assignment ("Ch" and "Ch+1" assigned as a pair, for a stereo convert-

er).

7.15.6. DAC1 (NID = 14h): EAPDBTLLR

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 70Ch

Get F0C00h

Field Name Bits R/W Default Reset

Rsvd2 31:3 R00000000h N/A (Hard-coded)

Reserved.

SwapEn 2RW 0h POR - DAFG - ULR

Swap enable: 1 = L/R swap enabled, 0 = L/R swap disabled.

Rsvd1 1:0 R0h N/A (Hard-coded)

Reserved.

Field Name Bits R/W Default Reset

TSI™ CONFIDENTIAL

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7.16. ADC0 (NID = 15h): WCap

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set

Get F0009h

Field Name Bits R/W Default Reset

Rsvd2 31:24 R00h N/A (Hard-coded)

Reserved.

Type 23:20 R1h N/A (Hard-coded)

Widget type:

0h = Out Converter

1h = In Converter

2h = Summing (Mixer)

3h = Selector (Mux)

4h = Pin Complex

5h = Power

6h = Volume Knob

7h = Beep Generator

8h-Eh = Reserved

Fh = Vendor Defined

Delay 19:16 RDh N/A (Hard-coded)

Number of sample delays through widget.

Rsvd1 15:12 R0h N/A (Hard-coded)

Reserved.

SwapCap 11 R0h N/A (Hard-coded)

Left/right swap support: 1 = yes, 0 = no.

PwrCntrl 10 R1h N/A (Hard-coded)

Power state support: 1 = yes, 0 = no.

Dig 9 R 0h N/A (Hard-coded)

Digital stream support: 1 = yes (digital), 0 = no (analog).

ConnList 8 R 1h N/A (Hard-coded)

Connection list present: 1 = yes, 0 = no.

UnSolCap 7 R 0h N/A (Hard-coded)

Unsolicited response support: 1 = yes, 0 = no.

TSI™ CONFIDENTIAL

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ProcWidget 6 R 1h N/A (Hard-coded)

Processing state support: 1 = yes, 0 = no.

Stripe 5 R 0h N/A (Hard-coded)

Striping support: 1 = yes, 0 = no.

FormatOvrd 4 R 0h N/A (Hard-coded)

Stream format override: 1 = yes, 0 = no.

AmpParOvrd 3 R 0h N/A (Hard-coded)

Amplifier capabilities override: 1 = yes, no.

OutAmpPrsnt 2 R 0h N/A (Hard-coded)

Output amp present: 1 = yes, 0 = no.

InAmpPrsnt 1 R 0h N/A (Hard-coded)

Input amp present: 1 = yes, 0 = no.

Stereo 0 R 1h N/A (Hard-coded)

Stereo stream support: 1 = yes (stereo), 0 = no (mono).

7.16.1. ADC0 (NID = 15h): ConLst

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set

Get F000Eh

Field Name Bits R/W Default Reset

Rsvd 31:8 R000000h N/A (Hard-coded)

Reserved.

LForm 7 R 0h N/A (Hard-coded)

Connection list format: 1 = long-form (15-bit) NID entries, 0 = short-form (7-bit)

NID entries.

ConL 6:0 R01h N/A (Hard-coded)

Number of NID entries in connection list.

Field Name Bits R/W Default Reset

TSI™ CONFIDENTIAL

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7.16.2. ADC0 (NID = 15h): ConLstEntry0

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set

Get F0200h

Field Name Bits R/W Default Reset

ConL3 31:24 R00h N/A (Hard-coded)

Unused list entry.

ConL2 23:16 R00h N/A (Hard-coded)

Unused list entry.

ConL1 15:8 R00h N/A (Hard-coded)

Unused list entry.

ConL0 7:0 R20h N/A (Hard-coded)

ADC0Mux Selector widget (0x17)

7.16.3. ADC0 (NID = 15h): Cnvtr

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 2h

Get A0000h

Field Name Bits R/W Default Reset

Rsvd2 31:16 R0000h N/A (Hard-coded)

Reserved.

StrmType 15 R0h N/A (Hard-coded)

Stream type: 1 = Non-PCM, 0 = PCM.

FrmtSmplRate 14 RW 0h POR - DAFG - ULR

Sample base rate: 1 = 44.1kHz, 0 = 48kHz.

TSI™ CONFIDENTIAL

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SmplRateMultp 13:11 RW 0h POR - DAFG - ULR

Sample base rate multiple:

000b= x1 (48kHz/44.1kHz or less)

001b= x2 (96kHz/88.2kHz/32kHz)

010b= x3 (144kHz)

011b= x4 (192kHz/176.4kHz)

100b-111b Reserved

SmplRateDiv 10:8 RW 0h POR - DAFG - ULR

Sample base rate divider:

000b= Divide by 1 (48kHz/44.1kHz)

001b= Divide by 2 (24kHz/20.05kHz)

010b= Divide by 3 (16kHz/32kHz)

011b= Divide by 4 (11.025kHz)

100b= Divide by 5 (9.6kHz)

101b= Divide by 6 (8kHz)

110b= Divide by 7

111b= Divide by 8 (6kHz)

Rsvd1 7 R 0h N/A (Hard-coded)

Reserved.

BitsPerSmpl 6:4 RW 3h POR - DAFG - ULR

Bits per sample:

000b= 8 bits

001b= 16 bits

010b= 20 bits

011b= 24 bits

100b= 32 bits

101b-111b= Reserved

NmbrChan 3:0 RW 1h POR - DAFG - ULR

Total number of channels in the stream assigned to this converter:

0000b-1111b= 1-16 channels.

7.16.4. ADC0 (NID = 15h): ProcState

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 703h

Get F0300h

Field Name Bits R/W Default Reset

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Field Name Bits R/W Default Reset

Rsvd2 31:8 R000000h N/A (Hard-coded)

Reserved.

HPFOCDIS 7RW 0h POR - DAFG - ULR

HPF offset calculation disable. 1 = calculation disabled; 0 = calculation en-

abled.

Rsvd1 6:2 R00h N/A (Hard-coded)

Reserved.

ADCHPFByp 1:0 RW 1h POR - DAFG - ULR

Processing State: 00b= bypass the ADC HPF ("off"), 01b-11b= ADC HPF is en-

abled ("on" or "benign").

7.16.5. ADC0 (NID = 15h): PwrState

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 705h

Get F0500h

Field Name Bits R/W Default Reset

Rsvd4 31:11 R000000h N/A (Hard-coded)

Reserved.

SettingsReset 10 R1h POR - DAFG - ULR

Indicates if any persistent settings in this Widget have been reset. Cleared by

PwrState 'Get', or a 'Set' to any Verb in this Widget.

Rsvd3 9 R 0h N/A (Hard-coded)

Reserved.

Error 8 R 0h POR - DAFG - ULR

Error indicator: 1 = cannot enter requested power state, 0 = no problem with

requested power state.

Rsvd2 7:6 R0h N/A (Hard-coded)

Reserved.

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Act 5:4 R3h POR - DAFG - LR

Actual power state of this widget.

Rsvd1 3:2 R0h N/A (Hard-coded)

Reserved.

Set 1:0 RW 3h POR - DAFG - LR

Current power state setting for this widget.

7.16.6. ADC0 (NID = 15h): CnvtrID

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 706h

Get F0600h

Field Name Bits R/W Default Reset

Rsvd 31:8 R000000h N/A (Hard-coded)

Reserved.

Strm 7:4 RW 0h POR - S&DAFG - LR - PS

Stream ID: 0h = Converter "off", 1h-Fh = valid ID's.

Ch 3:0 RW 0h POR - S&DAFG - LR - PS

Channel assignment ("Ch" and "Ch+1" assigned as a pair, for a stereo convert-

er).

7.17. ADC1 (NID = 1Bh): WCap

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set

Get F0009h

Field Name Bits R/W Default Reset

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Field Name Bits R/W Default Reset

Rsvd2 31:24 R00h N/A (Hard-coded)

Reserved.

Type 23:20 R1h N/A (Hard-coded)

Widget type:

0h = Out Converter

1h = In Converter

2h = Summing (Mixer)

3h = Selector (Mux)

4h = Pin Complex

5h = Power

6h = Volume Knob

7h = Beep Generator

8h-Eh = Reserved

Fh = Vendor Defined

Delay 19:16 RDh N/A (Hard-coded)

Number of sample delays through widget.

Rsvd1 15:12 R0h N/A (Hard-coded)

Reserved.

SwapCap 11 R0h N/A (Hard-coded)

Left/right swap support: 1 = yes, 0 = no.

PwrCntrl 10 R1h N/A (Hard-coded)

Power state support: 1 = yes, 0 = no.

Dig 9 R 0h N/A (Hard-coded)

Digital stream support: 1 = yes (digital), 0 = no (analog).

ConnList 8 R 1h N/A (Hard-coded)

Connection list present: 1 = yes, 0 = no.

UnSolCap 7 R 0h N/A (Hard-coded)

Unsolicited response support: 1 = yes, 0 = no.

ProcWidget 6 R 1h N/A (Hard-coded)

Processing state support: 1 = yes, 0 = no.

Stripe 5 R 0h N/A (Hard-coded)

Striping support: 1 = yes, 0 = no.

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FormatOvrd 4 R 0h N/A (Hard-coded)

Stream format override: 1 = yes, 0 = no.

AmpParOvrd 3 R 0h N/A (Hard-coded)

Amplifier capabilities override: 1 = yes, no.

OutAmpPrsnt 2 R 0h N/A (Hard-coded)

Output amp present: 1 = yes, 0 = no.

InAmpPrsnt 1 R 0h N/A (Hard-coded)

Input amp present: 1 = yes, 0 = no.

Stereo 0 R 1h N/A (Hard-coded)

Stereo stream support: 1 = yes (stereo), 0 = no (mono).

7.17.1. ADC1 (NID = 1Bh): ConLst

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set

Get F000Eh

Field Name Bits R/W Default Reset

Rsvd 31:8 R000000h N/A (Hard-coded)

Reserved.

LForm 7 R 0h N/A (Hard-coded)

Connection list format: 1 = long-form (15-bit) NID entries, 0 = short-form (7-bit)

NID entries.

ConL 6:0 R01h N/A (Hard-coded)

Number of NID entries in connection list.

7.17.2. ADC1 (NID = 1Bh): ConLstEntry0

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set

Get F0200h

Field Name Bits R/W Default Reset

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Field Name Bits R/W Default Reset

ConL3 31:24 R00h N/A (Hard-coded)

Unused list entry.

ConL2 23:16 R00h N/A (Hard-coded)

Unused list entry.

ConL1 15:8 R00h N/A (Hard-coded)

Unused list entry.

ConL0 7:0 R18h N/A (Hard-coded)

ADC1Mux widget (0x18)

7.17.3. ADC1 (NID = 1Bh): Cnvtr

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 2h

Get A0000h

Field Name Bits R/W Default Reset

Rsvd2 31:16 R0000h N/A (Hard-coded)

Reserved.

StrmType 15 R0h N/A (Hard-coded)

Stream type: 1 = Non-PCM, 0 = PCM.

FrmtSmplRate 14 RW 0h POR - DAFG - ULR

Sample base rate: 1 = 44.1kHz, 0 = 48kHz.

SmplRateMultp 13:11 RW 0h POR - DAFG - ULR

Sample base rate multiple:

000b= x1 (48kHz/44.1kHz or less)

001b= x2 (96kHz/88.2kHz/32kHz)

010b= x3 (144kHz)

011b= x4 (192kHz/176.4kHz)

100b-111b Reserved

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SmplRateDiv 10:8 RW 0h POR - DAFG - ULR

Sample base rate divider:

000b= Divide by 1 (48kHz/44.1kHz)

001b= Divide by 2 (24kHz/20.05kHz)

010b= Divide by 3 (16kHz/32kHz)

011b= Divide by 4 (11.025kHz)

100b= Divide by 5 (9.6kHz)

101b= Divide by 6 (8kHz)

110b= Divide by 7

111b= Divide by 8 (6kHz)

Rsvd1 7 R 0h N/A (Hard-coded)

Reserved.

BitsPerSmpl 6:4 RW 3h POR - DAFG - ULR

Bits per sample:

000b= 8 bits

001b= 16 bits

010b= 20 bits

011b= 24 bits

100b= 32 bits

101b-111b= Reserved

NmbrChan 3:0 RW 1h POR - DAFG - ULR

Total number of channels in the stream assigned to this converter:

0000b-1111b= 1-16 channels.

7.17.4. ADC1 (NID = 1Bh): ProcState

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 703h

Get F0300h

Field Name Bits R/W Default Reset

Rsvd2 31:8 R000000h N/A (Hard-coded)

Reserved.

HPFOCDIS 7RW 0h POR - DAFG - ULR

HPF offset calculation disable. 1 = calculation disabled; 0 = calculation en-

abled.

Field Name Bits R/W Default Reset

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Rsvd1 6:2 R00h N/A (Hard-coded)

Reserved.

ADCHPFByp 1:0 RW 1h POR - DAFG - ULR

Processing State: 00b= bypass the ADC HPF ("off"), 01b-11b= ADC HPF is en-

abled ("on" or "benign").

7.17.5. ADC1 (NID = 1Bh): PwrState

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 705h

Get F0500h

Field Name Bits R/W Default Reset

Rsvd4 31:11 R000000h N/A (Hard-coded)

Reserved.

SettingsReset 10 R1h POR - DAFG - ULR

Indicates if any persistent settings in this Widget have been reset. Cleared by

PwrState 'Get', or a 'Set' to any Verb in this Widget.

Rsvd3 9 R 0h N/A (Hard-coded)

Reserved.

Error 8 R 0h POR - DAFG - ULR

Error indicator: 1 = cannot enter requested power state, 0 = no problem with

requested power state.

Rsvd2 7:6 R0h N/A (Hard-coded)

Reserved.

Act 5:4 R3h POR - DAFG - LR

Actual power state of this widget.

Rsvd1 3:2 R0h N/A (Hard-coded)

Reserved.

Set 1:0 RW 3h POR - DAFG - LR

Current power state setting for this widget.

Field Name Bits R/W Default Reset

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7.17.6. ADC1 (NID = 1Bh): CnvtrID

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 706h

Get F0600h

Field Name Bits R/W Default Reset

Rsvd 31:8 R000000h N/A (Hard-coded)

Reserved.

Strm 7:4 RW 0h POR - S&DAFG - LR - PS

Stream ID: 0h = Converter "off", 1h-Fh = valid ID's.

Ch 3:0 RW 0h POR - S&DAFG - LR - PS

Channel assignment ("Ch" and "Ch+1" assigned as a pair, for a stereo convert-

er).

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7.18. ADC0Mux (NID = 17h): WCap

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set

Get F0009h

Field Name Bits R/W Default Reset

Rsvd2 31:24 R00h N/A (Hard-coded)

Reserved.

Type 23:20 R3h N/A (Hard-coded)

Widget type:

0h = Out Converter

1h = In Converter

2h = Summing (Mixer)

3h = Selector (Mux)

4h = Pin Complex

5h = Power

6h = Volume Knob

7h = Beep Generator

8h-Eh = Reserved

Fh = Vendor Defined

Delay 19:16 R0h N/A (Hard-coded)

Number of sample delays through widget.

Rsvd1 15:12 R0h N/A (Hard-coded)

Reserved.

SwapCap 11 R1h N/A (Hard-coded)

Left/right swap support: 1 = yes, 0 = no.

PwrCntrl 10 R1h N/A (Hard-coded)

Power state support: 1 = yes, 0 = no.

DigitalStrm 9 R 0h N/A (Hard-coded)

Digital stream support: 1 = yes (digital), 0 = no (analog).

ConnList 8 R 1h N/A (Hard-coded)

Connection list present: 1 = yes, 0 = no.

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UnsolCap 7 R 0h N/A (Hard-coded)

Unsolicited response support: 1 = yes, 0 = no.

ProcWidget 6 R 0h N/A (Hard-coded)

Processing state support: 1 = yes, 0 = no.

Stripe 5 R 0h N/A (Hard-coded)

Striping support: 1 = yes, 0 = no.

FormatOvrd 4 R 0h N/A (Hard-coded)

Stream format override: 1 = yes, 0 = no.

AmpParamOvrd 3 R 1h N/A (Hard-coded)

Amplifier capabilities override: 1 = yes, no.

OutAmpPrsnt 2 R 1h N/A (Hard-coded)

Output amp present: 1 = yes, 0 = no.

InAmpPrsnt 1 R 0h N/A (Hard-coded)

Input amp present: 1 = yes, 0 = no.

Stereo 0 R 1h N/A (Hard-coded)

Stereo stream support: 1 = yes (stereo), 0 = no (mono).

7.18.1. ADC0Mux (NID = 17h): ConLst

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set

Get F000Eh

Field Name Bits R/W Default Reset

Rsvd 31:8 R000000h N/A (Hard-coded)

Reserved.

Field Name Bits R/W Default Reset

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LForm 7 R 0h N/A (Hard-coded)

Connection list format: 1 = long-form (15-bit) NID entries, 0 = short-form (7-bit)

NID entries.

ConL 6:0 R07‘h N/A (Hard-coded)

Number of NID entries in connection list.

7.18.2. ADC0Mux (NID = 17h): ConLstEntry4

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set

Get F0204h

Field Name Bits R/W Default Reset

ConL7 31:24 R00h N/A (Hard-coded)

Unused list entry.

ConL6 23:16 R12h N/A (Hard-coded)

DMIC1 widget (0x12)

ConL5 15:8 R11h N/A (Hard-coded)

DMIC0 widget (0x11)

ConL4 7:0 R0Fh N/A (Hard-coded)

Port F widget (0x0F)

7.18.3. ADC0Mux (NID = 17h): ConLstEntry0

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set

Get F0200h

Field Name Bits R/W Default Reset

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Field Name Bits R/W Default Reset

ConL3 31:24 R0Eh N/A (Hard-coded)

Port E Pin widget (0x0E)

ConL2 23:16 R0Ch N/A (Hard-coded)

Port C Pin widget (0x0C)

ConL1 15:8 R0Ah N/A (Hard-coded)

Port A Pin widget (0x0A)

ConL0 7:0 R1Bh N/A (Hard-coded)

Mixer Summing widget (0x1B)

7.18.4. ADC0Mux (NID = 17h): OutAmpCap

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set

Get F0012h

Field Name Bits R/W Default Reset

Mute 31 R1h N/A (Hard-coded)

Mute support: 1 = yes, 0 = no.

Rsvd3 30:23 R00h N/A (Hard-coded)

Reserved.

StepSize 22:16 R03h N/A (Hard-coded)

Size of each step in the gain range: 0 to 127 = .25dB to 32dB, in .25dB steps.

Rsvd2 15 R0h N/A (Hard-coded)

Reserved.

NumSteps 14:8 R2Eh N/A (Hard-coded)

Number of gains steps (number of possible settings - 1).

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Rsvd1 7 R 0h N/A (Hard-coded)

Reserved.

Offset 6:0 R10h N/A (Hard-coded)

Indicates which step is 0dB

7.18.5. ADC0Mux (NID = 17h): OutAmpLeft

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 3A0h

Get BA000h

Field Name Bits R/W Default Reset

Rsvd2 31:8 R000000h N/A (Hard-coded)

Reserved.

Mute 7RW 1h POR - DAFG - ULR

Amp mute: 1 = muted, 0 = not muted.

Rsvd1 6 R 0h N/A (Hard-coded)

Reserved.

Gain 5:0 RW 10h POR - DAFG - ULR

Amp gain step number (see OutAmpCap parameter pertaining to this widget).

7.18.6. ADC0Mux (NID = 17h): OutAmpRight

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 390h

Get B8000h

Field Name Bits R/W Default Reset

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Field Name Bits R/W Default Reset

Rsvd2 31:8 R000000h N/A (Hard-coded)

Reserved.

Mute 7RW 1h POR - DAFG - ULR

Amp mute: 1 = muted, 0 = not muted.

Rsvd1 6 R 0h N/A (Hard-coded)

Reserved.

Gain 5:0 RW 10h POR - DAFG - ULR

Amp gain step number (see OutAmpCap parameter pertaining to this widget).

7.18.7. ADC0Mux (NID = 17h): ConSelectCtrl

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 701h

Get F0100h

Field Name Bits R/W Default Reset

Rsvd 31:3 R00000000h N/A (Hard-coded)

Reserved.

Index 2:0 RW 0h POR - DAFG - ULR

Connection select control index.

7.18.8. ADC0Mux (NID = 17h): PwrState

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 705h

Get F0500h

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Field Name Bits R/W Default Reset

Rsvd4 31:11 R000000h N/A (Hard-coded)

Reserved.

SettingsReset 10 R1h POR - DAFG - ULR

Indicates if any persistent settings in this Widget have been reset. Cleared by

PwrState 'Get', or a 'Set' to any Verb in this Widget.

Rsvd3 9 R 0h N/A (Hard-coded)

Reserved.

Error 8 R 0h POR - DAFG - ULR

Error indicator: 1 = cannot enter requested power state, 0 = no problem with

requested power state.

Rsvd2 7:6 R0h N/A (Hard-coded)

Reserved.

Act 5:4 R3h POR - DAFG - LR

Actual power state of this widget.

Rsvd1 3:2 R0h N/A (Hard-coded)

Reserved.

Set 1:0 RW 0h POR - DAFG - LR

Current power state setting for this widget.

7.18.9. ADC0Mux (NID = 17h): EAPDBTLLR

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 70Ch

Get F0C00h

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Field Name Bits R/W Default Reset

Rsvd2 31:3 R00000000h N/A (Hard-coded)

Reserved.

SwapEn 2RW 0h POR - DAFG - ULR

Swap enable: 1 = L/R swap enabled, 0 = L/R swap disabled.

Rsvd1 1:0 R0h N/A (Hard-coded)

Reserved.

7.19. ADC1Mux (NID = 18h): WCap

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set

Get F0009h

Field Name Bits R/W Default Reset

Rsvd2 31:24 R00h N/A (Hard-coded)

Reserved.

Type 23:20 R3h N/A (Hard-coded)

Widget type:

0h = Out Converter

1h = In Converter

2h = Summing (Mixer)

3h = Selector (Mux)

4h = Pin Complex

5h = Power

6h = Volume Knob

7h = Beep Generator

8h-Eh = Reserved

Fh = Vendor Defined

Delay 19:16 R0h N/A (Hard-coded)

Number of sample delays through widget.

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Rsvd1 15:12 R0h N/A (Hard-coded)

Reserved.

SwapCap 11 R1h N/A (Hard-coded)

Left/right swap support: 1 = yes, 0 = no.

PwrCntrl 10 R1h N/A (Hard-coded)

Power state support: 1 = yes, 0 = no.

DigitalStrm 9 R 0h N/A (Hard-coded)

Digital stream support: 1 = yes (digital), 0 = no (analog).

ConnList 8 R 1h N/A (Hard-coded)

Connection list present: 1 = yes, 0 = no.

UnsolCap 7 R 0h N/A (Hard-coded)

Unsolicited response support: 1 = yes, 0 = no.

ProcWidget 6 R 0h N/A (Hard-coded)

Processing state support: 1 = yes, 0 = no.

Stripe 5 R 0h N/A (Hard-coded)

Striping support: 1 = yes, 0 = no.

FormatOvrd 4 R 0h N/A (Hard-coded)

Stream format override: 1 = yes, 0 = no.

AmpParamOvrd 3 R 1h N/A (Hard-coded)

Amplifier capabilities override: 1 = yes, no.

OutAmpPrsnt 2 R 1h N/A (Hard-coded)

Output amp present: 1 = yes, 0 = no.

InAmpPrsnt 1 R 0h N/A (Hard-coded)

Input amp present: 1 = yes, 0 = no.

Stereo 0 R 1h N/A (Hard-coded)

Stereo stream support: 1 = yes (stereo), 0 = no (mono).

Field Name Bits R/W Default Reset

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7.19.1. ADC1Mux (NID = 18h): ConLst

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set

Get F000Eh

Field Name Bits R/W Default Reset

Rsvd 31:8 R000000h N/A (Hard-coded)

Reserved.

LForm 7 R 0h N/A (Hard-coded)

Connection list format: 1 = long-form (15-bit) NID entries, 0 = short-form (7-bit)

NID entries.

ConL 6:0 R07h N/A (Hard-coded)

Number of NID entries in connection list.

7.19.2. ADC1Mux (NID = 18h): ConLstEntry4

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set

Get F0204h

Field Name Bits R/W Default Reset

ConL7 31:24 R00h N/A (Hard-coded)

Unused list entry.

ConL6 23:16 R12h N/A (Hard-coded)

DMIC1 widget (0x12h)

ConL5 15:8 R11h N/A (Hard-coded)

DMIC0 widget (0x11)

ConL4 7:0 R0Fh N/A (Hard-coded)

Port F Pin widget (0x0F)

TSI™ CONFIDENTIAL

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7.19.3. ADC1Mux (NID = 18h): ConLstEntry0

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set

Get F0200h

Field Name Bits R/W Default Reset

ConL3 31:24 R1Eh N/A (Hard-coded)

Port E Pin widget (0x1E)

ConL2 23:16 R0Ch N/A (Hard-coded)

Port C Pin widget (0x10)

ConL1 15:8 R0Ah N/A (Hard-coded)

Port A Pin widget (0x0A)

ConL0 7:0 R1Bh N/A (Hard-coded)

Mixer Summing widget (0x1B)

7.19.4. ADC1Mux (NID = 18h): OutAmpCap

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set

Get F0012h

Field Name Bits R/W Default Reset

Mute 31 R1h N/A (Hard-coded)

Mute support: 1 = yes, 0 = no.

Rsvd3 30:23 R00h N/A (Hard-coded)

Reserved.

StepSize 22:16 R03h N/A (Hard-coded)

Size of each step in the gain range: 0 to 127 = .25dB to 32dB, in .25dB steps.

Rsvd2 15 R0h N/A (Hard-coded)

Reserved.

TSI™ CONFIDENTIAL

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NumSteps 14:8 R2Eh N/A (Hard-coded)

Number of gains steps (number of possible settings - 1).

Rsvd1 7 R 0h N/A (Hard-coded)

Reserved.

Offset 6:0 R10h N/A (Hard-coded)

Indicates which step is 0dB

7.19.5. ADC1Mux (NID = 18h): OutAmpLeft

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 3A0h

Get BA000h

Field Name Bits R/W Default Reset

Rsvd2 31:8 R000000h N/A (Hard-coded)

Reserved.

Mute 7RW 1h POR - DAFG - ULR

Amp mute: 1 = muted, 0 = not muted.

Rsvd1 6 R 0h N/A (Hard-coded)

Reserved.

Gain 5:0 RW 10h POR - DAFG - ULR

Amp gain step number (see OutAmpCap parameter pertaining to this widget).

7.19.6. ADC1Mux (NID = 18h): OutAmpRight

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 390h

Get B8000h

Field Name Bits R/W Default Reset

TSI™ CONFIDENTIAL

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SINGLE CHIP PC AUDIO SYSTEM,CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO

Field Name Bits R/W Default Reset

Rsvd2 31:8 R000000h N/A (Hard-coded)

Reserved.

Mute 7RW 1h POR - DAFG - ULR

Amp mute: 1 = muted, 0 = not muted.

Rsvd1 6 R 0h N/A (Hard-coded)

Reserved.

Gain 5:0 RW 10h POR - DAFG - ULR

Amp gain step number (see OutAmpCap parameter pertaining to this widget).

7.19.7. ADC1Mux (NID = 18h): ConSelectCtrl

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 701h

Get F0100h

Field Name Bits R/W Default Reset

Rsvd 31:3 R00000000h N/A (Hard-coded)

Reserved.

Index 2:0 RW 0h POR - DAFG - ULR

Connection select control index.

7.19.8. ADC1Mux (NID = 18h): PwrState

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 705h

Get F0500h

Field Name Bits R/W Default Reset

Rsvd4 31:11 R000000h N/A (Hard-coded)

Reserved.

TSI™ CONFIDENTIAL

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SettingsReset 10 R1h POR - DAFG - ULR

Indicates if any persistent settings in this Widget have been reset. Cleared by

PwrState 'Get', or a 'Set' to any Verb in this Widget.

Rsvd3 9 R 0h N/A (Hard-coded)

Reserved.

Error 8 R 0h POR - DAFG - ULR

Error indicator: 1 = cannot enter requested power state, 0 = no problem with

requested power state.

Rsvd2 7:6 R0h N/A (Hard-coded)

Reserved.

Act 5:4 R3h POR - DAFG - LR

Actual power state of this widget.

Rsvd1 3:2 R0h N/A (Hard-coded)

Reserved.

Set 1:0 RW 0h POR - DAFG - LR

Current power state setting for this widget.

7.19.9. ADC1Mux (NID = 18h): EAPDBTLLR

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 70Ch

Get F0C00h

Field Name Bits R/W Default Reset

Rsvd2 31:3 R00000000h N/A (Hard-coded)

Reserved.

SwapEn 2RW 0h POR - DAFG - ULR

Swap enable: 1 = L/R swap enabled, 0 = L/R swap disabled.

Rsvd1 1:0 R0h N/A (Hard-coded)

Reserved.

Field Name Bits R/W Default Reset

TSI™ CONFIDENTIAL

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7.20. MonoMux (NID = 19h): WCap

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set

Get F0009h

Field Name Bits R/W Default Reset

Rsvd2 31:24 R00h N/A (Hard-coded)

Reserved.

Type 23:20 R3h N/A (Hard-coded)

Widget type:

0h = Out Converter

1h = In Converter

2h = Summing (Mixer)

3h = Selector (Mux)

4h = Pin Complex

5h = Power

6h = Volume Knob

7h = Beep Generator

8h-Eh = Reserved

Fh = Vendor Defined

Delay 19:16 R0h N/A (Hard-coded)

Number of sample delays through widget.

Rsvd1 15:12 R0h N/A (Hard-coded)

Reserved.

SwapCap 11 R0h N/A (Hard-coded)

Left/right swap support: 1 = yes, 0 = no.

PwrCntrl 10 R1h N/A (Hard-coded)

Power state support: 1 = yes, 0 = no.

Dig 9 R 0h N/A (Hard-coded)

Digital stream support: 1 = yes (digital), 0 = no (analog).

ConnList 8 R 1h N/A (Hard-coded)

Connection list present: 1 = yes, 0 = no.

UnSolCap 7 R 0h N/A (Hard-coded)

Unsolicited response support: 1 = yes, 0 = no.

TSI™ CONFIDENTIAL

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ProcWidget 6 R 0h N/A (Hard-coded)

Processing state support: 1 = yes, 0 = no.

Stripe 5 R 0h N/A (Hard-coded)

Striping support: 1 = yes, 0 = no.

FormatOvrd 4 R 0h N/A (Hard-coded)

Stream format override: 1 = yes, 0 = no.

AmpParOvrd 3 R 0h N/A (Hard-coded)

Amplifier capabilities override: 1 = yes, no.

OutAmpPrsnt 2 R 0h N/A (Hard-coded)

Output amp present: 1 = yes, 0 = no.

InAmpPrsnt 1 R 0h N/A (Hard-coded)

Input amp present: 1 = yes, 0 = no.

Stereo 0 R 1h N/A (Hard-coded)

Stereo stream support: 1 = yes (stereo), 0 = no (mono).

7.20.1. MonoMux (NID = 19h): ConLst

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set

Get F000Eh

Field Name Bits R/W Default Reset

Rsvd 31:8 R000000h N/A (Hard-coded)

Reserved.

LForm 7 R 0h N/A (Hard-coded)

Connection list format: 1 = long-form (15-bit) NID entries, 0 = short-form (7-bit)

NID entries.

ConL 6:0 R03h N/A (Hard-coded)

Number of NID entries in connection list.

Field Name Bits R/W Default Reset

TSI™ CONFIDENTIAL

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7.20.2. MonoMux (NID = 19h): ConLstEntry0

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set

Get F0200h

Field Name Bits R/W Default Reset

ConL3 31:24 R00h N/A (Hard-coded)

DAC2 Converter widget (0x22)

ConL2 23:16 R1Ch N/A (Hard-coded)

MixerOutVol Selector widget (0x1C)

ConL1 15:8 R14h N/A (Hard-coded)

DAC1 Converter widget (0x14)

ConL0 7:0 R13h N/A (Hard-coded)

DAC0 Converter widget (0x13)

7.20.3. MonoMux (NID = 19h): ConSelectCtrl

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 701h

Get F0100h

Field Name Bits R/W Default Reset

Rsvd 31:2 R0000000h N/A (Hard-coded)

Reserved.

Index 1:0 RW 0h POR - DAFG - ULR

Connection select control index.

7.20.4. MonoMux (NID = 19h): PwrState

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 705h

Get F0500h

TSI™ CONFIDENTIAL

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SINGLE CHIP PC AUDIO SYSTEM,CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO

Field Name Bits R/W Default Reset

Rsvd4 31:11 R000000h N/A (Hard-coded)

Reserved.

SettingsReset 10 R1h POR - DAFG - ULR

Indicates if any persistent settings in this Widget have been reset. Cleared by

PwrState 'Get', or a 'Set' to any Verb in this Widget.

Rsvd3 9 R 0h N/A (Hard-coded)

Reserved.

Error 8 R 0h POR - DAFG - ULR

Error indicator: 1 = cannot enter requested power state, 0 = no problem with

requested power state.

Rsvd2 7:6 R0h N/A (Hard-coded)

Reserved.

Act 5:4 R3h POR - DAFG - LR

Actual power state of this widget.

Rsvd1 3:2 R0h N/A (Hard-coded)

Reserved.

Set 1:0 RW 0h POR - DAFG - LR

Current power state setting for this widget.

7.21. MonoMix (NID = 1Ah): WCap

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set

Get F0009h

Field Name Bits R/W Default Reset

Rsvd2 31:24 R00h N/A (Hard-coded)

Reserved.

TSI™ CONFIDENTIAL

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Type 23:20 R2h N/A (Hard-coded)

Widget type:

0h = Out Converter

1h = In Converter

2h = Summing (Mixer)

3h = Selector (Mux)

4h = Pin Complex

5h = Power

6h = Volume Knob

7h = Beep Generator

8h-Eh = Reserved

Fh = Vendor Defined

Delay 19:16 R0h N/A (Hard-coded)

Number of sample delays through widget.

Rsvd1 15:12 R0h N/A (Hard-coded)

Reserved.

SwapCap 11 R0h N/A (Hard-coded)

Left/right swap support: 1 = yes, 0 = no.

PwrCntrl 10 R1h N/A (Hard-coded)

Power state support: 1 = yes, 0 = no.

Dig 9 R 0h N/A (Hard-coded)

Digital stream support: 1 = yes (digital), 0 = no (analog).

ConnList 8 R 1h N/A (Hard-coded)

Connection list present: 1 = yes, 0 = no.

UnSolCap 7 R 0h N/A (Hard-coded)

Unsolicited response support: 1 = yes, 0 = no.

ProcWidget 6 R 0h N/A (Hard-coded)

Processing state support: 1 = yes, 0 = no.

Stripe 5 R 0h N/A (Hard-coded)

Striping support: 1 = yes, 0 = no.

FormatOvrd 4 R 0h N/A (Hard-coded)

Stream format override: 1 = yes, 0 = no.

Field Name Bits R/W Default Reset

TSI™ CONFIDENTIAL

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AmpParOvrd 3 R 0h N/A (Hard-coded)

Amplifier capabilities override: 1 = yes, no.

OutAmpPrsnt 2 R 0h N/A (Hard-coded)

Output amp present: 1 = yes, 0 = no.

InAmpPrsnt 1 R 0h N/A (Hard-coded)

Input amp present: 1 = yes, 0 = no.

Stereo 0 R 0h N/A (Hard-coded)

Stereo stream support: 1 = yes (stereo), 0 = no (mono).

7.21.1. MonoMix (NID = 1Ah): ConLst

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set

Get F000Eh

Field Name Bits R/W Default Reset

Rsvd 31:8 R000000h N/A (Hard-coded)

Reserved.

LForm 7 R 0h N/A (Hard-coded)

Connection list format: 1 = long-form (15-bit) NID entries, 0 = short-form (7-bit)

NID entries.

ConL 6:0 R01h N/A (Hard-coded)

Number of NID entries in connection list.

7.21.2. MonoMix (NID = 1Ah): ConLstEntry0

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set

Get F0200h

Field Name Bits R/W Default Reset

TSI™ CONFIDENTIAL

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Field Name Bits R/W Default Reset

ConL3 31:24 R00h N/A (Hard-coded)

Unused list entry.

ConL2 23:16 R00h N/A (Hard-coded)

Unused list entry.

ConL1 15:8 R00h N/A (Hard-coded)

Unused list entry.

ConL0 7:0 R19h N/A (Hard-coded)

MonoMux Selector widget (0x19)

7.21.3. MonoMix (NID = 1Ah): PwrState

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 705h

Get F0500h

Field Name Bits R/W Default Reset

Rsvd4 31:11 R000000h N/A (Hard-coded)

Reserved.

SettingsReset 10 R1h POR - DAFG - ULR

Indicates if any persistent settings in this Widget have been reset. Cleared by

PwrState 'Get', or a 'Set' to any Verb in this Widget.

Rsvd3 9 R 0h N/A (Hard-coded)

Reserved.

Error 8 R 0h POR - DAFG - ULR

Error indicator: 1 = cannot enter requested power state, 0 = no problem with

requested power state.

Rsvd2 7:6 R0h N/A (Hard-coded)

Reserved.

Act 5:4 R3h POR - DAFG - LR

Actual power state of this widget.

TSI™ CONFIDENTIAL

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Rsvd1 3:2 R0h N/A (Hard-coded)

Reserved.

Set 1:0 RW 0h POR - DAFG - LR

Current power state setting for this widget.

Field Name Bits R/W Default Reset

TSI™ CONFIDENTIAL

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7.22. Mixer (NID = 1Bh): WCap

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set

Get F0009h

Field Name Bits R/W Default Reset

Rsvd2 31:24 R00h N/A (Hard-coded)

Reserved.

Type 23:20 R2h N/A (Hard-coded)

Widget type:

0h = Out Converter

1h = In Converter

2h = Summing (Mixer)

3h = Selector (Mux)

4h = Pin Complex

5h = Power

6h = Volume Knob

7h = Beep Generator

8h-Eh = Reserved

Fh = Vendor Defined

Delay 19:16 R0h N/A (Hard-coded)

Number of sample delays through widget.

Rsvd1 15:12 R0h N/A (Hard-coded)

Reserved.

SwapCap 11 R0h N/A (Hard-coded)

Left/right swap support: 1 = yes, 0 = no.

PwrCntrl 10 R1h N/A (Hard-coded)

Power state support: 1 = yes, 0 = no.

Dig 9 R 0h N/A (Hard-coded)

Digital stream support: 1 = yes (digital), 0 = no (analog).

ConnList 8 R 1h N/A (Hard-coded)

Connection list present: 1 = yes, 0 = no.

UnSolCap 7 R 0h N/A (Hard-coded)

Unsolicited response support: 1 = yes, 0 = no.

TSI™ CONFIDENTIAL

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ProcWidget 6 R 0h N/A (Hard-coded)

Processing state support: 1 = yes, 0 = no.

Stripe 5 R 0h N/A (Hard-coded)

Striping support: 1 = yes, 0 = no.

FormatOvrd 4 R 0h N/A (Hard-coded)

Stream format override: 1 = yes, 0 = no.

AmpParOvrd 3 R 1h N/A (Hard-coded)

Amplifier capabilities override: 1 = yes, no.

OutAmpPrsnt 2 R 0h N/A (Hard-coded)

Output amp present: 1 = yes, 0 = no.

InAmpPrsnt 1 R 1h N/A (Hard-coded)

Input amp present: 1 = yes, 0 = no.

Stereo 0 R 1h N/A (Hard-coded)

Stereo stream support: 1 = yes (stereo), 0 = no (mono).

7.22.1. Mixer (NID = 1Bh): InAmpCap

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set

Get F000Dh

Field Name Bits R/W Default Reset

Mute 31 R1h N/A (Hard-coded)

Mute support: 1 = yes, 0 = no.

Rsvd3 30:23 R00h N/A (Hard-coded)

Reserved.

StepSize 22:16 R05h N/A (Hard-coded)

Size of each step in the gain range: 0 to 127 = .25dB to 32dB, in .25dB steps.

Field Name Bits R/W Default Reset

TSI™ CONFIDENTIAL

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Rsvd2 15 R0h N/A (Hard-coded)

Reserved.

NumSteps 14:8 R1Fh N/A (Hard-coded)

Number of gains steps (number of possible settings - 1).

Rsvd1 7 R 0h N/A (Hard-coded)

Reserved.

Offset 6:0 R17h N/A (Hard-coded)

Indicates which step is 0dB

7.22.2. Mixer (NID = 1Bh): ConLst

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set

Get F000Eh

Field Name Bits R/W Default Reset

Rsvd 31:8 R000000h N/A (Hard-coded)

Reserved.

LForm 7 R 0h N/A (Hard-coded)

Connection list format: 1 = long-form (15-bit) NID entries, 0 = short-form (7-bit)

NID entries.

ConL 6:0 R06h N/A (Hard-coded)

Number of NID entries in connection list.

7.22.3. Mixer (NID = 1Bh): ConLstEntry4

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set

Get F0204h

Field Name Bits R/W Default Reset

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Field Name Bits R/W Default Reset

ConL7 31:24 R00h N/A (Hard-coded)

Unused list entry.

ConL6 23:16 R00h N/A (Hard-coded)

Unused list entry.

ConL5 15:8 R0Fh N/A (Hard-coded)

Port F Pin Widget (0x0F)

ConL4 7:0 R0Eh N/A (Hard-coded)

Port E Pin Widget (0x0E).

7.22.4. Mixer (NID = 1Bh): ConLstEntry0

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set

Get F0200h

Field Name Bits R/W Default Reset

ConL3 31:24 R0Ch N/A (Hard-coded)

Port C Pin widget (0x0C). Uses InAmpLeft3/InAmpRight3 controls.

ConL2 23:16 R0Ah N/A (Hard-coded)

Port A Pin widget (0x0A). Uses InAmpLeft2/InAmpRight2 controls.

ConL1 15:8 R14h N/A (Hard-coded)

DAC1 widget (0x14). Uses InAmpLeft1/InAmpRight1 controls.

ConL0 7:0 R13h N/A (Hard-coded)

DAC0 widget (0x13). Uses InAmpLeft0/InAmpRight0 controls.

7.22.5. Mixer (NID = 1Bh): InAmpLeft0

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 360h

Get B2000h

TSI™ CONFIDENTIAL

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Field Name Bits R/W Default Reset

Rsvd2 31:8 R000000h N/A (Hard-coded)

Reserved.

Mute 7RW 1h POR - DAFG - ULR

Amp mute: 1 = muted, 0 = not muted.

Rsvd1 6:5 R0h N/A (Hard-coded)

Reserved.

Gain 4:0 RW 17h POR - DAFG - ULR

Amp gain step number (see InAmpCap parameter pertaining to this widget).

7.22.6. Mixer (NID = 1Bh): InAmpRight0

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 350h

Get B0000h

Field Name Bits R/W Default Reset

Rsvd2 31:8 R000000h N/A (Hard-coded)

Reserved.

Mute 7RW 1h POR - DAFG - ULR

Amp mute: 1 = muted, 0 = not muted.

Rsvd1 6:5 R0h N/A (Hard-coded)

Reserved.

Gain 4:0 RW 17h POR - DAFG - ULR

Amp gain step number (see InAmpCap parameter pertaining to this widget).

7.22.7. Mixer (NID = 1Bh): InAmpLeft1

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 361h

Get B2001h

TSI™ CONFIDENTIAL

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Field Name Bits R/W Default Reset

Rsvd2 31:8 R000000h N/A (Hard-coded)

Reserved.

Mute 7RW 1h POR - DAFG - ULR

Amp mute: 1 = muted, 0 = not muted.

Rsvd1 6:5 R0h N/A (Hard-coded)

Reserved.

Gain 4:0 RW 17h POR - DAFG - ULR

Amp gain step number (see InAmpCap parameter pertaining to this widget).

7.22.8. Mixer (NID = 1Bh): InAmpRight1

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 351h

Get B0001h

Field Name Bits R/W Default Reset

Rsvd2 31:8 R000000h N/A (Hard-coded)

Reserved.

Mute 7RW 1h POR - DAFG - ULR

Amp mute: 1 = muted, 0 = not muted.

Rsvd1 6:5 R0h N/A (Hard-coded)

Reserved.

Gain 4:0 RW 17h POR - DAFG - ULR

Amp gain step number (see InAmpCap parameter pertaining to this widget).

7.22.9. Mixer (NID = 1Bh): InAmpLeft2

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 362h

Get B2002h

TSI™ CONFIDENTIAL

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Field Name Bits R/W Default Reset

Rsvd2 31:8 R000000h N/A (Hard-coded)

Reserved.

Mute 7RW 1h POR - DAFG - ULR

Amp mute: 1 = muted, 0 = not muted.

Rsvd1 6:5 R0h N/A (Hard-coded)

Reserved.

Gain 4:0 RW 17h POR - DAFG - ULR

Amp gain step number (see InAmpCap parameter pertaining to this widget).

7.22.10. Mixer (NID = 1Bh): InAmpRight2

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 352h

Get B0002h

Field Name Bits R/W Default Reset

Rsvd2 31:8 R000000h N/A (Hard-coded)

Reserved.

Mute 7RW 1h POR - DAFG - ULR

Amp mute: 1 = muted, 0 = not muted.

Rsvd1 6:5 R0h N/A (Hard-coded)

Reserved.

Gain 4:0 RW 17h POR - DAFG - ULR

Amp gain step number (see InAmpCap parameter pertaining to this widget).

7.22.11. Mixer (NID = 1Bh): InAmpLeft3

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 363h

Get B2003h

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Field Name Bits R/W Default Reset

Rsvd2 31:8 R000000h N/A (Hard-coded)

Reserved.

Mute 7RW 1h POR - DAFG - ULR

Amp mute: 1 = muted, 0 = not muted.

Rsvd1 6:5 R0h N/A (Hard-coded)

Reserved.

Gain 4:0 RW 17h POR - DAFG - ULR

Amp gain step number (see InAmpCap parameter pertaining to this widget).

7.22.12. Mixer (NID = 1Bh): InAmpRight3

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 353h

Get B0003h

Field Name Bits R/W Default Reset

Rsvd2 31:8 R000000h N/A (Hard-coded)

Reserved.

Mute 7RW 1h POR - DAFG - ULR

Amp mute: 1 = muted, 0 = not muted.

Rsvd1 6:5 R0h N/A (Hard-coded)

Reserved.

Gain 4:0 RW 17h POR - DAFG - ULR

Amp gain step number (see InAmpCap parameter pertaining to this widget).

7.22.13. Mixer (NID = 1Bh): InAmpLeft4

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 364h

Get B2004h

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Field Name Bits R/W Default Reset

Rsvd2 31:8 R000000h N/A (Hard-coded)

Reserved.

Mute 7RW 1h POR - DAFG - ULR

Amp mute: 1 = muted, 0 = not muted.

Rsvd1 6:5 R0h N/A (Hard-coded)

Reserved.

Gain 4:0 RW 17h POR - DAFG - ULR

Amp gain step number (see InAmpCap parameter pertaining to this widget).

7.22.14. Mixer (NID = 1Bh): InAmpRight4

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 354h

Get B0004h

Field Name Bits R/W Default Reset

Rsvd2 31:8 R000000h N/A (Hard-coded)

Reserved.

Mute 7RW 1h POR - DAFG - ULR

Amp mute: 1 = muted, 0 = not muted.

Rsvd1 6:5 R0h N/A (Hard-coded)

Reserved.

Gain 4:0 RW 17h POR - DAFG - ULR

Amp gain step number (see InAmpCap parameter pertaining to this widget).

7.22.15. Mixer (NID = 1Bh): InAmpLeft5

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 365h

Get B2005h

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Field Name Bits R/W Default Reset

Rsvd2 31:8 R000000h N/A (Hard-coded)

Reserved.

Mute 7RW 1h POR - DAFG - ULR

Amp mute: 1 = muted, 0 = not muted.

Rsvd1 6:5 R0h N/A (Hard-coded)

Reserved.

Gain 4:0 RW 17h POR - DAFG - ULR

Amp gain step number (see InAmpCap parameter pertaining to this widget).

7.22.16. Mixer (NID = 1Bh): InAmpRight5

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 355h

Get B0005h

Field Name Bits R/W Default Reset

Rsvd2 31:8 R000000h N/A (Hard-coded)

Reserved.

Mute 7RW 1h POR - DAFG - ULR

Amp mute: 1 = muted, 0 = not muted.

Rsvd1 6:5 R0h N/A (Hard-coded)

Reserved.

Gain 4:0 RW 17h POR - DAFG - ULR

Amp gain step number (see InAmpCap parameter pertaining to this widget).

7.22.17. Mixer (NID = 1Bh): PwrState

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 705h

Get F0500h

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Field Name Bits R/W Default Reset

Rsvd4 31:11 R000000h N/A (Hard-coded)

Reserved.

SettingsReset 10 R1h POR - DAFG - ULR

Indicates if any persistent settings in this Widget have been reset. Cleared by

PwrState 'Get', or a 'Set' to any Verb in this Widget.

Rsvd3 9 R 0h N/A (Hard-coded)

Reserved.

Error 8 R 0h POR - DAFG - ULR

Error indicator: 1 = cannot enter requested power state, 0 = no problem with

requested power state.

Rsvd2 7:6 R0h N/A (Hard-coded)

Reserved.

Act 5:4 R3h POR - DAFG - LR

Actual power state of this widget.

Rsvd1 3:2 R0h N/A (Hard-coded)

Reserved.

Set 1:0 RW 0h POR - DAFG - LR

Current power state setting for this widget.

7.23. MixerOutVol (NID = 1Ch): WCap

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set

Get F0009h

Field Name Bits R/W Default Reset

Rsvd2 31:24 R00h N/A (Hard-coded)

Reserved.

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Type 23:20 R3h N/A (Hard-coded)

Widget type:

0h = Out Converter

1h = In Converter

2h = Summing (Mixer)

3h = Selector (Mux)

4h = Pin Complex

5h = Power

6h = Volume Knob

7h = Beep Generator

8h-Eh = Reserved

Fh = Vendor Defined

Delay 19:16 R0h N/A (Hard-coded)

Number of sample delays through widget.

Rsvd1 15:12 R0h N/A (Hard-coded)

Reserved.

SwapCap 11 R0h N/A (Hard-coded)

Left/right swap support: 1 = yes, 0 = no.

PwrCntrl 10 R1h N/A (Hard-coded)

Power state support: 1 = yes, 0 = no.

Dig 9 R 0h N/A (Hard-coded)

Digital stream support: 1 = yes (digital), 0 = no (analog).

ConnList 8 R 1h N/A (Hard-coded)

Connection list present: 1 = yes, 0 = no.

UnSolCap 7 R 0h N/A (Hard-coded)

Unsolicited response support: 1 = yes, 0 = no.

ProcWidget 6 R 0h N/A (Hard-coded)

Processing state support: 1 = yes, 0 = no.

Stripe 5 R 0h N/A (Hard-coded)

Striping support: 1 = yes, 0 = no.

FormatOvrd 4 R 0h N/A (Hard-coded)

Stream format override: 1 = yes, 0 = no.

Field Name Bits R/W Default Reset

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AmpParOvrd 3 R 1h N/A (Hard-coded)

Amplifier capabilities override: 1 = yes, no.

OutAmpPrsnt 2 R 1h N/A (Hard-coded)

Output amp present: 1 = yes, 0 = no.

InAmpPrsnt 1 R 0h N/A (Hard-coded)

Input amp present: 1 = yes, 0 = no.

Stereo 0 R 1h N/A (Hard-coded)

Stereo stream support: 1 = yes (stereo), 0 = no (mono).

7.23.1. MixerOutVol (NID = 1Ch): ConLst

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set

Get F000Eh

Field Name Bits R/W Default Reset

Rsvd 31:8 R000000h N/A (Hard-coded)

Reserved.

LForm 7 R 0h N/A (Hard-coded)

Connection list format: 1 = long-form (15-bit) NID entries, 0 = short-form (7-bit)

NID entries.

ConL 6:0 R01h N/A (Hard-coded)

Number of NID entries in connection list.

7.23.2. MixerOutVol (NID = 1Ch): ConLstEntry0

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set

Get F0200h

Field Name Bits R/W Default Reset

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Field Name Bits R/W Default Reset

ConL3 31:24 R00h N/A (Hard-coded)

Unused list entry.

ConL2 23:16 R00h N/A (Hard-coded)

Unused list entry.

ConL1 15:8 R00h N/A (Hard-coded)

Unused list entry.

ConL0 7:0 R1Bh N/A (Hard-coded)

Mixer Summing widget (0x1B)

7.23.3. MixerOutVol (NID = 1Ch): OutAmpCap

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set

Get F0012h

Field Name Bits R/W Default Reset

Mute 31 R1h N/A (Hard-coded)

Mute support: 1 = yes, 0 = no.

Rsvd3 30:23 R00h N/A (Hard-coded)

Reserved.

StepSize 22:16 R05h N/A (Hard-coded)

Size of each step in the gain range: 0 to 127 = .25dB to 32dB, in .25dB steps.

Rsvd2 15 R0h N/A (Hard-coded)

Reserved.

NumSteps 14:8 R1Fh N/A (Hard-coded)

Number of gains steps (number of possible settings - 1).

Rsvd1 7 R 0h N/A (Hard-coded)

Reserved.

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Offset 6:0 R1Fh N/A (Hard-coded)

Indicates which step is 0dB

7.23.4. MixerOutVol (NID = 1Ch): OutAmpLeft

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 3A0h

Get BA000h

Field Name Bits R/W Default Reset

Rsvd2 31:8 R000000h N/A (Hard-coded)

Reserved.

Mute 7RW 1h POR - DAFG - ULR

Amp mute: 1 = muted, 0 = not muted.

Rsvd1 6:5 R0h N/A (Hard-coded)

Reserved.

Gain 4:0 RW 1Fh POR - DAFG - ULR

Amp gain step number (see OutAmpCap parameter pertaining to this widget).

7.23.5. MixerOutVol (NID = 1Ch): OutAmpRight

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 390h

Get B8000h

Field Name Bits R/W Default Reset

Rsvd2 31:8 R000000h N/A (Hard-coded)

Reserved.

Mute 7RW 1h POR - DAFG - ULR

Amp mute: 1 = muted, 0 = not muted.

Field Name Bits R/W Default Reset

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Rsvd1 6:5 R0h N/A (Hard-coded)

Reserved.

Gain 4:0 RW 1Fh POR - DAFG - ULR

Amp gain step number (see OutAmpCap parameter pertaining to this widget).

7.23.6. MixerOutVol (NID = 1Ch): PwrState

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 705h

Get F0500h

Field Name Bits R/W Default Reset

Rsvd4 31:11 R000000h N/A (Hard-coded)

Reserved.

SettingsReset 10 R1h POR - DAFG - ULR

Indicates if any persistent settings in this Widget have been reset. Cleared by

PwrState 'Get', or a 'Set' to any Verb in this Widget.

Rsvd3 9 R 0h N/A (Hard-coded)

Reserved.

Error 8 R 0h POR - DAFG - ULR

Error indicator: 1 = cannot enter requested power state, 0 = no problem with

requested power state.

Rsvd2 7:6 R0h N/A (Hard-coded)

Reserved.

Act 5:4 R3h POR - DAFG - LR

Actual power state of this widget.

Rsvd1 3:2 R0h N/A (Hard-coded)

Reserved.

Set 1:0 RW 0h POR - DAFG - LR

Current power state setting for this widget.

Field Name Bits R/W Default Reset

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7.24. SPDIFOut0 (NID = 1Dh): WCap

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set

Get F0009h

Field Name Bits R/W Default Reset

Rsvd2 31:24 R00h N/A (Hard-coded)

Reserved.

Type 23:20 R0h N/A (Hard-coded)

Widget type:

0h = Out Converter

1h = In Converter

2h = Summing (Mixer)

3h = Selector (Mux)

4h = Pin Complex

5h = Power

6h = Volume Knob

7h = Beep Generator

8h-Eh = Reserved

Fh = Vendor Defined

Delay 19:16 R4h N/A (Hard-coded)

Number of sample delays through widget.

Rsvd1 15:12 R0h N/A (Hard-coded)

Reserved.

SwapCap 11 R0h N/A (Hard-coded)

Left/right swap support: 1 = yes, 0 = no.

PwrCntrl 10 R1h N/A (Hard-coded)

Power state support: 1 = yes, 0 = no.

Dig 9 R 1h N/A (Hard-coded)

Digital stream support: 1 = yes (digital), 0 = no (analog).

ConnList 8 R 0h N/A (Hard-coded)

Connection list present: 1 = yes, 0 = no.

UnSolCap 7 R 0h N/A (Hard-coded)

Unsolicited response support: 1 = yes, 0 = no.

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ProcWidget 6 R 0h N/A (Hard-coded)

Processing state support: 1 = yes, 0 = no.

Stripe 5 R 0h N/A (Hard-coded)

Striping support: 1 = yes, 0 = no.

FormatOvrd 4 R 1h N/A (Hard-coded)

Stream format override: 1 = yes, 0 = no.

AmpParOvrd 3 R 1h N/A (Hard-coded)

Amplifier capabilities override: 1 = yes, no.

OutAmpPrsnt 2 R 1h N/A (Hard-coded)

Output amp present: 1 = yes, 0 = no.

InAmpPrsnt 1 R 0h N/A (Hard-coded)

Input amp present: 1 = yes, 0 = no.

Stereo 0 R 1h N/A (Hard-coded)

Stereo stream support: 1 = yes (stereo), 0 = no (mono).

7.24.1. SPDIFOut0 (NID = 1Dh): PCMCap

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set

Get F000Ah

Field Name Bits R/W Default Reset

Rsvd2 31:21 R000h N/A (Hard-coded)

Reserved.

B32 20 R0h N/A (Hard-coded)

32 bit audio format support: 1 = yes, 0 = no.

B24 19 R1h N/A (Hard-coded)

24 bit audio format support: 1 = yes, 0 = no.

Field Name Bits R/W Default Reset

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B20 18 R1h N/A (Hard-coded)

20 bit audio format support: 1 = yes, 0 = no.

B16 17 R1h N/A (Hard-coded)

16 bit audio format support: 1 = yes, 0 = no.

B8 16 R0h N/A (Hard-coded)

8 bit audio format support: 1 = yes, 0 = no.

Rsvd1 15:12 R0h N/A (Hard-coded)

Reserved.

R12 11 R0h N/A (Hard-coded)

384kHz rate support: 1 = yes, 0 = no.

R11 10 R1h N/A (Hard-coded)

192kHz rate support: 1 = yes, 0 = no.

R10 9 R 0h N/A (Hard-coded)

176.4kHz rate support: 1 = yes, 0 = no.

R9 8 R 1h N/A (Hard-coded)

96kHz rate support: 1 = yes, 0 = no.

R8 7 R 1h N/A (Hard-coded)

88.2kHz rate support: 1 = yes, 0 = no.

R7 6 R 1h N/A (Hard-coded)

48kHz rate support: 1 = yes, 0 = no.

R6 5 R 1h N/A (Hard-coded)

44.1kHz rate support: 1 = yes, 0 = no.

R5 4 R 0h N/A (Hard-coded)

32kHz rate support: 1 = yes, 0 = no.

R4 3 R 0h N/A (Hard-coded)

22.05kHz rate support: 1 = yes, 0 = no.

R3 2 R 0h N/A (Hard-coded)

16kHz rate support: 1 = yes, 0 = no.

Field Name Bits R/W Default Reset

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R2 1 R 0h N/A (Hard-coded)

11.025kHz rate support: 1 = yes, 0 = no.

R1 0 R 0h N/A (Hard-coded)

8kHz rate support: 1 = yes, 0 = no.

7.24.2. SPDIFOut0 (NID = 1Dh): StreamCap

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set

Get F000Bh

Field Name Bits R/W Default Reset

Rsvd 31:3 R00000000h N/A (Hard-coded)

Reserved.

AC3 2 R 1h N/A (Hard-coded)

AC-3 formatted data support: 1 = yes, 0 = no.

Float32 1 R 0h N/A (Hard-coded)

Float32 formatted data support: 1 = yes, 0 = no.

PCM 0 R 1h N/A (Hard-coded)

PCM-formatted data support: 1 = yes, 0 = no.

7.24.3. SPDIFOut0 (NID = 1Dh): OutAmpCap

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set

Get F0012h

Field Name Bits R/W Default Reset

Mute 31 R1h N/A (Hard-coded)

Mute support: 1 = yes, 0 = no.

Field Name Bits R/W Default Reset

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Rsvd3 30:23 R00h N/A (Hard-coded)

Reserved.

StepSize 22:16 R00h N/A (Hard-coded)

Size of each step in the gain range: 0 to 127 = .25dB to 32dB, in .25dB steps.

Rsvd2 15 R0h N/A (Hard-coded)

Reserved.

NumSteps 14:8 R00h N/A (Hard-coded)

Number of gains steps (number of possible settings - 1).

Rsvd1 7 R 0h N/A (Hard-coded)

Reserved.

Offset 6:0 R00h N/A (Hard-coded)

Indicates which step is 0dB

7.24.4. SPDIFOut0 (NID = 1Dh): Cnvtr

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 2h

Get A0000h

Field Name Bits R/W Default Reset

Rsvd2 31:16 R0000h N/A (Hard-coded)

Reserved.

FrmtNonPCM 15 RW 0h POR - DAFG - ULR

Stream type: 1 = Non-PCM, 0 = PCM.

FrmtSmplRate 14 RW 0h POR - DAFG - ULR

Sample base rate: 1 = 44.1kHz, 0 = 48kHz.

Field Name Bits R/W Default Reset

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SmplRateMultp 13:11 RW 0h POR - DAFG - ULR

Sample base rate multiple:

000b= x1 (48kHz/44.1kHz or less)

001b= x2 (96kHz/88.2kHz/32kHz)

010b= x3 (144kHz)

011b= x4 (192kHz/176.4kHz)

100b-111b Reserved

SmplRateDiv 10:8 RW 0h POR - DAFG - ULR

Sample base rate divider:

000b= Divide by 1 (48kHz/44.1kHz)

001b= Divide by 2 (24kHz/20.05kHz)

010b= Divide by 3 (16kHz/32kHz)

011b= Divide by 4 (11.025kHz)

100b= Divide by 5 (9.6kHz)

101b= Divide by 6 (8kHz)

110b= Divide by 7

111b= Divide by 8 (6kHz)

Rsvd1 7 R 0h N/A (Hard-coded)

Reserved.

BitsPerSmpl 6:4 RW 3h POR - DAFG - ULR

Bits per sample:

000b= 8 bits

001b= 16 bits

010b= 20 bits

011b= 24 bits

100b= 32 bits

101b-111b= Reserved

NmbrChan 3:0 RW 1h POR - DAFG - ULR

Total number of channels in the stream assigned to this converter:

0000b-1111b= 1-16 channels.

7.24.5. SPDIFOut0 (NID = 1Dh): OutAmpLeft

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 3A0h

Get BA000h

Field Name Bits R/W Default Reset

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Field Name Bits R/W Default Reset

Rsvd2 31:8 R000000h N/A (Hard-coded)

Reserved.

Mute 7RW 0h POR - DAFG - ULR

Amp mute: 1 = muted, 0 = not muted.

Rsvd1 6:0 R00h N/A (Hard-coded)

Reserved.

7.24.6. SPDIFOut0 (NID = 1Dh): OutAmpRight

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 390h

Get B8000h

Field Name Bits R/W Default Reset

Rsvd2 31:8 R000000h N/A (Hard-coded)

Reserved.

Mute 7RW 0h POR - DAFG - ULR

Amp mute: 1 = muted, 0 = not muted.

Rsvd1 6:0 R00h N/A (Hard-coded)

Reserved.

7.24.7. SPDIFOut0 (NID = 1Dh): PwrState

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 705h

Get F0500h

Field Name Bits R/W Default Reset

Rsvd4 31:11 R000000h N/A (Hard-coded)

Reserved.

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SettingsReset 10 R1h POR - DAFG - ULR

Indicates if any persistent settings in this Widget have been reset. Cleared by

PwrState 'Get', or a 'Set' to any Verb in this Widget.

Rsvd3 9 R 0h N/A (Hard-coded)

Reserved.

Error 8 R 0h POR - DAFG - ULR

Error indicator: 1 = cannot enter requested power state, 0 = no problem with

requested power state.

Rsvd2 7:6 R0h N/A (Hard-coded)

Reserved.

Act 5:4 R3h POR - DAFG - LR

Actual power state of this widget.

Rsvd1 3:2 R0h N/A (Hard-coded)

Reserved.

Set 1:0 RW 3h POR - DAFG - LR

Current power state setting for this widget.

7.24.8. SPDIFOut0 (NID = 1Dh): CnvtrID

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 706h

Get F0600h

Field Name Bits R/W Default Reset

Rsvd 31:8 R000000h N/A (Hard-coded)

Reserved.

Strm 7:4 RW 0h POR - S&DAFG - LR - PS

Stream ID: 0h = Converter "off", 1h-Fh = valid ID's.

Ch 3:0 RW 0h POR - S&DAFG - LR - PS

Channel assignment ("Ch" and "Ch+1" assigned as a pair, for a stereo convert-

er).

Field Name Bits R/W Default Reset

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7.24.9. SPDIFOut0 (NID = 1Dh): DigCnvtr

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 73Fh 73Eh 70Eh 70Dh

Get F0E00h / F0D00h

Field Name Bits R/W Default Reset

Rsvd2 31:24 R00h N/A (Hard-coded)

Reserved.

KeepAlive 23 RW 0h POR - DAFG - ULR

Keep Alive Enable: 1 = clocking information maintained during D3, 0 = clock

information not required during D3.

Rsvd1 22:15 R00h N/A (Hard-coded)

Reserved.

CC 14:8 RW 00h POR - DAFG - ULR

CC: Category Code.

L 7 RW 0h POR - DAFG - ULR

L: Generation Level.

PRO 6RW 0h POR - DAFG - ULR

PRO: Professional.

AUDIO 5RW 0h POR - DAFG - ULR

/AUDIO: Non-Audio.

COPY 4RW 0h POR - DAFG - ULR

COPY: Copyright.

PRE 3RW 0h POR - DAFG - ULR

PRE: Preemphasis.

VCFG 2RW 0h POR - DAFG - ULR

VCFG: Validity Config.

V 1 RW 0h POR - DAFG - ULR

V: Validity.

TSI™ CONFIDENTIAL

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SINGLE CHIP PC AUDIO SYSTEM,CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO

DigEn 0RW 0h POR - DAFG - ULR

Digital enable: 1 = converter enabled, 0 = converter disable.

7.25. SPDIFOut1 (NID = 1Eh): WCap

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set

Get F0009h

Field Name Bits R/W Default Reset

Rsvd2 31:24 R00h N/A (Hard-coded)

Reserved.

Type 23:20 R0h N/A (Hard-coded)

Widget type:

0h = Out Converter

1h = In Converter

2h = Summing (Mixer)

3h = Selector (Mux)

4h = Pin Complex

5h = Power

6h = Volume Knob

7h = Beep Generator

8h-Eh = Reserved

Fh = Vendor Defined

Delay 19:16 R4h N/A (Hard-coded)

Number of sample delays through widget.

Rsvd1 15:12 R0h N/A (Hard-coded)

Reserved.

SwapCap 11 R0h N/A (Hard-coded)

Left/right swap support: 1 = yes, 0 = no.

PwrCntrl 10 R1h N/A (Hard-coded)

Power state support: 1 = yes, 0 = no.

Dig 9 R 1h N/A (Hard-coded)

Digital stream support: 1 = yes (digital), 0 = no (analog).

Field Name Bits R/W Default Reset

TSI™ CONFIDENTIAL

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SINGLE CHIP PC AUDIO SYSTEM,CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO

ConnList 8 R 0h N/A (Hard-coded)

Connection list present: 1 = yes, 0 = no.

UnSolCap 7 R 0h N/A (Hard-coded)

Unsolicited response support: 1 = yes, 0 = no.

ProcWidget 6 R 0h N/A (Hard-coded)

Processing state support: 1 = yes, 0 = no.

Stripe 5 R 0h N/A (Hard-coded)

Striping support: 1 = yes, 0 = no.

FormatOvrd 4 R 1h N/A (Hard-coded)

Stream format override: 1 = yes, 0 = no.

AmpParOvrd 3 R 1h N/A (Hard-coded)

Amplifier capabilities override: 1 = yes, no.

OutAmpPrsnt 2 R 1h N/A (Hard-coded)

Output amp present: 1 = yes, 0 = no.

InAmpPrsnt 1 R 0h N/A (Hard-coded)

Input amp present: 1 = yes, 0 = no.

Stereo 0 R 1h N/A (Hard-coded)

Stereo stream support: 1 = yes (stereo), 0 = no (mono).

7.25.1. SPDIFOut1 (NID = 1Eh): PCMCap

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set

Get F000Ah

Field Name Bits R/W Default Reset

Rsvd2 31:21 R000h N/A (Hard-coded)

Reserved.

Field Name Bits R/W Default Reset

TSI™ CONFIDENTIAL

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B32 20 R0h N/A (Hard-coded)

32 bit audio format support: 1 = yes, 0 = no.

B24 19 R1h N/A (Hard-coded)

24 bit audio format support: 1 = yes, 0 = no.

B20 18 R1h N/A (Hard-coded)

20 bit audio format support: 1 = yes, 0 = no.

B16 17 R1h N/A (Hard-coded)

16 bit audio format support: 1 = yes, 0 = no.

B8 16 R0h N/A (Hard-coded)

8 bit audio format support: 1 = yes, 0 = no.

Rsvd1 15:12 R0h N/A (Hard-coded)

Reserved.

R12 11 R0h N/A (Hard-coded)

384kHz rate support: 1 = yes, 0 = no.

R11 10 R1h N/A (Hard-coded)

192kHz rate support: 1 = yes, 0 = no.

R10 9 R 0h N/A (Hard-coded)

176.4kHz rate support: 1 = yes, 0 = no.

R9 8 R 1h N/A (Hard-coded)

96kHz rate support: 1 = yes, 0 = no.

R8 7 R 1h N/A (Hard-coded)

88.2kHz rate support: 1 = yes, 0 = no.

R7 6 R 1h N/A (Hard-coded)

48kHz rate support: 1 = yes, 0 = no.

R6 5 R 1h N/A (Hard-coded)

44.1kHz rate support: 1 = yes, 0 = no.

R5 4 R 0h N/A (Hard-coded)

32kHz rate support: 1 = yes, 0 = no.

Field Name Bits R/W Default Reset

TSI™ CONFIDENTIAL

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R4 3 R 0h N/A (Hard-coded)

22.05kHz rate support: 1 = yes, 0 = no.

R3 2 R 0h N/A (Hard-coded)

16kHz rate support: 1 = yes, 0 = no.

R2 1 R 0h N/A (Hard-coded)

11.025kHz rate support: 1 = yes, 0 = no.

R1 0 R 0h N/A (Hard-coded)

8kHz rate support: 1 = yes, 0 = no.

7.25.2. SPDIFOut1 (NID = 1Eh): StreamCap

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set

Get F000Bh

Field Name Bits R/W Default Reset

Rsvd 31:3 R00000000h N/A (Hard-coded)

Reserved.

AC3 2 R 1h N/A (Hard-coded)

AC-3 formatted data support: 1 = yes, 0 = no.

Float32 1 R 0h N/A (Hard-coded)

Float32 formatted data support: 1 = yes, 0 = no.

PCM 0 R 1h N/A (Hard-coded)

PCM-formatted data support: 1 = yes, 0 = no.

7.25.3. SPDIFOut1 (NID = 1Eh): OutAmpCap

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set

Get F0012h

Field Name Bits R/W Default Reset

TSI™ CONFIDENTIAL

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SINGLE CHIP PC AUDIO SYSTEM,CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO

Field Name Bits R/W Default Reset

Mute 31 R1h N/A (Hard-coded)

Mute support: 1 = yes, 0 = no.

Rsvd3 30:23 R00h N/A (Hard-coded)

Reserved.

StepSize 22:16 R00h N/A (Hard-coded)

Size of each step in the gain range: 0 to 127 = .25dB to 32dB, in .25dB steps.

Rsvd2 15 R0h N/A (Hard-coded)

Reserved.

NumSteps 14:8 R00h N/A (Hard-coded)

Number of gains steps (number of possible settings - 1).

Rsvd1 7 R 0h N/A (Hard-coded)

Reserved.

Offset 6:0 R00h N/A (Hard-coded)

Indicates which step is 0dB

7.25.4. SPDIFOut1 (NID = 1Eh): Cnvtr

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 2h

Get A0000h

Field Name Bits R/W Default Reset

Rsvd2 31:16 R0000h N/A (Hard-coded)

Reserved.

FrmtNonPCM 15 RW 0h POR - DAFG - ULR

Stream type: 1 = Non-PCM, 0 = PCM.

FrmtSmplRate 14 RW 0h POR - DAFG - ULR

Sample base rate: 1 = 44.1kHz, 0 = 48kHz.

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SmplRateMultp 13:11 RW 0h POR - DAFG - ULR

Sample base rate multiple:

000b= x1 (48kHz/44.1kHz or less)

001b= x2 (96kHz/88.2kHz/32kHz)

010b= x3 (144kHz)

011b= x4 (192kHz/176.4kHz)

100b-111b Reserved

SmplRateDiv 10:8 RW 0h POR - DAFG - ULR

Sample base rate divider:

000b= Divide by 1 (48kHz/44.1kHz)

001b= Divide by 2 (24kHz/20.05kHz)

010b= Divide by 3 (16kHz/32kHz)

011b= Divide by 4 (11.025kHz)

100b= Divide by 5 (9.6kHz)

101b= Divide by 6 (8kHz)

110b= Divide by 7

111b= Divide by 8 (6kHz)

Rsvd1 7 R 0h N/A (Hard-coded)

Reserved.

BitsPerSmpl 6:4 RW 3h POR - DAFG - ULR

Bits per sample:

000b= 8 bits

001b= 16 bits

010b= 20 bits

011b= 24 bits

100b= 32 bits

101b-111b= Reserved

NmbrChan 3:0 RW 1h POR - DAFG - ULR

Total number of channels in the stream assigned to this converter:

0000b-1111b= 1-16 channels.

7.25.5. SPDIFOut1 (NID = 1Eh): OutAmpLeft

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 3A0h

Get BA000h

Field Name Bits R/W Default Reset

TSI™ CONFIDENTIAL

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SINGLE CHIP PC AUDIO SYSTEM,CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO

Field Name Bits R/W Default Reset

Rsvd2 31:8 R000000h N/A (Hard-coded)

Reserved.

Mute 7RW 0h POR - DAFG - ULR

Amp mute: 1 = muted, 0 = not muted.

Rsvd1 6:0 R00h N/A (Hard-coded)

Reserved.

7.25.6. SPDIFOut1 (NID = 1Eh): OutAmpRight

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 390h

Get B8000h

Field Name Bits R/W Default Reset

Rsvd2 31:8 R000000h N/A (Hard-coded)

Reserved.

Mute 7RW 0h POR - DAFG - ULR

Amp mute: 1 = muted, 0 = not muted.

Rsvd1 6:0 R00h N/A (Hard-coded)

Reserved.

7.25.7. SPDIFOut1 (NID = 1Eh): PwrState

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 705h

Get F0500h

Field Name Bits R/W Default Reset

Rsvd4 31:11 R000000h N/A (Hard-coded)

Reserved.

TSI™ CONFIDENTIAL

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SettingsReset 10 R1h POR - DAFG - ULR

Indicates if any persistent settings in this Widget have been reset. Cleared by

PwrState 'Get', or a 'Set' to any Verb in this Widget.

Rsvd3 9 R 0h N/A (Hard-coded)

Reserved.

Error 8 R 0h POR - DAFG - ULR

Error indicator: 1 = cannot enter requested power state, 0 = no problem with

requested power state.

Rsvd2 7:6 R0h N/A (Hard-coded)

Reserved.

Act 5:4 R3h POR - DAFG - LR

Actual power state of this widget.

Rsvd1 3:2 R0h N/A (Hard-coded)

Reserved.

Set 1:0 RW 3h POR - DAFG - LR

Current power state setting for this widget.

7.25.8. SPDIFOut1 (NID = 1Eh): CnvtrID

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 706h

Get F0600h

Field Name Bits R/W Default Reset

Rsvd 31:8 R000000h N/A (Hard-coded)

Reserved.

Strm 7:4 RW 0h POR - S&DAFG - LR - PS

Stream ID: 0h = Converter "off", 1h-Fh = valid ID's.

Ch 3:0 RW 0h POR - S&DAFG - LR - PS

Channel assignment ("Ch" and "Ch+1" assigned as a pair, for a stereo convert-

er).

Field Name Bits R/W Default Reset

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7.25.9. SPDIFOut1 (NID = 1Eh): DigCnvtr

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 73Fh 73Eh 70Eh 70Dh

Get F0E00h / F0D00h

Field Name Bits R/W Default Reset

Rsvd2 31:24 R00h N/A (Hard-coded)

Reserved.

KeepAlive 23 RW 0h POR - DAFG - ULR

Keep Alive Enable: 1 = clocking information maintained during D3, 0 = clock

information not required during D3.

Rsvd1 22:15 R00h N/A (Hard-coded)

Reserved.

CC 14:8 RW 00h POR - DAFG - ULR

CC: Category Code.

L 7 RW 0h POR - DAFG - ULR

L: Generation Level.

PRO 6RW 0h POR - DAFG - ULR

PRO: Professional.

AUDIO 5RW 0h POR - DAFG - ULR

/AUDIO: Non-Audio.

COPY 4RW 0h POR - DAFG - ULR

COPY: Copyright.

PRE 3RW 0h POR - DAFG - ULR

PRE: Preemphasis.

VCFG 2RW 0h POR - DAFG - ULR

VCFG: Validity Config.

V 1 RW 0h POR - DAFG - ULR

V: Validity.

TSI™ CONFIDENTIAL

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SINGLE CHIP PC AUDIO SYSTEM,CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO

DigEn 0RW 0h POR - DAFG - ULR

Digital enable: 1 = converter enabled, 0 = converter disable.

7.26. Dig0Pin (NID = 1Fh): WCap

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set

Get F0009h

Field Name Bits R/W Default Reset

Rsvd2 31:24 R00h N/A (Hard-coded)

Reserved.

Type 23:20 R4h N/A (Hard-coded)

Widget type:

0h = Out Converter

1h = In Converter

2h = Summing (Mixer)

3h = Selector (Mux)

4h = Pin Complex

5h = Power

6h = Volume Knob

7h = Beep Generator

8h-Eh = Reserved

Fh = Vendor Defined

Delay 19:16 R0h N/A (Hard-coded)

Number of sample delays through widget.

Rsvd1 15:12 R0h N/A (Hard-coded)

Reserved.

SwapCap 11 R0h N/A (Hard-coded)

Left/right swap support: 1 = yes, 0 = no.

PwrCntrl 10 R1h N/A (Hard-coded)

Power state support: 1 = yes, 0 = no.

Dig 9 R 1h N/A (Hard-coded)

Digital stream support: 1 = yes (digital), 0 = no (analog).

Field Name Bits R/W Default Reset

TSI™ CONFIDENTIAL

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ConnList 8 R 1h N/A (Hard-coded)

Connection list present: 1 = yes, 0 = no.

UnSolCap 7 R 1h N/A (Hard-coded)

Unsolicited response support: 1 = yes, 0 = no.

ProcWidget 6 R 0h N/A (Hard-coded)

Processing state support: 1 = yes, 0 = no.

Stripe 5 R 0h N/A (Hard-coded)

Striping support: 1 = yes, 0 = no.

FormatOvrd 4 R 0h N/A (Hard-coded)

Stream format override: 1 = yes, 0 = no.

AmpParOvrd 3 R 0h N/A (Hard-coded)

Amplifier capabilities override: 1 = yes, no.

OutAmpPrsnt 2 R 0h N/A (Hard-coded)

Output amp present: 1 = yes, 0 = no.

InAmpPrsnt 1 R 0h N/A (Hard-coded)

Input amp present: 1 = yes, 0 = no.

Stereo 0 R 1h N/A (Hard-coded)

Stereo stream support: 1 = yes (stereo), 0 = no (mono).

7.26.1. Dig0Pin (NID = 1Fh): PinCap

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set

Get F000Ch

Field Name Bits R/W Default Reset

Rsvd2 31:17 R0000h N/A (Hard-coded)

Reserved.

Field Name Bits R/W Default Reset

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EapdCap 16 R0h N/A (Hard-coded)

EAPD support: 1 = yes, 0 = no.

VrefCntrl 15:8 R00h N/A (Hard-coded)

Vref support:

bit 7 = Reserved

bit 6 = Reserved

bit 5 = 100% support (1 = yes, 0 = no)

bit 4 = 80% support (1 = yes, 0 = no)

bit 3 = Reserved

bit 2 = GND support (1 = yes, 0 = no)

bit 1 = 50% support (1 = yes, 0 = no)

bit 0 = Hi-Z support (1 = yes, 0 = no)

Rsvd1 7 R 0h N/A (Hard-coded)

Reserved.

BalancedIO 6 R 0h N/A (Hard-coded)

Balanced I/O support: 1 = yes, 0 = no.

InCap 5 R 0h N/A (Hard-coded)

Input support: 1 = yes, 0 = no.

OutCap 4 R 1h N/A (Hard-coded)

Output support: 1 = yes, 0 = no.

HdphDrvCap 3 R 0h N/A (Hard-coded)

Headphone amp present: 1 = yes, 0 = no.

PresDtctCap 2 R 1h N/A (Hard-coded)

Presence detection support: 1 = yes, 0 = no.

TrigRqd 1 R 0h N/A (Hard-coded)

Trigger required for impedance sense: 1 = yes, 0 = no.

ImpSenseCap 0 R 0h N/A (Hard-coded)

Impedance sense support: 1 = yes, 0 = no.

7.26.2. Dig0Pin (NID = 1Fh): ConLst

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set

Get F000Eh

Field Name Bits R/W Default Reset

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Field Name Bits R/W Default Reset

Rsvd 31:8 R000000h N/A (Hard-coded)

Reserved.

LForm 7 R 0h N/A (Hard-coded)

Connection list format: 1 = long-form (15-bit) NID entries, 0 = short-form (7-bit)

NID entries.

ConL 6:0 R01h N/A (Hard-coded)

Number of NID entries in connection list.

7.26.3. Dig0Pin (NID = 1Fh): ConLstEntry0

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set

Get F0200h

Field Name Bits R/W Default Reset

ConL3 31:24 R00h N/A (Hard-coded)

Unused list entry.

ConL2 23:16 R00h N/A (Hard-coded)

Unused list entry.

ConL1 15:8 R00h N/A (Hard-coded)

Unused list entry.

ConL0 7:0 R1Dh N/A (Hard-coded)

SPDIFOut0 Converter widget (0x1D)

7.26.4. Dig0Pin (NID = 1Fh): PwrState

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 705h

Get F0500h

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Field Name Bits R/W Default Reset

Rsvd4 31:11 R000000h N/A (Hard-coded)

Reserved.

SettingsReset 10 R1h POR - DAFG - ULR

Indicates if any persistent settings in this Widget have been reset. Cleared by

PwrState 'Get', or a 'Set' to any Verb in this Widget.

Rsvd3 9 R 0h N/A (Hard-coded)

Reserved.

Error 8 R 0h POR - DAFG - ULR

Error indicator: 1 = cannot enter requested power state, 0 = no problem with

requested power state.

Rsvd2 7:6 R0h N/A (Hard-coded)

Reserved.

Act 5:4 R3h POR - DAFG - LR

Actual power state of this widget.

Rsvd1 3:2 R0h N/A (Hard-coded)

Reserved.

Set 1:0 RW 0h POR - DAFG - LR

Current power state setting for this widget.

7.26.5. Dig0Pin (NID = 1Fh): PinWCntrl

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 707h

Get F0700h

Field Name Bits R/W Default Reset

Rsvd2 31:7 R0000000h N/A (Hard-coded)

Reserved.

OutEn 6RW 0h POR - DAFG - ULR

Output enable: 1 = enabled, 0 = disabled.

TSI™ CONFIDENTIAL

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Rsvd1 5:0 R00h N/A (Hard-coded)

Reserved.

7.26.6. Dig0Pin (NID = 1Fh): UnsolResp

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 708h

Get F0800h

Field Name Bits R/W Default Reset

Rsvd2 31:8 R000000h N/A (Hard-coded)

Reserved.

En 7RW 0h POR - DAFG - ULR

Unsolicited response enable (also enables Wake events for this Widget): 1 =

enabled, 0 = disabled.

Rsvd1 6 R 0h N/A (Hard-coded)

Reserved.

Tag 5:0 RW 00h POR - DAFG - ULR

Software programmable field returned in top six bits (31:26) of every Unsolicit-

ed Response generated by this node.

7.26.7. Dig0Pin (NID = 1Fh): ChSense

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 709h

Get F0900h

Field Name Bits R/W Default Reset

PresDtct 31 R0h POR

Presence detection indicator: 1 = presence detected; 0 = presence not detect-

ed.

Field Name Bits R/W Default Reset

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Rsvd 30:0 R00000000h N/A (Hard-coded)

Reserved.

7.26.8. Dig0Pin (NID = 1Fh): ConfigDefault

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 71Fh 71Eh 71Dh 71Ch

Get F1F00h / F1E00h / F1D00h / F1C00h

Field Name Bits R/W Default Reset

PortConnectivity 31:30 RW 0h POR

Port connectivity:

0h = Port complex is connected to a jack

1h = No physical connection for port

2h = Fixed function device is attached

3h = Both jack and internal device attached (info in all other fields refers to in-

tegrated device, any presence detection refers to jack)

Location 29:24 RW 1h POR

Location

Bits [5..4]:

0h = External on primary chassis

1h = Internal

2h = Separate chassis

3h = Other

Bits [3..0]:

0h = N/A

1h = Rear

2h = Front

3h = Left

4h = Right

5h = Top

6h = Bottom

7h-9h = Special

Ah-Fh = Reserved

Field Name Bits R/W Default Reset

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Device 23:20 RW 4h POR

Default device:

0h = Line out

1h = Speaker

2h = HP out

3h = CD

4h = SPDIF Out

5h = Digital other out

6h = Modem line side

7h = Modem handset side

8h = Line in

9h = Aux

Ah = Mic in

Bh = Telephony

Ch = SPDIF In

Dh = Digital other in

Eh = Reserved

Fh = Other

ConnectionType 19:16 RW 5h POR

Connection type:

0h = Unknown

1h = 1/8" stereo/mono

2h = 1/4" stereo/mono

3h = ATAPI internal

4h = RCA

5h = Optical

6h = Other digital

7h = Other analog

8h = Multichannel analog (DIN)

9h = XLR/Professional

Ah = RJ-11 (modem)

Bh = Combination

Ch-Eh = Reserved

Fh = Other

Field Name Bits R/W Default Reset

TSI™ CONFIDENTIAL

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Color 15:12 RW 1h POR

Color:

0h = Unknown

1h = Black

2h = Grey

3h = Blue

4h = Green

5h = Red

6h = Orange

7h = Yellow

8h = Purple

9h = Pink

Ah-Dh = Reserved

Eh = White

Fh = Other

Misc 11:8 RW 1h POR

Miscellaneous:

Bits [3..1] = Reserved

Bit 0 = Jack detect override

Association 7:4 RW 6h POR

Default assocation.

Sequence 3:0 RW 0h POR

Sequence.

7.27. Dig1Pin (NID = 20h): WCap

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set

Get F0009h

Field Name Bits R/W Default Reset

Rsvd2 31:24 R00h N/A (Hard-coded)

Reserved.

Field Name Bits R/W Default Reset

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Type 23:20 R4h N/A (Hard-coded)

Widget type:

0h = Out Converter

1h = In Converter

2h = Summing (Mixer)

3h = Selector (Mux)

4h = Pin Complex

5h = Power

6h = Volume Knob

7h = Beep Generator

8h-Eh = Reserved

Fh = Vendor Defined

Delay 19:16 R0h N/A (Hard-coded)

Number of sample delays through widget.

Rsvd1 15:12 R0h N/A (Hard-coded)

Reserved.

SwapCap 11 R0h N/A (Hard-coded)

Left/right swap support: 1 = yes, 0 = no.

PwrCntrl 10 R1h N/A (Hard-coded)

Power state support: 1 = yes, 0 = no.

Dig 9 R 1h N/A (Hard-coded)

Digital stream support: 1 = yes (digital), 0 = no (analog).

ConnList 8 R 1h N/A (Hard-coded)

Connection list present: 1 = yes, 0 = no.

UnSolCap 7 R 1h N/A (Hard-coded)

Unsolicited response support: 1 = yes, 0 = no.

ProcWidget 6 R 0h N/A (Hard-coded)

Processing state support: 1 = yes, 0 = no.

Stripe 5 R 0h N/A (Hard-coded)

Striping support: 1 = yes, 0 = no.

FormatOvrd 4 R 0h N/A (Hard-coded)

Stream format override: 1 = yes, 0 = no.

Field Name Bits R/W Default Reset

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AmpParOvrd 3 R 0h N/A (Hard-coded)

Amplifier capabilities override: 1 = yes, no.

OutAmpPrsnt 2 R 0h N/A (Hard-coded)

Output amp present: 1 = yes, 0 = no.

InAmpPrsnt 1 R 0h N/A (Hard-coded)

Input amp present: 1 = yes, 0 = no.

Stereo 0 R 1h N/A (Hard-coded)

Stereo stream support: 1 = yes (stereo), 0 = no (mono).

7.27.1. Dig1Pin (NID = 20h): PinCap

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set

Get F000Ch

Field Name Bits R/W Default Reset

Rsvd2 31:17 R0000h N/A (Hard-coded)

Reserved.

EapdCap 16 R0h N/A (Hard-coded)

EAPD support: 1 = yes, 0 = no.

VrefCntrl 15:8 R00h N/A (Hard-coded)

Vref support:

bit 7 = Reserved

bit 6 = Reserved

bit 5 = 100% support (1 = yes, 0 = no)

bit 4 = 80% support (1 = yes, 0 = no)

bit 3 = Reserved

bit 2 = GND support (1 = yes, 0 = no)

bit 1 = 50% support (1 = yes, 0 = no)

bit 0 = Hi-Z support (1 = yes, 0 = no)

Rsvd1 7 R 0h N/A (Hard-coded)

Reserved.

Field Name Bits R/W Default Reset

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BalancedIO 6 R 0h N/A (Hard-coded)

Balanced I/O support: 1 = yes, 0 = no.

InCap 5 R 1h N/A (Hard-coded)

Input support: 1 = yes, 0 = no.

OutCap 4 R 1h N/A (Hard-coded)

Output support: 1 = yes, 0 = no.

HdphDrvCap 3 R 0h N/A (Hard-coded)

Headphone amp present: 1 = yes, 0 = no.

PresDtctCap 2 R 1h N/A (Hard-coded)

Presence detection support: 1 = yes, 0 = no.

TrigRqd 1 R 0h N/A (Hard-coded)

Trigger required for impedance sense: 1 = yes, 0 = no.

ImpSenseCap 0 R 0h N/A (Hard-coded)

Impedance sense support: 1 = yes, 0 = no.

7.27.2. Dig1Pin (NID = 20h): ConLst

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set

Get F000Eh

Field Name Bits R/W Default Reset

Rsvd 31:8 R000000h N/A (Hard-coded)

Reserved.

LForm 7 R 0h N/A (Hard-coded)

Connection list format: 1 = long-form (15-bit) NID entries, 0 = short-form (7-bit)

NID entries.

ConL 6:0 R01h N/A (Hard-coded)

Number of NID entries in connection list.

Field Name Bits R/W Default Reset

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7.27.3. Dig1Pin (NID = 20h): ConLstEntry0

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set

Get F0200h

Field Name Bits R/W Default Reset

ConL3 31:24 R00h N/A (Hard-coded)

Unused list entry.

ConL2 23:16 R00h N/A (Hard-coded)

Unused list entry.

ConL1 15:8 R00h N/A (Hard-coded)

Unused list entry.

ConL0 7:0 R1Eh N/A (Hard-coded)

SPDIFOut1 Converter widget (0x1E)

7.27.4. Dig1Pin (NID = 20h): PwrState

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 705h

Get F0500h

Field Name Bits R/W Default Reset

Rsvd4 31:11 R000000h N/A (Hard-coded)

Reserved.

SettingsReset 10 R1h POR - DAFG - ULR

Indicates if any persistent settings in this Widget have been reset. Cleared by

PwrState 'Get', or a 'Set' to any Verb in this Widget.

Rsvd3 9 R 0h N/A (Hard-coded)

Reserved.

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Error 8 R 0h POR - DAFG - ULR

Error indicator: 1 = cannot enter requested power state, 0 = no problem with

requested power state.

Rsvd2 7:6 R0h N/A (Hard-coded)

Reserved.

Act 5:4 R3h POR - DAFG - LR

Actual power state of this widget.

Rsvd1 3:2 R0h N/A (Hard-coded)

Reserved.

Set 1:0 RW 0h POR - DAFG - LR

Current power state setting for this widget.

7.27.5. Dig1Pin (NID = 20h): PinWCntrl

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 707h

Get F0700h

Field Name Bits R/W Default Reset

Rsvd2 31:7 R0000000h N/A (Hard-coded)

Reserved.

OutEn 6RW 0h POR - DAFG - ULR

Output enable: 1 = enabled, 0 = disabled.

InEn 5RW 0h POR - DAFG - ULR

Input enable: 1 = enabled, 0 = disabled.

Rsvd1 4:0 R00h N/A (Hard-coded)

Reserved.

Field Name Bits R/W Default Reset

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7.27.6. Dig1Pin (NID = 20h): ConfigDefault

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 71Fh 71Eh 71Dh 71Ch

Get F1F00h / F1E00h / F1D00h / F1C00h

Field Name Bits R/W Default Reset

PortConnectivity 31:30 RW 2h POR

Port connectivity:

0h = Port complex is connected to a jack

1h = No physical connection for port

2h = Fixed function device is attached

3h = Both jack and internal device attached (info in all other fields refers to in-

tegrated device, any presence detection refers to jack)

Location 29:24 RW 18h POR

Location

Bits [5..4]:

0h = External on primary chassis

1h = Internal

2h = Separate chassis

3h = Other

Bits [3..0]:

0h = N/A

1h = Rear

2h = Front

3h = Left

4h = Right

5h = Top

6h = Bottom

7h-9h = Special

Ah-Fh = Reserved

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Device 23:20 RW 5h POR

Default device:

0h = Line out

1h = Speaker

2h = HP out

3h = CD

4h = SPDIF Out

5h = Digital other out

6h = Modem line side

7h = Modem handset side

8h = Line in

9h = Aux

Ah = Mic in

Bh = Telephony

Ch = SPDIF In

Dh = Digital other in

Eh = Reserved

Fh = Other

ConnectionType 19:16 RW 6h POR

Connection type:

0h = Unknown

1h = 1/8" stereo/mono

2h = 1/4" stereo/mono

3h = ATAPI internal

4h = RCA

5h = Optical

6h = Other digital

7h = Other analog

8h = Multichannel analog (DIN)

9h = XLR/Professional

Ah = RJ-11 (modem)

Bh = Combination

Ch-Eh = Reserved

Fh = Other

Field Name Bits R/W Default Reset

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Color 15:12 RW 0h POR

Color:

0h = Unknown

1h = Black

2h = Grey

3h = Blue

4h = Green

5h = Red

6h = Orange

7h = Yellow

8h = Purple

9h = Pink

Ah-Dh = Reserved

Eh = White

Fh = Other

Misc 11:8 RW 1h POR

Miscellaneous:

Bits [3..1] = Reserved

Bit 0 = Jack detect override

Association 7:4 RW 7h POR

Default assocation.

Sequence 3:0 RW 0h POR

Sequence.

Field Name Bits R/W Default Reset

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7.28. DigBeep (NID = 21h): WCap

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set

Get F0009h

Field Name Bits R/W Default Reset

Rsvd4 31:24 R00h N/A (Hard-coded)

Reserved.

Type 23:20 R7h N/A (Hard-coded)

Widget type:

0h = Out Converter

1h = In Converter

2h = Summing (Mixer)

3h = Selector (Mux)

4h = Pin Complex

5h = Power

6h = Volume Knob

7h = Beep Generator

8h-Eh = Reserved

Fh = Vendor Defined

Rsvd3 19:11 R0h N/A (Hard-coded)

Reserved.

PwrCntrl 10 R1h N/A (Hard-coded)

Power state support: 1 = yes, 0 = no."

Rsvd2 9:4 R0h N/A (Hard-coded)

Reserved

AmpParOvrd 3 R 1h N/A (Hard-coded)

Amplifier capabilities override: 1 = yes, no.

OutAmpPrsnt 2 R 1h N/A (Hard-coded)

Output amp present: 1 = yes, 0 = no.

Rsvd1 1:0 R0h N/A (Hard-coded)

Reserved.

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7.28.1. DigBeep (NID = 21h): OutAmpCap

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set

Get F0012h

Field Name Bits R/W Default Reset

Mute 31 R1h N/A (Hard-coded)

Mute support: 1 = yes, 0 = no.

Rsvd3 30:23 R00h N/A (Hard-coded)

Reserved.

StepSize 22:16 R17h N/A (Hard-coded)

Size of each step in the gain range: 0 to 127 = .25dB to 32dB, in .25dB steps.

Rsvd2 15 R0h N/A (Hard-coded)

Reserved.

NumSteps 14:8 R03h N/A (Hard-coded)

Number of gains steps (number of possible settings - 1).

Rsvd1 7 R 0h N/A (Hard-coded)

Reserved.

Offset 6:0 R03h N/A (Hard-coded)

Indicates which step is 0dB

7.28.2. DigBeep (NID = 21h): OutAmpLeft

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 3A0h

Get BA000h

Field Name Bits R/W Default Reset

Rsvd2 31:8 R000000h N/A (Hard-coded)

Reserved.

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Mute 7RW 0h POR - DAFG - ULR

Amp mute: 1 = muted, 0 = not muted.

Rsvd1 6:2 R00h N/A (Hard-coded)

Reserved.

Gain 1:0 RW 1h POR - DAFG - ULR

Amp gain step number (see OutAmpCap parameter pertaining to this widget).

7.28.3. DigBeep (NID = 21h): PwrState

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 705h

Get F0500h

Field Name Bits R/W Default Reset

Rsvd4 31:11 R000000h N/A (Hard-coded)

Reserved.

SettingsReset 10 R1h POR - DAFG - ULR

Indicates if any persistent settings in this Widget have been reset. Cleared by

PwrState 'Get', or a 'Set' to any Verb in this Widget.

Rsvd3 9 R 0h N/A (Hard-coded)

Reserved.

Error 8 R 0h POR - DAFG - ULR

Error indicator: 1 = cannot enter requested power state, 0 = no problem with

requested power state.

Rsvd2 7:6 R0h N/A (Hard-coded)

Reserved.

Act 5:4 R3h POR - DAFG - LR

Actual power state of this widget.

Rsvd1 3:2 R0h N/A (Hard-coded)

Reserved.

Field Name Bits R/W Default Reset

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Set 1:0 RW 0h POR - DAFG - LR

Current power state setting for this widget.

7.28.4. DigBeep (NID = 21h): Gen

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 70Ah

Get F0A00h

Field Name Bits R/W Default Reset

Rsvd 31:8 R000000h N/A (Hard-coded)

Reserved.

Divider 7:0 RW 00h POR - DAFG - LR

Enable internal PC-Beep generation. Divider == 00h disables internal PC Beep

generation and enables normal operation of the codec. Divider != 00h gener-

ates the beep tone on all Pin Complexes that are currently configured as out-

puts. The HD Audio spec states that the beep tone frequency = (48kHz HD

Audio SYNC rate) / (4*Divider), producing tones from 47 Hz to 12 kHz (logarith-

mic scale).

7.28.5. DigBeep (NID = 21h): Gain

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 77Ah

Get F7A00h

Field Name Bits R/W Default Reset

Rsvd 31:3 R000000h N/A (Hard-coded)

Reserved.

Divider 2:0 RW 05h POR - DAFG - LR

Digital PC Beep Gain adjust in digital side 0h = -9dB, 1h = -6dB, 2h = -3dB, 3h

= 0dB, 4h = +3db, 5h = +6db

Field Name Bits R/W Default Reset

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This register is reset by POR

7.29. AdvancedFunctions (NID = 22h): WCap

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set

Get F0009h

Field Name Bits R/W Default Reset

Rsvd2 31:24 R00h N/A (Hard-coded)

Reserved.

Type 23:20 RFh N/A (Hard-coded)

Widget type:

0h = Out Converter

1h = In Converter

2h = Summing (Mixer)

3h = Selector (Mux)

4h = Pin Complex

5h = Power

6h = Volume Knob

7h = Beep Generator

8h-Eh = Reserved

Fh = Vendor Defined

Delay 19:16 R0h N/A (Hard-coded)

Number of sample delays through widget.

Rsvd1 15:12 R0h N/A (Hard-coded)

Reserved.

SwapCap 11 R0h N/A (Hard-coded)

Left/right swap support: 1 = yes, 0 = no.

PwrCntrl 10 R0h N/A (Hard-coded)

Power state support: 1 = yes, 0 = no.

Dig 9 R 0h N/A (Hard-coded)

Digital stream support: 1 = yes (digital), 0 = no (analog).

ConnList 8 R 0h N/A (Hard-coded)

Connection list present: 1 = yes, 0 = no.

UnSolCap 7 R 0h N/A (Hard-coded)

Unsolicited response support: 1 = yes, 0 = no.

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All registers are available when in normal mode through the HD Audio interface. Most are

implemented using vendor defined verbs but some (volume controls specifically) are sup-

ported through standard verbs at the pin widgets

This register is reset by POR

ProcWidget 6 R 0h N/A (Hard-coded)

Processing state support: 1 = yes, 0 = no.

Stripe 5 R 0h N/A (Hard-coded)

Striping support: 1 = yes, 0 = no.

FormatOvrd 4 R 0h N/A (Hard-coded)

Stream format override: 1 = yes, 0 = no.

AmpParOvrd 3 R 0h N/A (Hard-coded)

Amplifier capabilities override: 1 = yes, no.

OutAmpPrsnt 2 R 0h N/A (Hard-coded)

Output amp present: 1 = yes, 0 = no.

InAmpPrsnt 1 R 0h N/A (Hard-coded)

Input amp present: 1 = yes, 0 = no.

Stereo 0 R 1h N/A (Hard-coded)

Stereo stream support: 1 = yes (stereo), 0 = no (mono).

7.29.1. AdvancedFunctions (NID = 22h): Cntrl0

Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0)

Set 770h:&7AFh

Get F7700h: 7AF0h

Field Name Bits R/W Default Reset

Rsvd 31:8 R000000h N/A (Hard-coded)

Reserved.

Value 7:0 RW 0h POR - DAFG - ULR

Contrl register value of module

Field Name Bits R/W Default Reset

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7.29.1.1. SPKVOL L/R Registers

Prior to WC revision, this register reset by POR/DAFG/ULR. WC revision, reset by POR only. Writing

to NID22h verb 77F will cause reset on all silicon revisions.

7.29.1.2. PWRM Register

Prior to WC revision, this register reset by POR/DAFG/ULR. WC revision, reset by POR only. Writing

to NID22h verb 77F will cause reset on all silicon revisions.

verb F71/771 (Left)

verb F72/772 (Right)

verb 773 (Left and Right -

write only)

7:0 VOL[7:0] RW 30

+36 to -91.5dB in 0.75dB steps

0x00 = +36dB

0x01 = +35.25dB

...

0x2F = +0.75dB

0x30 = 0dB

0x31 = -0.75dB

...

0xA9 = -90.75

0xAA to 0xFE = -91.5dB

0xFF = mute

verb F79/779

7 RSVD RO 0 Reserved

6 RSVD RO 0 Reserved

5 RSVD RO 0 Reserved

4 HPPWD RW 0 Headphone ports are forced off in Aux Audio Mode (including

charge pump)

3 SPKRON RW 0 BTL (port D) is forced on in Aux Audio Mode

2 DMICPWD RW 0 DMIC powered down in Aux Audio Mode (including DAC)

1 RSVD RW 0 Reserved

0 RSVD RW 0 Reserved

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7.29.1.3. RESET Register

7.29.1.4. STATUS Register

Prior to WC revision, this register reset by POR/DAFG/ULR. WC revision, reset by POR only. Writing

to NID22h verb 77F will cause reset on all silicon revisions.

7.29.1.5. INIT Register

Prior to WC revision, this register reset by POR/DAFG/ULR. WC revision, reset by POR only. Writing

to NID22h verb 77F will cause reset on all silicon revisions.

verb F7F/77F 7:0 RESET RW 0 Writing causes registers to revert to their default values (similar

to a function group reset)

verb F80/780

7 limit1latch RO 0 Latched version of limit1, clear via GAINCTRL_LO[7]

6 limit0latch RO 0 Latched version of limit0, clear via GAINCTRL_LO[7]

5:3 Reserved RO 0x0 RESERVED

2 limit1 RO 0 Set (1) if regz saturation after gain multiply for CH1. may

change on a sample by sample basis.

1 limit0 RO 0 Set (1) if regz saturation after gain multiply for CH0. may

change on a sample by sample basis.

0 zerodet_flag RO 0 Set when input zero detect of long string of zeroes.

verb F81/781

7:4 Reserved RO 0 RESERVED

3 anabeep_dcbyp RW 0 1 = bypass analog Beep DC filter

2:1 anabeep_dc_coef

fRW 0x2

0: dc_coef = 24’h004000;

1: dc_coef = 24’h001000;

2: dc_coef = 24’h000400;

3: dc_coef = 24’h000100;

0 Initialize RW 0 1= Initialize/soft reset data path. Must be set when changing

the config0 or config1 registers.

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7.29.1.6. CONFIG Register

Prior to WC revision, this register reset by POR/DAFG/ULR. WC revision, reset by POR only. Writing

to NID22h verb 77F will cause reset on all silicon revisions.

7.29.1.7. PWM4 Register

Prior to WC revision, this register reset by POR/DAFG/ULR. WC revision, reset by POR only. Writing

to NID22h verb 77F will cause reset on all silicon revisions.

7.29.1.8. PWM3 Register

Prior to WC revision, this register reset by POR/DAFG/ULR. WC revision, reset by POR only. Writing

to NID22h verb 77F will cause reset on all silicon revisions.

verb F82/782

7 BPFBYP RW 0 1= Bypass MonoOut band-pass filer

6 PREBYP RW 1 1= Bypass BTL EQ filter prescale

5 EQBYP RW 1 1= Bypass BTL EQ filter

4 BTL_dcbyp RW 0 1 = bypass BTL DC filter

3:1 Reserved RO 0 RESERVED

0 HPFBYP RW 0 1= Bypass BTL high-pass filter (not DC removal filter)

verb F83/783

7 sc_status_clear_right RWC 0 Write once operation will clear sc_fault_status_right

6 sc_status_clear_left RWC 0 Write once operation will clear sc_fault_status_left

5 Reserved RO 0 RESERVED

4 sc_Fault_status_right RO 0 1 = Fault occurs on right channel

3 sc_Fault_status_left RO 0 1 = Fault occurs on left channel

2:1 scdly_set RW 00 Used for short circuit detection; designer will set the value

0 evenbit RW 0 1=Noise Shaper output data are even

verb F84/784

7:6 outctrl RW 0

pwm output muxing

0 = normal

1 = swap 0/1

2 = ch0 on both

3 = ch1 on both

5:0 cvalue RW 0x2 Tristate constant value filed, must be even and not 0

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7.29.1.9. PWM2 Register

Prior to WC revision, this register reset by POR/DAFG/ULR. WC revision, reset by POR only. Writing

to NID22h verb 77F will cause reset on all silicon revisions.

7.29.1.10. PWM1Register

Prior to WC revision, this register reset by POR/DAFG/ULR. WC revision, reset by POR only. Writing

to NID22h verb 77F will cause reset on all silicon revisions.

7.29.1.11. PWM0 Register

Prior to WC revision, this register reset by POR/DAFG/ULR. WC revision, reset by POR only. Writing

to NID22h verb 77F will cause reset on all silicon revisions.

verb F85/785

7:2 dvalue RW 0x10 dvalue constant field.

1 pwm_outflip RW 0 1= swap pwm a/b output pair for all channels

0 pwm_outmode RW 1 1= tristate, 0 = binary

verb F86/786

7 Reserved RO 0 RESERVED

6:2 dithpos RW 0

Dither position, where dither inserted after NS

0,1,2 = dither bits 2:0

4 = dither bits 3:1

5 = dither bits 4:1

...

19 = dither bits 19:17

1 dither_range RW 0 1= dither -1 to +1, 0 = dither -3 to +3

0 dithclr RW 0 1 = disable dither

verb F87/787

7:6 PhaseOffset RW 01

PWM ch1 offset from ch0 at 8x sample rate by:

00 = 0 degrees

01 = 90 degrees

10 = 180 degrees

11 = NA

5 clk320mode R 1 1 = PCA clock 320 mode

0 = PCA clock 294 mode

4 roundup RW 1 1= roundup, 0 = truncate for quantizer

3 bfclr RW 0 1 = disable binomial filter

2 fourthorder RW 0 1 = fourth order binomial filter, 0 = 3rd order binomial filter

1 add3_sel RW 0 1 = 24-bit Noise Shaper output (pre-quantizer), 0 = 8/9/10-bit

quantizer output

0 Btl_test_mode RW 0 1 = power stage test mode

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7.29.1.12. LMTCTRL Register

Control operation of the volume Limiter (Compressor).

Prior to WC revision, this register reset by POR/DAFG/ULR. WC revision, reset by POR only. Writing

to NID22h verb 77F will cause reset on all silicon revisions.

7.29.1.13. LMTATKTIME (0x19), LMTHOLDTIME (0x1A), LMTRELTIME (0x1B) Registers

These 8-bit registers set the timer values between incrementing/decrementing the Compressor attenuation values. There is

one register each for Attack, Hold, and Release times, the configuration parameters are the same for all three and are

shown in the table below.

Prior to WC revision, these registers reset by POR/DAFG/ULR. WC revision, reset by POR only. Writing to NID22h verb

77F will cause reset on all silicon revisions..

7.29.1.14. LMTATKTH (0x1D–LO, 0x1C–HI), LMTRELTH (0x1F–LO, 0x1E–HI) Registers

These 16-bit registers set the threshold values. When in attack phase and the Attack Threshold is exceeded the

Compressor attenuation is incremented by stepsize (see LMTCTRL). When in release phase and the Release Threshold is

not exceeded the Compressor attenuation is incremented by stepsize (but not above 0)

Prior to WC revision, these registers reset by POR/DAFG/ULR. WC revision, reset by POR only. Writing to NID22h verb

77F will cause reset on all silicon revisions..

verb F88/788

7:4 – RO 0 Reserved for future use.

3 zerocross RW 0 1 = only change limiter gain value on zero cross.

2:1 stepsize RW 0 Gain stepsize when incrementing or decrementing:

0 - 0.75 dB, 1 - 1.5 dB, 2 - 3.0 dB, 3 - 6.0 dB

0 limiter_en RW 0 1 = enable limiter (compressor)

verb F89/789

7 ATK10ms RW 0 1 = value in bits 6:0 is in 10ms units, otherwise 1ms units.

6:0 LMTAT[6:0] RW 0 Timer value in units of 1 or 10ms.

verb F8A/78A

7 HOLD10ms RW 0 1 = value in bits 6:0 is in 10ms units, otherwise 1ms units.

6:0 LMTHT[6:0] RW 0 Timer value in units of 1 or 10ms.

verb F8B/78B

7 REL10ms RW 0 1 = value in bits 6:0 is in 10ms units, otherwise 1ms units.

6:0 LMTRT[6:0] RW 0 Timer value in units of 1 or 10ms.

verb F8C/78C 7:0 LATKTH[15:8] RW 7F 8’hFF would equal threshold level of +2.0dB. Each step below

this 8-bit full scale value reduces threshold level by 0.0078 dB.

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7.29.1.15. GAINCTRL_HI Register

Prior to WC revision, this register reset by POR/DAFG/ULR. WC revision, reset by POR only. Writing

to NID22h verb 77F will cause reset on all silicon revisions.

7.29.1.16. GAINCTRL_LO Register

Prior to WC revision, this register reset by POR/DAFG/ULR. WC revision, reset by POR only. Writing

to NID22h verb 77F will cause reset on all silicon revisions.

verb F8D/78D 7:0 LATKTH[7:0] RW FF Always 0. It isn’t necessary to provide threshold resolution to

the point where these lower 8 bits would be used.

verb F8E/78E 7:0 LRELTH[15:8] RW 0 8’hFF would equal threshold level of +2.0dB. Each step below

this 8-bit full scale value reduces threshold level by 0.0078 dB.

verb F8F/78F 7:0 LRELTH[7:0] RW 0 Always 0. It isn’t necessary to provide threshold resolution to

the point where these lower 8 bits would be used.

verb F90/790

7:5 Reserved RO 0 RESERVED

4:3 zerodetlen RW 0x2

enable mute if input consecutive zeros exceeds this length:

00 = 32

01 = 1000

10 = 2000

11 = 4000

2:0 step_time RW 0x5 step time units = 1<<step_time, units in GAINCTRL_LO bit 5

verb F91/791

7 clr_latch RW 0 1 = clear limit 0/1 latches, see STATUS register

6 RSVD RO 0 Reserved

5 step_10ms RW 0 1 = units for step_time are 10ms

0 = units for step_time are 1ms

4 stepped_change RW 0 1 = step volume progressively to new setting

3 disable_gain RW 0 1 = disable all gain functions (bypass gain multiply)

2 auto_mute RW 1 1 = auto mute if detect long strings of zeros on input

1 change_mode RW 0 1 = change gain immediately

0 = change on zero cross

0 mute_mode RW 1 1 = hard mute after reset, 0 = soft mute

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7.29.1.17. MUTE Register

Prior to WC revision, this register reset by POR/DAFG/ULR. WC revision, reset by POR only. Writing

to NID22h verb 77F will cause reset on all silicon revisions.

7.29.1.18. ATTEN Register

Prior to WC revision, this register reset by POR/DAFG/ULR. WC revision, reset by POR only. Writing

to NID22h verb 77F will cause reset on all silicon revisions.

7.29.1.19. DC_COEF_SEL Register

Prior to WC revision, this register reset by POR/DAFG/ULR. WC revision, reset by POR only. Writing

to NID22h verb 77F will cause reset on all silicon revisions.

verb F92/792

7:3 Reserved RO 0x0 RESERVED

2 Mute RW 0 1 = mute all channels

1 mute1 RW 0 1 = mute ch1

0 mute0 RW 0 1 = mute ch0

verb F93/793 7:0 atten RW 0x0

Attenuation. Each bit represents 0.5dB of attenuation to be

applied to the channel. The range will be -125dB to 2dB as

follows:

0x00: +2dB

0x01: +1.5dB

0x02: +1.0dB

...

0x47: -33.5dB

0x48: -34.0dB

0x49: -34.5dB

...

0xFE: -125dB

0xFF: Hard Master Mute

verb F94/794

7:3 Reserved RO 0 RESERVED

2:0 dc_coef_sel RW 0x5

0:dc_coef = 24’h100000;

//2^^-3 = 0.125

1:dc_coef = 24’h040000;

2:dc_coef = 24’h010000;

3:dc_coef = 24’h004000;

4:dc_coef = 24’h001000;

5:dc_coef = 24’h000400;

6:dc_coef = 24’h000100;

//2^^-15 = 0.000330517

7:dc_coef = 24’h000040;

//2^^-17

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7.29.1.20. BTL High-Pass Filter COEF_SEL Register

Prior to WC revision, this register reset by POR/DAFG/ULR. WC revision, reset by POR only. Writing

to NID22h verb 77F will cause reset on all silicon revisions.

7.29.1.21. Mono Band-Pass Filter COEF_SEL Register

Prior to WC revision, this register reset by POR/DAFG/ULR. WC revision, reset by POR only. Writing

to NID22h verb 77F will cause reset on all silicon revisions.

verb F95/795

7:3 Reserved RO 0 RESERVED

2:0 hp_coef_sel RW 0x2

Select IIR coefficients for BTL amplifier high pass filter corner

frequency

000 = 100Hz

001 = 200Hz

010 = 300Hz

011 = 400Hz

100 = 500Hz

101 = 750Hz

110 = 1000Hz

111 = 2000Hz

verb F96/796

7 Reserved RO 0 RESERVED

6:4 bph_coef_sel RW 0x3

Select IIR coefficients for MonoOut band-pass filter lower

corner frequency

000 = 63Hz

001 = 80Hz

010 = 100Hz

011 = 120Hz

100 = 150Hz

101 = 200Hz

110 = 315Hz

111 = 400Hz

3 Reserved RO 0 RESERVED

2:0 bpl_coef_sel RW 0x2

Select IIR coefficients for MonoOut band-pass filter upper

corner frequency

000 = 150Hz

001 = 200Hz

010 = 250Hz

011 = 315Hz

100 = 400Hz

101 = 500Hz

110 = 630Hz

111 = 800Hz

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7.29.1.22. BTL Class-D Power Stage Register Settings

Prior to WC revision, these registers reset by POR/DAFG/ULR. WC revision, reset by POR only.

Writing to NID22h verb 77F will cause NOT generate a reset.

verb F97/797

7 ENABLE RW 1 1 = Enable BTL Power stage

6 TRC_ESD RO 0 1 = ESD trigger detected

0 = No trigger

5 STRENDRV RW 0 1 = Strengthen pre-drive

0 = Normal

4:3 SCTHR RW 01

Short circuit threshold current

00 = 10% of PVDD

01 = 14% of PVDD

10 = 16% of PVDD

11 = 20% of PVDD

2:0 DEADTIME RW 001

Dead time for output FETs

000 = 0.5ns

001 = 1.0ns

010 = 1.5ns

011 = 2ns

100 = 4ns

101 = 8ns

110 = 8ns

111 = 8ns

verb F98/798

7 TEST_EN RW 0 1 = Enable short circuit test

6 SC_DIS RW 0 1 = disable short circuit protection

5 RSVD RW 0 Reserved

4 FAULT_SC RO 0 1 = Fault

3 RSVD RW 0 Reserved

2 PNSEL RW 0 1=PFET tested, 0=NFET tested

1 FORCE_SC RW 0 1 = force short circuit

0 TEST RW 0 1 = Pos PFET / Neg NFET on, 0 = Pos NFET / Neg PFET on

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verb F99/799

7 ENABLE RW 1 1 = Enable BTL Power stage

6 TRC_ESD RO 0 1 = ESD trigger detected

0 = No trigger

5 STRENDRV RW 0 1 = Strengthen pre-drive

0 = Normal

4:3 SCTHR RW 01

Short circuit threshold current

00 = 10% of PVDD

01 = 14% of PVDD

10 = 16% of PVDD

11 = 20% of PVDD

2:0 DEADTIME RW 001

Dead time for output FETs

000 = 0.5ns

001 = 1.0ns

010 = 1.5ns

011 = 2ns

100 = 4ns

101 = 8ns

110 = 8ns

111 = 8ns

verb F9A/79A

7 TEST_EN RW 0 1 = Enable short circuit test

6 SC_DIS RW 0 1 = disable short circuit protection

5 RSVD RW 0 Reserved

4 FAULT_SC RO 0 1 = Fault

3 RSVD RW 0 Reserved

2 PNSEL RW 0 1=PFET tested, 0=NFET tested

1 FORCE_SC RW 0 1 = force short circuit

0 TEST RW 0 1 = Pos PFET / Neg NFET on, 0 = Pos NFET / Neg PFET on

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7.29.1.23. LDO LEVEL CONTROL Register

Prior to WC revision, this register reset by POR/DAFG/ULR. WC revision, reset by POR only. Writing

to NID22h verb 77F will cause NOT generate a reset.

7.29.1.24. EQRAM

The EQ RAM is a 52 x 48-bit SRAM that contains the EQ coefficients

Prior to WC revision, this register reset by POR/DAFG/ULR. WC revision, reset by POR only OR

when a BIST is run under certain conditions, contact TSI for more information. Writing to NID22h

verb 77F will cause NOT generate a reset..

verb F9B/79B

7:3 Reserved RO 0x0 RESERVED

2 Lv_QUAD_BIAS RW 0

1:0 Lv_reg_cntrl_bit RW 0x0

Two bits are defined to program the output of the 1.8V LDO

00 = normal operation (3.3V in to 1.8V out)

01 = 1.8V*1.1 = 1.98V

10 = 1.8V*0.9 = 1.62V

11 = power down LDO/bypass. When disabled, the

DVDD_Core pin must be supplied with a nominal 1.8V from

an external source.

Address Channel RIGHT Coefficients (24bit) Channel LEFT Coefficients (24bit)

EQRAM

Bits

[47:24] [23:00]

based on 44.1Khz sample rate

0x00 EQ_COEF_F0_B0 EQ_COEF_F0_B0

0x01 EQ_COEF_F0_B1 EQ_COEF_F0_B1

0x02 EQ_COEF_F0_B2 EQ_COEF_F0_B2

0x03 EQ_COEF_F0_A1 EQ_COEF_F0_A1

0x04 EQ_COEF_F0_A2 EQ_COEF_F0_A2

0x05 EQ_COEF_F1_B0 EQ_COEF_F1_B0

0x06 EQ_COEF_F1_B1 EQ_COEF_F1_B1

0x07 EQ_COEF_F1_B2 EQ_COEF_F1_B2

0x08 EQ_COEF_F1_A1 EQ_COEF_F1_A1

0x09 EQ_COEF_F1_A2 EQ_COEF_F1_A2

0x0A EQ_COEF_F2_B0 EQ_COEF_F2_B0

0x0B EQ_COEF_F2_B1 EQ_COEF_F2_B1

0x0C EQ_COEF_F2_B2 EQ_COEF_F2_B2

0x0D EQ_COEF_F2_A1 EQ_COEF_F2_A1

0x0E EQ_COEF_F2_A2 EQ_COEF_F2_A2

0x0F EQ_COEF_F3_B0 EQ_COEF_F3_B0

0x10 EQ_COEF_F3_B1 EQ_COEF_F3_B1

0x11 EQ_COEF_F3_B2 EQ_COEF_F3_B2

0x12 EQ_COEF_F3_A1 EQ_COEF_F3_A1

0x13 EQ_COEF_F3_A2 EQ_COEF_F3_A2

0x14 EQ_COEF_F4_B0 EQ_COEF_F4_B0

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The EQRAM is programmed indirectly through the Control Bus in the following manner:

1) Write the 48-bit write data to the EQRAM_WRITE register

2) Write the target address to the EQ_ADDRESS register

3) Set bit 7 of the EQRAM_CTRL register

The write will occur when the EQRAM is not being accessed by the DSP audio processing routines. When complete

the hardware will automatically clear this bit.

Reading back from the EQRAM is done in the following manner:

1) Write target address to EQ_ADDR register

2) Set bit 6 of the EQRAM_CTRL register

When the hardware completes the read it will automatically clear this bit.

3) When bit 6 of the EQRAM_CTRL register has been cleared, read the 48bit data from the EQRAM_READ register.

0x15 EQ_COEF_F4_B1 EQ_COEF_F4_B1

0x16 EQ_COEF_F4_B2 EQ_COEF_F4_B2

0x17 EQ_COEF_F4_A1 EQ_COEF_F4_A1

0x18 EQ_COEF_F4_A2 EQ_COEF_F4_A2

0x19 EQ_PRESCALE EQ_PRESCALE

based on 48Khz sample rate

0x1A EQ_COEF_F0_B0 EQ_COEF_F0_B0

0x1B EQ_COEF_F0_B1 EQ_COEF_F0_B1

0x1C EQ_COEF_F0_B2 EQ_COEF_F0_B2

0x1D EQ_COEF_F0_A1 EQ_COEF_F0_A1

0x1E EQ_COEF_F0_A2 EQ_COEF_F0_A2

0x1F EQ_COEF_F1_B0 EQ_COEF_F1_B0

0x20 EQ_COEF_F1_B1 EQ_COEF_F1_B1

0x21 EQ_COEF_F1_B2 EQ_COEF_F1_B2

0x22 EQ_COEF_F1_A1 EQ_COEF_F1_A1

0x23 EQ_COEF_F1_A2 EQ_COEF_F1_A2

0x24 EQ_COEF_F2_B0 EQ_COEF_F2_B0

0x25 EQ_COEF_F2_B1 EQ_COEF_F2_B1

0x26 EQ_COEF_F2_B2 EQ_COEF_F2_B2

0x27 EQ_COEF_F2_A1 EQ_COEF_F2_A1

0x28 EQ_COEF_F2_A2 EQ_COEF_F2_A2

0x29 EQ_COEF_F3_B0 EQ_COEF_F3_B0

0x2A EQ_COEF_F3_B1 EQ_COEF_F3_B1

0x2B EQ_COEF_F3_B2 EQ_COEF_F3_B2

0x2C EQ_COEF_F3_A1 EQ_COEF_F3_A1

0x2D EQ_COEF_F3_A2 EQ_COEF_F3_A2

0x2E EQ_COEF_F4_B0 EQ_COEF_F4_B0

0x2F EQ_COEF_F4_B1 EQ_COEF_F4_B1

0x30 EQ_COEF_F4_B2 EQ_COEF_F4_B2

0x31 EQ_COEF_F4_A1 EQ_COEF_F4_A1

0x32 EQ_COEF_F4_A2 EQ_COEF_F4_A2

0x33 EQ_PRESCALE EQ_PRESCALE

Address Channel RIGHT Coefficients (24bit) Channel LEFT Coefficients (24bit)

EQRAM

Bits

[47:24] [23:00]

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7.29.1.25. EQRAM Read Data (0x30–0x35), EQRAM Write Data (0x36–3B) Registers

These two 48-bit registers (addressed as 12 8-bit registers) are 48-bit data holding registers used

when doing indirect writes/reads to the EQRAM

Prior to WC revision, these registers reset by POR/DAFG/ULR. WC revision, reset by POR only

Writing to NID22h verb 77F will cause NOT generate a reset to EQRAMREAD registers, it will how-

ever work for EQRAMWRITE registers.]]

EQRAM_READ[47:40]

verb FA0/7A0 7:0 EQRD[47:40] RW 0x00

48-bit data register, contains the contents of the most recent

EQRAM address read from the RAM. The address read will

have been specified by the EQRAM Address fields.

EQRAM_READ[39:32]

verb FA1/7A1 7:0 EQRD[39:32] RW 0x00

48-bit data register, contains the contents of the most recent

EQRAM address read from the RAM. The address read will

have been specified by the EQRAM Address fields.

EQRAM_READ[31:24]

verb FA2/7A2 7:0 EQRD[31:24] RW 0x00

48-bit data register, contains the contents of the most recent

EQRAM address read from the RAM. The address read will

have been specified by the EQRAM Address fields.

EQRAM_READ[23:16]

verb FA3/7A3 7:0 EQRD[23:16] RW 0x00

48-bit data register, contains the contents of the most recent

EQRAM address read from the RAM. The address read will

have been specified by the EQRAM Address fields.

EQRAM_READ[15:8]

verb FA4/7A4 7:0 EQRD[15:8] RW 0x00

48-bit data register, contains the contents of the most recent

EQRAM address read from the RAM. The address read will

have been specified by the EQRAM Address fields.

EQRAM_READ[7:0]

verb FA5/7A5 7:0 EQRD[7:0] RW 0x00

48-bit data register, contains the contents of the most recent

EQRAM address read from the RAM. The address read will

have been specified by the EQRAM Address fields.

EQRAM_WRITE[47:40]

verb FA6/7A6 7:0 EQWD[47:40] RW 0x00

48-bit data register, contains the values to be written to the

EQRAM. The address written will have be specified by the

EQRAM Address fields.

EQRAM_WRITE[39:32]

verb FA7/7A7 7:0 EQWD[39:32] RW 0x00

48-bit data register, contains the values to be written to the

EQRAM. The address written will have be specified by the

EQRAM Address fields.

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7.29.1.26. EQRAM Address Register

This 8-bit register provides the address to the internal RAM when doing indirect writes/reads to the

EQRAM.

Prior to WC revision, this register reset by POR/DAFG/ULR. WC revision, reset by POR only. Writing

to NID22h verb 77F will generate a reset for all revisions.

7.29.1.27. EQRAM Control Register

This control register provides the write/read enable when doing indirect writes/reads to the EQRAM

Prior to WC revision, this register reset by POR/DAFG/ULR. WC revision, reset by POR only. Writing

to NID22h verb 77F will generate a reset for all revisions.

EQRAM_WRITE[31:24]

verb FA8/7A8 7:0 EQWD[31:24] RW 0x00

48-bit data register, contains the values to be written to the

EQRAM. The address written will have be specified by the

EQRAM Address fields.

EQRAM_WRITE[23:16]

verb FA9/7A9 7:0 EQWD[23:16] RW 0x00

48-bit data register, contains the values to be written to the

EQRAM. The address written will have be specified by the

EQRAM Address fields.

EQRAM_WRITE[15:8]

verb FAA/7AA 7:0 EQWD[15:8] RW 0x00

48-bit data register, contains the values to be written to the

EQRAM. The address written will have be specified by the

EQRAM Address fields.

EQRAM_WRITE[7:0]

verb FAB/7AB 7:0 EQWD[7:0] RW 0x00

48-bit data register, contains the values to be written to the

EQRAM. The address written will have be specified by the

EQRAM Address fields.

verb FAC/7AC

7:6 RSVD RO 0x00 Reserved

5:0 EQADD[5:0] RW 0x00

Contains the address (between 0x00 and 0x33) of the

EQRAM to be accessed by a read or write. This is not a byte

address--it is the address of the 48-bit data item to be

accessed from the EQRAM.

verb FAD/7AD

7 EQRAM_wr RW 0 1 = write to EQRAM, cleared by HW when done

6 EQRAM_rd RW 0 1 = read from EQRAM, cleared by HW when done

5:0 RSVD RO 0 Reserved

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8. PINOUT AND PACKAGING

Figure 22. 48QFN Pin Assignment

QFN

DVDD_CORE**

DMIC_CLK/GPIO 1

DMIC_0/GPIO 2

SDATA_OUT

BITCLK

DVSS**

SDATA_IN

DVDD*

SYNC

RESET#

PCBEEP

Cap+

Cap-

V-

Mono_Out

AVSS1

AVDD1

PORTE_L

PORTE_R

PORTC_L

PORTC_R

PORTF_L

PORTF_R

PORTD_+R

PORTD_-R

PORTD_-L

PORTD_+L

DMIC1/GPIO 0/SPDIFOUT1

Vreg(+2.5V)

AVDD2

DVDD_IO

EAPD

SPDIF OUT0/GPIO3

PVDD

PVSS

PVDD

AVSS2

PORTB_R

PORTB_L

AVSS2

PORTA_R

PORTA_L

VrefOut_A

VrefOut_C/GPIO4

SENSE_A

SENSE_B

VrefFilt

CAP2

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8.0.1. 48QFN Pin Table

Pin Name Pin Function I/O Internal

Pull-up/Pull-down

48 pin

location

DVDD_CORE 1.5V Digital Core Regulator Filter Cap O(Digital) None 1

DMIC_CLK/GPIO1 Digital Mic Clock Output/GPIO1 I/O(Digital) 60K Pull-down 2

DVDD_IO Reference Voltage (1.5V or 3.3V) I(Digital) None 3

DMIC0/GPIO2 Digital Mic 01 Input/GPIO2 I/O(Digital) 60K Pull-down 4

SDATA_OUT HD Audio Serial Data output from controller I/O(Digital) None 5

BITCLK HD Audio Bit Clock I(Digital) None 6

DVSS Digital Ground I(Digital) None 7

SDATA_IN HD Audio Serial Data Input to controller O(Digital) None 8

DVDD Digital Vdd= 3.3V I(Digital) None 9

SYNC HD Audio Frame Sync I(Digital) None 10

RESET# HD Audio Reset I(Digital) None 11

PC_BEEP PC Beep I(Analog) None 12

SENSE_A Jack insertion detection Ports A,B,C,

SPDIFOUT0 I(Analog) None 13

SENSE_B Jack insertion detection Ports E,F, DMIC0,

SPDIFOUT1 (DMIC1) I(Analog) None 14

PORTE_L Port E Left I/O(Analog) None 15

PORTE_R Port E Right I/O(Analog) None 16

PORTF_L Port F Left I/O(Analog) None 17

PORTF_R Port F Right I/O(Analog) None 18

PORTC_L Port C Left I/O(Analog) None 19

PORTC_R Port C Right I/O(Analog) None 20

VREFFILT Analog Virtual Ground O(Analog) None 21

CAP2 Reference filter Cap O(Analog) None 22

VREFOUT-A Reference Voltage out drive (intended for mic bias) O(Analog) None 23

VREFOUT-C/GPIO4 Reference Voltage out drive (intended for mic bias)

or general purpose I/O O(Analog) None 24

Mono_Out Mono output O(Analog) None 25

AVSS1 Analog Ground I(Analog) None 26

AVDD1 Analog Vdd=5.0V or 3.3V I(Analog) None 27

PORTA_L (HP0) Port A Output Left I/O(Analog) None 28

PORTA_R (HP0) Port A Output Right I/O(Analog) None 29

AVSS Analog Ground I(Analog) None 30

PORTB_L (HP1) Port B Output Left I/O(Analog) None 31

PORTB_R (HP1) Port B Output Right I/O(Analog) None 32

AVSS Analog Ground I(Analog) None 33

V- Negative analog supply O(Analog) None 34

Table 33. 48QFN Pin Description

TSI™ CONFIDENTIAL

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SINGLE CHIP PC AUDIO SYSTEM,CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO

CAP- Charge pump cap - O(Analog) None 35

CAP+ Charge pump cap + O(Analog) None 36

VREG Linear Regulator Output (2.5V) filter cap O(Analog) None 37

AVDD2 Analog Supply for VREG I(Analog) None 38

PVDD Analog Supply for Class-D amp I(Analog) None 39

PORTD_+L BTL amp Left + O(Analog) None 40

PORTD_-L BTL amp Left - O(Analog) None 41

PVSS Analog Ground I(Analog) None 42

PORTD_-R BTL amp Right - O(Analog) None 43

PORTD_+R BTL amp Right + O(Analog) None 44

PVDD Analog Supply for Class-D amp I(Analog) None 45

DMIC1/GPIO/SPDIFOUT1 Digital Microphone input, SPDIF Output, or GPIO0 I/O(Digital) 60K Pull-down 46

EAPD EAPD I/O (Digital) 60K Pull-up 47

SPDIFOUT0/GPIO3 SPDIF0 O(Digital) 60K pull-down 48

Pin Name Pin Function I/O Internal

Pull-up/Pull-down

48 pin

location

Table 33. 48QFN Pin Description

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SINGLE CHIP PC AUDIO SYSTEM,CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO

8.0.2. 48QFN Package Outline and Package Dimensions

Package dimensions are kept current with JEDEC Publication No. 95

Figure 23. 48QFN Package Diagram

Key

QFN Dimensions in mm

Min Nom Max

A 0.80 0.90 1.0

A1 0.00 0.02 0.05

A3 0.20 REF

D 7.00 BSC

D1 5.50 BSC

E 7.00 BSC

E1 5.50 BSC

L 0.35 0.40 0.45

e 0.50 BSC

R 0.20-0.25

b 0.18 0.25 0.30

D2 5.50 5.65 5.80

E2 5.50 5.65 5.80

ZD 0.75 BSC

ZE 0.75 BSC

Additional

Approved

Option

TSI™ CONFIDENTIAL

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SINGLE CHIP PC AUDIO SYSTEM,CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO

8.1. Standard Reflow Profile Data

Note: These devices can be hand soldered at 360 oC for 3 to 5 seconds.

FROM: IPC / JEDEC J-STD-020C “Moisture/Reflow Sensitivity Classification for Nonhermetic Solid

State Surface Mount Devices” (www.jedec.org/download).

Profile Feature Pb Free Assembly

Average Ramp-Up Rate (Tsmax - Tp) 3 oC / second max

Preheat:

Temperature Min (Tsmin)

Temperature Max (Tsmax)

Time (tsmin - tsmax)

150 oC

200 oC

60 - 180 seconds

Time maintained above: Temperature (TL)

Time (tL)

217 oC

60 - 150 seconds

Peak / Classification Temperature (Tp) See “Package Classification Reflow Temperatures”

Time within 5 oC of actual Peak Temperature (tp) 20 - 40 seconds

Ramp-Down rate 6 oC / second max

Time 25 oC to Peak Temperature 8 minutes max

Note: All temperatures refer to topside of the package, measured on the package body surface.

Table 34. Standard Reflow Profile

TSI™ CONFIDENTIAL

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SINGLE CHIP PC AUDIO SYSTEM, CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO

9. DISCLAIMER

While the information presented herein has been checked for both accuracy and reliability, manufac-

turer assumes no responsibility for either its use or for the infringement of any patents or other rights

of third parties, which would result from its use. No other circuits, patents, or licenses are implied.

This product is intended for use in normal commercial applications. Any other applications, such as

those requiring extended temperature range, high reliability, or other extraordinary environmental

requirements, are not recommended without additional processing by manufacturer. Manufacturer

reserves the right to change any circuitry or specifications without notice. Manufacturer does not

authorize or warrant any product for use in life support devices or critical medical instruments.

TSI™ CONFIDENTIAL

301 V 1.6 09/14

92HD91

SINGLE CHIP PC AUDIO SYSTEM,CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO

10.DOCUMENT REVISION HISTORY

Revision Date Description of Change

0.5 November 2009 Initial release

0.8 March 2010 Added widget details, front page feature bullet updates

0.85 June 2010 Aux mode section added

0.9 September 2010

Added changes for YA silicon revision (ZA/ZB prior settings referenced)

AFG EAPD bit added for PortE Headphone control. AFG ComJack bits added to select debounce

time. Port E headphone enable bit added. AFG EAPD Aux audio bit added for Port E.Removed SCS

support. Updated conditions of performance characteristics, added HDA signalling voltage to

condition for power measurements. Default changed on BTL/HD_Mode from 0 to 1. Updated Record

Path behavior tabel for Aux mode. Updated Pin Configuration Default Settings.Corrected Combo

Jack diagram.

0.91 October 2010

Updated LDO Level Control values. Corrected step size and thermal trip in BTL section. Updated

SPKVOL L/R step size to .75dB. Added additional verb for updating speaker L and R volume at the

same time (to match HDA implementation). Widget 22h verbs added/reordered. Clarified AuxMode

section wording related to D3Cold entry. Added description text for High pass and Mono band pass

filter features.

0.92 May 2011 Corrected Sense A/B description and table.

0.93 June 2011 Corrected front page bullet for BTL voltage.

1.0 October 2011

Corrected Left vs Right channel for the EQ coefficients to match silicon. Updated electrical

characteristics for typical values. Removed Preliminary. Removed comments related to ZA and ZB

silicon since they were non-production. Added WB silicon widget items: ComboJackTiming in the

AFG and ScStableTimeSel added to AFG AnaBTL. Added PVDD value for the digital maximum

supply voltage and footnote to the GPIO characteristics for the Input Low and High Voltage. Added

missing EAPD widget details.

1.1 November 2011 Added feature bullet and description section for microphone input mute which is available only on

silicon revisions WB and beyond.

1.2 January 2012

Corrections for 022FB0 / 0227B0 to 022FB6 / 0227B6 as they are not reachable via NID22 but must

be accessed through the Port Nodes.UpdatedNID22 registers with reset information, which is

different for WC silicon revision.

1.3 March 2012 Added ComboJackTime widget and EAPD widget details.

1.4 June 2012 Added THD+N setting to Class D Output power and 3W typical line.

1.5 February 2013 Added Industrial temp package option for revisions WC and beyond.

1.6 September 2014 Released in TSI Format

92HD91

SINGLE CHIP PC AUDIO SYSTEM, CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO

www.temposemi.com

8627 N. MoPac Expwy Suite 130

Austin, Texas 78759

DISCLAIMER Tempo Semiconductor, Inc. (TSI) and its subsidiaries reserve the right to modify the products and/or specifications described

herein at any time and at TSI’s sole discretion. All information in this document, including descriptions of product features and performance, is

subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the

independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is

provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of TSI’s products

for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This docu-

ment is presented only as a guide and does not convey any license under intellectual property rights of TSI or any third parties.

TSI’s products are not intended for use in life support systems or similar devices where the failure or malfunction of an TSI product can be

reasonably expected to significantly affect the health or safety of users. Anyone using an TSI product in such a manner does so at their own

risk, absent an express, written agreement by TSI.

Tempo Semiconductor, TSI and the TSI logo are registered trademarks of TSI. Other trademarks and service marks used herein, including

protected names, logos and designs, are the property of TSI or their respective third party owners.

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