fax id: 6107 1CY 7C34 2B CY7C342B 128-Macrocell MAX(R) EPLDs Features The 128 macrocells in the CY7C342B are divided into 8 Logic Array Blocks (LABs), 16 per LAB. There are 256 expander product terms, 32 per LAB, to be used and shared by the macrocells within each LAB. * * * * 128 macrocells in 8 LABs 8 dedicated inputs, 52 bidirectional I/O pins Programmable interconnect array Advanced 0.65-micron CMOS technology to increase performance * Available in 68-pin HLCC, PLCC, and PGA Each LAB is interconnected with a programmable interconnect array, allowing all signals to be routed throughout the chip. Functional Description The CY7C342B is an Erasable Programmable Logic Device (EPLD) in which CMOS EPROM cells are used to configure logic functions within the device. The MAX architecture is 100% user configurable, allowing the devices to accommodate a variety of independent logic functions. The speed and density of the CY7C342B allows it to be used in a wide range of applications, from replacement of large amounts of 7400-series TTL logic, to complex controllers and multifunction chips. With greater than 25 times the functionality of 20-pin PLDs, the CY7C342B allows the replacement of over 50 TTL devices. By replacing large amounts of logic, the CY7C342B reduces board space, part count, and increases system reliability. Logic Block Diagram 1 (B6) INPUT/CLK INPUT (A7) 2 (A6) INPUT INPUT (A8) 68 66 32 (L4) INPUT INPUT (L6) 36 34 (L5) INPUT INPUT (K6) 35 SYSTEM CLOCK 4 (A5) 5 (B4) 6 (A4) 7 (B3) 8 (A3) 9 (A2) 10 (B2) 11 (B1) 12 (C2) 13 (C1) 14 (D2) 15 (D1) 17 (E1) LAB A MACROCELL 1 MACROCELL 2 MACROCELL 3 MACROCELL 4 MACROCELL 5 MACROCELL 6 MACROCELL 7 MACROCELL 8 MACROCELL 9-16 LAB H MACROCELL 120 MACROCELL 119 MACROCELL 118 MACROCELL 117 MACROCELL 116 MACROCELL 115 MACROCELL 114 MACROCELL 113 MACROCELL 121-128 LAB B MACROCELL 17 MACROCELL 18 MACROCELL 19 MACROCELL 20 MACROCELL 21 LAB G MACROCELL 101 MACROCELL 100 MACROCELL 99 MACROCELL 98 MACROCELL 97 MACROCELL 22-32 18 (F2) 19 (F1) 21 (G1) 22 (H2) 23 (H1) 24 (J2) 25 (J1) 26 (K1) 27 (K2) 28 (L2) 29 (K3) 30 (L3) 31 (K4) (B8) 65 (A9) 64 (B9) 63 (A10) 62 (B10) 61 (B11) 60 (C11) 59 (C10) 58 (D11) 57 (D10) 56 (E11) 55 (F11) 53 (F10) 52 MACROCELL 102-112 P I A LAB C MACROCELL 33 MACROCELL 34 MACROCELL 35 MACROCELL 36 MACROCELL 37 LAB F MACROCELL 85 MACROCELL 84 MACROCELL 83 MACROCELL 82 MACROCELL 81 MACROCELL 38-48 MACROCELL 86-96 LAB D MACROCELL 49 MACROCELL 50 MACROCELL 51 MACROCELL 52 MACROCELL 53 MACROCELL 54 MACROCELL 55 MACROCELL 56 LAB E MACROCELL 72 MACROCELL 71 MACROCELL 70 MACROCELL 69 MACROCELL 68 MACROCELL 67 MACROCELL 66 MACROCELL 65 (G11) 51 (H11) 49 (H10) 48 (J11) 47 (J10) 46 (K11) 45 (K10) 44 (L10) 43 (L9) 42 (K9) 41 (L8) 40 (K8) 39 (L7) 38 MACROCELL 73- 80 MACROCELL 57- 64 3, 20, 37, 54 (B5, G2, K7, E10) VCC 16, 33, 50, 67 (E2, K5, G10, B7) GND () - PERTAIN TO 68-PIN PGA PACKAGE C342B-1 MAX is a registered trademark of Altera Corporation. Warp2 and Warp3 are registered trademarks of Cypress Semiconductor. Cypress Semiconductor Corporation * 3901 North First Street * San Jose * CA 95134 * 408-943-2600 October 1989 - Revised October 1995 CY7C342B Selection Guide 7C342B-12 7C342B-15 7C342B-20 7C342B-25 7C342B-30 7C342B-35 Maximum Access Time (ns) 12 15 20 25 30 35 Maximum Operating Current (mA) 250 250 250 250 250 250 Military 320 320 320 320 320 Industrial 320 320 320 320 320 Commercial Maximum Static Current (mA) Commercial 225 225 225 225 225 Military 225 275 275 275 275 275 Industrial 275 275 275 275 275 Pin Configurations PLCC Top View PGA BottomView L 9 I/O I/O I/O I/O I/O 5 4 3 2 17 18 19 VCC 20 21 I/O I/O K I/O I/O INPUT INPUT INPUT I/O GND INPUT I/O I/O I/O I/O VCC I/O I/O I/O I/O 1 68 67 66 65 64 63 62 61 60 59 58 57 56 55 13 14 I/O I/O I/O I/O I/O 6 12 15 I/O 7 10 11 I/O GND I/O I/O I/O 8 I/O 54 53 16 52 51 50 7C342B 49 48 47 46 22 23 24 45 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 4344 C342B-2 I/O J I/O I/O I/O I/O I/O I/O I/O H I/O I/O I/O I/O I/O VCC G I/O VCC GND I/O I/O I/O I/O F I/O I/O I/O I/O E I/O GND VCC I/O D I/O I/O I/O I/O C I/O I/O I/O I/O B I/O I/O I/O I/O VCC INPUT/ GND CLK I/O I/O I/O I/O I/O I/O I/O INPUT INPUT INPUT I/O I/O 2 3 4 5 9 10 I/O GND I/O I/O I/O 7C342B I/O I/O I/O A 1 6 7 I/O 8 11 C342B-3 2 CY7C342B DC Input Voltage[1] ........................................-3.0V to + 7.0V Maximum Ratings DC Program Voltage .................................................... 13.0V (Above which the useful life may be impaired. For user guidelines, not tested.) Static Discharge Voltage ........................................... >1100V (per MIL-STD-883, Method 3015) Storage Temperature ..................................-65C to+150C Ambient Temperature with Power Applied....................................................0C to+70C Operating Range Maximum Junction Temperature (under bias).................................................................. 150C Ambient Temperature VCC 0C to +70C 5V 5% -40C to +85C 5V 10% -55C to +125C (Case) 5V 10% Range Commercial Supply Voltage to Ground Potential ................ -3.0V to+7.0V Industrial Maximum Power Dissipation................................... 2500 mW Military DC VCC or GND Current ............................................ 500 mA DC Output Current per Pin........................ -25 mA to+25 mA Electrical Characteristics Over the Operating Range[2] Parameter Description Test Conditions VOH Output HIGH Voltage VCC = Min., IOH = -4.0 mA VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA VIH Input HIGH Voltage VIL Input LOW Voltage IIX Input Current GND < VIN < VCC IOZ Output Leakage Current IOS Output Short Circuit Current ICC1 Power Supply Current (Static) VI = GND (No Load) ICC2 Power Supply Current[5] VI = VCC or GND (No Load) f = 1.0 MHz[4] Min. Max. Unit 2.4 V 0.45 V 2.2 VCC +0.3 V -0.3 0.8 V -10 +10 A VO = VCC or GND -40 +40 A VCC = Max., VOUT = 0.5V[3, 4] -30 -90 mA Com'l 225 mA Mil/Ind 275 Com'l 250 Mil/Ind 320 mA tR Recommended Input Rise Time 100 ns tF Recommended Input Fall Time 100 ns Capacitance[6] Parameter Description Test Conditions Max. Unit CIN Input Capacitance VIN = 2V, f = 1.0 MHz 10 pF COUT Output Capacitance VOUT = 2V, f = 1.0 MHz 10 pF Notes: 1. Minimum DC input is -0.3V. During transitions, the inputs may undershoot to -3.0V for periods less than 20 ns. 2. Typical values are for TA = 25C and V CC = 5V. 3. Not more than one output should be tested at a time. Duration of the short circuit should not be more than one second. VOUT = 0.5V has been chosen to avoid test problems caused by tester ground degradation. 4. Guaranteed but not 100% tested. 5. This parameter is measured with device programmed as a 16-bit counter in each LAB. 6. Part (a) in AC Test Load and Waveforms is used for all parameters except tER and tXZ , which is used for part (b) in AC Test Load and Waveforms. All external timing parameters are measured referenced to external pins of the device. 3 CY7C342B AC Test Loads and Waveforms[5] R1 464 R1 464 5V 5V OUTPUT ALL INPUT PULSES OUTPUT R2 250 50 pF INCLUDING JIG AND SCOPE Equivalent to: 3.0V (a) R2 250 5 pF INCLUDING JIG AND SCOPE 10% 90% GND 6 ns C342B-4 (b) 90% 10% 6 ns C342B-5 THEVENIN EQUIVALENT (commercial/military) 163 OUTPUT 1.75V ment and routing iterations required for a programmable gate array to achieve design timing objectives. Logic Array Blocks There are 8 logic array blocks in the CY7C342B. Each LAB consists of a macrocell array containing 16 macrocells, an expander product term array containing 32 expanders, and an I/O block. The LAB is fed by the programmable interconnect array and the dedicated input bus. All macrocell feedbacks go to the macrocell array, the expander array, and the programmable interconnect array. Expanders feed themselves and the macrocell array. All I/O feedbacks go to the programmable interconnect array so that they may be accessed by macrocells in other LABs as well as the macrocells in the LAB in which they are situated. Timing Delays Timing delays within the CY7C342B may be easily determined using Warp2(R) or Warp3(R) software by the model shown in Figure 1. The CY7C342B has fixed internal delays, allowing the user to determine the worst case timing delays for any design. For complete timing information the Warp3 software provides a timing simulator. Design Recommendations Externally, the CY7C342B provides eight dedicated inputs, one of which may be used as a system clock. There are 52 I/O pins that may be individually configured for input, output, or bidirectional data flow. Operation of the devices described herein with conditions above those listed under "Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this datasheet is not implied. Exposure to absolute maximum ratings conditions for extended periods of time may affect device reliability. The CY7C342B contains circuitry to protect device pins from high static voltages or electric fields, but normal precautions should be taken to avoid application of any voltage higher than the maximum rated voltages. Programmable Interconnect Array The Programmable Interconnect Array (PIA) solves interconnect limitations by routing only the signals needed by each logic array block. The inputs to the PIA are the outputs of every macrocell within the device and the I/O pin feedback of every pin on the device. For proper operation, input and output pins must be constrained to the range GND < (VIN or VOUT) < VCC. Unused inputs must always be tied to an appropriate logic level (either V CC or GND). Each set of V CC and GND pins must be connected together directly at the device. Power supply decoupling capacitors of at least 0.2 F must be connected between VCC and GND. For the most effective decoupling, each V CC pin should be separately decoupled to GND directly at the device. Decoupling capacitors should have good frequency response, such as monolithic ceramic types have. Unlike masked or programmable gate arrays, which induce variable delay dependent on routing, the PIA has a fixed delay. This eliminates undesired skews among logic signals that may cause glitches in internal or external logic. The fixed delay, regardless of programmable interconnect array configuration, simplifies design by assuring that internal signal skews or races are avoided. The result is ease of design implementation, often in a signal pass, without the multiple internal logic place- 4 CY7C342B EXPANDER DELAY tEXP LOGIC ARRAY CONTROL DELAY tLAC INPUT INPUT DELAY tIN LOGIC ARRAY DELAY tLAD REGISTER OUTPUT DELAY tCLR tPRE tRSU tRH OUTPUT tRD tCOMB tLATCH tOD tXZ tZX SYSTEM CLOCK DELAY tICS PIA DELAY tPIA CLOCK DELAY tIC FEEDBACK DELAY tFD I/O DELAY tIO C342B-6 Figure 1. CY7C342B Internal Timing Model 5 CY7C342B Design Security Timing Considerations The CY7C342B contains a programmable design security feature that controls the access to the data programmed into the device. If this programmable feature is used, a proprietary design implemented in the device cannot be copied or retrieved. This enables a high level of design control to be obtained since programmed data within EPROM cells is invisible. The bit that controls this function, along with all other program data, may be reset simply by erasing the entire device. Unless otherwise stated, propagation delays do not include expanders. When using expanders, add the maximum expander delay tEXP to the overall delay. Similarly, there is an additional tPIA delay for an input from an I/O pin when compared to a signal from straight input pin. When calculating synchronous frequencies, use tS1 if all inputs are on dedicated input pins. The parameter tS2 should be used if data is applied at an I/O pin. If tS2 is greater than tCO1, 1/tS2 becomes the limiting frequency in the data path mode unless 1/(tWH + tWL) is less than 1/tS2. The CY7C342B is fully functionally tested and guaranteed through complete testing of each programmable EPROM bit and all internal logic elements thus ensuring 100% programming yield. When expander logic is used in the data path, add the appropriate maximum expander delay, tEXP to tS1. Determine which of 1/(tWH + tWL), 1/tCO1, or 1/(tEXP + tS1) is the lowest frequency. The lowest of these frequencies is the maximum data path frequency for the synchronous configuration. The erasable nature of these devices allows test programs to be used and erased during early stages of the production flow. The devices also contain on-board logic test circuitry to allow verification of function and AC specification once encapsulated in non-windowed packages. When calculating external asynchronous frequencies, use tAS1 if all inputs are on the dedicated input pins. If any data is applied to an I/O pin, tAS2 must be used as the required set-up time. If (tAS2 + tAH) is greater than tACO1, 1/(tAS2 + tAH) becomes the limiting frequency in the data path mode unless 1/(tAWH + tAWL) is less than 1/(tAS2 + tAH). Typical ICC vs. fMAX 400 When expander logic is used in the data path, add the appropriate maximum expander delay, tEXP to tAS1. Determine which of 1/(tAWH + tAWL), 1/tACO1, or 1/(tEXP + tAS1) is the lowest frequency. The lowest of these frequencies is the maximum data path frequency for the asynchronous configuration. 300 VCC =5.0V RoomTemp. 200 The parameter tOH indicates the system compatibility of this device when driving other synchronous logic with positive input hold times, which is controlled by the same synchronous clock. If tOH is greater than the minimum required input hold time of the subsequent synchronous logic, then the devices are guaranteed to function properly with a common synchronous clock under worst-case environmental and supply voltage conditions. 100 0 100 Hz 1 kHz 10 kHz 100 kHz 1 MHz 10 MHz 50 MHz The parameter tAOH indicates the system compatibility of this device when driving subsequent registered logic with a positive hold time and using the same asynchronous clock as the CY7C342B. MAXIMUM FREQUENCY Output Drive Current In general, if tAOH is greater than the minimum required input hold time of the subsequent logic (synchronous or asynchronous) then the devices are guaranteed to function properly under worst-case environmental and supply voltage conditions, provided the clock signal source is the same. This also applies if expander logic is used in the clock signal path of the driving device, but not for the driven device. This is due to the expander logic in the second device's clock signal path adding an additional delay (tEXP) causing the output data from the preceding device to change prior to the arrival of the clock signal at the following device's register. 100 IOL 80 VCC =5.0V RoomTemp. 60 40 IOH 20 0 0.45 1 2 3 4 5 VO OUTPUT VOLTAGE (V) 6 CY7C342B Commercial and Industrial External Synchronous Switching Characteristics [6] Over Operating Range Parameter Description 7C342B-12 7C342B-15 7C342B-20 Min. Min. Min. [7] Max. Max. Max. Unit tPD1 Dedicated Input to Combinatorial Output Delay 12 15 20 ns tPD2 I/O Input to Combinatorial Output Delay[8] 20 25 32 ns tPD3 Dedicated Input to Combinatorial Output Delay with Expander Delay[9] 18 23 30 ns tPD4 I/O Input to Combinatorial Output Delay with Expander Delay[4,10] 26 33 42 ns tEA Input to Output Enable Delay[4, 7] 12 15 20 ns tER Input to Output Disable Delay[4, 7] 12 15 20 ns tCO1 Synchronous Clock Input to Output Delay 6 7 8 ns tCO2 Synchronous Clock to Local Feedback to Combinatorial Output[4, 11] 14 17 20 ns tS1 Dedicated Input or Feedback Set-Up Time to Synchronous Clock Input[4, 12] 8 10 13 ns tS2 I/O Input Set-Up Time to Synchronous Clock Input[7] 16 20 24 ns Input[7] tH Input Hold Time from Synchronous Clock 0 0 0 ns tWH Synchronous Clock Input HIGH Time 4.5 5 7 ns tWL Synchronous Clock Input LOW Time 4.5 5 7 ns tRW Asynchronous Clear Width[4, 7] 12 15 20 ns Time[4, 7] tRR Asynchronous Clear Recovery tRO Asynchronous Clear to Registered Output Delay[7] 12 Width[4, 7] tPW Asynchronous Preset tPR Asynchronous Preset Recovery Time[4,7] Asynchronous Preset to Registered Output tCF Synchronous Clock to Local Feedback Input[4, 13] (1/(fMAX3))[4] 20 15 ns 20 ns 12 15 20 ns 12 15 20 ns Delay[7] tPO 15 12 12 15 20 ns 3 3 3 ns tP External Synchronous Clock Period 9 12 15 ns fMAX1 External Feedback Maximum Frequency (1/(tCO1 + tS1))[4, 14] 71.4 58.8 47.6 MHz fMAX2 Internal Local Feedback Maximum Frequency, lesser of (1/(tS1 + tCF)) or (1/tCO1)[4, 15] 90.9 76.9 62.5 MHz Notes: 7. This specification is a measure of the delay from input signal applied to a dedicated input (68-pin PLCC input pin 1, 2, 32, 34, 35, 66, or 68) to combinatorial output on any output pin. This delay assumes no expander terms are used to form the logic function. When this note is applied to any parameter specification it indicates that the signal (data, asynchronous clock, asynchronous clear, and/or asynchronous preset) is applied to a dedicated input only and no signal path (either clock or data) employs expander logic. If an input signal is applied to an I/O pin an additional delay equal to tPIA should be added to the comparable delay for a dedicated input. If expanders are used, add the maximum expander delay t EXP to the overall delay for the comparable delay without expanders. 8. This specification is a measure of the delay from input signal applied to an I/O macrocell pin to any output. This delay assumes no expander terms are used to form the logic function. 9. This specification is a measure of the delay from an input signal applied to a dedicated input (68-pin PLCC input pin 1, 2, 32, 34, 35, 36, 66, or 68) to combinatorial output on any output pin. This delay assumes expander terms are used to form the logic function and includes the worst-case expander logic delay for one pass through the expander logic. 10. This specification is a measure of the delay from an input signal applied to an I/O macrocell pin to any output. This delay assumes expander terms are used to form the logic function and includes the worst-case expander logic delay for one pass through the expander logic. This parameter is tested periodically by sampling production material. 11. This specification is a measure of the delay from synchronous register clock to internal feedback of the register output signal to the input of the LAB logic array and then to a combinatorial output. This delay assumes no expanders are used, register is synchronously clocked and all feedback is within the same LAB. This parameter is tested periodically by sampling production material. 12. If data is applied to an I/O input for capture by a macrocell register, the I/O pin input set-up time minimums should be observed. These parameters are t S2 for synchronous operation and tAS2 for asynchronous operation. 13. This specification is a measure of the delay associated with the internal register feedback path. This is the delay from synchronous clock to LAB logic array input. This delay plus the register set-up time, tS1, is the minimum internal period for an internal synchronous state machine configuration. This delay is for feedback within the same LAB. This parameter is tested periodically by sampling production material. 14. This specification indicates the guaranteed maximum frequency, in synchronous mode, at which a state machine configuration with external feedback can operate. It is assumed that all data inputs and feedback signals are applied to dedicated inputs. All feedback is assumed to be local originating within the same LAB. 15. This specification indicates the guaranteed maximum frequency at which a state machine with internal-only feedback can operate. If register output states must also control external points, this frequency can still be observed as long as this frequency is less than 1/tCO1. 7 CY7C342B Commercial and Industrial External Synchronous Switching Characteristics [6] Over Operating Range Parameter Description 7C342B-12 7C342B-15 7C342B-20 Min. Min. Min. Max. Max. Max. Unit fMAX3 Data Path Maximum Frequency, lesser of (1/(tWL + tWH)), (1/(tS1 + tH )) or (1/tCO1)[4, 16] 111.1 100 71.4 MHz fMAX4 Maximum Register Toggle Frequency (1/(t WL+tWH))[4,17] 111.1 100 71.4 MHz 3 3 3 ns tOH [4, 18] Output Data Stable Time from Synchronous Clock Input Parameter Description 7C342B-25 7C342B-30 7C342B-35 Min. Min. Min. Delay[7] Max. Max. Max. Unit tPD1 Dedicated Input to Combinatorial Output 25 30 35 ns tPD2 I/O Input to Combinatorial Output Delay[8] 39 46 55 ns tPD3 Dedicated Input to Combinatorial Output Delay with Expander Delay[9] 37 44 55 ns tPD4 I/O Input to Combinatorial Output Delay with Expander Delay[4,8] 51 60 75 ns tEA Input to Output Enable Delay[4, 8] 25 30 35 ns tER Input to Output Disable Delay[4, 7] 25 30 35 ns tCO1 Synchronous Clock Input to Output Delay 14 16 20 ns tCO2 Synchronous Clock to Local Feedback to Combinatorial Output[4, 9] 30 35 42 ns tS1 Dedicated Input or Feedback Set-Up Time to Synchronous Clock Input[7, 10] 15 20 25 ns tS2 I/O Input Set-Up Time to Synchronous Clock Input[7] 29 36 45 ns tH Input Hold Time from Synchronous Clock tWH Synchronous Clock Input HIGH Time tWL tRW Input[7] 0 0 0 ns 8 10 12.5 ns Synchronous Clock Input LOW Time 8 10 12.5 ns Asynchronous Clear Width[4, 7] 25 30 35 ns Time[4, 7] tRR Asynchronous Clear Recovery tRO Asynchronous Clear to Registered Output Delay[7] 25 Width[4, 7] tPW Asynchronous Preset tPR Asynchronous Preset Recovery Time[4,7] Asynchronous Preset to Registered Output tCF Synchronous Clock to Local Feedback Input[4, 11] (1/(fMAX3))[4] 35 30 ns 35 ns 25 30 35 ns 25 30 35 ns Delay[7] tPO 30 25 25 30 35 ns 3 3 6 ns tP External Synchronous Clock Period 16 20 25 ns fMAX1 External Feedback Maximum Frequency (1/(tCO1 + tS1))[4, 12] 34.5 27.7 22.2 MHz fMAX2 Internal Local Feedback Maximum Frequency, lesser of (1/(tS1 + tCF)) or (1/tCO1)[4, 13] 55.5 43.4 32.2 MHz fMAX3 Data Path Maximum Frequency, lesser of (1/(tWL + tWH)), (1/(tS1 + tH )) or (1/tCO1)[4, 14] 62.5 50 40 MHz fMAX4 Maximum Register Toggle Frequency (1/(t WL+tWH))[4,15] 62.5 50 40 MHz tOH Output Data Stable Time from Synchronous Clock Input[4, 16] 3 3 3 ns Notes: 16. This frequency indicates the maximum frequency at which the device may operate in data path mode (dedicated input pin to output pin). This assumes data input signals are applied to dedicated input pins and no expander logic is used. If any of the data inputs are I/O pins, tS2 is the appropriate tS for calculation. 17. This specification indicates the guaranteed maximum frequency, in synchronous mode, at which an individual output or buried register can be cycled by a clock signal applied to the dedicated clock input pin. 18. This parameter indicates the minimum time after a synchronous register clock input that the previous register output data is maintained on the output pin. 8 CY7C342B Commercial and Industrial External Asynchronous Switching Characteristics[6] Over Operating Range Parameter Description 7C342B-12 7C342B-15 7C342B-20 Min. Min. Min. [7] Max. Max. Max. Unit tACO1 Asynchronous Clock Input to Output Delay 12 15 20 ns tACO2 Asynchronous Clock Input to Local Feedback to Combinatorial Output[19] 20 25 32 ns tAS1 Dedicated Input or Feedback Set-Up Time to Asynchronous Clock Input[7] 4 5 5 ns tAS2 I/O Input Set-Up Time to Asynchronous Clock Input[7] 12 14.5 17 ns 4 5 6 ns 8 9 10 ns tAH Input Hold Time from Asynchronous Clock Input tAWH Asynchronous Clock Input HIGH Time[7] [7] Time[7, 20] tAWL Asynchronous Clock Input LOW tACF Asynchronous Clock to Local Feedback Input[4,21] 6 7 9 (1/(fMAXA4))[4] 8 11 ns 13 ns tAP External Asynchronous Clock Period 14 16 18 ns fMAXA1 External Feedback Maximum Frequency in Asynchronous Mode (1/(tACO1 + tAS1))[4,22] 62.5 50 40 MHz fMAXA2 Maximum Internal Asynchronous Frequency[4,23] 71.4 62.5 55.5 MHz 83.3 66.6 50 MHz 71.4 62.5 55.5 MHz 12 12 12 ns Mode[4,24] fMAXA3 Data Path Maximum Frequency in Asynchronous fMAXA4 Maximum Asynchronous Register Toggle Frequency 1/(tAWH + tAWL)[4,25] tAOH Output Data Stable Time from Asynchronous Clock Input[4,26] Notes: 19. This specification is a measure of the delay from an asynchronous register clock input to internal feedback of the register output signal to the input of the LAB logic array and then to a combinatorial output. This delay assumes no expanders are used in the logic of combinatorial output or the asynchronous clock input. The clock signal is applied to the dedicated clock input pin and all feedback is within a single LAB. This parameter is tested periodically by sampling production material. 20. This parameter is measured with a positive-edge triggered clock at the register. For negative edge triggering, the tAWH and tAWL parameters must be swapped. If a given input is used to clock multiple registers with both positive and negative polarity, tAWH should be used for both tAWH and tAWL. 21. This specification is a measure of the delay associated with the internal register feedback path for an asynchronous clock to LAB logic array input. This delay plus the asynchronous register set-up time, tAS1, is the minimum internal period for an internal asynchronously clocked state machine configuration. This delay is for feedback within the same LAB, assumes no expander logic in the clock path, and assumes that the clock input signal is applied to a dedicated input pin. This parameter is tested periodically by sampling production material. 22. This specification indicates the guaranteed maximum frequency at which an asynchronously clocked state machine configuration with external feedback can operate. It is assumed that all data inputs, clock inputs, and feedback signals are applied to dedicated inputs and that no expander logic is employed in the clock signal path or data path. 23. This specification indicates the guaranteed maximum frequency at which an asynchronously clocked state machine with internal-only feedback can operate. This parameter is determined by the lesser of (1/(tACF + tAS1)) or (1/(tAWH + tAWL)). If register output states must also control external points, this frequency can still be observed as long as this frequency is less than 1/tACO1. This specification assumes no expander logic is utilized, all data inputs and clock inputs are applied to dedicated inputs, and all state feedback is within a single LAB. This parameter is tested periodically by sampling production material. 24. This frequency is the maximum frequency at which the device may operate in the asynchronously clocked data path mode. This specification is determined by the lesser of 1/(tAWH + tAWL), 1/(tAS1 + tAH) or 1/tACO1. It assumes data and clock input signals are applied to dedicated input pins and no expander logic is used. 25. This specification indicates the guaranteed maximum frequency at which an individual output or buried register can be cycled in asynchronously clocked mode by a clock signal applied to an external dedicated input pin. 26. This parameter indicates the minimum time that the previous register output data is maintained on the output after an asynchronous register clock input applied to an external dedicated input pin. 9 CY7C342B Commercial and Industrial External Asynchronous Switching Characteristics[6] Over Operating Range (continued) Parameter Description 7C342B-25 7C342B-30 7C342B-35 Min. Min. Min. [7] Max. Max. Max. Unit tACO1 Asynchronous Clock Input to Output Delay 25 30 35 ns tACO2 Asynchronous Clock Input to Local Feedback to Combinatorial Output[19] 39 46 55 ns tAS1 Dedicated Input or Feedback Set-Up Time to Asynchronous Clock Input[7] 5 6 8 ns tAS2 I/O Input Set-Up Time to Asynchronous Clock Input[7] 19 22 28 ns 6 8 10 ns 11 14 16 ns tAH Input Hold Time from Asynchronous Clock tAWH Asynchronous Clock Input HIGH Time[7] Input[7] Time[7, 20] tAWL Asynchronous Clock Input LOW tACF Asynchronous Clock to Local Feedback Input[4,21] 9 11 15 (1/(fMAXA4))[4] tAP External Asynchronous Clock Period fMAXA1 External Feedback Maximum Frequency in Asynchronous Mode (1/(tACO1 + tAS1))[4,22] fMAXA2 Maximum Internal Asynchronous Frequency[4,23] Mode[4,24] 14 18 ns 22 ns 20 25 30 ns 33.3 27.7 23.2 MHz 50 40 33.3 MHz fMAXA3 Data Path Maximum Frequency in Asynchronous 40 33.3 28.5 MHz fMAXA4 Maximum Asynchronous Register Toggle Frequency 1/(tAWH + tAWL)[4,25] 50 40 33.3 MHz tAOH Output Data Stable Time from Asynchronous Clock Input[4,26] 15 15 15 ns Commercial and Industrial Typical Internal Switching Characteristics Over Operating Range Parameter Description 7C342B-12 7C342B-15 7C342B-20 Min. Min. Min. Max. Max. Max. Unit tIN Dedicated Input Pad and Buffer Delay 2.5 3 4 ns tIO I/O Input Pad and Buffer Delay 2.5 3 4 ns tEXP Expander Array Delay 6 8 10 ns tLAD Logic Array Data Delay 6 8 10 ns tLAC Logic Array Control Delay 5 5 7 ns tOD Output Buffer and Pad Delay 3 3 3 ns 5 5 5 ns 5 5 5 ns Delay[27] tZX Output Buffer Enable tXZ Output Buffer Disable Delay tRSU Register Set-Up Time Relative to Clock Signal at Register 2 4 5 ns tRH Register Hold Time Relative to Clock Signal at Register 4 4 5 ns tLATCH Flow Through Latch Delay tRD Register Delay Delay[28] tCOMB Transparent Mode tCH Clock HIGH Time 3 tCL Clock LOW Time 3 tIC Asynchronous Clock Logic Delay tICS Synchronous Clock Delay tFD Feedback Delay tPRE Asynchronous Register Preset Time 1 1 2 ns 0.5 1 1 ns 2 ns 1 1 4 6 4 ns 6 ns 5 6 8 ns 0.5 0.5 0.5 ns 1 1 1 ns 3 3 3 ns Notes: 27. Sample tested only for an output change of 500 mV. 28. This specification guarantees the maximum combinatorial delay associated with the macrocell register bypass when the macrocell is configured for combinatorial operation. 10 CY7C342B Commercial and Industrial Typical Internal Switching Characteristics Over Operating Range (continued) Parameter Description 7C342B-12 7C342B-15 7C342B-20 Min. Min. Min. Max. 3 Max. 3 Max. Unit 3 ns tCLR Asynchronous Register Clear Time tPCW Asynchronous Preset and Clear Pulse Width 2 3 4 ns tPCR Asynchronous Preset and Clear Recovery Time 2 3 4 ns tPIA Programmable Interconnect Array Delay Time 8 10 12 ns Commercial and Industrial Typical Internal Switching Characteristics Over Operating Range (continued) Parameter Description 7C342B-25 7C342B-30 7C342B-35 Min. Min. Min. Max. 5 Max. Max. Unit 9 ns 6 9 ns 14 20 ns 14 16 ns 12 13 ns 5 6 ns 11 13 ns 13 ns tIN Dedicated Input Pad and Buffer Delay 7 tIO I/O Input Pad and Buffer Delay 6 tEXP Expander Array Delay 12 tLAD Logic Array Data Delay 12 tLAC Logic Array Control Delay 10 tOD Output Buffer and Pad Delay 5 tZX Output Buffer Enable Delay[27] 10 tXZ Output Buffer Disable Delay tRSU Register Set-Up Time Relative to Clock Signal at Register 6 tRH Register Hold Time Relative to Clock Signal at Register 6 tLATCH Flow Through Latch Delay 3 4 4 ns tRD Register Delay 1 2 2 ns tCOMB Transparent Mode Delay[28] 3 4 4 ns tCH Clock HIGH Time 8 10 12.5 ns tCL Clock LOW Time 8 10 12.5 ns tIC Asynchronous Clock Logic Delay 14 16 18 ns tICS Synchronous Clock Delay 2 2 3 ns tFD Feedback Delay 1 1 2 ns tPRE Asynchronous Register Preset Time 5 6 7 ns tCLR Asynchronous Register Clear Time 7 ns tPCW Asynchronous Preset and Clear Pulse Width 5 tPCR Asynchronous Preset and Clear Recovery Time 5 tPIA Programmable Interconnect Array Delay Time 10 11 8 8 5 ns 10 6 6 ns 7 6 14 11 10 ns 7 16 ns 20 ns CY7C342B Military External Synchronous Switching Characteristics[6] Over Operating Range Parameter Description 7C342B-15 7C342B-20 7C342B-25 7C342B-30 7C342B-35 Min. Min. Min. Min. Min. Max. Max. Max. Max. Max. Unit tPD1 Dedicated Input to Combinatorial Output Delay[7] 15 20 25 30 35 ns tPD2 I/O Input to Combinatorial Output Delay[8] 25 32 39 46 55 ns tPD3 Dedicated Input to Combinatorial Output Delay with Expander Delay[9] 23 30 37 44 55 ns tPD4 I/O Input to Combinatorial Output Delay with Expander Delay[4,10] 33 42 51 60 75 ns tEA Input to Output Enable Delay[4,7] 15 20 25 30 35 ns tER Input to Output Disable Delay[4,7] 15 20 25 30 35 ns tCO1 Synchronous Clock Input to Output Delay 7 8 14 16 20 ns tCO2 Synchronous Clock to Local Feedback to Combinatorial Output[4, 11] 17 20 30 35 42 ns tS1 Dedicated Input or Feedback Set-Up Time to Synchronous Clock Input[7,12] 10 13 15 20 25 ns tS2 I/O Input Set-Up Time to Synchronous Clock Input [7] 20 24 29 36 45 ns tH Input Hold Time from Synchronous Clock Input [7] 0 0 0 0 0 ns tWH Synchronous Clock Input HIGH Time 5 7 8 10 12.5 ns tWL Synchronous Clock Input LOW Time 5 7 8 10 12.5 ns tRW Asynchronous Clear Width[4, 7] 15 20 25 30 35 ns tRR Asynchronous Clear Recovery Time[4, 7] 15 20 25 30 35 ns tRO Asynchronous Clear to Registered Output Delay[7] tPW Asynchronous Preset Width[4,7] 15 20 25 30 35 ns tPR Asynchronous Preset Recovery Time[4,7] 15 20 25 30 35 ns tPO Asynchronous Preset to Registered Output Delay[7] 15 20 25 30 35 ns tCF Synchronous Clock to Local Feedback Input[4,13] 3 3 3 3 6 ns tP External Synchronous Clock Period (1/(fMAX3))[4] 12 14 16 20 25 ns fMAX1 External Feedback Maximum Frequency (1/(tCO1 + tS1))[4,14] 58.8 47.6 34.5 27.7 22.2 MHz fMAX2 Internal Local Feedback Maximum Frequency, lesser of (1/(tS1 + tCF)) or (1/tCO1)[4, 15] 76.9 62.5 55.5 43.4 32.2 MHz 15 20 12 25 30 35 ns CY7C342B Military External Synchronous Switching Characteristics[6] Over Operating Range (continued) Parameter 7C342B-15 7C342B-20 7C342B-25 7C342B-30 7C342B-35 Min. Min. Min. Min. Description Min. fMAX3 Data Path Maximum Frequency, lesser of (1/(tWL + tWH)), (1/(tS1 + tH)) or (1/tCO1)[4,16] 100 Max. 71.4 Max. 62.5 Max. 50 Max. 40 Max. MHz Unit fMAX4 Maximum Register Toggle Frequency (1/(tWL + tWH))[4,17] 100 71.4 62.5 50 40 MHz tOH Output Data Stable Time from Synchronous Clock Input [4,18] 3 3 3 3 3 ns Military External Asynchronous Switching Characteristics[6] Over Operating Range Parameter Description 7C342B-15 7C342B-20 7C342B-25 7C342B-30 7C342B-35 Min. Min. Min. Min. Min. Max. Max. Max. Max. Max. Unit tACO1 Asynchronous Clock Input to Output Delay[7] 15 20 25 30 35 ns tACO2 Asynchronous Clock Input to Local Feedback to Combinatorial Output[19] 25 32 39 46 55 ns tAS1 Dedicated Input or Feedback Set-Up Time to Asynchronous Clock Input[7] tAS2 5 5 5 6 8 ns I/O Input Set-Up Time to Asynchronous Clock Input[7] 14.5 17 19 22 28 ns tAH Input Hold Time from Asynchronous Clock Input[7] 5 6 6 8 10 ns tAWH Asynchronous Clock Input HIGH Time[7] 9 10 11 14 16 ns tAWL Asynchronous Clock Input LOW Time[7, 20] 7 8 9 11 14 ns tACF Asynchronous Clock to Local Feedback Input[4,21] tAP External Asynchronous Clock Period (1/(fMAXA4))[4] 16 18 20 25 30 ns fMAXA1 External Feedback Maximum Frequency in Asynchronous Mode (1/(tACO1 + tAS1))[4,22] 50.0 40 33.3 27.7 23.2 MHz fMAXA2 Maximum Internal Asynchronous Frequency[4,23] 62.5 55.5 50 40 33.3 MHz fMAXA3 Data Path Maximum Frequency in Asynchronous Mode[4,24] 66.6 50 40 33.3 28.5 MHz fMAXA4 Maximum Asynchronous Register Toggle Frequency 1/(tAWH + tAWL)[4,25] 62.5 55.5 50 40 33.3 MHz tAOH Output Data Stable Time from Asynchronous Clock Input[4,26] 12 12 15 15 15 ns 11 13 13 15 18 22 ns CY7C342B Military Typical Internal Switching Characteristics Over Operating Range Parameter Description 7C342B-15 7C342B-20 7C342B-25 7C342B-30 7C342B-35 Min. Min. Min. Min. Min. Max. Max. 4 Max. Unit 9 ns Dedicated Input Pad and Buffer Delay 3 tIO I/O Input Pad and Buffer Delay 3 4 6 6 9 ns tEXP Expander Array Delay 8 10 12 14 20 ns tLAD Logic Array Data Delay 8 10 12 14 16 ns tLAC Logic Array Control Delay 5 7 10 12 13 ns tOD Output Buffer and Pad Delay 3 3 5 5 6 ns tZX Output Buffer Enable Delay[27] 5 5 10 11 13 ns tXZ Output Buffer Disable Delay 13 ns tRSU Register Set-Up Time Relative to Clock Signal at Register 4 5 6 8 10 ns tRH Register Hold Time Relative to Clock Signal at Register 4 5 6 8 10 ns tLATCH Flow Through Latch Delay 1 2 3 4 4 ns tRD Register Delay 1 1 1 2 2 ns tCOMB Transparent Mode Delay[28] 1 2 3 4 4 ns tCH Clock HIGH Time 4 6 8 10 12.5 ns tCL Clock LOW Time 4 6 8 10 12.5 ns tIC Asynchronous Clock Logic Delay tICS Synchronous Clock Delay tFD tPRE 5 7 Max. tIN 5 5 Max. 10 11 6 8 14 16 18 ns 0.5 0.5 2 2 3 ns Feedback Delay 1 1 1 1 2 ns Asynchronous Register Preset Time 3 3 5 6 7 ns tCLR Asynchronous Register Clear Time 3 3 5 6 7 ns tPCW Asynchronous Preset and Clear Pulse Width 3 4 5 6 7 ns tPCR Asynchronous Preset and Clear Recovery Time 3 4 5 6 7 ns tPIA Programmable Interconnect Array Delay Time 10 12 14 14 16 20 ns CY7C342B Switching Waveforms External Combinatorial DEDICATED INPUT/ I/O INPUT tPD1[7] /t PD2 [8] COMBINATORIAL OUTPUT tER[7] COMBINATORIAL OR REGISTERED OUTPUT HIGH-IMPEDANCE THREE-STATE tEA [7] HIGH-IMPEDANCE THREE-STATE VALID OUTPUT C342B-7 External Synchronous DEDICATED INPUTS OR REGISTERED FEEDBACK [7] tS1 tH tWH tWL SYNCHRONOUS CLOCK tCO1 ASYNCHRONOUS CLEAR/PRESET [7] tRW/t PW tRR/t PR tOH tRO/t PO REGISTERED OUTPUTS tCO2 COMBINATORIAL OUTPUT FROM REGISTERED FEEDBACK [11] C342B-8 External Asynchronous DEDICATED INPUTS OR REGISTERED FEEDBACK tAS1 ASYNCHRONOUS CLOCK INPUT ASYNCHRONOUS CLEAR/PRESET tAH tAWH tACO1 tRW/t PW tAWL tRR/t PR tAOH tRO/t PO ASYNCHRONOUS REGISTERED OUTPUTS tACO2 COMBINATORIAL OUTPUT FROM ASYNCHRONOUS REGISTERED FEEDBACK C342B-9 15 CY7C342B Switching Waveforms (continued) Internal Combinatorial tIN INPUT PIN tPIA tIO I/O PIN tEXP EXPANDER ARRAY DELAY tLAC, tLAD LOGIC ARRAY INPUT LOGIC ARRAY OUTPUT C342B-10 Internal Asynchronous tAWH tIOtR tAWL tF CLOCK PIN tIN CLOCK INTO LOGIC ARRAY tIC CLOCK FROM LOGIC ARRAY tRSU tRH DATA FROM LOGIC ARRAY tRD,tLATCH tFD tCLR,tPRE tFD REGISTER OUTPUT TO LOCAL LAB LOGIC ARRAY tPIA REGISTER OUTPUT TO ANOTHER LAB C342B-11 Internal Synchronous tCH tCL SYSTEM CLOCK PIN tIN tICS tRSU tRH SYSTEM CLOCK AT REGISTER DATA FROM LOGIC ARRAY C342B-12 16 CY7C342B Switching Waveforms (continued) Internal Synchronous CLOCK FROM LOGIC ARRAY tRD tOD DATA FROM LOGIC ARRAY tXZ OUTPUT PIN tZX HIGH IMPEDANCE STATE C342B-13 Ordering Information Speed (ns) 12 15 20 25 30 35 Ordering Code CY7C342B-12HC Package Name Package Type H81 68-Pin Windowed Leaded Chip Carrier CY7C342B-12JC J81 68-Lead Plastic Leaded Chip Carrier CY7C342B-12RC R68 68-Pin Windowed Ceramic Pin Grid Array CY7C342B-15HC/HI H81 68-Pin Windowed Leaded Chip Carrier CY7C342B-15JC/JI J81 68-Lead Plastic Leaded Chip Carrier CY7C342B-15RC/RI R68 68-Pin Windowed Ceramic Pin Grid Array CY7C342B-15HMB H81 68-Pin Windowed Leaded Chip Carrier CY7C342B-15RMB R68 68-Pin Windowed Ceramic Pin Grid Array CY7C342B-20HC/HI H81 68-Pin Windowed Leaded Chip Carrier CY7C342B-20JC/JI J81 68-Lead Plastic Leaded Chip Carrier CY7C342B-20RC/RI R68 68-Pin Windowed Ceramic Pin Grid Array CY7C342B-20HMB H81 68-Pin Windowed Leaded Chip Carrier CY7C342B-20RMB R68 68-Pin Windowed Ceramic Pin Grid Array CY7C342B-25HC/HI H81 68-Pin Windowed Leaded Chip Carrier CY7C342B-25JC/JI J81 68-Lead Plastic Leaded Chip Carrier CY7C342B-25RC R68 68-Pin Windowed Ceramic Pin Grid Array CY7C342B-25HMB H81 68-Pin Windowed Leaded Chip Carrier CY7C342B-25RMB R68 68-Pin Windowed Ceramic Pin Grid Array CY7C342B-30HC/HI H81 68-Pin Windowed Leaded Chip Carrier CY7C342B-30JC/JI J81 68-Lead Plastic Leaded Chip Carrier CY7C342B-30RC/RI R68 68-Pin Windowed Ceramic Pin Grid Array CY7C342B-30HMB H81 68-Pin Windowed Leaded Chip Carrier CY7C342B-30RMB R68 68-Pin Windowed Ceramic Pin Grid Array CY7C342B-35HC/HI H81 68-Pin Windowed Leaded Chip Carrier CY7C342B-35JC/JI J81 68-Lead Plastic Leaded Chip Carrier CY7C342B-35RC/RI R68 68-Pin Windowed Ceramic Pin Grid Array CY7C342B-35HMB H81 68-Pin Windowed Leaded Chip Carrier CY7C342B-35RMB R68 68-Pin Windowed Ceramic Pin Grid Array 17 Operating Range Commercial Commercial/ Industrial Military Commercial/ Industrial Military Commercial/ Industrial Military Commercial/ Industrial Military Commercial/ Industrial Military CY7C342B MILITARY SPECIFICATIONS Group A Subgroup Testing DC Characteristics Switching Characteristics Parameter Subgroups Parameter Subgroups VOH 1, 2, 3 tPD1 7, 8, 9, 10, 11 VOL 1, 2, 3 tPD2 7, 8, 9, 10, 11 VIH 1, 2, 3 tPD3 7, 8, 9, 10, 11 VIL 1, 2, 3 tCO1 7, 8, 9, 10, 11 IIX 1, 2, 3 tS1 7, 8, 9, 10, 11 IOZ 1, 2, 3 tS2 7, 8, 9, 10, 11 ICC1 1, 2, 3 tH 7, 8, 9, 10, 11 tWH 7, 8, 9, 10, 11 tWL 7, 8, 9, 10, 11 tRO 7, 8, 9, 10, 11 tPO 7, 8, 9, 10, 11 tACO1 7, 8, 9, 10, 11 tAS1 7, 8, 9, 10, 11 tAH 7, 8, 9, 10, 11 tAWH 7, 8, 9, 10, 11 tAWL 7, 8, 9, 10, 11 Document #: 38-00119-G 18 CY7C342B Package Diagrams 68-Pin Windowed Leaded Chip Carrier H81 19 CY7C342B Package Diagrams (continued) 68-Lead Plastic Leaded Chip Carrier J81 68-Pin Windowed PGA Ceramic R68 (c) Cypress Semiconductor Corporation, 1995. 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