1. General description
The 74HC595; 74HCT595 is an 8-bit serial- in/serial or parallel-out shift register with a
storage regis te r an d 3- state outp u ts. Both the shift and storage register have separate
clocks. The device features a serial input (DS) and a serial output (Q7S) to enable
cascading and an a synchronous reset MR input. A LOW on MR will reset the shift register.
Data is shifted on the LOW-to-HIGH transitions of the SHCP input. The data in the shift
register is transferred to the storage register on a LOW-to- HIGH tran sition of the STCP
input. If both clocks are connected together, the shift register will always be one clock
pulse ahead of the storage register. Data in the storage register appears at the output
whenever the output ena ble input (OE) is LOW. A HIGH on OE causes the outp uts to
assume a high-impedance OFF-state. Operation of the OE input does not affect the state
of the registers. Inputs include clamp diodes. This enables the use of current limiting
resistors to interface inputs to voltages in excess of VCC.
2. Features and benefits
8-bit serial input
8-bit serial or parallel output
Storage register with 3-state outputs
Shift register with direct clear
100 MHz (typical) shift out frequency
Complies with JEDEC standard no. 7A
Input levels:
For 74HC595: CMOS level
For 74HCT595: TTL level
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A ex ce ed s 200 V
Multiple package options
Specified from 40 C to +85 C and from 40 C to +125 C
3. Applications
Serial-to-parallel data conversion
Remote control holding register
74HC595; 74HCT595
8-bit serial-in, serial or parallel-out shift register with output
latches; 3-state
Rev. 8 — 25 February 2016 Product data sheet
© Nexperia B.V. 2017. All rights reserved
74HC_HCT595 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 8 — 25 February 2016 2 of 23
Nexperia 74HC595; 74HCT595
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
4. Ordering information
5. Functional diagram
Table 1. Ordering information
Type number Package
Temperature rang e Name Description Version
74HC595D 40 C to +125 C SO16 plastic small outline package; 16 leads;
body width 3.9 mm SOT109-1
74HCT595D
74HC595DB 40 C to +125 C SSOP16 plastic shrink small outline package; 16 leads;
body width 5.3 mm SOT338-1
74HCT595DB
74HC595PW 40 C to +125 C TSSOP16 plastic thin shrink small outline package; 16 leads;
body width 4.4 mm SOT403-1
74HCT595PW
74HC595BQ 40 C to +125 C DHVQFN16 plastic dual in-line compatible thermal enhanced
very thin quad flat package; no leads; 16 terminals;
body 2.5 3.5 0.85 mm
SOT763-1
74HCT595BQ
Fig 1. Functional di agram
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67$*(6+,)75(*,67(5
4 4444444
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© Nexperia B.V. 2017. All rights reserved
74HC_HCT595 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 8 — 25 February 2016 3 of 23
Nexperia 74HC595; 74HCT595
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
Fig 2. Logic symbol Fig 3. IEC logic symbol
2(05
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4
4
4
4
4
4
4
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46
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Fig 4. Logic diag ram
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© Nexperia B.V. 2017. All rights reserved
74HC_HCT595 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 8 — 25 February 2016 4 of 23
Nexperia 74HC595; 74HCT595
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
6. Pinning information
6.1 Pinning
6.2 Pin description
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 5. Pin configuration SO16, SSOP16 and
TSSOP16 Fig 6. Pin configuration for DHVQFN16
+&
+&7
49
&&
44
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4 6+&3
405
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DDR
+&
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4
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4
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7UDQVSDUHQWWRSYLHZ
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LQGH[DUHD
*1'
Table 2. Pin description
Symbol Pin Description
Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7 15, 1, 2, 3, 4, 5, 6, 7 parallel data output
GND 8 ground (0 V)
Q7S 9 serial data output
MR 10 master reset (active LOW)
SHCP 11 shift register clock input
STCP 12 storage register clock input
OE 13 output enable input (active LOW)
DS 14 serial data input
Q0 15 parallel data output 0
VCC 16 supply voltage
© Nexperia B.V. 2017. All rights reserved
74HC_HCT595 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 8 — 25 February 2016 5 of 23
Nexperia 74HC595; 74HCT595
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
7. Functional description
[1] H = HIGH voltage state;
L = LOW voltage state;
= LOW-to-HIGH transition;
X = don’t care;
NC = no change;
Z = high-impedance OFF-state.
Table 3. Function table[1]
Control Input Output Function
SHCP STCP OE MR DS Q7S Qn
X X L L X L NC a LOW-level on MR only affects the shift registers
XL L X L L empty shift register loaded into storage register
X X H L X L Z shift register clear; parallel outputs in high-impedance OFF-state
X L H H Q6S NC logic HIGH-level shifted into shift register stage 0. Contents of all
shift register stages shifted through, e.g. previous state of stage 6
(internal Q6S) appears on the serial output (Q7S).
XL H X NC QnS contents of shift register stages (internal QnS) are transferred to
the storage register and parallel output stages
L H X Q6S QnS contents of shif t re gi st er sh ifted thro ugh; previous contents of the
shift register is transferred to the storage register and the parallel
output stages
Fig 7. Timing diagram
6+&3
'6
67&3
05
2(
4
4
4
4
46
=VWDWH
=VWDWH
=VWDWH
=VWDWH
PQD
© Nexperia B.V. 2017. All rights reserved
74HC_HCT595 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 8 — 25 February 2016 6 of 23
Nexperia 74HC595; 74HCT595
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
8. Limiting values
[1] For SO16 package: Ptot derates linearly with 8 mW/K above 70 C.
[2] For SSOP16 and TSSOP16 packages: Ptot derates linearly with 5.5 mW/K above 60 C.
[3] For DHVQFN16 package: Ptot derates linearly with 4.5 mW/K above 60 C.
9. Recommended operating conditions
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
VCC supply voltage 0.5 +7 V
IIK input clamping current VI < 0.5 V or VI>V
CC + 0.5 V - 20 mA
IOK output clamping current VO<0.5 V or VO > VCC + 0.5 V - 20 mA
IOoutput current VO=0.5 V to (VCC +0.5V)
pin Q7S - 25 mA
pins Qn - 35 mA
ICC supply current -70mA
IGND ground current 70 - mA
Tstg storage temperature 65 +150 C
Ptot total power dissipation SO16 package [1] -500mW
SSOP16 package [2] -500mW
TSSOP16 package [2] -500mW
DHVQFN16 package [3] -500mW
Table 5. Recommended operating con ditions
Symbol Parameter Conditions 74HC595 74HCT595 Unit
Min Typ Max Min Typ Max
VCC supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V
VIinput voltage 0 - VCC 0-V
CC V
VOoutput voltage 0 - VCC 0-V
CC V
t/V input transition rise and
fall rate VCC = 2.0 V - - 625 - - - ns/V
VCC = 4.5 V - 1.67 139 - 1.67 139 ns/V
VCC =6.0V - - 83 - - - ns/V
Tamb ambient temperature 40 +25 +125 40 +25 +125 C
© Nexperia B.V. 2017. All rights reserved
74HC_HCT595 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 8 — 25 February 2016 7 of 23
Nexperia 74HC595; 74HCT595
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
10. Static characteristics
Table 6. Static chara cteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 40 C to +85 C40 C to +125 CUnit
Min Typ Max Min Max
74HC595
VIH HIGH-level
input voltage VCC = 2.0 V 1.5 1.2 - 1.5 - V
VCC = 4.5 V 3.15 2.4 - 3.15 - V
VCC = 6.0 V 4.2 3.2 - 4.2 - V
VIL LOW-level
input voltage VCC = 2.0 V - 0.8 0.5 - 0.5 V
VCC = 4.5 V - 2.1 1.35 - 1.35 V
VCC = 6.0 V - 2.8 1.8 - 1.8 V
VOH HIGH-level
output voltage VI=V
IH or VIL
all outputs
IO=20 A; VCC = 2.0 V 1.9 2.0 - 1.9 - V
IO=20 A; VCC = 4.5 V 4.4 4.5 - 4.4 - V
IO=20 A; VCC = 6.0 V 5.9 6.0 - 5.9 - V
Q7S output
IO=4mA; V
CC = 4.5 V 3.84 4.32 - 3.7 - V
IO=5.2 mA; VCC = 6.0 V 5.34 5.81 - 5.2 - V
Qn bus driver outputs
IO=6mA; V
CC = 4.5 V 3.84 4.32 - 3.7 - V
IO=7.8 mA; VCC = 6.0 V 5.34 5.81 - 5.2 - V
VOL LOW-level
output voltage VI=V
IH or VIL
all outputs
IO=20A; VCC = 2.0 V - 0 0.1 - 0.1 V
IO=20A; VCC = 4.5 V - 0 0.1 - 0.1 V
IO=20A; VCC = 6.0 V - 0 0.1 - 0.1 V
Q7S output
IO=4mA; V
CC = 4.5 V - 0.15 0.33 - 0.4 V
IO=5.2mA; V
CC = 6.0 V - 0.16 0.33 - 0.4 V
Qn bus driver outputs
IO=6mA; V
CC = 4.5 V - 0.15 0.33 - 0.4 V
IO=7.8mA; V
CC = 6.0 V - 0.16 0.33 - 0.4 V
IIinput leakage
current VI=V
CC or GND; VCC =6.0V - - 1.0 - 1.0 A
IOZ OFF-state
output current VI=V
IH or VIL; VCC =6.0V;
VO=V
CC or GND --5.0 - 10 A
ICC supply current VI=V
CC or GND; IO=0A;
VCC =6.0V - - 80 - 160 A
CIinput
capacitance -3.5- - -pF
© Nexperia B.V. 2017. All rights reserved
74HC_HCT595 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 8 — 25 February 2016 8 of 23
Nexperia 74HC595; 74HCT595
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
74HCT595
VIH HIGH-level
input voltage VCC = 4.5 V to 5.5 V 2.0 1.6 - 2.0 - V
VIL LOW-level
input voltage VCC = 4.5 V to 5.5 V - 1.2 0.8 - 0.8 V
VOH HIGH-level
output voltage VI=V
IH or VIL; VCC =4.5V
all outputs
IO=20 A 4.4 4.5 - 4.4 - V
Q7S output
IO=4 mA 3.84 4.32 - 3.7 - V
Qn bus driver outputs
IO=6 mA 3.7 4.32 - 3.7 - V
VOL LOW-level
output voltage VI=V
IH or VIL; VCC =4.5V
all outputs
IO=20A - 0 0.1 - 0.1 V
Q7S output
IO= 4.0 mA - 0.15 0.33 - 0.4 V
Qn bus driver outputs
IO= 6.0 mA - 0.16 0.33 - 0.4 V
IIinput leakage
current VI=V
CC or GND; VCC =5.5V - - 1.0 - 1.0 A
IOZ OFF-state
output current VI=V
IH or VIL; VCC =5.5 V;
VO=V
CC or GND --5.0 - 10 A
ICC supply current VI=V
CC or GND; IO=0A;
VCC =5.5V - - 80 - 160 A
ICC additional
supply current per input pin; IO=0A; V
I=V
CC
2.1 V; other inputs at VCC or GND;
VCC = 4.5 V to 5.5 V
pins MR, SHCP, STCP, OE - 150 675 - 735 A
pin DS - 25 113 - 123 A
CIinput
capacitance -3.5- - -pF
Table 6. Static chara cteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 40 C to +85 C40 C to +125 CUnit
Min Typ Max Min Max
© Nexperia B.V. 2017. All rights reserved
74HC_HCT595 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 8 — 25 February 2016 9 of 23
Nexperia 74HC595; 74HCT595
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
11. Dynamic characteristics
Table 7. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 13.
Symbol Parameter Conditions 25 C40 C to +85 C40 C to +125 CUnit
Min Typ[1] Max Min Max Min Max
74HC595
tpd propagation
delay SHCP to Q7S; see Figure 8 [2]
VCC = 2 V - 52 160 - 200 - 240 ns
VCC = 4.5 V - 19 32 - 40 - 48 ns
VCC = 6 V - 15 27 - 34 - 41 ns
STCP to Qn; see Figure 9 [2]
VCC = 2 V - 55 175 - 220 - 265 ns
VCC = 4.5 V - 20 35 - 44 - 53 ns
VCC = 6 V - 16 30 - 37 - 45 ns
MR to Q7S; see Figure 11 [3]
VCC = 2 V - 47 175 - 220 - 265 ns
VCC = 4.5 V - 17 35 - 44 - 53 ns
VCC = 6 V - 14 30 - 37 - 45 ns
ten enable time OE to Qn; see Figure 12 [4]
VCC = 2 V - 47 150 - 190 - 225 ns
VCC = 4.5 V - 17 30 - 38 - 45 ns
VCC = 6 V - 14 26 - 33 - 38 ns
tdis disable time OE to Qn; see Figure 12 [5]
VCC = 2 V - 41 150 - 190 - 225 ns
VCC = 4.5 V - 15 30 - 38 - 45 ns
VCC = 6 V - 12 27 - 33 - 38 ns
tWpulse width SHCP HIGH or LOW;
see Figure 8
VCC = 2 V 75 17 - 95 - 110 - ns
VCC = 4.5 V 15 6 - 19 - 22 - ns
VCC = 6 V 13 5 - 16 - 19 - ns
STCP HIGH or LOW;
see Figure 9
VCC = 2 V 75 11 - 95 - 110 - ns
VCC = 4.5 V 15 4 - 19 - 22 - ns
VCC = 6 V 13 3 - 16 - 19 - ns
MR LOW; see Figure 11
VCC = 2 V 75 17 - 95 - 110 - ns
VCC = 4.5 V 15 6 - 19 - 22 - ns
VCC = 6 V 13 5 - 16 - 19 - ns
© Nexperia B.V. 2017. All rights reserved
74HC_HCT595 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 8 — 25 February 2016 10 of 23
Nexperia 74HC595; 74HCT595
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
tsu set-up time DS to SHCP; see Figure 9
VCC = 2 V 50 11 - 65 - 75 - ns
VCC = 4.5 V 10 4 - 13 - 15 - ns
VCC = 6 V 9 3 - 11 - 13 - ns
SHCP to STCP;
see Figure 10
VCC = 2 V 75 22 - 95 - 110 - ns
VCC = 4.5 V 15 8 - 19 - 22 - ns
VCC = 6 V 13 7 - 16 - 19 - ns
thhold time DS to SHCP; see Figure 10
VCC = 2 V 3 6- 3 - 3 - ns
VCC = 4.5 V 3 2- 3 - 3 - ns
VCC = 6 V 3 2- 3 - 3 - ns
trec recovery
time MR to SHCP; see Figure 11
VCC = 2 V 5 0 19 - 65 - 75 - ns
VCC = 4.5 V 10 7- 13 - 15 - ns
VCC = 6 V 9 6- 11 - 13 - ns
fmax maximum
frequency SHCP or STCP;
see Figure 8 and 9
VCC = 2 V 9 30 - 4.8 - 4 - MHz
VCC = 4.5 V 30 91 - 24 - 20 - MHz
VCC = 6 V 35 108 - 28 - 24 - MHz
CPD power
dissipation
capacitance
fi = 1 MHz; VI=GNDtoV
CC [6][7] -115- - - - - pF
Table 7. Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 13.
Symbol Parameter Conditions 25 C40 C to +85 C40 C to +125 CUnit
Min Typ[1] Max Min Max Min Max
© Nexperia B.V. 2017. All rights reserved
74HC_HCT595 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 8 — 25 February 2016 11 of 23
Nexperia 74HC595; 74HCT595
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
[1] Typical values are measured at nominal supply voltage.
[2] tpd is the same as tPHL and tPLH.
[3] tpd is the same as tPHL only.
[4] ten is the same as tPZL and tPZH.
[5] tdis is the same as tPLZ and tPHZ.
[6] CPD is used to determine the dynamic power dissipation (PDin W).
PD=C
PD VCC2fi+(CLVCC2fo) where:
fi= input frequency in MHz;
fo= output frequency in MHz;
(CLVCC2fo) = sum of outputs;
CL= output load capacitance in pF;
VCC = supply voltage in V.
[7] All 9 outputs switching.
74HCT595; VCC = 4.5 V to 5.5 V
tpd propagation
delay SHCP to Q7S; see Figure 8 [2] -2542- 53 - 63ns
STCP to Qn; see Figure 9 [2] -2440- 50 - 60ns
MR to Q7S; see Figure 11 [3] -2340- 50 - 60ns
ten enable time OE to Qn; see Figure 12 [4] -2135- 44 - 53ns
tdis disable time OE to Qn; see Figure 12 [5] -1830- 38 - 45ns
tWpulse width SHCP HIGH or LOW;
see Figure 8 16 6 - 20 - 24 - ns
STCP HIGH or LOW;
see Figure 9 16 5 - 20 - 24 - ns
MR LOW; see Figure 11 20 8 - 25 - 30 - ns
tsu set-up time DS to SHCP; see Figure 9 16 5 - 20 - 24 - ns
SHCP to STCP;
see Figure 10 16 8 - 20 - 24 - ns
thhold time DS to SHCP; see Figure 10 32- 3 - 3 - ns
trec recovery
time MR to SHCP; see Figure 11 10 7- 13 - 15 - ns
fmax maximum
frequency SHCP and STCP;
see Figure 8 and 930 52 - 24 - 20 - MHz
CPD power
dissipation
capacitance
fi = 1 MHz;
VI=GNDtoV
CC 1.5 V [6]
[7] - 130 - - - - - pF
Table 7. Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 13.
Symbol Parameter Conditions 25 C40 C to +85 C40 C to +125 CUnit
Min Typ[1] Max Min Max Min Max
© Nexperia B.V. 2017. All rights reserved
74HC_HCT595 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 8 — 25 February 2016 12 of 23
Nexperia 74HC595; 74HCT595
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
12. Waveforms
Measurement points are given in Table 8.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 8. Shift clock pulse, maximum frequency and inp ut to ou tput propagation delays
PQD
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W3/+ W3+/
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IPD[
90
92+
9,
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90
Measurement points are given in Table 8.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 9. Storage clock to output propagation delays
PQD
67&3LQSXW
4QRXWSXW
W3/+ W3+/
W:
WVX IPD[
90
92+
9,
*1'
92/
90
6+&3LQSXW
9,
*1'
90
© Nexperia B.V. 2017. All rights reserved
74HC_HCT595 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 8 — 25 February 2016 13 of 23
Nexperia 74HC595; 74HCT595
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
Measurement points are given in Table 8.
The shaded areas indicate when the input is permitted to change for predictable output performance.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 10. Data set-up and ho ld times
PQD
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WK
WVX
WK
WVX
90
90
90
9,
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Measurement points are given in Table 8.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 11. Master reset to output propagation delays
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05LQSXW
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3+/
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9
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0
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© Nexperia B.V. 2017. All rights reserved
74HC_HCT595 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 8 — 25 February 2016 14 of 23
Nexperia 74HC595; 74HCT595
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
Measurement points are given in Table 8.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 12. Enable and disable times
PVD
W3/=
W3+=
RXWSXWV
GLVDEOHG
RXWSXWV
HQDEOHG
RXWSXWV
HQDEOHG
2(LQSXW 90
W3=/
W3=+
90
90
4QRXWSXW
/2:WR2))
2))WR/2:
4QRXWSXW
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2))WR+,*+
WUWI
Table 8. Measurement points
Type Input Output
VMVM
74HC595 0.5VCC 0.5VCC
74HCT595 1.3 V 1.3 V
© Nexperia B.V. 2017. All rights reserved
74HC_HCT595 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 8 — 25 February 2016 15 of 23
Nexperia 74HC595; 74HCT595
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
Test data is given in Table 9.
Definitions for test circuit:
CL = load capacitance including jig and probe capacitance.
RL = load resistance.
RT = termination resistance should be equal to the output impedance Zo of the pulse generator.
S1 = test selection switch.
Fig 13. Test circuit for measuring switching times
9
0
9
0
W
:
W
:
9
9
,
9
,
QHJDWLYH
SXOVH
SRVLWLYH
SXOVH
9
9
0
9
0
W
I
W
U
W
U
W
I
DDG
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9
&&
9
&&
9,92
57
5/6
&/
RSHQ
*
Table 9. Test data
Type Input Load S1 position
VItr, tfCLRLtPHL, tPLH tPZH, tPHZ tPZL, tPLZ
74HC595 VCC 6 ns 50 pF 1 kopen GND VCC
74HCT595 3 V 6 ns 50 pF 1 kopen GND VCC
© Nexperia B.V. 2017. All rights reserved
74HC_HCT595 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 8 — 25 February 2016 16 of 23
Nexperia 74HC595; 74HCT595
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
13. Package outline
Fig 14. Package outline SOT109-1 (SO16)
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© Nexperia B.V. 2017. All rights reserved
74HC_HCT595 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 8 — 25 February 2016 17 of 23
Nexperia 74HC595; 74HCT595
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
Fig 15. Package outline SOT338-1 (SSOP16)
81,7 $
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© Nexperia B.V. 2017. All rights reserved
74HC_HCT595 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 8 — 25 February 2016 18 of 23
Nexperia 74HC595; 74HCT595
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
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© Nexperia B.V. 2017. All rights reserved
74HC_HCT595 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 8 — 25 February 2016 19 of 23
Nexperia 74HC595; 74HCT595
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
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© Nexperia B.V. 2017. All rights reserved
74HC_HCT595 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 8 — 25 February 2016 20 of 23
Nexperia 74HC595; 74HCT595
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
14. Abbreviations
15. Revision history
Table 10. Abbreviations
Acronym Abbreviation
CMOS Complementary Metal Oxide Semiconductor
DUT Device Under Test
ESD ElectroStatic Discharge
HBM Human Body Model
LSTTL Low-power Schottky Transistor-Transistor Logic
MM Machine Model
Table 11. Revision history
Document ID Release date Data sheet status Change notice Supersedes
74HC_HCT595 v.8 20160225 Product data sheet - 74HC_HCT595 v.7
Modifications: •Type numbers 74HC595N and 74HCT595N (SOT38-4) removed .
74HC_HCT595 v.7 20150126 Product data sheet - 74HC_HCT595 v.6
Modifications: •Table 7: Power dissipation capacitance condi tio n fo r 74 HCT 5 95 is corr ected.
74HC_HCT595 v.6 20111212 Product data sheet - 74HC_HCT595 v.5
Modifications: •Legal pages updated.
74HC_HCT595 v.5 20110628 Product data sheet - 74HC_HCT595 v.4
74HC_HCT595 v.4 20030604 Produ ct s pecification - 74HC_HCT595_CNV v.3
74HC_HCT595_CNV v.3 19980604 Product specification - -
© Nexperia B.V. 2017. All rights reserved
74HC_HCT595 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 8 — 25 February 2016 21 of 23
Nexperia 74HC595; 74HCT595
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
16. Legal information
16.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of device (s) descr ibed in this d ocument m ay have cha nged since thi s document w as published and may dif fe r in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nexperia.com.
16.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. Nexperia does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liab ility for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and tit le. A short data sh eet is intended
for quick reference only and shou ld not b e relied u pon to cont ain det ailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local Nexperia sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall pre va il.
Product specificat io n — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
Nexperia and its customer, unless Nexperia and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the Nexperia product is
deemed to off er functions and qualities beyond those described in the
Product data sheet.
16.3 Disclaimers
Limited warr a nty and liability — Information in this document is believed to
be accurate and reliable. However, Nexperia does not give any
representations or warrant ies, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. Nexperia takes no
responsibility for the content in this document if provided by an information
source outside of Nexperia.
In no event shall Nexperia be liable for any indirect, incidental,
punitive, special or consequ ential damages (including - wit hout limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, Nexperia’s aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of Nexperia.
Right to make changes — Nexperia reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all informa tion supplied prior
to the publication hereof .
Suitability for use — Nexperia products are not designed,
authorized or warranted to be suitable for use in life support , life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of a Nexperia product can reasonably be expected
to result in perso nal injury, death or severe property or environmental
damage. Nexperia and its suppliers accept no liability for
inclusion and/or use of Nexperia products in such equipment or
applications and ther efore such inclu sion and/or use is at the cu stomer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. Nexperia makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and ope ration of their applications
and products using Nexperia products, and Nexperia
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the Nexperia
product is suitable and fit for the customer’s applications and
products planned, as well as fo r the planned application and use of
customer’s third party customer(s). Custo mers should provide appropriate
design and operating safeguards to minimize the risks associate d with t heir
applications and products.
Nexperia does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party custo mer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using Nexperia
products in order to avoid a default of the applications and
the products or of the application or use by cust omer’s third party
customer(s). Nexperia does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — Nexperia
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nexperia.com/profile/terms, unless otherwise
agreed in a valid written individua l agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. Nexperia hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of Nexperia products by customer.
No offer to sell or license — Nothing i n this document may be interpreted or
construed as an of fer t o sell product s that is open for accept ance or the gr ant,
conveyance or implication of any license under any copyrights, patents or
other industrial or inte llectual property rights.
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contain s data from the objective specification for product development.
Preliminary [short] dat a sheet Qualification This document contain s data from the preliminar y specification.
Product [short] data sheet Production This document contains the product specification.
© Nexperia B.V. 2017. All rights reserved
74HC_HCT595 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 8 — 25 February 2016 22 of 23
Nexperia 74HC595; 74HCT595
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific Nexperia product is automotive qualified,
the product is not suitable for aut omo tive use. It i s neither qua lif ied nor test ed
in accordance with automotive testing or application requirements. Nexperia
accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automot ive specifications and standards, custome r
(a) shall use the product without Nexperia’s warranty of the
product for such au tomotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
Nexperia’s specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies Nexperia for any
liability, damages or failed product cl aims resulting from custome r design and
use of the product for automotive applications beyond Nexperia’s
standard warranty and Nexperia’s product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
16.4 Trademarks
Notice: All referenced b rands, produc t names, service names and trademarks
are the property of their respective ow ners.
17. Contact information
For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: salesaddresses@nexperia.com
Nexperia 74HC595; 74HCT595
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
18. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3 Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
4 Ordering information. . . . . . . . . . . . . . . . . . . . . 2
5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
7 Functional description . . . . . . . . . . . . . . . . . . . 5
8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6
9 Recommended operating conditions. . . . . . . . 6
10 Static characteristics. . . . . . . . . . . . . . . . . . . . . 7
11 Dynamic characteristics . . . . . . . . . . . . . . . . . . 9
12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 16
14 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 20
15 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 20
16 Legal information. . . . . . . . . . . . . . . . . . . . . . . 21
16.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 21
16.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
16.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 21
16.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 22
17 Contact information. . . . . . . . . . . . . . . . . . . . . 22
18 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
© Nexperia B.V. 2017. All rights reserved
For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: salesaddresses@nexperia.com
Date of release:
25 February 2016
