S-8232 Series
www.sii-ic.com
BATTERY PROTECTION IC
FOR 2-SERIAL-CELL PACK
© Seiko Instruments Inc., 1999-2011 Rev.6.1_00
Seiko Instruments Inc. 1
The S-8232 series is a lithium-ion / lithium-polymer rechargeable battery protection IC incorporating high-
accuracy voltage detection circuit and delay circuit.
The S-8232 series is suitable for 2-cell serial lithium-ion / lithium-p olymer battery packs.
Features
(1) Internal high-accuracy voltage detection circuit
• Overcharge detection voltage 3.85 V ± 25 mV to 4.60 V ± 25 mV Applicable in 5 mV step
• Overcharge release voltage 3.60 V ± 50 mV to 4.60 V ± 50 mV Applicable in 5 mV step
(The overcharge release voltage can be selected within the range where a difference from overcharge
detection voltage is 0 V to 0.3 V.)
• Overdischarge detection voltage 1.70 V ± 80 mV to 2.60 V ± 80 mV Applicable in 50 mV step
• Overdischarge release voltage 1.70 V ± 100 mV to 3.80 V ± 100 mV Applicable in 50 mV step
(The overdischarge release voltage can be selected within the range where a difference from
overdischarge detection voltage is 0 V to 1.2 V.)
• Overcurrent detection voltage 1 0.07 V ± 20 mV to 0.30 V ± 20 mV Applicable in 5 mV step
(2) High input-voltage devi ce : Absolute maximum ratings 18 V.
(3) Wide operating voltage range : 2.0 V to 16 V
(4) The delay time for every detection can be set via an external capacitor.
(Each delay time for Overcharge detection, Overdischarge detection, Overcurrent detection are
“Proportion of hundred to ten to one”.)
(5) Two overcurrent detection levels (Protection for short-circuiting)
(6) Internal auxiliary over voltage detection circuit (Fail-safe for overcharge detection voltage)
(7) Internal charge circuit for 0 V battery (Unavail able is option)
(8) Low current consumption
• Operation mode 7.5 μA typ. 14.2 μA max. (− 40°C to + 85°C)
• Power-down mode 0.2 nA typ. 0.1 μA max. (− 40°C to + 85°C)
(9) Lead-free, Sn100%, halogen -free*1
*1. Refer to “ Product Name Structure” for details.
Applications
• Lithium-ion rechargeable battery packs
• Lithium- polymer rechargeable battery packs
Package
• 8-Pin TSSOP
BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK
S8232 Series Rev.6.1_00
Seiko Instruments Inc.
2
Block Diagram
Auxiliary
overcharge
detector 1
Reference
voltage 1
DO, CO control signal
CO
DO
ICT
VM
VSS
VC
SENS
VCC
RCOL
Overcharge
detector 1
Over-
discharge
detector 1
Over-
discharge
detector 2
Overcharge
detector 2
Auxiliary
overcharge
detector 2
Reference
voltage 2
Control
logic
Delay circuit
control signal
Delay circuit control signal
Delay circuit
control signal Delay circuit
Delay circuit
control signal
Over current
detection circuit
−
+
−
+
−
+
+
−
+
−
+
−
Remark Resistor (RCOL) is connected to the Nch transistor although CO pin serves as a CMOS output.
For this, impedance becomes high when outputting “L” from CO pin. Refer to the “ Electrical
Characteristics” for the impeda nce value.
Figure 1
BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK
Rev6.1_00 S-8232 Series
Seiko Instruments Inc. 3
Product Name Structure
1. Product Name
S-8232 xx FT - T2 - x
IC direction in tape specifications
*1
Package code
FT : 8-Pin TSSOP
Serial code
Sequentially set from AA to ZZ
Environmental code
U: Lead-free (Sn 100%), halogen-free
S: Lead-free, halogen-free
G: Lead-free (for details, please contact our sales office)
*1. Refer to the tape specifications.
2. Package
Drawing Code
Package Name Package Tape Reel
8-Pin TSSOP FT008-A-P-SD FT008-E-C-SD FT008 -E-R-SD
BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK
S8232 Series Rev.6.1_00
Seiko Instruments Inc.
4
3. Product Name List
Table 1 (1 / 2)
Product name
Overcharge
detection
voltage 1, 2
[V
CU
]
Overcharge
release vo ltage 1, 2
[V
CD
]
Overdischarge
detection
voltage 1, 2
[V
DD
]
Overdischarge
release
voltage1, 2
[V
DU
]
Overcurrent
detection
voltage 1
[V
IOV1
]
Overcharge
detection
delay t ime
[t
CU
]
(C3
=
0.22
μ
F)
0 V battery
charging
function
S-8232AAFT-T2-x 4.25 V
±
25 mV 4 .05 V
±
50 mV 2.40 V
±
80 mV 3.00 V
±
100 mV 0.150 V
±
20 mV 1.0 s Available
S-8232ABFT-T2-x 4.35 V
±
25 mV 4 .15 V
±
50 mV 2.30 V
±
80 mV 3.00 V
±
100 mV 0.300 V
±
20 mV 1.0 s Available
S-8232ACFT-T2-x 4.35 V
±
25 mV 4 .15 V
±
50 mV 2.30 V
±
80 mV 3.00 V
±
100 mV 0.300 V
±
20 mV 1 .0 s Unavailable
S-8232AEFT-T2-x 4.35 V
±
25 mV 4 .28 V
±
50 mV 2.15 V
±
80 mV 2.80 V
±
100 mV 0.100 V
±
20 mV 1.0 s Available
S-8232AFFT-T2-x 4.25 V
±
25 mV 4 .05 V
±
50 mV 2.30 V
±
80 mV 2.70 V
±
100 mV 0.300 V
±
20 mV 1.0 s Available
S-8232AGFT-T2-x 4.25 V
±
25 mV 4 .05 V
±
50 mV 2.20 V
±
80 mV 2.40 V
±
100 mV 0.200 V
±
20 mV 1.0 s Available
S-8232AHFT-T2-x 4.25 V
±
25 mV 4 .05 V
±
50 mV 2.20 V
±
80 mV 2.40 V
±
100 mV 0.300 V
±
20 mV 1.0 s Available
S-8232AIFT-T2-x 4.325 V
±
25 mV 4.325 V
±
25 mV
*1
*2
2.40 V
±
80 mV 3.00 V
±
100 mV 0.300 V
±
20 mV 1 .0 s Unavailable
S-8232AJFT-T2-x 4.25 V
±
25 mV 4 .05 V
±
50 mV 2.40 V
±
80 mV 3.00 V
±
100 mV 0.150 V
±
20 mV 1 .0 s Unavailable
S-8232AKFT-T2-x 4.20 V
±
25 mV 4 .00 V
±
50 mV 2.30 V
±
80 mV 2.90 V
±
100 mV 0.200 V
±
20 mV 1.0 s Available
S-8232ALFT-T2-x 4.30 V
±
25 mV 4 .05 V
±
50 mV 2.00 V
±
80 mV 3.00 V
±
100 mV 0.200 V
±
20 mV 1.0 s Available
S-8232AMFT-T2-x 4.19 V
±
25 mV 4 .19 V
±
25 mV
*1
2.00 V
±
80 mV 3.00 V
±
100 mV 0.190 V
±
20 mV 1.0 s Available
S-8232ANFT-T2-x 4.325 V
±
25 mV 4.325 V
±
25 mV
*1
*3
2.40 V
±
80 mV 3.00 V
±
100 mV 0.300 V
±
20 mV 1 .0 s Unavailable
S-8232AOFT-T2-x 4.30 V
±
25 mV 4 .05 V
±
50 mV 2.00 V
±
80 mV 3.00 V
±
100 mV 0.230 V
±
20 mV 1.0 s Available
S-8232APFT-T2-x 4.28 V
±
25 mV 4 .05 V
±
50 mV 2.30 V
±
80 mV 2.90 V
±
100 mV 0.100 V
±
20 mV 1 .0 s Unavailable
S-8232ARFT-T2-x 4.325 V
±
25 mV 4.325 V
±
25 mV
*1
*3
2.00 V
±
80 mV 2.50 V
±
100 mV 0.300 V
±
20 mV 1 .0 s Unavailable
S-8232ASFT-T2-x
*4
4.295 V
±
25 mV 4.20 V
±
50 mV
*3
2.30 V
±
80 mV 3.00 V
±
100 mV 0.300 V
±
20 mV 1 .0 s Unavailable
S-8232ATFT-T2-x 4.125 V
±
25 mV 4.125 V
±
25 mV
*1
2.00 V
±
80 mV 3.00 V
±
100 mV 0.190 V
±
20 mV 1.0 s Available
S-8232AUFT-T2-x 4.30 V
±
25 mV 4 .10 V
±
50 mV 2.40 V
±
80 mV 3.00 V
±
100 mV 0.200 V
±
20 mV 1 .0 s Unavailable
S-8232AVFT-T2-x 4.30 V
±
25 mV 4 .05 V
±
50 mV 2.00 V
±
80 mV 3.00 V
±
100 mV 0.300 V
±
20mV 1.0 s Available
S-8232AWFT-T2-x 4.35 V
±
25 mV 4 .15 V
±
50 mV 2.30 V
±
80 mV 3.00 V
±
100 mV 0.150 V
±
20 mV 1 .0 s Unavailable
S-8232AXFT-T2-x 4.325 V
±
25 mV 4.200 V
±
50 mV 2.30 V
±
80 mV 3.00 V
±
100 mV 0.20 V
±
20 mV 1.0 s Unavailable
S-8232AYFT-T2-x 4.30 V
±
25 mV 4 .05 V
±
50 mV 2.00 V
±
80 mV 2.00 V
±
80 mV 0.20 V
±
20 mV 1.0 s Available
S-8232AZFT-T2-x 4.30 V
±
25 mV 4 .05 V
±
50 mV 2.30 V
±
80 mV 2.30 V
±
80 mV 0.20 V
±
20 mV 1.0 s Available
S-8232NAFT-T2-x 4.325 V
±
25 mV 4.325 V
±
25 mV
*1
*3
2.40 V
±
80 mV 3.00 V
±
100 mV 0.15 V
±
20 mV 1.0 s Unavailable
S-8232NBFT-T2-x 4.35 V
±
25 mV 4 .25 V
±
50 mV 3.00 V
±
80 mV 3.70 V
±
100 mV 0.30 V
±
20 mV 1.0 s Unavailable
S-8232NCFT-T2-x 4.275 V
±
25 mV 4.05 V
±
50 mV 2.20 V
±
80 mV 3.00 V
±
100 mV 0.20 V
±
20 mV 1.0 s Unavailable
S-8232NDFT-T2-x 4.35 V
±
25 mV 4.15 V
±
50 mV 2.30 V
±
80 mV 2.30 V
±
80 mV 0.15 V
±
20 mV 1.0 s Available
S-8232NEFT-T2-x 4.35 V
±
25 mV 4.15 V
±
50 mV 2.30 V
±
80 mV 3.00 V
±
100 mV 0.23 V
±
20 mV 1.0 s Available
S-8232NFFT-T2-x 4.325 V
±
25 mV 4.1 V
±
50 mV
*3
2.30 V
±
80 mV 2.90 V
±
100 mV 0.21 V
±
20 mV 1.0 s Unavailable
S-8232NGFT-T2-x 4.35 V
±
25 mV 4.15 V
±
50 mV 2.60 V
±
80 mV 3.00 V
±
100 mV 0.30 V
±
20 mV 1.0 s Available
S-8232NHFT-T2-x 4.28 V
±
25 mV 4.05 V
±
50 mV 2.30 V
±
80 mV 2.90 V
±
100 mV 0.11 V
±
20 mV 1.0 s Unavailable
S-8232NIFT-T2-x 4.25 V
±
25 mV 4.05 V
±
50 mV
*3
2.50 V
±
80 mV 3.00 V
±
100 mV 0.15 V
±
20 mV 1.0 s Unavailable
S-8232NJFT-T2-x 4.28 V
±
25 mV 4.05 V
±
50 mV 2.30 V
±
80 mV 2.90 V
±
100 mV 0.11 V
±
20 mV 1.0 s Available
S-8232NKFT-T2-x 4.35 V
±
25 mV 4.15 V
±
50 mV 2.30 V
±
80 mV 2.30 V
±
80 mV 0.12 V
±
20 mV 1.0 s Available
S-8232NLFT-T2-x 4.30 V
±
25 mV 4.05 V
±
50 mV 2.30 V
±
80 mV 3.00 V
±
100 mV 0.23 V
±
20 mV 1.0 s Available
S-8232NMFT-T2-x 4.28 V
±
25 mV 4.05 V
±
50 mV 2.30 V
±
80 mV 2.90 V
±
100 mV 0.08 V
±
20 mV 1.0 s Available
BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK
Rev6.1_00 S-8232 Series
Seiko Instruments Inc. 5
Table 1 (2 / 2)
Product name
Overcharge
detection
voltage 1, 2
[V
CU
]
Overcharge
release vo ltage 1, 2
[V
CD
]
Overdischarge
detection
voltage 1, 2
[V
DD
]
Overdischarge
release
voltage1, 2
[V
DU
]
Overcurrent
detection
voltage 1
[V
IOV1
]
Overcharge
detection
delay t ime
[t
CU
]
(C3
=
0.22
μ
F)
0 V battery
charging
function
S-8232NNFT-T2-x 4.28 V
±
25 mV 4.08 V
±
50 mV
*3
2.20 V
±
80 mV 2.40 V
±
100 mV 0.13 V
±
20 mV 1.0 s Unavailable
S-8232NOFT-T2-x 4.295 V
±
25 mV 4.045 V
±
50 mV
*3
2.20 V
±
80 mV 2.40 V
±
100 mV 0.13 V
±
20 mV 1.0 s Unavailable
S-8232NPFT-T2-x 4.25 V
±
25 mV 4.05 V
±
50 mV 2.30 V
±
80 mV 3.00 V
±
100 mV 0.30 V
±
20 mV 1.0 s Unavailable
S-8232NQFT-T2-x 4.25 V
±
25 mV 4.05 V
±
50 mV 2.60 V
±
80 mV 3.00 V
±
100 mV 0.30 V
±
20 mV 1.0 s Unavailable
S-8232NRFT-T2-x 4.15 V
±
25 mV 3.95 V
±
50 mV 2.60 V
±
80 mV 3.00 V
±
100 mV 0.30 V
±
20 mV 1.0 s Unavailable
S-8232NSFT-T2-x 4.15 V
±
25 mV 3.95 V
±
50 mV 2.30 V
±
80 mV 3.00 V
±
100 mV 0.30 V
±
20 mV 1.0 s Unavailable
S-8232NTFT-T2-x 4.225 V
±
25 mV 4 .15 V
±
50 mV 2.00 V
±
80 mV 2.00 V
±
80 mV 0.09 V
±
20 mV 1.0 s Unavailable
S-8232NUFT-T2-x 3.85 V
±
25 mV 3.75 V
±
50 mV 2.23 V
±
80 mV 2.23 V
±
80 mV 0.15 V
±
20 mV 1.0 s Available
S-8232NWFT-T2-x 4.21 V
±
25 mV 4.125 V
±
50 mV 2.00 V
±
80 mV 2.00 V
±
80 mV 0.09 V
±
20 mV 1.0 s Unavailable
S-8232NXFT-T2-x 4.25 V
±
25 mV 4.05 V
±
50 mV 2.80 V
±
80 mV 3.10 V
±
100 mV 0.30 V
±
20 mV 1.0 s Unavailable
S-8232NYFT-T2-x 4.25 V
±
25 mV 4.15 V
±
50 mV 2.90 V
±
80 mV 3.10 V
±
100 mV 0.30 V
±
20 mV 1.0 s Unavailable
S-8232NZFT-T2-x 4.21 V
±
25 mV 3.98 V
±
50 mV 2.30 V
±
80 mV 2.90 V
±
100 mV 0.11 V
±
20 mV 1.0 s Unavailable
S-8232PAFT-T2-x 4.305 V
±
25 mV 4.125 V
±
50 mV 2.00 V
±
80 mV 2.00 V
±
80 mV 0.09 V
±
20 mV 1.0 s Unavailable
S-8232PBFT-T2-y 4.35 V
±
25 mV 4.15 V
±
50 mV 2.30 V
±
80 mV 3.00 V
±
100 mV 0.20 V
±
20 mV 1.0 s Unavailable
S-8232PCFT-T2-x 4.21 V
±
25 mV 4.00 V
±
50 mV 2.40 V
±
80 mV 3.00 V
±
100 mV 0.20 V
±
20 mV 1.0 s Unavailable
S-8232PFFT-T2-U 4.225 V
±
25 mV 4.025 V
±
50 mV
*2
2.70 V
±
80 mV 3.40 V
±
100 mV 0.15 V
±
20 mV 1.0 s Unavailable
*1. No overcharge detection / release hysteresis
*2. The magnification of final overcharge is 1.11; the others are 1.25.
*3. No final overcharging function
*4. Refer to the *2 in the “ Operation”.
Remark 1. Please contact our sales office for the products with detection voltage value other than those
specified above.
2. x: G or U
y: S or U
3. Please select products of environmental code = U for Sn 100%, halogen-free products.
4. The overdischarge detection voltage can b e selected within the range from 1.7 to 3.0 V. When the
overdischarge detection voltage is higher than 2.6 V, the overcharge detection voltage and the
overcharge release voltage are limited as “Table 2”.
Table 2
Overdischarge
detection voltage 1, 2
[VDD]
Overcharge
detection voltage 1, 2
[VCU]
Voltage difference between overcharge detection
voltage and overcharge release voltage
[VCU − VCD]
1.70 V to 2.60 V 3.85 V to 4.60 V 0 V to 0.30 V
1.70 V to 2.80 V 3.85 V to 4.60 V 0 V to 0.20 V
1.70 V to 3.00 V 3.85 V to 4.50 V 0 V to 0.10 V
BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK
S8232 Series Rev.6.1_00
Seiko Instruments Inc.
6
Pin Configuration
Table 3
Pin No. Symbol Description
1 SENS
Detection pin for voltage between VC an d
SENS (Detection pin for overcharge and
overdischarge)
SENS
DO
CO
VM
VCC
VC
ICT
VSS
8-Pin T SSOP
Top view
1
2
3
4
8
7
6
5 2 DO
FET gate connection pin for discharge
control (CMOS output)
Figure 2 3 CO
FET gate connection pin for charge control
(CMOS output)
4 VM
Detection pin for voltage between VSS and
VM (Overcurrent detection pin)
5 VSS Input pin for negative power supply
6 ICT Capacitor connection pin for detection d elay
7 VC Input pin for middle voltage
8 VCC Input pin for positive power supply
BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK
Rev6.1_00 S-8232 Series
Seiko Instruments Inc. 7
Absolute Maximum Ratings
Table 4 (Ta = 25°C unless otherwise spe cified)
Item Symbol Applied Pin Absolute Maximum Rating Unit
Input voltage between VCC and VSS VDS VCC VSS − 0.3 to VSS + 18 V
SENS input pin voltage VSENS SENS VSS − 0.3 to VCC + 0.3 V
ICT input pin voltage VICT ICT VSS − 0.3 to VCC + 0.3 V
VM input pin voltage VVM VM VCC − 18 to VCC + 0.3 V
DO output pin voltage VDO DO VSS − 0.3 to VCC + 0.3 V
CO output pin voltage VCO CO VVM − 0.3 to VCC + 0.3 V
300 (When not mounted on board) mW
Power dissipation PD ⎯ 700*1 mW
Operating ambient temperature Topr ⎯ − 40 to + 85 °C
Storage temperature Tstg ⎯ − 40 to + 125 °C
*1. When mounted on board
[Mounted board]
(1) Board size : 114.3 mm × 76.2 mm × t1.6 mm
(2) Name : JEDEC STANDARD51-7
Caution The absolute maximum ratings are rated values exceeding which the product could suffer
physical damage. These values must therefore not be exceeded under any conditions.
0 50 100 150
700
400
0
Power Dissi
p
ation
(
PD
)
[
mW
]
Ambi en t Tem
p
erature
(
T
a
)
[
°C
]
200
600
500
300
100
800
Figure 3 Power Dissipation of Package (When Mounted on Board)
BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK
S8232 Series Rev.6.1_00
Seiko Instruments Inc.
8
Electrical Characteristics
Table 5 (Ta = 25°C unless otherwise specified)
Item Symbol Condition Min. Typ. Max. Unit
Test
Condition Test
Circuit
DETECTION V OLTAGE
Overcharge detection voltage 1, 2 V
CU1, 2
3.85 V to 4.60 V,
Adjustable
V
CU1, 2
−
0.025 V
CU1, 2
V
CU1, 2
+
0.025
V 1, 2 1
V
CUaux1, 2
V
CU1, 2
×
1.25
V
CU1, 2
×
1.21 V
CU1, 2
×
1.25 V
CU1, 2
×
1.29
V 1, 2 1 Auxiliary overcharge detection voltage 1, 2
*1
V
CUaux1
, V
CUaux2
=
V
CU1
, V
CU2
×
1.25 or
V
CUaux1
, V
CUaux2
=
V
CU1
, V
CU2
×
1.11 V
CUaux1, 2
V
CU1, 2
×
1.11
V
CU1, 2
×
1.07 V
CU1, 2
×
1.11 V
CU1, 2
×
1.15
V 1, 2 1
Overcharge release voltage 1, 2 V
CD1, 2
3.60 V to 4.60 V,
Adjustable
V
CD1, 2
−
0.050 V
CD1, 2
V
CD1, 2
+
0.050
V 1, 2 1
Overdischarge detection voltage 1, 2 V
DD1, 2
1.70 V to 2.60 V,
Adjustable
V
DD1, 2
−
0.080 V
DD1, 2
V
DD1 ,2
+
0.080
V 1, 2 1
Overdischarge release voltage 1, 2 V
DU1, 2
1.70 V to 3.80 V,
Adjustable
V
DU1, 2
−
0.100 V
DU1, 2
V
DU1, 2
+
0.100
V 1, 2 1
Overcurrent detection voltage 1 V
IOV1
0.07 V to 0.30 V,
Adjustable
V
IOV1
−
0.020 V
IOV1
V
IOV1
+
0.020
V 3 1
Overcurrent detection voltage 2 V
IOV2
Load short circuit,
V
CC
reference
−
1.57
−
1.20
−
0.83
V 3 1
Temperature coefficient 1 for detection voltage
*2
T
COE1
Ta
=
−
40°C to
+
85°C
*4
−
0.6 0 0.6
mV/°C
⎯
⎯
Temperature coefficient 2 for detection voltage
*3
T
COE2
Ta
=
−
40°C to
+
85°C
*4
−
0.24
−
0.05 0
mV/°C
⎯
⎯
DELAY TIME (C3
=
0.22
μ
F)
Overcharge detection delay time 1, 2 t
CU1, 2
1.0 s
0.73 1.00 1.35
s 8, 9 5
Overdischarge detection delay time 1, 2 t
DD1, 2
0.1 s
68 100 138
ms 8, 9 5
Overcurrent detection delay time 1 t
IOV1
0.01 s
6.7 10 13.9
ms 10 5
INPUT VOLTAGE
Input voltage between VCC and VSS V
DS
Absolute maximum
rating
−
0.3
⎯
18
V
⎯
⎯
OPERATING VOLT AGE
Operating voltage between VCC and VSS
*5
V
DSOP
Output logic fixed
2.0
⎯
16
V
⎯
⎯
CURRENT CONSUMP TION
Current consumption during normal operation I
OPE
V1
=
V2
=
3.6 V
2.1 7.5 12.7
μ
A 4 2
Current consumption at power down I
PDN
V1
=
V2
=
1.5 V
0 0.0002 0.04
μ
A 4 2
OUTPUT VOLT AGE
DO voltage “H” V
DO(H)
I
OUT
=
10
μ
A
V
CC
−
0.05 V
CC
−
0.003 V
CC
V 6 3
DO voltage “L” V
DO(L)
I
OUT
=
10
μ
A
V
SS
V
SS
+
0.003 V
SS
+
0.05
V 6 3
CO voltage “H” V
CO(H)
I
OUT
=
10
μ
A
V
CC
−
0.15 V
CC
−
0.019 V
CC
V 7 4
CO PIN INTERNAL RESISTANCE
Resistance between VSS and CO R
COL
V
CO
−
V
SS
=
9.4 V
0.29 0.6 1.44
M
Ω
7 4
INTERNAL RESISTANCE
Resistance between VCC and VM R
VCM
V
CC
−
V
VM
=
0.5 V
105 240 575
k
Ω
5 2
Resistance between VSS and VM R
VSM
V
VM
−
V
SS
=
1.1 V
511 597 977
k
Ω
5 2
0 V BATTERY CHARGE FUNCTION
0 V battery charge starting charger voltage V
0CHA
0 V battery charging
function “available”
0.38 0.75 1.12
V 11 6
0 V battery charge inhibition battery voltage 1, 2 V
0INH1, 2
0 V battery charging
function “unavailable”
0.32 0.88 1.44
V 12, 13 6
*1. Auxiliary overcharge detection voltage is equal to the overcharge detection voltage times 1.11 for the
products without overcharge hystere sis, and times 1.25 for other p r oducts.
*2. Temperature coefficient 1 for detection voltage should be applied to overcharge detection voltage,
overcharge release voltage, overdischarge detection voltage, and overdischarge release volt age.
*3. Temperature coefficient 2 for detection voltage s hould be applied to overcurrent detection voltage.
*4. Since products are n ot screened at high and low temperature, the specification for this temperature range is
guaranteed by design, not tested in production.
*5. The DO and CO pin logic are establi sh ed at the operating voltage.
BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK
Rev6.1_00 S-8232 Series
Seiko Instruments Inc. 9
Table 6
(Ta = − 20°C to + 70°C unless otherwi se specified
*1
)
Item Symbol Condition Min. Typ. Max. Unit
Test
Condition Test
Circuit
DETECTION V OLTAGE
Overcharge detection voltage 1, 2 V
CU1, 2
3.85 V to 4.60 V,
Adjustable
V
CU1, 2
−
0.045 V
CU1, 2
V
CU1, 2
+
0.040
V 1, 2 1
V
CUaux1, 2
V
CU1, 2
×
1.25
V
CU1, 2
×
1.19 V
CU1, 2
×
1.25 V
CU1, 2
×
1.31
V 1, 2 1 Auxiliary overcharge detection voltage 1, 2
*2
V
CUaux1
, V
CUaux2
=
V
CU1
, V
CU2
×
1.25 or
V
CUaux1
, V
CUaux2
=
V
CU1
, V
CU2
×
1.11 V
CUaux1, 2
V
CU1, 2
×
1.11
V
CU1, 2
×
1.05 V
CU1, 2
×
1.11 V
CU1, 2
×
1.17
V 1, 2 1
Overcharge release voltage 1, 2 V
CD1, 2
3.60 V to 4.60 V,
Adjustable
V
CD1, 2
−
0.070 V
CD1, 2
V
CD1, 2
+
0.065
V 1, 2 1
Overdischarge detection voltage 1, 2 V
DD1, 2
1.70 V to 2.60 V,
Adjustable
V
DD1, 2
−
0.100 V
DD1, 2
V
DD1 ,2
+
0.095
V 1, 2 1
Overdischarge release voltage 1, 2 V
DU1, 2
1.70 V to 3.80 V,
Adjustable
V
DU1, 2
−
0.120 V
DU1, 2
V
DU1, 2
+
0.115
V 1, 2 1
Overcurrent detection voltage 1 V
IOV1
0.07 V to 0.30 V,
Adjustable
V
IOV1
−
0.029 V
IOV1
V
IOV1
+
0.029
V 3 1
Overcurrent detection voltage 2 V
IOV2
Load short circuit,
V
CC
reference
−
1.66
−
1.20
−
0.74
V 3 1
Temperature coefficient 1 for detection voltage
*3
T
COE1
Ta
=
−
40°C to
+
85°C
*1
−
0.6 0 0.6
mV/°C
⎯
⎯
Temperature coefficient 2 for detection voltage
*4
T
COE2
Ta
=
−
40°C to
+
85°C
*1
−
0.24
−
0.05 0
mV/°C
⎯
⎯
DELAY TIME (C3
=
0.22
μ
F)
Overcharge detection delay time 1, 2 t
CU1, 2
1.0 s
0.60 1.00 1.84
s 8, 9 5
Overdischarge detection delay time 1, 2 t
DD1, 2
0.1 s
67 100 140
ms 8, 9 5
Overcurrent detection delay time 1 t
IOV1
0.01 s
6.5 10 14.5
ms 10 5
INPUT VOLTAGE
Input voltage between VCC and VSS V
DS
Absolute maximum
rating
−
0.3
⎯
18
V
⎯
⎯
OPERATING VOLT AGE
Operating voltage between VCC and VSS
*5
V
DSOP
Output logic fixed
2.0
⎯
16
V
⎯
⎯
CURRENT CONSUMP TION
Current consumption during normal operation I
OPE
V1
=
V2
=
3.6 V
1.9 7.5 13.8
μ
A 4 2
Current consumption at power down I
PDN
V1
=
V2
=
1.5 V
0 0.0002 0.06
μ
A 4 2
OUTPUT VOLT AGE
DO voltage “H” V
DO(H)
I
OUT
=
10
μ
A
V
CC
−
0.14 V
CC
−
0.003 V
CC
V 6 3
DO voltage “L” V
DO(L)
I
OUT
=
10
μ
A
V
SS
V
SS
+
0.003 V
SS
+
0.14
V 6 3
CO voltage “H” V
CO(H)
I
OUT
=
10
μ
A
V
CC
−
0.24 V
CC
−
0.019 V
CC
V 7 4
CO PIN INTERNAL RESISTANCE
Resistance between VSS and CO R
COL
V
CO
−
V
SS
=
9.4 V
0.24 0.6 1.96
M
Ω
7 4
INTERNAL RESISTANCE
Resistance between VCC and VM R
VCM
V
CC
−
V
VM
=
0.5 V
86 240 785
k
Ω
5 2
Resistance between VSS and VM R
VSM
V
VM
−
V
SS
=
1.1 V
418 597 1332
k
Ω
5 2
0 V BATTERY CHARGE FUNCTION
0 V battery charge starting charger voltage V
0CHA
0 V battery charging
function “available”
0.29 0.75 1.21
V 11 6
0 V battery charge inhibition battery voltage 1, 2 V
0INH1, 2
0 V battery charging
function “unavailable”
0.23 0.88 1.53
V 12, 13 6
*1. Since products are not scre ened at high and low temperature, the specification for this temperature range is
guaranteed by design, not tested in production.
*2. Auxiliary overcharge detection voltage is equal to the overcharge detection voltage times 1.11 for the
products without overcharge hystere sis, and times 1.25 for other p r oducts.
*3. Temperature coefficient 1 for detection voltage should be applied to overcharge detection voltage,
overcharge release voltage, overdischarge detection voltage, and overdischarge release volt age.
*4. Temperature coefficient 2 for detection voltage s hould be applied to overcurrent detection voltage.
*5. The DO pin and CO pin logic are e stablished at the operating voltage.
BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK
S8232 Series Rev.6.1_00
Seiko Instruments Inc.
10
Table 7
(Ta = − 40°C to +85°C unless oth erwise specified
*1
)
Item Symbol Condition Min. Typ. Max. Unit
Test
C
onditio
n
Test
Circui
t
DETECTION V OLTAGE
Overcharge detection voltage 1, 2 V
CU1, 2
3.85 V to 4.60 V,
Adjustable
V
CU1, 2
−
0.055 V
CU1, 2
V
CU1, 2
+
0.045
V 1, 2 1
V
CUaux1, 2
V
CU1, 2
×
1.25
V
CU1, 2
×
1.19 V
CU1, 2
×
1.25 V
CU1, 2
×
1.31
V 1, 2 1 Auxiliary overcharge detection voltage 1, 2
*2
V
CUaux1
, V
CUaux2
=
V
CU1
, V
CU2
×
1.25 or
V
CUaux1
, V
CUaux2
=
V
CU1
, V
CU2
×
1.11 V
CUaux1, 2
V
CU1, 2
×
1.11
V
CU1, 2
×
1.05 V
CU1, 2
×
1.11 V
CU1, 2
×
1.17
V 1, 2 1
Overcharge release voltage 1, 2 V
CD1, 2
3.60 V to 4.60 V,
Adjustable
V
CD1, 2
−
0.080 V
CD1, 2
V
CD1, 2
+
0.070
V 1, 2 1
Overdischarge detection voltage 1, 2 V
DD1, 2
1.70 V to 2.60 V,
Adjustable
V
DD1, 2
−
0.110 V
DD1, 2
V
DD1 ,2
+
0.100
V 1, 2 1
Overdischarge release voltage 1, 2 V
DU1, 2
1.70 V to 3.80 V,
Adjustable
V
DU1, 2
−
0.130 V
DU1, 2
V
DU1, 2
+
0.120
V 1, 2 1
Overcurrent detection voltage 1 V
IOV1
0.07 V to 0.30 V,
Adjustable
V
IOV1
−
0.033 V
IOV1
V
IOV1
+
0.033
V 3 1
Overcurrent detection voltage 2 V
IOV2
Load short circuit,
V
CC
reference
−
1.70
−
1.20
−
0.71
V 3 1
Temperature coefficient 1 for detection voltage
*3
T
COE1
Ta
=
−
40°C to
+
85°C
*1
−
0.6 0 0.6
mV/°C
⎯
⎯
Temperature coefficient 2 for detection voltage
*4
T
COE2
T
a
=
−
40°C to
+
85°C
*1
−
0.24
−
0.05 0
mV/°C
⎯
⎯
DELAY TIME (C3
=
0.22
μ
F)
Overcharge detection delay time 1, 2 t
CU1, 2
1.0 s
0.55 1.00 2.06
s 8, 9 5
Overdischarge detection delay time 1, 2 t
DD1, 2
0.1 s
67 100 141
ms 8, 9 5
Overcurrent detection delay time 1 t
IOV1
0.01 s
6.3 10 14.7
ms 10 5
INPUT VOLTAGE
Input voltage between VCC and VSS V
DS
Absolute maximum
rating
−
0.3
⎯
18
V
⎯
⎯
OPERATING VOLT AGE
Operating voltage between VCC and VSS
*5
V
DSOP
Output logic fixed
2.0
⎯
16
V
⎯
⎯
CURRENT CONSUMP TION
Current consumption during normal operation I
OPE
V1
=
V2
=
3.6 V
1.8 7.5 14.2
μ
A 4 2
Current consumption at power down I
PDN
V1
=
V2
=
1.5 V
0 0.0002 0.10
μ
A 4 2
OUTPUT VOLT AGE
DO voltage “H” V
DO(H)
I
OUT
=
10
μ
A
V
CC
−
0.17 V
CC
−
0.003 V
CC
V 6 3
DO voltage “L” V
DO(L)
I
OUT
=
10
μ
A
V
SS
V
SS
+
0.003 V
SS
+
0.17
V 6 3
CO voltage “H” V
CO(H)
I
OUT
=
10
μ
A
V
CC
−
0.27 V
CC
−
0.019 V
CC
V 7 4
CO PIN INTERNAL RESISTANCE
Resistance between VSS and CO R
COL
V
CO
−
V
SS
=
9.4 V
0.22 0.6 2.20
M
Ω
7 4
INTERNAL RESISTANCE
Resistance between VCC and VM R
VCM
V
CC
−
V
VM
=
0.5 V
79 240 878
k
Ω
5 2
Resistance between VSS and VM R
VSM
V
VM
−
V
SS
=
1.1 V
387 597 1491
k
Ω
5 2
0 V BATTERY CHARGE FUNCTION
0 V battery charge starting charger voltage V
0CHA
0 V battery charging
function “available”
0.26 0.75 1.25
V 11 6
0 V battery charge inhibition battery voltage 1, 2 V
0INH1, 2
0 V battery charging
function “unavailable”
0.20 0.88 1.57
V 12, 13 6
*1. Since products are not scre ened at high and low temperature, the specification for this temperature range is
guaranteed by design, not tested in production.
*2. Auxiliary overcharge detection voltage is equal to the overcharge detection voltage times 1.11 for the
products without overcharge hystere sis, and times 1.25 for other p r oducts.
*3. Temperature coefficient 1 for detection voltage should be applied to overcharge detection voltage,
overcharge release voltage, overdischarge detection voltage, and overdischarge release volt age.
*4. Temperature coefficient 2 for detection voltage s hould be applied to overcurrent detection voltage.
*5. The DO pin and CO pin logic are e stablished at the operating voltage.
BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK
Rev6.1_00 S-8232 Series
Seiko Instruments Inc. 11
Test Circuits
(1) Test Condition 1, Test Circuit 1
Set S1 = OFF, V1 = V2 = 3.6 V, and V3 = 0 V under normal status. Increase V1 from 3.6 V gradually.
The V1 voltage when CO = “L” is overcharge detection voltage 1 (VCU1). Decrease V1 gradually. The V1
voltage when CO = “H” is overcharge release voltage 1 (VCD1). Further decrease V1. The V1 voltage
when DO = “L” is overdischarge voltage 1 (VDD1). Increase V1 gradually. The V1 voltage when DO = “H”
is overdischarge release voltage 1 (VDU1). Set S1 = ON, and V1 = V2 = 3.6 V and V3 = 0 V under normal
status. Increase V1 from 3.6 V gradually. The V1 voltage when CO = “L” is auxiliary overcharge detection
voltage 1 (VCUaux1).
(2) Test Condition 2, Test Circuit 1
Set S1 = OFF, V1 = V2 = 3.6 V, and V3 = 0 V under normal status. Increase V2 from 3.6 V gradually.
The V2 voltage when CO = “L” is overcharge detection voltage 2 (VCU2). Decrease V2 gradually. The V2
voltage when CO = “H” is overcharge release voltage 2 (VCD2). Further decrease V2. The V2 voltage
when DO = “L” is overdischarge voltage 2 (VDD2). Increase V2 gradually. The V2 voltage when DO = “H”
is overdischarge release voltage 2 (VDU2). Set S1 = ON, and V1 = V2 = 3.6 V and V3 = 0 V under normal
status. Increase V2 from 3.6 V gradually. The V2 voltage when CO = “L” is auxiliary overcharge
detection voltage 2 (VCUaux2).
(3) Test Condition 3, Test Circuit 1
Set S1 = OFF, V1 = V2 = 3.6 V, and V3 = 0 V under normal status. Increase V3 from 0 V gradually. The
V3 voltage when DO = “L” is overcurrent detection voltage 1 (VIOV1). Set S1 = ON, V1 = V2 = 3.6 V, V3 =
0 under normal status. Increase V3 from 0 V gradually. (The voltage change rate < 1.0 V / ms) V3 − (V1
+ V2) voltage when DO = “L” is overcurrent detection voltage 2 (VIOV2).
(4) Test Condition 4, Test Circuit 2
Set S1 = ON, V1 = V2 = 3.6 V, and V3 = 0 V under normal status and measure current consumption.
Current consumption I1 is the normal status current consumption (IOPE). Set S1 = OFF, V1 = V2 =
1.5 V under overdischarge status and measure current consumption. Current consumption I1 is the
power-down current consu mption (IPDN).
(5) Test Condition 5, Test Circuit 2
Set S1 = ON, V1 = V2 = V3 = 1.5 V, and V3 = 2.5 V under overdischarge status. (V1 + V2 − V3) / I2 is the
internal resistance betwee n VCC an d VM (RVCM).
Set S1 = ON, V1 = V2 = 3.6 V, and V3 = 1.1 V under overcurrent status. V3 / I2 is the internal resistance
between VSS and VM (RVSM).
(6) Test Condition 6, Test Circuit 3
Set S1 = ON, S2 = OFF, V1 = V2 = 3.6 V, and V3 = 0 V under normal status. Increase V4 from 0 V
gradually. The V4 voltage when I1 = 10 μA is DO voltage “H” (VDO(H)).
Set S1 = OFF, S2 = ON, V1 = V2 = 3.6 V, and V3 = 0.5 V under overcurrent status. Increase V5 from 0 V
gradually. The V5 voltage when I2 = 10 μA is the DO voltage “L” (VDO(L)).
BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK
S8232 Series Rev.6.1_00
Seiko Instruments Inc.
12
(7) Test Condition 7, Test Circuit 4
Set S1 = ON, S2 = OFF, V1 = V2 = 3.6 V and V3 = 0 V under normal status. Increase V4 from 0 V
gradually. The V4 voltage when I1 = 10 μA is the CO “H” voltage (VCO(H)).
Set S1 = OFF, S2 = ON, V1 = V2 = 4.7, V3 = 0 V, and V5 = 9.4 V under overcharge status. (V5) / I2 is
the CO pin internal resistance (RCO(L)).
(8) Test Condition 8, Test Circuit 5
Set V1 = V2 = 3.6 V, and V3 = 0 V under normal status. Increase V1 from (VCU1 − 0.2 V) to (VCU1 +
0.2 V) immediately (within 10 μs). The time after V1 becomes (VCU1 + 0.2 V) until CO goes “L” is the
overcharge detection delay time 1 (tCU1).
Set V1 = V2 = 3.6 V, and V3 = 0 V under normal status. Decrease V1 from (VDD1 + 0.2 V) to (VDD1 − 0.2
V) immediately (within 10 μs). The time after V1 becomes (VDD1 − 0.2 V) until DO goes “L” is the
overdischarge detection d elay time 1 (tDD1).
(9) Test Condition 9, Test Circuit 5
Set V1 = V2 = 3.6 V, and V3 = 0 V under normal status. Increase V2 from (VCU2 − 0.2 V) to (VCU2 +
0.2 V) immediately (within 10 μs). The time after V2 becomes (VCU2 + 0.2 V) until CO goes “L” is the
overcharge detection delay time 2 (tCU2).
Set V1 = V2 = 3.6 V, and V3 = 0 V under normal status. Decrease V2 from (VDD2 + 0.2 V) to (VDD2 − 0.2
V) immediately (within 10 μs). The time after V2 becomes (VDD2 − 0.2 V) until DO goes “L” is the
overdischarge detection d elay time 2 (tDD2).
(10) Test Condition 10, Test Circuit 5
Set V1 = V2 = 3.6 V, and V3 = 0 V under normal status. Increase V3 from 0 V to 0.5 V immediately
(within 10 μs). The time after V3 becomes 0.5 V until DO goes “L” is the overcurrent detection delay time
1 (tIOV1).
(11) Test Condition 11, Test Circuit 6
Set V1 = V2 = 0 V, and V3 = 0 V, and increase V3 gradually. The V3 voltage when CO = “L” (VVM + 0.3 V
or higher) is the 0 V charge starting volt age (V0CHA).
(12) Test Condition 12, Test Circuit 6
Set V1 = 0 V, V2 = 3.6 V, and V3 = 12 V, and increase V1 gradually. The V1 voltage when CO = “H” (VVM
+ 0.3 V or higher) is the 0 V charge inhibiting voltage 1 (V0INH1).
(13) Test Condition 13, Test Circuit 6
Set V1 = 3.6 V, V2 = 0 V, and V3 = 12 V, and increase V2 gradually. The V2 voltage when CO = “H” (VVM
+ 0.3 V or higher) is the 0 V charge inhibiting voltage 2 (V0INH2).
BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK
Rev6.1_00 S-8232 Series
Seiko Instruments Inc. 13
VSS DO CO
VM
ICT
VCC
SENS
V1
S1
VC
V2
V3
S-8232 Series
VSS DO CO
VM
ICT
VCC
SENS
V2
V3
S1
I1
I2
VC
V1 S-8232 Series
Test Circuit 1 Test Circuit 2
VSS DO CO
VM
ICT
VC
SENS
V1
V3
V4 S1
V5 S2
I1
I2
VCC
V2
S-8232 Series
VSS DO CO
VM
ICT
VCC
SENS
V1
V3
I1
V4 S1
V5 S2 I2
VC
V2
S-8232 Series
Test Circuit 3 Test Circuit 4
VSS DO CO
VM
ICT
VCC
SENS
V1
C3
C3 = 0.22 μF
V3
V2
VC
S-8232 Series
VSS DO CO
VM
ICT
VCC
SENS
V1
4.7 MΩ
V3
VC
V2
S-8232 Series
Test Circuit 5 Test Circuit 6
Figure 4
BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK
S8232 Series Rev.6.1_00
Seiko Instruments Inc.
14
Operation
Remark Refer to “ Battery Protection IC Conne ction Example”.
Normal Status *1, *2
This IC monitors the voltages of the two serially connected batteries and the discharge current to control charging and
discharging. When the voltages of two batteries are more than the overdischarge detecti on voltage (V
DD1, 2
), le ss than
the overcharge detection voltage (V
CU1, 2
), and the current flowing through the batteries b ecomes equal or lower than a
specified value (the VM pin voltage is equal or lower than overcurrent detection voltage 1), the charging and
discharging FETs are turned on. In this status, charging and discharging can be carried out freely. This is normal
status. In this status, the VM and VSS pins are shorted by the RVSM resistor.
Overcurrent Status
When the discharging current becomes equal to or higher than a specified value (the VM pin voltage is equal to or
higher than the overcurrent detection voltage1) during discharging under the normal status and it continues for the
overcurrent detection delay time (t
IOV1
) or longer, the discharging FET is turned off to stop discharging. This is
overcurrent status. The VM and VSS pins are shorted by the RVSM resistor in this status. The charging FET is also
turned off. While the discharging FET is off and a load is connected, the VM pin voltage is equal to the V
CC
potential.
The overcurrent status returns to the normal status when impedance between the EB
−
and EB
+
pins (refer to
Figure
8
) is 200 M
Ω
or higher, by action such as releasing the load. When the load is released, the VM pin, which is shorted
to the VSS pin by the RVSM resistor, goes back to the V
SS
potential. The IC detects that the VM pin potential returns
to overcurrent detection voltage 1 (V
IOV1
) or lower and returns to the normal status.
Overcharge Status
Following two cases are detected as overch arge status :
(1) If any of the battery voltages becomes higher than the overcharge detection voltage (V
CU1, 2
) during charging
under the normal status and it continu es for the overcharge detection delay time (t
CU1, 2
) or longer, the charging
FET turns off to stop charging. This is overcharge status. In this status, the VM and VSS pins are shorted by
the RVSM resistor.
(2) Although the status is shorter than the overcharge detection delay time (t
CU1, 2
), if any of the battery voltages
becomes higher than the auxiliary overcharge detection voltage (V
CUaux1, 2
), the charging FET turns off to stop
charging. This is also overcharge status. In this status, the VM and VSS pins are shorted by the RVSM
resistor.
The auxiliary overcharge detection voltages ( V
CUaux1, 2
) are correlated with the overchar ge detection voltages (V
CU1, 2
)
and are defined by following equati ons :
V
CUaux1, 2
[V]
=
1.25
×
V
CU1, 2
[V]
or V
CUaux1, 2
[V]
=
1.11
×
V
CU1, 2
[V]
The overcharge status is released in two cases :
(1) The battery voltage which exceeded the overcharge detection voltage (V
CU1, 2
) falls below the overcharge
release voltage (V
CD1, 2
), the charging FET turns on and the IC returns to the normal status.
(2) If the battery voltage which exceeded the overcharge detection voltage (V
CU1, 2
) is equal or higher than the
overcharge release voltage (V
CD1, 2
), however, discharging starts with removing the char ger and connecting the
load, the charging FET turns on and the IC returns to the normal status.
The mechanism to release is as follows: the discharge current flows via an internal parasitic diode of the charging
FET, immediately after connecting the load and discharging starts. Therefore the VM pin’s voltage momentarily
increases about 0.6 V (voltage as much as V
F
voltage of the diode has) plus the VSS pin’s voltage. The IC detects this
voltage by using overcurrent detection voltage 1 (V
IOV1
) so that the IC releases the overcharge status and returns to
the normal status.
Overdischarge Status
If any of the battery voltages falls below the overdischarge detection voltage (V
DD1, 2
) during discharging under the
normal status and it continues for the overdischarge detection delay time (t
DD1, 2
) or longer, the discharging FET turns
off and discharging stops. This is overdischarge status. When the discharging FET turns off, the VM pin voltage
becomes equal to the V
CC
voltage and the IC’s current consumption falls below the power-down current consumptio n
(I
PDN
). This is power-down status. The VM and VCC pins are shorted by the RVCM resistor in the overdischarg e and
power-down statuses.
The power-down status is released when the charger is connected and the voltage between VM and VCC is
overcurrent detection voltage 2 or higher. In this status, When all the battery voltages becomes equal to or higher
than the overdischarge release voltage (V
DU1, 2
) in this status, The IC returns to the normal status from the
overdischarge status.
BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK
Rev6.1_00 S-8232 Series
Seiko Instruments Inc. 15
Delay Circuit
The overcharge detection delay time (t
CU1, 2
), the overdischarge detection delay time (t
DD1, 2
), and the overcurrent
detection delay time 1 (t
IOV1
) change with an external capacitor (C3). Since one capac itor determine eac h delay time,
delay times are correlated as seen in the following ratio :
Overcharge delay time : Overdischarge dela y time : Overcurrent delay time
=
100 : 10 : 1
The delay times are calculated by the following equations : (Ta
=
−
40°C to
+
85°C)
Min., Typ., Max.
Overcharge detection delay time t
CU
[s]
=
Delay factor ( 2.500, 4.545, 9.364 )
×
C3 [
μ
F]
Overdischarge detection delay time t
DD
[s]
=
Delay factor ( 0.3045, 0.4545, 0.6409 )
×
C3 [
μ
F]
Overcurrent detection delay time t
IOV1
[s]
=
Delay factor ( 0.02864, 0.04545, 0.06682 )
×
C3 [
μ
F]
Remark
The overcurrent detection delay time 2 is not set Overcurrent detection voltage 2 (V
IOV2
).
0 V Battery Charging Function *3
This function is used to recharge both of two serially-connected batteries after t hey self-discharge to 0 V. When the 0
V charging start voltage (V
0CHA
) or higher is applied to between VM and VC C by connecting the charger, t he charging
FET gate is fixed to V
CC
potential.
When the voltage between the gate an d the source of the chargin g FET becomes equal to or high er than the turn-on
voltage by the charger voltage, the charging FET turns on to start charging. At this time, the discharging FET turns
off and the charging current flows through the internal parasitic diode in the discharging FET. If all the battery
voltages become equal to or higher than the overdischarge release voltage (V
DU1, 2
), the IC returns to the normal
status.
0 V Battery Charge Inhibiting Function *3
This function is used for inhibiting chargi ng after either of the connected batteries goes 0 V due to its self-discharge.
When the voltage of either of the conn ected batteries goes below the 0 V charge inhibit voltage 1 and 2 (V
0INH1, 2
), the
charging FET gate is fixed to "EB
−
" to inhibit charging. Charging is possibl e only when the voltage of both connected
batteries goes 0 V charge inhibit voltage 1 and 2 (V
0INH1, 2
) or more.
Note that charging may be possible when the total voltag e of both connected batteries is less than the minimum value
(V
DSOPmin
) of the operating voltage between VCC and VSS even if the voltage of either of the connected batteries is
the 0 V charge inhibit voltage 1 and 2 (V
0INH1, 2
) or less. Charging is inhibited when the total voltage of both
connected batteries reaches the minimum value (V
DSOPmin
) of the operating voltage between VCC and VSS.
When using this optional function, a resistor of 4.7 M
Ω
is needed between the gate and the source of the charging
control FET (refer to
Figure 8
).
*1.
When connecting batteries for the first time, the IC may fail to enter the nor mal status (is not in the status to charge).
If so, once set the VM pin to VSS voltage (short between VM and VSS or connect a charger) to return to the normal
status.
*2.
In this product with “overchar ge detection/release hysteresi s”, “no final overcharge function”, and “0 V battery charg e
inhibiting function” (indicated in
*4
, in “
2. Product Name List
” in “
Product Name Structure
”), the following action,
other products do not have, is seen. But it does not affect on actual use.
In the normal status, the battery voltage is the overcharge release voltage (V
CD1, 2
) or higher, and the overcharge
detection voltage (V
CU1, 2
) or lower but after that, the IC goes in the overcurrent status by connecting an overload.
Usually the IC returns to the normal status by detaching the overload, but the charging FET may turn off and the IC
may go in the overcharge status. After that, connect the load again to start charging. The FET turns on and the IC
returns to the normal status (Refer to “
Overcharge status
”).
*3.
Some lithium ion batteries are not recomme nded to be recharged after having bee n completely discharged. Please
contact battery manufacturer when you select a 0 V battery charging function.
BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK
S8232 Series Rev.6.1_00
Seiko Instruments Inc.
16
Timing Charts
1. Overcharge Detection
VCUaux
VCU
VCD
VDU
VDD
VSS
Battery
voltage
DO pin
voltage
VCC
VSS
VCC
VSS
EB−
VCC
VIOV2
VIOV1
VSS
EB−
CO pin
voltage
Charger connection
Delay
Load connection
Status
*1
<2> <1> <1> <1> <1> <2>
V1 batter
y
V2 batter
y
<1> <2> <2>
Delay time
=
0
V1 over volta
g
e detect V2 over volta
g
e detect V1 auxiliary over
voltag e de t ec t V2 auxiliary over
voltage detect
VM pin
voltage
Delay Delay time
=
0
*1. <1> Normal status
<2> Over charge status
<3> Over discharge status
<4> Over current status
Remark The charger is assumed to charge with a constant current.
Figure 5
BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK
Rev6.1_00 S-8232 Series
Seiko Instruments Inc. 17
2. Overdischarge Detection
VCU
VCD
VDU
VDD
VSS
VCC
VSS
Vcc
Vss
EB−
VCC
VIOV2
VIOV1
VSS
EB−
Charger connection
Load connection
Status
*
1
<3> <1> <1> <3> <2> & <3>
V1 batter
y
V2 batter
y
Battery
voltage
DO pin
voltage
CO pin
voltage
VM pin
voltage
Delay Delay No Delay
<3>
*1. <1> Normal status
<2> Over charge status
<3> Over discharge status
<4> Over current status
Remark The charger is assumed to charge with a constant current.
Figure 6
BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK
S8232 Series Rev.6.1_00
Seiko Instruments Inc.
18
3. Overcurrent Detection
VCU
VCD
VDU
VDD
VCC
VSS
VCC
VSS
EB−
delay = tIOV1 delay = tIOV2
<4> <1> <4>
V1 =V2 batter
y
VCC
VIOV1
VSS
EB−
<1> <1>
VIOV2
< tIOV1
Battery
voltage
DO pin
voltage
CO pin
voltage
VM pin
voltage
Charger connection
Load connection
Status
*1
*1. <1> Normal status
<2> Over charge status
<3> Over discharge status
<4> Over current status
Remark The charger is assumed to charge with a constant current.
Figure 7
BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK
Rev6.1_00 S-8232 Series
Seiko Instruments Inc. 19
Battery Protection IC Connection Example
EB+
EB−
S-8232 Series
R4
1 kΩ
VSS DO
SENS
ICT
R3
1 kΩ
C2
C3
CO VM
Delay time setting
FET1 FET2
R2
1 kΩ VC
R1
1 kΩ VCC
C1 0.22
μ
F
0.22 μF
0.22 μF
R5
4.7 MΩ
Battery 1
Battery 2
Figure 8
Table 8 Constants for External Comp onents
Symbol Parts Purpose Typ. Min. Max. Remark
FET1 Nch MOS FET Discharge control ⎯ ⎯ ⎯ ⎯
FET2 Nch MOS FET Charge control ⎯ ⎯ ⎯ ⎯
R1 Chip resistor ESD protection 1 kΩ 300 Ω 1 kΩ ⎯
C1 Chip capacitor For power fluctuation 0.22 μF 0 μF 1 μF ⎯
R2 Chip resistor ESD protection 1 kΩ 300 Ω 1 kΩ ⎯
C2 Chip capacitor For power fluctuation 0.22 μF 0 μF 1 μF ⎯
R4 Chip resistor ESD protection 1 kΩ = R1 min. = R1 max. Same value as R1 and R2. *1
C3 Chip capacitor Delay time setting 0.22 μF 0 μF 1 μF Attention should be paid to leak
current of C3. *2
R3 Chip resistor
Protection for
charger reverse
connection 1 kΩ 300 Ω 5 kΩ Discharge can’t be stopped at less
than 300 Ω when a charger is
reverse-connected. *3
R5 Chip resistor
0 V battery
charging inhibit ion (4.7 MΩ) (1 MΩ) (10 MΩ)
R5 should be added when the
product has 0 V battery charge
inhibition. Lower resistance
increases current consumption. *4
*1. R4
=
R1 is required. Overcharge detection voltage increases by R4. For example 10 k
Ω
(R4) increases overcharge
detection voltage by 20 mV.
*2. The overcharge detection delay time (tCU), the overdischarge detection delay time (tCD), and the over current detection
delay time (tIOV) change with the external capacitor C3.
*3. When the resistor R3 is set less than 300
Ω
and a charger is reverse-connected, current which exceeds the power
dissipation of the package will flow and the IC may break. But excessive R3 causes increase of overcurrent detection
voltage 1 (VIOV1). VIOV1 changes to VIOV1 = (R3 + RVSM) / RVSM × VIOV1. For example, 50 k
Ω
resistor (R3) increases
overcurrent detection voltag e 1 (VIOV1) from 0.100 V to 0.113 V.
*4. A 4.7 M
Ω
resistor is needed for R5 to inhibit 0 V battery charging. Current consumption increases when the R5
resistance is below 4.7 MΩ. R5 should be connected when the product has 0 V battery charging inhibition.
Caution 1. The above constants may be changed without notice.
2. It has not been confirmed whether the operation is normal or not in circuits other than the above example
of connection. In addition, the example of connection shown above and the constant do not guarantee
proper operation. Perform through evaluation using the actual application to set the constant.
BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK
S8232 Series Rev.6.1_00
Seiko Instruments Inc.
20
Precautions
• After the overcurrent detection delay, if either one of battery voltages equals the overdischarge detection
voltage (VDD1,2) or lower, the overdischarge detection delay time becomes shorter than 10ms (min.). It
occurs because capacitor C3 sets all of delay times (refer to the Figure 9) .
VDD
0 V
VCC
VSS
VCC
VIOV2
VIOV1
VSS
EB−
Battery
v
oltage
DO pin
v
olta
g
e
V
M pin
v
olta
g
e
Load connect
The over current dela
y
The over discharge dela
y
Th
e
d
e
l
ay t
i
me
b
ecomes s
h
orter t
h
an typ
i
ca
l
Th
e
b
attery vo
l
tage
i
s equa
l
to
or less the overdischarge voltage (V
DD
)
after stopping the overcurrent.
Figure 9
[Cause]
When overcurrent detection is released until tIOV1, the capacitor C3 is charged by S-8232 Series. If all
battery voltage is lower than VDD1, 2 at that time, charging goes on. So delay time is shorter than
typical.
[Conclusion]
This phenomenon occurs when all battery voltage is nearly equal to the overdischarge voltage (VDD1, 2 )
after overcurrent detected. It means that the battery capacity is small and those must be charged in
the future. Even if the state changes to overdischarge status, the battery package capacity is same as
typical.
• When one of the battery voltages is overdischarge detection voltage (VDD1, 2) or lower and the other one
becomes higher than the overcharge detection voltage (VCU1, 2), the IC detects the overcharge without the
overcharge detection delay time (tCU) (refer to the Figure 10) .
VCU
VCD
VDU
VDD
CO pin
v
oltage
VCC
VSS
EB−
VCU
VCD
VDU
VDD
Battery
v
oltage
V
1
Battery
v
oltage
V
2
Overcharge d etect Overdischar
g
e state
Delay time = 0
Charger connected
Figure 10
[Cause]
It is same as the overdischarge detection under the overcurrent status. It occurs because capacitor
C3 sets all of delay times.
[Conclusion]
This phenomenon occurs when one battery voltage is lower than overdischarge voltage (VDD1, 2) and
batteries are charged by charger. Since voltage difference between two batteries is large in this
situation, the S-8232 Series immediately stops the charging of the other battery to reduce voltage
difference. This action improves the safety of a battery pack and dose not do any harm to the pack.
BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK
Rev6.1_00 S-8232 Series
Seiko Instruments Inc. 21
• After the overcurrent detection, the load was connected for a long time, even if one of the battery voltage
became lower than overdischarge detection voltage (VDD1, 2), the IC can’t detects the overdischarge as
long as the load is connected. Therefore the IC’s current consumption at the one of the battery voltage is
lower than the overdischarge detection voltage is same as normal status current consumption (IOPE) (refer
to the Figure 11).
VDD
0 V
VCC
VSS
VCC
VIOV2
VIOV1
VSS
EB−
IOPE
IPDN
0 A
Battery
voltage
Current
consum ption
DO pin
voltage
VM pin
voltage
Load connect The over current delay
Long haul load connected
The battery voltage is less than the overdischarge
detection voltage, by self current consumption
A s long a s t h e load is c onne c ted, th e IC’s cur rent is
same as norm al current consum ption (IOPE)
Figure 11
[Cause]
The reason is as follows. If the overcurrent detection and overdischarge detection occur at same time,
the overcurrent detection takes precedence the overdischarge detection. As long as the IC detects
overcurrent, the IC can’t detect overdischarge.
[Conclusion]
If the load is taken off at least one time, the overcurrent is released and the overdischarge detection
works.
Unless keeping the IC with load for a long time, the reduction of battery voltage will be neglected,
because of the IC’s current consumption (typ. 7.5 μA) is small.
• Do not apply an electrostatic discharge to this IC that exceeds the performance ratings of the built-in
electrostatic protection circuit.
• SII claims no responsibility for any and all disputes arising out of or in connection with any infringement
of the products including this IC upon patents owned by a third party.
BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK
S8232 Series Rev.6.1_00
Seiko Instruments Inc.
22
Characteristics (Typical Data)
1. Detection Voltage Temperature Charac teristics
Overcharge detection voltage1 vs. temperature Overcharge detection voltage2 vs. temperature
4.2
4.3
4.4
-40 -20 0 20 40 60 80 100
VCU1 = 4.30 V
Ta [°C]
VCU1 [V]
4.2
4.3
4.4
-40 -20 020 40 60 80 100
VCU2 = 4.30 V
Ta [°C]
VCU2 [V]
Overcharge release voltage1 vs. temperature Overcharge release voltage2 vs. temperature
3.9
4
4.1
-40 -20 0 20 40 60 80 100
VCD1 = 4.00 V
VCD1 [V]
3.9
4
4.1
-40 -20 0 20 40 60 80 100
Ta [°C]
3.9
4
4.1
-40 -20 020 40 60 80 100
VCD2 = 4.00 V
Ta [°C]
VCD2 [V]
Auxiliary overcharge detection voltage1 vs. temperature Auxiliary overcharge detection voltage2 vs. temperature
5.25
5.35
5.45 VCUaux1 = 5.375 V
-40 -20 0 20 40 60 80 100
Ta [°C]
VCUaux1 [V]
5.25
5.35
5.45 VCUaux2 = 5.375 V
-40 -20 020 40 60 80 100
Ta [°C]
VCUaux2 [V]
BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK
Rev6.1_00 S-8232 Series
Seiko Instruments Inc. 23
Overdischarge detection voltage1 vs. temper ature Overdischarge detection voltage2 vs. temper ature
1.9
2
2.1
-40 -20 0 20 40 60 80 100
VDD1 = 2.00 V
Ta [°C]
VDD1 [V]
1.9
2
2.1
-40 -20 020 40 60 80 100
VDD2 = 2.00 V
Ta [°C]
VDD2 [V]
Overdischarge release voltage1 vs. temperature Overdischarge release voltage1 vs. temperature
2.5
2.6
2.7
-40 -20 0 20 40 60 80 100
VDU1 = 2.60 V
Ta [°C]
VDU1 [V]
2.5
2.6
2.7
-40 -20 020 40 60 80 100
VDU2 = 2.60 V
Ta [°C]
VDU2 [V]
Overcurrent1 detection voltage vs. temperature Overcurrent1 detection voltage vs. temperature
0.08
0.12
-40 -20 0 20 40 60 80 100
VIOV1 = 0.1 V
Ta [°C]
VIOV1 [V]
0.10
-1.30
-1.25
-1.20
-1.15
-1.10
-40 -20 020 40 60 80 100
VIOV2 [V]
VIOV2 = 1.20 V (VCC reference)
Ta [°C]
BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK
S8232 Series Rev.6.1_00
Seiko Instruments Inc.
24
2. Current Consumption Temperature Characte ristics
Current consumption vs. temperature in normal mode Current consumption vs. temperature in power-down mode
0
5
10
15
-40 -20 0 20 40 60 80 100
V
CC
= 7.2 V
Ta [°C]
IOPE [μA]
0
50
100
-40 -20 020 40 60 80 100
VCC = 3.0 V
Ta [°C]
IPDN [nA]
3. Delay Time Temperature Characteristics
Overcharge detection1 time vs. temperature Overcharge detection1 time vs. temperature
0.5
1
1.5
-40 -20 0 20 40 60 80 100
C3 = 0.22
μ
F
Ta [°C]
tCU [s]
50
100
150
-40 -20 020 40 60 80 100
C3 = 0.22
μ
F
Ta [°C]
TDD [ms]
Overcurrent1 detection time vs. temperature
7
8
9
10
11
12
-40 -20 0 20 40 60 80 100
C3 = 0.22
μ
F
Ta [°C]
tIOV1 [ms]
Caution Please design all applications of the S-8232 Series with safety in mind.
No.
TITLE
SCALE
UNIT
Seiko Instruments Inc.
TSSOP8-E-PKG Dimensions
No. FT008-A-P-SD-1.1
FT008-A-P-SD-1.1
0.17±0.05
3.00 +0.3
-0.2
0.65
0.2±0.1
14
5
8
mm
No.
TITLE
SCALE
UNIT
Seiko Instruments Inc.
ø1.55±0.05
2.0±0.05
8.0±0.1 ø1.55 +0.1
-0.05
(4.4)
0.3±0.05
1
45
8
4.0±0.1
Feed direction
TSSOP8-E-Carrier Tape
No. FT008-E-C-SD-1.0
FT008-E-C-SD-1.0
+0.4
-0.2
6.6
mm
No.
TITLE
SCALE
UNIT
Seiko Instruments Inc.
Enlarged drawing in the central part
No. FT008-E-R-SD-1.0
2±0.5
ø13±0.5
ø21±0.8
13.4±1.0
17.5±1.0
3,000
QTY.
TSSOP8-E-Reel
FT008-E-R-SD-1.0
mm
www.sii-ic.com
• The information described herein is subject to change without notice.
• Seiko Instruments Inc. is not responsible for any problems caused by circuits or diagrams described herein
whose related industrial properties, patents, or other rights belong to third parties. The application circuit
examples explain typical applications of the products, and do not guarantee the success of any specific
mass-production design.
• When the products described herein are regulated products subject to the Wassenaar Arrangement or other
agreements, they may not be exported without authorization from the approp riate governmental authority.
• Use of the information described herein for other purposes and/or reproduction or copying without the
express permissi on of Seiko Instruments Inc. is strictly prohibited.
• The products described herein cannot be used as part of any device or equipment affecting the human
body, such as exercise equipment, medical equipment, security systems, gas equipment, or any apparatus
installed in airplanes and other vehicle s, without prior written permission of Seiko Instrum ents Inc.
• The products described herein are n ot de signed to be radiation-proof.
• Although Seiko Instruments Inc. exerts the greatest possible effort to ensure high quality and reliability, the
failure or malfunction of semiconductor products may occur. The user of these products should therefore
give thorough consideration to safety design, including redundancy, fire-prevention measures, and
malfunction prevention, to prevent any accidents, fires, or comm unity damage that may ensue.
