NT1GC72B89A0NL / NT2GC72B8PA0NL NT4GC72B4NA1NL / NT4GC72B8NA1NL / NT8GTC72B4NA1NL 1GB: 128M x 72 / 2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72 PC3-8500 / PC3-10600 Registered DDR3 SDRAM DIMM Based on DDR3-1066/1333 128Mx8 (1GB/2GB/4GB) / 256Mx4 (4GB) / 512Mx4 (DDP) (8GB) SDRAM A-Die Features *Performance: Speed Sort DIMM CAS Latency fck - Clock Frequency PC3-8500 PC3-10600 -BE -CG 7 9 Unit 533 667 tck - Clock Cycle 1.875 1.5 MHz ns fDQ - DQ Burst Frequency 1066 1333 Mbps * 240-Pin Registered Dual In-Line Memory Module (RDIMM) * 1GB/2GB/4GB: 128Mx72/256Mx72/512Mx72 DDR3 Registered DIMM based on 128Mx8 DDR3 SDRAM A-Die devices. * 4GB: 512Mx72 DDR3 Registered DIMM based on 256Mx4 DDR3 SDRAM A-Die devices. * 8GB: 1Gx72 DDR3 Registered DIMM based on 512Mx4 (DDP) DDR3 SDRAM A-Die devices. * Intended for 533MHz/667MHz applications * Inputs and outputs are SSTL-15 compatible * VDD = VDDQ = 1.5V 0.075V * SDRAMs have 8 internal banks for concurrent operation * Differential clock inputs * Data is read or written on both clock edges * DRAM DLL aligns DQ and DQS transitions with clock transitions. * Address and control signals are fully synchronous to positive clock edge * Nominal and Dynamtic On-Die Termination support * Programmable Operation: - DIMM Latency: 6,7,8,9 - Burst Type: Sequential or Interleave - Burst Length: BC4, BL8 - Operation: Burst Read and Write * Two different termination values (Rtt_Nom & Rtt_WR) * 14/10/1 (row/column/rank) Addressing for 1GB * 14/10/2 (row/column/rank) Addressing for 2GB * 14/10/4 (row/column/rank) Addressing for 4GB (128Mx8 Device) * 14/11/2 (row/column/rank) Addressing for 4GB (256Mx4 Device) * 14/11/4 (row/column/rank) Addressing for 8GB * Extended operating temperature rage * Auto Self-Refresh option * Serial Presence Detect * Gold contacts * SDRAMs are in 78-ball BGA Package * RoHS compliance * Halogen free product Description NT1GC72B89A0NL, NT2GC72B8PA0NL, NT4GC72B8NA1NL, NT4GC72B4NA1NL and NT8GTC72B4NA1NL are 240-Pin Double Data Rate 3 (DDR3) Synchronous DRAM Registered Dual In-Line Memory Module, organized as one rank of 128Mx72 (1GB), two ranks of 256Mx72 (2GB), two or four ranks of 512Mx72 (4GB) and four ranks of 1Gx72 (8GB) high-speed memory array. Modules use nine 128Mx8 (1GB) 78-ball BGA packaged devices, eighteen 128Mx8 (2GB) 78-ball BGA packaged devices, thirty-six 256Mx4 (4GB) 78-ball BGA packaged devices and thirty-six 512Mx4 (DDP) (8GB) 78-ball BGA packaged devices. These DIMMs are manufactured using raw cards developed for broad industry use as reference designs. The use of these common design files minimizes electrical variation between suppliers. All NANYA DDR3 SDRAM DIMMs provide a high-performance, flexible 8-byte interface in a 5.25" long space-saving footprint. The DIMM is intended for use in applications operating of 533MHz/667MHz clock speeds and achieves high-speed data transfer rates of 1066Mbps/1333Mbps. Prior to any access operation, the device latency and burst/length/operation type must be programmed into the DIMM by address inputs A0-A13 and I/O inputs BA0~BA2 using the mode register set cycle. The DIMM uses serial presence-detect implemented via a serial EEPROM using a standard IIC protocol. The first 128 bytes of SPD data are programmed and locked during module assembly. The remaining 128 bytes are available for use by the customer. REV 1.1 06/2009 1 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GC72B89A0NL / NT2GC72B8PA0NL NT4GC72B4NA1NL / NT4GC72B8NA1NL / NT8GTC72B4NA1NL 1GB: 128M x 72 / 2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72 PC3-8500 / PC3-10600 Registered DDR3 SDRAM DIMM Ordering Information Part Number Speed Organization Power NT1GC72B89A0NL-BE DDR3-1066 PC3-8500 NT1GC72B89A0NL-CG DDR3-1333 PC3-10600 667MHz (1.5ns @ CL = 9) NT2GC72B8PA0NL-BE DDR3-1066 PC3-8500 NT2GC72B8PA0NL-CG DDR3-1333 PC3-10600 667MHz (1.5ns @ CL = 9) NT4GC72B4NA1NL-BE DDR3-1066 PC3-8500 NT4GC72B4NA1NL-CG DDR3-1333 PC3-10600 667MHz (1.5ns @ CL = 9) NT4GC72B8NA1NL-BE DDR3-1066 PC3-8500 NT4GC72B8NA1NL-CG DDR3-1333 PC3-10600 667MHz (1.5ns @ CL = 9) NT8GTC72B4NA1NL-BE DDR3-1066 PC3-8500 NT8GTC72B4NA1NL-CG DDR3-1333 PC3-10600 667MHz (1.5ns @ CL = 9) Leads Note 533MHz (1.875ns @ CL = 7) 128Mx72 533MHz (1.875ns @ CL = 7) 256Mx72 533MHz (1.875ns @ CL = 7) 1.5V Gold 512Mx72 533MHz (1.875ns @ CL = 7) 533MHz (1.875ns @ CL = 7) 1Gx72 Pin Description Pin Name Description CK0, CK1 Clock Inputs, positive line , Clock Inputs, negative line CKE0, CKE1 Pin Name Description ODT0, ODT1 DQ0-DQ63 Clock Enable Active termination control lines Data input/output DQS0-DQS17 Data strobes - Data strobes complement Row Address Strobe Column Address Strobe TDQS9-TDQS17 Termination data strobes Write Enable - Termination data strobes - Chip Selects A0-A9, A11, A13 Address Inputs DM0-DM8 Data Masks CB0-CB7 ECC Check Bits A10/AP Address Input/Auto-Precharge Temperature event pin A12/ Address Input/Burst Chop Reset pin BA0-BA2 SDRAM Bank Address Inputs VREFDQ , VREFCA Serial Presence Detect Clock Input SDA Serial Presence Detect Data input/output Par_In Parity bit for the Address and Control bus Vtt Termination voltage Parity error found on the Address and Control bus VSS Ground No Connect VDD Core and I/O power NC REV 1.1 06/2009 VDDSPD Input/Output Reference SCL SPD and Temp sensor power SA0, SA1, SA2 Serial Presence Detect Address Inputs 2 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GC72B89A0NL / NT2GC72B8PA0NL NT4GC72B4NA1NL / NT4GC72B8NA1NL / NT8GTC72B4NA1NL 1GB: 128M x 72 / 2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72 PC3-8500 / PC3-10600 Registered DDR3 SDRAM DIMM DDR3 SDRAM Pin Assignment Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back 1 VREFDQ 121 VSS 31 DQ25 151 VSS 61 A2 181 A1 91 DQ41 211 VSS 2 VSS 122 DQ4 32 VSS 152 DM3/DQS12 /TDQS12 62 VDD 182 VDD 92 VSS 212 DM5/DQS14 /TDQS14 3 DQ0 123 DQ5 33 153 NC/ / 63 NC 183 VDD 93 213 NC/ / 4 DQ1 124 VSS 34 DQS3 154 VSS 64 NC 184 CK0 94 DQS5 214 VSS 5 VSS 125 DM0/DQS9/ TDQS9 35 VSS 155 DQ30 65 VDD 185 95 VSS 215 DQ46 6 126 NC/ / 36 DQ26 156 DQ31 66 VDD 186 VDD 96 DQ42 216 DQ47 7 DQS0 127 VSS 37 DQ27 157 VSS 67 VREFCA 187 97 DQ43 217 VSS 8 VSS 128 DQ6 38 VSS 158 CB4 68 Par_In/NC 188 A0 98 VSS 218 DQ52 9 DQ2 129 DQ7 39 CB0 159 CB5 69 VDD 189 VDD 99 DQ48 219 DQ53 10 DQ3 130 VSS 40 CB1 160 VSS 70 A10/AP 190 BA1 100 DQ49 220 VSS 11 VSS 131 DQ12 41 VSS 161 DM8/DQS17 /TDQS17 71 BA0 191 VDD 101 VSS 221 DM6/DQS15 /TDQS15 12 DQ8 132 DQ13 42 162 NC/ / 72 VDD 192 102 222 NC/ / 13 DQ9 133 VSS 43 DQS8 163 VSS 73 193 103 DQS6 223 VSS 14 VSS 134 DM1/DQS10 /TDQS10 44 VSS 164 CB6 74 194 VDD 104 VSS 224 DQ54 45 CB2 165 CB7 75 VDD 195 ODT0 105 DQ50 225 DQ55 /NC 196 A13 106 DQ51 226 VSS ODT1/NC 197 VDD 107 VSS 227 DQ60 DQ61 15 135 NC/ / 16 DQS1 136 VSS 46 CB3 166 VSS 76 17 VSS 137 DQ14 47 VSS 167 NC 77 18 DQ10 138 DQ15 48 VTT/NC 168 78 VDD 198 /NC 108 DQ56 228 19 DQ11 139 VSS 49 VTT/NC 169 CKE1/NC 79 /NC 199 VSS 109 DQ57 229 VSS 20 VSS 140 DQ20 50 CKE0 170 VDD 80 VSS 200 DQ36 110 VSS 230 DM7/DQS16 /TDQS16 21 DQ16 141 DQ21 51 VDD 171 NC 81 DQ32 201 DQ37 111 231 NC/ / 22 DQ17 142 VSS 52 BA2 172 NC 82 DQ33 202 VSS 112 DQS7 232 VSS 53 /NC 173 VDD 83 VSS 203 DM4/DQS13 /TDQS13 113 VSS 233 DQ62 23 VSS 143 DM2/DQS11 /TDQS11 24 144 NC/ / 54 VDD 174 A12/ 84 204 NC/ / 114 DQ58 234 DQ63 25 DQS2 145 VSS 55 A11 175 A9 85 DQS4 205 VSS 115 DQ59 235 VSS 26 VSS 146 DQ22 56 A7 176 VDD 86 VSS 206 DQ38 116 VSS 236 VDDSPD 27 DQ18 147 DQ23 57 VDD 177 A8 87 DQ34 207 DQ39 117 SA0 237 SA1 28 DQ19 148 VSS 58 A5 178 A6 88 DQ35 208 VSS 118 SCL 238 SDA 29 VSS 149 DQ28 59 A4 179 VDD 89 VSS 209 DQ44 119 SA2 239 VSS 30 DQ24 150 DQ29 60 VDD 180 A3 90 DQ40 210 DQ45 120 VTT 240 VTT Note: 1. CKE1, and ODT1 are for 2GB/4GB/8GB only. 2. and are for 8GB only. 3. TDQS9-TDQS17 and - are for 1GB/2GB only. REV 1.1 06/2009 3 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GC72B89A0NL / NT2GC72B8PA0NL NT4GC72B4NA1NL / NT4GC72B8NA1NL / NT8GTC72B4NA1NL 1GB: 128M x 72 / 2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72 PC3-8500 / PC3-10600 Registered DDR3 SDRAM DIMM Input/Output Functional Description Symbol Type Polarity Function CK0, CK1 , Input Cross point The system clock inputs. All address and command lines are sampled on the cross point of the rising edge of CK and falling edge of . A Delay Locked Loop (DLL) circuit is driven from the clock inputs and output timing for read operations is synchronized to the input clock. However, CK1 and are terminated but not used on RDIMMs. CKE0, CKE1 Input Active High Activates the DDR3 SDRAM CK signal when high and deactivates the CK signal when low. By deactivating the clocks, CKE low initiates the Power Down mode or the Self Refresh mode. - Input Active Low Enable the command decoders for the associated rank of SDRAM when low and disables decoders when high. When decoders are disabled, new commands are ignored and previous operations continue. Other combinations of these input signals perform unique functions, including disabling all outputs (except CKE and ODT) of the register(s) on the DIMM or accessing internal control words in the register device(s). For modules with two registers, and operate similarly to and for the second set of register outputs or register control words. , , Input Active Low When sampled at the positive rising edge of CK and falling edge of , signals , , define the operation to be executed by the SDRAM. ODT0, ODT1 Input Active High Asserts on-die termination for DQ, DM, DQS, and signals if enabled via the DDR3 SDRAM mode register. DM0 - DM8 Input Active High The data write masks, associated with one data byte. In Write mode, DM operates as a byte mask by allowing input data to be written if it is low but blocks the write operation if it is high. In Read mode, DM lines have no effect. Cross point The data strobes, associated with one data byte, sourced with data transfers. In Write mode, the data strobe is sourced by the controller and is centered in the data window. In Read mode, the data strobe is sourced by the DDR3 SDRAM and is sent at the leading edge of the data window. signals are complements, and timing is relative to the cross point of respective DQS and . If the module is to be operated in single ended strobe mode, all signals must be tied on the system board to VSS and DDR3 SDRAM mode registers programmed appropriately. DQS0 - DQS17 - I/O TDQS9 - TDQS17 - Output BA0, BA1, BA2 Input TDQS/ is applicable for x8 DRAMs only. When enabled via mode register A11=1 in MR1, DRAM will enable the same termination resistance function on TDQS/ that is applied to DQS/. When disabled via mode register A11=0 in MR1, DM/TDQS will provide the data mask function is not used. X4/x16 DRAMs must disable the TDQS function via mode register A11=0 in MR1. - Selects which DDR3 SDRAM internal bank of four or eight is activated. A0 - A9 A10/AP A11 A12/ A13 Input - During a Bank Activate command cycle, defines the row address when sampled at the cross point of the rising edge of CK and falling edge of . During a Read or Write command cycle, defines the column address when sampled at the cross point of the rising edge of CK and falling edge of . In addition to the column address, AP is used to invoke autoprecharge operation at the end of the burst read or write cycle. If AP is high, autoprecharge is selected and BA0-BAn defines the bank to be precharged. If AP is low, autoprecharge is disabled. During a Precharge command cycle, AP is used in conjunction with BA0-BAn to control which bank(s) to precharge. If AP is high, all banks will be precharged regardless of the state of BA0-BAn inputs. If AP is low, then BA0-BAn are used to define which bank to precharge. DQ0 - DQ63 Input - Data Input/Output pins. CB0 - CB7 I/O - Check bits are used for ECC. VDD, VDDSPD, VSS Supply - Power supplies for core, I/O, Serial Presence Detect, Temp sensor, and ground for the module. VREFDQ, VREFCA Supply - Reference voltage for SSTL15 inputs. SDA I/O - This is a bidirectional pin used to transfer data into or out of the SPD EEPROM and temp sensor. A resistor must be connected from the SDA bus line to VDDSPD on the system planar to act as a pull up. SCL Input - This signal is used to clock data into and out of the SPD EEPROM and Temp sensor. SA0 - SA2 Input - Address pins used to select the Serial Presence Detect and Temp sensor base address. Output - The pin is reserved for use to flag critical module temperature. Input - This signal resets the DDR3 SDRAM. Par_In Input - Parity bit for the Address and Control bus. Output - Parity error detected on the Address and Control bus. A resistor may be connected from bus line to VDD on the system planar to act as a pull up. REV 1.1 06/2009 4 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GC72B89A0NL / NT2GC72B8PA0NL NT4GC72B4NA1NL / NT4GC72B8NA1NL / NT8GTC72B4NA1NL 1GB: 128M x 72 / 2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72 PC3-8500 / PC3-10600 Registered DDR3 SDRAM DIMM DQS3 DM3/DQS12 DQ[31:24] DQS TDQS DQ[7:0] DQS2 DM2/DQS11 DQ[23:16] DQS TDQS DQ[7:0] DQS1 DM1/DQS10 DQ[15:8] DQS TDQS DQ[7:0] DQS0 DM0/DQS9 DQ[7:0] DQS TDQS DQ[7:0] ZQ D8 DQS4 DM4/DQS13 CB[39:32] DQS TDQS DQ[7:0] DQS5 DM5/DQS14 DQ[47:40] DQS TDQS DQ[7:0] DQS6 DM6/DQS15 DQ[55:48] DQS TDQS DQ[7:0] DQS7 DM7/DQS16 DQ[63:56] DQS TDQS DQ[7:0] ZQ D4 CK CKE ODT A[13:0]B/ BA[2:0]B DQS TDQS DQ[7:0] CK CKE ODT A[13:0]A/ BA[2:0]A DQS8 DM8/DQS17 CB[7:0] PCK0A RCKE0B RODT0B A[13:0]B/ BA[2:0]B PCK0A RCKE0A RODT0A A[13:0]A/ BA[2:0]A Functional Block Diagram (Part 1 of 2) [1GB - 1 Rank, 128Mx8 DDR3 SDRAMs] ZQ D5 CK CKE ODT A[13:0]B/ BA[2:0]B CK CKE ODT A[13:0]A/ BA[2:0]A D3 ZQ ZQ D6 CK CKE ODT A[13:0]B/ BA[2:0]B CK CKE ODT A[13:0]A/ BA[2:0]A D2 ZQ ZQ D7 CK CKE ODT A[13:0]B/ BA[2:0]B CK CKE ODT A[13:0]A/ BA[2:0]A D1 ZQ ZQ VSS VDDSPD VDD VTT VREFCA VREFDQ VSS CK CKE ODT A[13:0]A/ BA[2:0]A D0 SPD D0-D8 D0-D8 D0-D8 D0-D8 D0-D8 VSS SPD w/ Integrated Thermal Sensor SCL SA0 SA1 SA2 SCL A0 A1 A2 SDA Notes : 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. ZQ resistors are 2401%. For all other resistor values refer to the appropriate wiring diagram. REV 1.1 06/2009 5 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GC72B89A0NL / NT2GC72B8PA0NL NT4GC72B4NA1NL / NT4GC72B8NA1NL / NT8GTC72B4NA1NL 1GB: 128M x 72 / 2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72 PC3-8500 / PC3-10600 Registered DDR3 SDRAM DIMM Functional Block Diagram (Part 2 of 2) [1GB - 1 Rank, 128Mx8 DDR3 SDRAMs] : SDRAMs D[3:0], D8 : SDRAMs D[7:4] BA[2:0] A[13:0] CKE0 ODT0 CK0 120 1% Register / PLL RBA[2:0]A BA[2:0]: SDRAMs D[3:0], D8 RBA[2:0]B BA[2:0]: SDRAMs D[7:4] RA[13:0]A A[13:0]: SDRAMs D[3:0], D8 RA[13:0]B A[13:0]: SDRAMs D[7:4] : SDRAMs D[3:0], D8 : SDRAMs D[7:4] : SDRAMs D[3:0], D8 : SDRAMs D[7:4] : SDRAMs D[3:0], D8 : SDRAMs D[7:4] RCKE0A CKE0: SDRAMs D[3:0], D8 RCKE0B CKE0: SDRAMs D[7:4] RODT0A ODT0: SDRAMs D[3:0], D8 RODT0B ODT0: SDRAMs D[7:4] PCK0A CK: SDRAMs D[3:0], D8 PCK0B CK: SDRAMs D[7:4] : SDRAMs D[3:0], D8 : SDRAMs D[7:4] CK1 120 5% PAR_IN : SDRAMs D[8:0] Note: S[3:2], CKE1, ODT1 are NC (Unused register inputs ODT1 and CKE1 have a 330 resistor to ground) REV 1.1 06/2009 6 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GC72B89A0NL / NT2GC72B8PA0NL NT4GC72B4NA1NL / NT4GC72B8NA1NL / NT8GTC72B4NA1NL 1GB: 128M x 72 / 2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72 PC3-8500 / PC3-10600 Registered DDR3 SDRAM DIMM D11 DQS TDQS DQ[7:0] ZQ DQS TDQS DQ[7:0] ZQ D10 DQS TDQS DQ[7:0] ZQ PCK1B RCKE1B RODT1B D14 DQS TDQS DQ[7:0] ZQ D15 DQS TDQS DQ[7:0] ZQ D16 VSS D9 VDDSPD VDD VTT VREFCA VREFDQ VSS VSS SPD D0-D17 D0-D17 D0-D17 D0-D17 D0-D17 SPD w/ Integrated Thermal Sensor SCL Notes : 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. ZQ resistors are 2401%. For all other resistor values refer to the appropriate wiring diagram. 3. Unless otherwise noted, resistor values are 155%. 4. See the wiring diagrams for all resistors associated with the command, address and control bus. REV 1.1 06/2009 D7 CK CKE ODT A[13:0]A/ BA[2:0]A DQS7 DM7/DQS16 DQ[63:56] D6 DQS TDQS DQ[7:0] ZQ CK CKE ODT A[13:0]A/ BA[2:0]A PCK0B RCKE0B RODT0B A[13:0]B/ BA[2:0]B PCK1A RCKE1A RODT1A DQS TDQS DQ[7:0] ZQ D13 CK CKE ODT A[13:0]A/ BA[2:0]A CK CKE ODT A[13:0]A/ BA[2:0]A CK CKE ODT A[13:0]A/ BA[2:0]A CK CKE ODT A[13:0]A/ BA[2:0]A CK CKE ODT A[13:0]A/ BA[2:0]A D0 DQS TDQS DQ[7:0] ZQ D5 DQS TDQS DQ[7:0] ZQ CK CKE ODT A[13:0]A/ BA[2:0]A DQS TDQS DQ[7:0] ZQ DQS6 DM6/DQS15 DQ[55:48] CK CKE ODT A[13:0]A/ BA[2:0]A DQS0 DM0/DQS9 DQ[7:0] D1 D12 CK CKE ODT A[13:0]A/ BA[2:0]A DQS TDQS DQ[7:0] ZQ DQS TDQS DQ[7:0] ZQ CK CKE ODT A[13:0]A/ BA[2:0]A DQS1 DM1/DQS10 DQ[15:8] D2 DQS TDQS DQ[7:0] ZQ D4 CK CKE ODT A[13:0]A/ BA[2:0]A DQS TDQS DQ[7:0] ZQ DQS5 DM5/DQS14 DQ[47:40] CK CKE ODT A[13:0]A/ BA[2:0]A DQS2 DM2/DQS11 DQ[23:16] D3 DQS TDQS DQ[7:0] ZQ CK CKE ODT A[13:0]A/ BA[2:0]A DQS TDQS DQ[7:0] ZQ D17 DQS4 DM4/DQS13 CB[39:32] CK CKE ODT A[13:0]A/ BA[2:0]A DQS3 DM3/DQS12 DQ[31:24] D8 DQS TDQS DQ[7:0] ZQ CK CKE ODT A[13:0]A/ BA[2:0]A DQS TDQS DQ[7:0] ZQ CK CKE ODT A[13:0]A/ BA[2:0]A DQS8 DM8/DQS17 CB[7:0] CK CKE ODT A[13:0]A/ BA[2:0]A PCK0A RCKE0A RODT0A A[13:0]A/ BA[2:0]A Functional Block Diagram (Part 1 of 2) [2GB - 2 Ranks, 128Mx8 DDR3 SDRAMs] SA0 SA1 SA2 SCL A0 A1 A2 SDA 7 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GC72B89A0NL / NT2GC72B8PA0NL NT4GC72B4NA1NL / NT4GC72B8NA1NL / NT8GTC72B4NA1NL 1GB: 128M x 72 / 2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72 PC3-8500 / PC3-10600 Registered DDR3 SDRAM DIMM Functional Block Diagram (Part 2 of 2) [2GB - 2 Ranks, 128Mx8 DDR3 SDRAMs] BA[2:0] A[13:0] : SDRAMs D[3:0], D8 : SDRAMs D[7:4] : SDRAMs D[12:9], D17 : SDRAMs D[16:13] RBA[2:0]A BA[2:0]: SDRAMs D[3:0], D[12:8], D17 RBA[2:0]B BA[2:0]: SDRAMs D[7:4], D[16:13] RA[13:0]A A[13:0]: SDRAMs D[3:0], D[12:8], D17 RA[13:0]B A[13:0]: SDRAMs D[7:4], D[16:13] : SDRAMs D[7:4], D[16:13] : SDRAMs D[3:0], D[12:8], D17 : SDRAMs D[7:4], D[16:13] : SDRAMs D[3:0], D[12:8], D17 Register / PLL CKE0 CKE1 ODT0 ODT1 CK0 120 1% : SDRAMs D[3:0], D[12:8], D17 : SDRAMs D[7:4], D[16:13] RCKE0A CKE0: SDRAMs D[3:0], D8 RCKE0B CKE0: SDRAMs D[7:4] RCKE1A CKE1: SDRAMs D[12:9], D17 RCKE1B CKE1: SDRAMs D[16:13] RODT0A ODT0: SDRAMs D[3:0], D8 RODT0B ODT0: SDRAMs D[7:4] RODT1A ODT1: SDRAMs D[12:9], D17 RODT1B ODT1: SDRAMs D[16:13] PCK0A CK: SDRAMs D[3:0], D8 PCK0B CK: SDRAMs D[7:4] PCK1A CK: SDRAMs D[12:9], D17 PCK1B CK: SDRAMs D[16:13] : SDRAMs D[3:0], D8 : SDRAMs D[7:4] : SDRAMs D[12:9], D17 : SDRAMs D[16:13] CK1 120 5% PAR_IN : SDRAMs D[17:0] REV 1.1 06/2009 8 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GC72B89A0NL / NT2GC72B8PA0NL NT4GC72B4NA1NL / NT4GC72B8NA1NL / NT8GTC72B4NA1NL 1GB: 128M x 72 / 2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72 PC3-8500 / PC3-10600 Registered DDR3 SDRAM DIMM DQS DQS TDQS TDQS DQ[7:0] ZQ CS RAS CAS WE CK CK CKE ODT A[13:0]A/ BA[2:0]A DQS DQS TDQS TDQS DQ[7:0] ZQ D18 DQS DQS TDQS TDQS DQ[7:0] ZQ D19 D35 CS RAS CAS WE CK CK CKE ODT A[13:0]A/ BA[2:0]A D26 DQS DQS TDQS TDQS DQ[7:0] ZQ D27 D36 CS RAS CAS WE CK CK CKE ODT A[13:0]A/ BA[2:0]A DQS DQS TDQS TDQS DQ[7:0] ZQ PCK1B PCK1B RCKE1B RODT1B RS3 PCK1B PCK1B RCKE1B RODT1B RS2 RS1 PCK1A PCK1A RCKE1A RODT1A D17 D34 DQS DQS TDQS TDQS DQ[7:0] ZQ D28 D37 CS RAS CAS WE CK CK CKE ODT A[13:0]A/ BA[2:0]A CS RAS CAS WE CK CK CKE ODT A[13:0]A/ BA[2:0]A CS RAS CAS WE CK CK CKE ODT A[13:0]A/ BA[2:0]A CS RAS CAS WE CK CK CKE ODT A[13:0]A/ BA[2:0]A D10 CS RAS CAS WE CK CK CKE ODT A[13:0]A/ BA[2:0]A DQS DQS TDQS TDQS DQ[7:0] ZQ DQS DQS TDQS TDQS DQ[7:0] ZQ CS RAS CAS WE CK CK CKE ODT A[13:0]A/ BA[2:0]A DQS7 DQS7 DM7/DQS16 DQS16 DQ[63:56] D9 DQS DQS TDQS TDQS DQ[7:0] ZQ D25 CS RAS CAS WE CK CK CKE ODT A[13:0]A/ BA[2:0]A DQS DQS TDQS TDQS DQ[7:0] ZQ DQS DQS TDQS TDQS DQ[7:0] ZQ DQS DQS TDQS TDQS DQ[7:0] ZQ CS RAS CAS WE CK CK CKE ODT A[13:0]A/ BA[2:0]A DQS6 DQS6 DM6/DQS15 DQS15 DQ[55:48] D8 D16 CS RAS CAS WE CK CK CKE ODT A[13:0]A/ BA[2:0]A DQS DQS TDQS TDQS DQ[7:0] ZQ DQS DQS TDQS TDQS DQ[7:0] ZQ CS RAS CAS WE CK CK CKE ODT A[13:0]A/ BA[2:0]A DQS5 DQS5 DM5/DQS14 DQS14 DQ[47:40] D7 DQS DQS TDQS TDQS DQ[7:0] ZQ CS RAS CAS WE CK CK CKE ODT A[13:0]A/ BA[2:0]A DQS DQS TDQS TDQS DQ[7:0] ZQ CS RAS CAS WE CK CK CKE ODT A[13:0]A/ BA[2:0]A DQS4 DQS4 DM4/DQS13 DQS13 DQ[39:32] CS RAS CAS WE CK CK CKE ODT A[13:0]A/ BA[2:0]A RS0 RRASA RCASA RWEA PCK0A PCK0A RCKE0A RODT0A A[13:0]A/ BA[2:0]A Functional Block Diagram (Part 1 of 3) [4GB - 4 Ranks, 128Mx8 DDR3 SDRAMs] VSS VDDSPD VDD VTT VREFCA VREFDQ VSS Notes : 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. ZQ resistors are 2401%. For all other resistor values refer to the appropriate wiring diagram. 3. Unless otherwise noted, resistor values are 155%. 4. See the wiring diagrams for all resistors associated with the command, address and control bus. SPD D0-D17 D0-D17 D0-D17 D0-D17 D0-D17 SPD w/ Integrated Thermal Sensor SCL SA0 SA1 SA2 SCL A0 A1 A2 SDA EVENT EVENT REV 1.1 06/2009 9 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GC72B89A0NL / NT2GC72B8PA0NL NT4GC72B4NA1NL / NT4GC72B8NA1NL / NT8GTC72B4NA1NL 1GB: 128M x 72 / 2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72 PC3-8500 / PC3-10600 Registered DDR3 SDRAM DIMM D11 DQS DQS TDQS TDQS DQ[7:0] ZQ D21 DQS DQS TDQS TDQS DQ[7:0] ZQ D20 PCK1B PCK1B RCKE1B RODT1B RS3 CS RAS CAS WE CK CK CKE ODT A[13:0]A/ BA[2:0]A D32 CS RAS CAS WE CK CK CKE ODT A[13:0]A/ BA[2:0]A DQS DQS TDQS TDQS DQ[7:0] ZQ DQS DQS TDQS TDQS DQ[7:0] ZQ D31 CS RAS CAS WE CK CK CKE ODT A[13:0]A/ BA[2:0]A D22 D33 DQS DQS TDQS TDQS DQ[7:0] ZQ D30 CS RAS CAS WE CK CK CKE ODT A[13:0]A/ BA[2:0]A PCK1B PCK1B RCKE1B RODT1B RS2 PCK1A PCK1A RCKE1A RODT1A RS1 DQS DQS TDQS TDQS DQ[7:0] ZQ DQS DQS TDQS TDQS DQ[7:0] ZQ DQS DQS TDQS TDQS DQ[7:0] ZQ DQS DQS TDQS TDQS DQ[7:0] ZQ D29 CS RAS CAS WE CK CK CKE ODT A[13:0]A/ BA[2:0]A CS RAS CAS WE CK CK CKE ODT A[13:0]A/ BA[2:0]A CS RAS CAS WE CK CK CKE ODT A[13:0]A/ BA[2:0]A CS RAS CAS WE CK CK CKE ODT A[13:0]A/ BA[2:0]A CS RAS CAS WE CK CK CKE ODT A[13:0]A/ BA[2:0]A D2 D12 CS RAS CAS WE CK CK CKE ODT A[13:0]A/ BA[2:0]A DQS DQS TDQS TDQS DQ[7:0] ZQ DQS DQS TDQS TDQS DQ[7:0] ZQ D23 CS RAS CAS WE CK CK CKE ODT A[13:0]A/ BA[2:0]A DQS0 DQS0 DM0/DQS9 DQS9 DQ[7:0] D3 D13 DQS DQS TDQS TDQS DQ[7:0] ZQ CS RAS CAS WE CK CK CKE ODT A[13:0]A/ BA[2:0]A DQS DQS TDQS TDQS DQ[7:0] ZQ DQS DQS TDQS TDQS DQ[7:0] ZQ D24 CS RAS CAS WE CK CK CKE ODT A[13:0]A/ BA[2:0]A DQS1 DQS1 DM1/DQS10 DQS10 DQ[15:8] D4 D14 DQS DQS TDQS TDQS DQ[7:0] ZQ CS RAS CAS WE CK CK CKE ODT A[13:0]A/ BA[2:0]A DQS DQS TDQS TDQS DQ[7:0] ZQ CS RAS CAS WE CK CK CKE ODT A[13:0]A/ BA[2:0]A DQS2 DQS2 DM2/DQS11 DQS11 DQ[23:16] D5 DQS DQS TDQS TDQS DQ[7:0] ZQ CS RAS CAS WE CK CK CKE ODT A[13:0]A/ BA[2:0]A DQS DQS TDQS TDQS DQ[7:0] ZQ D15 CS RAS CAS WE CK CK CKE ODT A[13:0]A/ BA[2:0]A DQS3 DQS3 DM3/DQS12 DQS12 DQ[31:24] D6 DQS DQS TDQS TDQS DQ[7:0] ZQ CS RAS CAS WE CK CK CKE ODT A[13:0]A/ BA[2:0]A DQS DQS TDQS TDQS DQ[7:0] ZQ CS RAS CAS WE CK CK CKE ODT A[13:0]A/ BA[2:0]A DQS8 DQS8 DM8/DQS17 DQS17 CB[7:0] CS RAS CAS WE CK CK CKE ODT A[13:0]A/ BA[2:0]A RS0 RRASA RCASA RWEA PCK0A PCK0A RCKE0A RODT0A A[13:0]A/ BA[2:0]A Functional Block Diagram (Part 2 of 3) [4GB - 4 Ranks, 128Mx8 DDR3 SDRAMs] VSS REV 1.1 06/2009 10 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GC72B89A0NL / NT2GC72B8PA0NL NT4GC72B4NA1NL / NT4GC72B8NA1NL / NT8GTC72B4NA1NL 1GB: 128M x 72 / 2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72 PC3-8500 / PC3-10600 Registered DDR3 SDRAM DIMM Functional Block Diagram (Part 3 of 3) [4GB - 4 Ranks, 128Mx8 DDR3 SDRAMs] S0 S1 S2 S3 BA[2:0] A[13:0] Register / PLL RAS CAS WE CKE0 CKE1 ODT0 ODT1 CK0 120 1% CK0 CS0_n CS0_n: SDRAMs D[10:2] CS1_n CS1_n: SDRAMs D[19:11] CS2_n CS2_n: SDRAMs D[28:20] CS3_n CS3_n: SDRAMs D[31:29] BA[2:0]A BA[2:0]: SDRAMs D[6:2], D[15:11], D[24:20], D[33:29] BA[2:0]B BA[2:0]: SDRAMs D[10:7], D[19:16], D[28:25], D[37:34] A[13:0]A A[13:0]: SDRAMs D[6:2], D[15:11], D[24:20], D[33:29] A[13:0]B A[13:0]: SDRAMs D[10:7], D[19:16], D[28:25], D[37:34] RRASA RAS: SDRAMs D[6:2], D[15:11], D[24:20], D[33:29] RRASB RAS: SDRAMs D[10:7], D[19:16], D[28:25], D[37:34] RCASA CAS: SDRAMs D[6:2], D[15:11], D[24:20], D[33:29] RCASB CAS: SDRAMs D[10:7], D[19:16], D[28:25], D[37:34] RWEA WE: SDRAMs D[6:2], D[15:11], D[24:20], D[33:29] RWEB WE: SDRAMs D[10:7], D[19:16], D[28:25], D[37:34] RCKE0A CKE0: SDRAMs D[6:2], D[24:20] RCKE0B CKE0: SDRAMs D[10:7], D[28:25] RCKE1A CKE1: SDRAMs D[15:11], D[33:29] RCKE1B CKE1: SDRAMs D[19:16], D[37:34] RODT0A ODT0: SDRAMs D[6:2] RODT0B ODT0: SDRAMs D[10:7] RODT1A ODT1: SDRAMs D[24:20] RODT1B ODT1: SDRAMs D[28:25] PCK0A CK: SDRAMs D[6:2], D[15:11] PCK0B CK: SDRAMs D[10:7], D[28:25] PCK1A CK: SDRAMs D[24:20], D[33:29] PCK1B CK: SDRAMs D[19:16], D[37:34] PCK0A CK: SDRAMs D[6:2], D[15:11] PCK0B CK: SDRAMs D[10:7], D[28:25] PCK1A CK: SDRAMs D[24:20], D[33:29] PCK1B CK: SDRAMs D[19:16], D[37:34] CK1 120 5% CK1 QERR PAR_IN RESET ERR_OUT RST RST: SDRAMs D[37:2] REV 1.1 06/2009 11 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GC72B89A0NL / NT2GC72B8PA0NL NT4GC72B4NA1NL / NT4GC72B8NA1NL / NT8GTC72B4NA1NL 1GB: 128M x 72 / 2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72 PC3-8500 / PC3-10600 Registered DDR3 SDRAM DIMM DQS DM DQ[3:0] D1 D19 CK CKE ODT A[13:0]A/ BA[2:0]A D18 DQS DM DQ[3:0] CK CKE ODT A[13:0]A/ BA[2:0]A D19 CK CKE ODT A[13:0]A/ BA[2:0]A DQS1 VSS CB[11:8] PCK1A RCKE1A RODT1A CK CKE ODT A[13:0]A/ BA[2:0]A CK CKE ODT A[13:0]A/ BA[2:0]A CK CKE ODT A[13:0]A/ BA[2:0]A CK CKE ODT A[13:0]A/ BA[2:0]A DQS DM DQ[3:0] D1 CK CKE ODT A[13:0]A/ BA[2:0]A CK CKE ODT A[13:0]A/ BA[2:0]A 06/2009 D20 DQS DM DQ[3:0] D28 CK CKE ODT A[13:0]A/ BA[2:0]A CK CKE ODT A[13:0]A/ BA[2:0]A DQS1 VSS CB[11:8] VSS REV 1.1 DQS DM DQ[3:0] D2 DQS DM DQ[3:0] D0 D21 DQS DM DQ[3:0] D29 CK CKE ODT A[13:0]A/ BA[2:0]A CK CKE ODT A[13:0]A/ BA[2:0]A DQS2 VSS CB[19:16] DQS DM DQ[3:0] DQS DM DQ[3:0] DQS DM DQ[3:0] D3 DQS DM DQ[3:0] DQS DM DQ[3:0] D26 DQS DM DQ[3:0] D30 D10 DQS0 VSS DQ[3:0] DQS3 VSS CB[27:24] CK CKE ODT A[13:0]A/ BA[2:0]A CK CKE ODT A[13:0]A/ BA[2:0]A DQS DM DQ[3:0] DQS DM DQ[3:0] D8 DQS DM DQ[3:0] D11 DQS10 VSS DQ[15:12] PCK0A RCKE0A RODT0A A[13:0]A/ BA[2:0]A D35 D12 DQS11 VSS DQ[23:20] DQS DM DQ[3:0] CK CKE ODT A[13:0]A/ BA[2:0]A DQS DM DQ[3:0] DQS8 VSS CB[3:0] CK CKE ODT A[13:0]A/ BA[2:0]A CK CKE ODT A[13:0]A/ BA[2:0]A D17 DQS12 VSS DQ[31:28] PCK1A RCKE1A RODT1A DQS DM DQ[3:0] CK CKE ODT A[13:0]A/ BA[2:0]A DQS DM DQ[3:0] CK CKE ODT A[13:0]A/ BA[2:0]A DQS17 VSS CB[7:4] PCK0A RCKE0A RODT0A A[13:0]A/ BA[2:0]A Functional Block Diagram (Part 1 of 3) [4GB - 2 Ranks, 256Mx4 DDR3 SDRAMs] VSS 12 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GC72B89A0NL / NT2GC72B8PA0NL NT4GC72B4NA1NL / NT4GC72B8NA1NL / NT8GTC72B4NA1NL 1GB: 128M x 72 / 2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72 PC3-8500 / PC3-10600 Registered DDR3 SDRAM DIMM DQS DM DQ[3:0] CK CKE ODT A[13:0]A/ BA[2:0]A D23 DQS DM DQ[3:0] DQS DM DQ[3:0] CK CKE ODT A[13:0]A/ BA[2:0]A D33 CK CKE ODT A[13:0]A/ BA[2:0]A DQS6 VSS CB[51:48] DQS DM DQ[3:0] D6 D24 CK CKE ODT A[13:0]A/ BA[2:0]A D25 VSS PCK1B RCKE1B RODT1B CK CKE ODT A[13:0]A/ BA[2:0]A DQS DM DQ[3:0] D15 CK CKE ODT A[13:0]A/ BA[2:0]A CK CKE ODT A[13:0]A/ BA[2:0]A DQS DM DQ[3:0] D34 CK CKE ODT A[13:0]A/ BA[2:0]A CK CKE ODT A[13:0]A/ BA[2:0]A DQS15 VSS CB[55:52] DQS DM DQ[3:0] D7 PCK0B RCKE0B RODT0B A[13:0]B/ BA[2:0]B DQS DM DQ[3:0] DQS DM DQ[3:0] D31 D5 CK CKE ODT A[13:0]A/ BA[2:0]A CK CKE ODT A[13:0]A/ BA[2:0]A DQS5 VSS CB[43:40] D22 D16 DQS7 VSS DQ[59:56] D13 DQS DM DQ[3:0] DQS DM DQ[3:0] DQS DM DQ[3:0] D22 D4 DQS16 VSS DQ[63:60] DQS DM DQ[3:0] CK CKE ODT A[13:0]A/ BA[2:0]A DQS DM DQ[3:0] DQS13 VSS DQ[39:36] CK CKE ODT A[13:0]A/ BA[2:0]A CK CKE ODT A[13:0]A/ BA[2:0]A D14 DQS4 VSS DQ[35:32] PCK1B RCKE1B RODT1B DQS DM DQ[3:0] CK CKE ODT A[13:0]A/ BA[2:0]A DQS DM DQ[3:0] CK CKE ODT A[13:0]A/ BA[2:0]A DQS14 VSS DQ[47:44] PCK0B RCKE0B RODT0B A[13:0]B/ BA[2:0]B Functional Block Diagram (Part 2 of 3) [4GB - 2 Ranks, 256Mx4 DDR3 SDRAMs] VSS VDDSPD VDD VTT VREFCA VREFDQ VSS Notes : 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. ZQ pins of each SDRAM are connected to individual RZQ resistors (2401%). 3. See the wiring diagrams for resistor values. SPD D0-D35 D0-D35 D0-D35 D0-D35 D0-D35 SPD w/ Integrated Thermal Sensor SCL SA0 SA1 SA2 SCL A0 A1 A2 SDA REV 1.1 06/2009 13 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GC72B89A0NL / NT2GC72B8PA0NL NT4GC72B4NA1NL / NT4GC72B8NA1NL / NT8GTC72B4NA1NL 1GB: 128M x 72 / 2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72 PC3-8500 / PC3-10600 Registered DDR3 SDRAM DIMM Functional Block Diagram (Part 3 of 3) [4GB - 2 Ranks, 256Mx4 DDR3 SDRAMs] : SDRAMs D[3:0], D[12:8], D17 : SDRAMs D[7:4], D[16:13] : SDRAMs D[21:18], D[30:26], D35 : SDRAMs D[25:22], D[34:31] BA[2:0] RBA[2:0]A BA[2:0]: SDRAMs D[3:0], D[12:8], D[21:17], D[30:26], D35 RBA[2:0]B BA[2:0]: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31] RA[13:0]A A[13:0]: SDRAMs D[3:0], D[12:8], D[21:17], D[30:26], D35 RA[13:0]B A[13:0]: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31] A[13:0] Register / PLL CKE0 CKE1 ODT0 ODT1 CK0 120 1% : SDRAMs D[3:0], D[12:8], D[21:17], D[30:26], D35 : SDRAMs D[7:4], D[16:13], D[25:22], D[34:31] : SDRAMs D[3:0], D[12:8], D[21:17], D[30:26], D35 : SDRAMs D[7:4], D[16:13], D[25:22], D[34:31] : SDRAMs D[3:0], D[12:8], D[21:17], D[30:26], D35 : SDRAMs D[7:4], D[16:13], D[25:22], D[34:31] RCKE0A CKE0: SDRAMs D[3:0], D[12:8], D17 RCKE0B CKE0: SDRAMs D[7:4], D[16:13] RCKE1A CKE1: SDRAMs D[21:18], D[30:26], D35 RCKE1B CKE1: SDRAMs D[25:22], D[34:31] RODT0A ODT0: SDRAMs D[3:0], D[12:8], D17 RODT0B ODT0: SDRAMs D[7:4], D[16:13] RODT1A ODT1: SDRAMs D[21:18], D[30:26], D35 RODT1B ODT1: SDRAMs D[25:22], D[34:31] PCK0A CK: SDRAMs D[3:0], D[12:8], D17 PCK0B CK: SDRAMs D[7:4], D[16:13] PCK1A CK: SDRAMs D[21:18], D[30:26], D35 PCK1B CK: SDRAMs D[25:22], D[34:31] : SDRAMs D[3:0], D[12:8], D17 : SDRAMs D[7:4], D[16:13] : SDRAMs D[21:18], D[30:26], D35 : SDRAMs D[25:22], D[34:31] CK1 120 5% PAR_IN : SDRAMs D[17:0] REV 1.1 06/2009 14 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GC72B89A0NL / NT2GC72B8PA0NL NT4GC72B4NA1NL / NT4GC72B8NA1NL / NT8GTC72B4NA1NL 1GB: 128M x 72 / 2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72 PC3-8500 / PC3-10600 Registered DDR3 SDRAM DIMM VSS ZQ DQS DM DQ[3:0] ZQ DQS DM DQ[3:0] VSS ZQ DQS DM DQ[3:0] VSS VSS D2 ZQ DQS DM DQ[3:0] VSS ZQ DQS DM DQ[3:0] VSS D49 VSS D51 VSS D53 D46 CK CKE ODT A[13:0]A/ BA[2:0] D47 ZQ DQS DM DQ[3:0] ZQ DQS DM DQ[3:0] D48 CK CKE ODT A[13:0]A/ BA[2:0] ZQ DQS DM DQ[3:0] BRCKE1A VDD CK CKE ODT A[13:0]A/ BA[2:0] CK CKE ODT A[13:0]A/ BA[2:0] D4 D0 BPCK0A BRCKE0A BRODT1A BRA[13:0]A /BRBA[2:0]A ARCKE1A VDD VSS CK CKE ODT A[13:0]A/ BA[2:0] D3 D1 ZQ DQS DM DQ[3:0] ZQ DQS DM DQ[3:0] D44 ZQ DQS DM DQ[3:0] D50 CK CKE ODT A[13:0]A/ BA[2:0] VSS CK CKE ODT A[13:0]A/ BA[2:0] DQS0 VSS DQ[3:0] D6 CK CKE ODT A[13:0]A/ BA[2:0] CK CKE ODT A[13:0]A/ BA[2:0] D5 CK CKE ODT A[13:0]A/ BA[2:0] DQS1 VSS DQ[11:8] VSS ZQ DQS DM DQ[3:0] ZQ DQS DM DQ[3:0] D52 CK CKE ODT A[13:0]A/ BA[2:0] ZQ DQS DM DQ[3:0] VSS D45 CK CKE ODT A[13:0]A/ BA[2:0] VSS D7 ZQ DQS DM DQ[3:0] VSS CK CKE ODT A[13:0]A/ BA[2:0] ZQ DQS DM DQ[3:0] VSS ZQ DQS DM DQ[3:0] CK CKE ODT A[13:0]A/ BA[2:0] VSS DQS2 VSS DQ[19:16] D8 CK CKE ODT A[13:0]A/ BA[2:0] ZQ DQS DM DQ[3:0] CK CKE ODT A[13:0]A/ BA[2:0] VSS DQS3 VSS DQ[27:24] VSS CK CKE ODT A[13:0]A/ BA[2:0] D9 ZQ DQS DM DQ[3:0] CK CKE ODT A[13:0]A/ BA[2:0] VSS CK CKE ODT A[13:0]A/ BA[2:0] ZQ DQS DM DQ[3:0] CK CKE ODT A[13:0]A/ BA[2:0] VSS DQS8 VSS CB[3:0] APCK0A ARCKE0A ARODT0A ARA[13:0]A /ARBA[2:0]A Functional Block Diagram (Part 1 of 5) [8GB - 4 Ranks, 512Mx4 (DDP) DDR3 SDRAMs] VSS REV 1.1 06/2009 15 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GC72B89A0NL / NT2GC72B8PA0NL NT4GC72B4NA1NL / NT4GC72B8NA1NL / NT8GTC72B4NA1NL 1GB: 128M x 72 / 2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72 PC3-8500 / PC3-10600 Registered DDR3 SDRAM DIMM VSS VSS CK CKE ODT A[13:0]A/ BA[2:0] ZQ DQS DM DQ[3:0] ZQ DQS DM DQ[3:0] ZQ DQS DM DQ[3:0] D20 ZQ DQS DM DQ[3:0] VSS ZQ DQS DM DQ[3:0] ZQ DQS DM DQ[3:0] D64 CK CKE ODT A[13:0]A/ BA[2:0] D65 VSS D67 VSS D69 VSS D71 BRCKE1A VDD CK CKE ODT A[13:0]A/ BA[2:0] CK CKE ODT A[13:0]A/ BA[2:0] VSS D18 BPCK1A BRCKE0A BRODT1A BRA[13:0]A /BRBA[2:0]A ARCKE1A VDD D22 CK CKE ODT A[13:0]A/ BA[2:0] CK CKE ODT A[13:0]A/ BA[2:0] D21 D19 VSS CK CKE ODT A[13:0]A/ BA[2:0] CK CKE ODT A[13:0]A/ BA[2:0] D23 ZQ DQS DM DQ[3:0] VSS ZQ DQS DM DQ[3:0] D66 CK CKE ODT A[13:0]A/ BA[2:0] ZQ DQS DM DQ[3:0] D24 ZQ DQS DM DQ[3:0] D62 ZQ DQS DM DQ[3:0] D68 CK CKE ODT A[13:0]A/ BA[2:0] VSS DQS9 VSS DQ[7:4] VSS ZQ DQS DM DQ[3:0] ZQ DQS DM DQ[3:0] D70 CK CKE ODT A[13:0]A/ BA[2:0] ZQ DQS DM DQ[3:0] VSS D63 CK CKE ODT A[13:0]A/ BA[2:0] VSS DQS10 VSS DQ[15:12] D25 ZQ DQS DM DQ[3:0] VSS CK CKE ODT A[13:0]A/ BA[2:0] ZQ DQS DM DQ[3:0] VSS ZQ DQS DM DQ[3:0] CK CKE ODT A[13:0]A/ BA[2:0] VSS DQS11 VSS DQ[23:20] D26 CK CKE ODT A[13:0]A/ BA[2:0] ZQ DQS DM DQ[3:0] CK CKE ODT A[13:0]A/ BA[2:0] VSS DQS12 VSS DQ[31:28] VSS CK CKE ODT A[13:0]A/ BA[2:0] D27 ZQ DQS DM DQ[3:0] CK CKE ODT A[13:0]A/ BA[2:0] VSS CK CKE ODT A[13:0]A/ BA[2:0] ZQ DQS DM DQ[3:0] CK CKE ODT A[13:0]A/ BA[2:0] VSS DQS17 VSS CB[7:4] APCK1A ARCKE0A ARODT0A ARA[13:0]A /ARBA[2:0]A Functional Block Diagram (Part 2 of 5) [8GB - 4 Ranks, 512Mx4 (DDP) DDR3 SDRAMs] Vtt REV 1.1 06/2009 16 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GC72B89A0NL / NT2GC72B8PA0NL NT4GC72B4NA1NL / NT4GC72B8NA1NL / NT8GTC72B4NA1NL 1GB: 128M x 72 / 2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72 PC3-8500 / PC3-10600 Registered DDR3 SDRAM DIMM VSS ZQ DQS DM DQ[3:0] D14 ZQ DQS DM DQ[3:0] VSS ZQ DQS DM DQ[3:0] CK CKE ODT A[13:0]A/ BA[2:0] VSS ZQ DQS DM DQ[3:0] D40 CK CKE ODT A[13:0]A/ BA[2:0] D41 VSS D39 VSS D37 BRCKE1B VDD BPCK0B BRCKE0B BRODT1B BRA[13:0]B /BRBA[2:0]B ARCKE1B VDD VSS D16 ZQ DQS DM DQ[3:0] D42 ZQ DQS DM DQ[3:0] D38 CK CKE ODT A[13:0]A/ BA[2:0] ZQ DQS DM DQ[3:0] CK CKE ODT A[13:0]A/ BA[2:0] CK CKE ODT A[13:0]A/ BA[2:0] D15 CK CKE ODT A[13:0]A/ BA[2:0] D12 CK CKE ODT A[13:0]A/ BA[2:0] CK CKE ODT A[13:0]A/ BA[2:0] VSS D17 VSS ZQ DQS DM DQ[3:0] ZQ DQS DM DQ[3:0] D36 CK CKE ODT A[13:0]A/ BA[2:0] ZQ DQS DM DQ[3:0] D13 ZQ DQS DM DQ[3:0] D43 CK CKE ODT A[13:0]A/ BA[2:0] VSS DQS7 VSS DQ[59:56] VSS VSS CK CKE ODT A[13:0]A/ BA[2:0] ZQ DQS DM DQ[3:0] D10 ZQ DQS DM DQ[3:0] CK CKE ODT A[13:0]A/ BA[2:0] VSS DQS6 VSS DQ[51:48] VSS CK CKE ODT A[13:0]A/ BA[2:0] ZQ DQS DM DQ[3:0] D11 ZQ DQS DM DQ[3:0] CK CKE ODT A[13:0]A/ BA[2:0] VSS DQS5 VSS DQ[43:40] VSS CK CKE ODT A[13:0]A/ BA[2:0] ZQ DQS DM DQ[3:0] CK CKE ODT A[13:0]A/ BA[2:0] VSS DQS4 VSS DQ[35:32] APCK0B ARCKE0B ARODT0B ARA[13:0]B /ARBA[2:0]B Functional Block Diagram (Part 3 of 5) [8GB - 4 Ranks, 512Mx4 (DDP) DDR3 SDRAMs] Vtt REV 1.1 06/2009 17 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GC72B89A0NL / NT2GC72B8PA0NL NT4GC72B4NA1NL / NT4GC72B8NA1NL / NT8GTC72B4NA1NL 1GB: 128M x 72 / 2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72 PC3-8500 / PC3-10600 Registered DDR3 SDRAM DIMM VSS ZQ DQS DM DQ[3:0] D32 ZQ DQS DM DQ[3:0] VSS ZQ DQS DM DQ[3:0] BRCKE1B VDD BPCK1B BRCKE0B BRODT1B BRA[13:0]B /BRBA[2:0]B CK CKE ODT A[13:0]A/ BA[2:0] ARCKE1B VDD VSS D34 VSS D59 ZQ DQS DM DQ[3:0] D58 CK CKE ODT A[13:0]A/ BA[2:0] ZQ DQS DM DQ[3:0] D60 VSS D57 ZQ DQS DM DQ[3:0] D56 CK CKE ODT A[13:0]A/ BA[2:0] ZQ DQS DM DQ[3:0] CK CKE ODT A[13:0]A/ BA[2:0] CK CKE ODT A[13:0]A/ BA[2:0] D33 CK CKE ODT A[13:0]A/ BA[2:0] D30 CK CKE ODT A[13:0]A/ BA[2:0] CK CKE ODT A[13:0]A/ BA[2:0] VSS D35 VSS ZQ DQS DM DQ[3:0] VSS D55 ZQ DQS DM DQ[3:0] D54 CK CKE ODT A[13:0]A/ BA[2:0] ZQ DQS DM DQ[3:0] D31 ZQ DQS DM DQ[3:0] D61 CK CKE ODT A[13:0]A/ BA[2:0] VSS DQS16 VSS DQ[63:60] VSS VSS CK CKE ODT A[13:0]A/ BA[2:0] ZQ DQS DM DQ[3:0] D28 ZQ DQS DM DQ[3:0] CK CKE ODT A[13:0]A/ BA[2:0] VSS DQS15 VSS DQ[55:52] VSS CK CKE ODT A[13:0]A/ BA[2:0] ZQ DQS DM DQ[3:0] D29 ZQ DQS DM DQ[3:0] CK CKE ODT A[13:0]A/ BA[2:0] VSS DQS14 VSS DQ[47:44] VSS CK CKE ODT A[13:0]A/ BA[2:0] ZQ DQS DM DQ[3:0] CK CKE ODT A[13:0]A/ BA[2:0] VSS DQS13 VSS DQ[39:36] APCK1B ARCKE0B ARODT0B ARA[13:0]B /ARBA[2:0]B Functional Block Diagram (Part 4 of 5) [8GB - 4 Ranks, 512Mx4 (DDP) DDR3 SDRAMs] Vtt VDDSPD VDD VTT VREFCA VREFDQ VSS Notes : 1. DQ-to-I/O wiring is may be changed within a nibble. 2, Resistor values are 155%. 2. ZQ resistors are 2401%. 3. See the wiring diagrams for resistor values. SPD D0-D71 D0-D71 D0-D71 D0-D71 D0-D71 SPD w/ Integrated Thermal Sensor SCL SA0 SA1 SA2 SCL A0 A1 A2 SDA REV 1.1 06/2009 18 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GC72B89A0NL / NT2GC72B8PA0NL NT4GC72B4NA1NL / NT4GC72B8NA1NL / NT8GTC72B4NA1NL 1GB: 128M x 72 / 2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72 PC3-8500 / PC3-10600 Registered DDR3 SDRAM DIMM Functional Block Diagram (Part 5 of 5) [8GB - 4 Ranks, 512Mx4 (DDP) DDR3 SDRAMs] BA[2:0] A[13:0] CKE0 CKE1 ODT0 CK0 120 1% CK1 Register / PLL A ARBA[2:0]A ARBA[2:0]B ARA[13:0]A ARA[13:0]B ARCKE0A ARCKE0B ARCKE1A ARCKE1B ARODT0A ARODT0B APCK0A APCK0B APCK1A APCK1B : SDRAMs D1, D3, D5, D7, D9, D19, D21, D23, D25, D27 : SDRAMs D11, D13, D15, D17, D29, D31, D33, D35 : SDRAMs D0, D2, D4, D6, D8, D18, D20, D22, D24, D26 : SDRAMs D10, D12, D14, D16, D28, D30, D32, D34 BA[2:0]: SDRAMs D[9:0], D[27:18] BA[2:0]: SDRAMs D[17:10], D[35:28] A[13:0]: SDRAMs D[9:0], D[27:18] A[13:0]: SDRAMs D[17:10], D[35:28] : SDRAMs D[9:0], D[27:18] : SDRAMs D[17:10], D[35:28] : SDRAMs D[9:0], D[27:18] : SDRAMs D[17:10], D[35:28] : SDRAMs D[9:0], D[27:18] : SDRAMs D[17:10], D[35:28] CKE1: SDRAMs D1, D3, D5, D7, D9, D19, D21, D23, D25, D27 CKE1: SDRAMs D11, D13, D15, D17, D29, D31, D33, D35 CKE0: SDRAMs D0, D2, D4, D6, D8, D18, D20, D22, D24, D26 CKE0: SDRAMs D10, D12, D14, D16, D28, D30, D32, D34 ODT1: SDRAMs D1, D3, D5, D7, D9, D19, D21, D23, D25, D27 ODT1: SDRAMs D11, D13, D15, D17, D29, D31, D33, D35 CK: SDRAMs D[9:0] CK: SDRAMs D[17:10] CK: SDRAMs D[27:18] CK: SDRAMs D[35:28] : SDRAMs D[9:0] : SDRAMs D[17:10] : SDRAMs D[27:18] : SDRAMs D[35:28] 120 5% PAR_IN : SDRAMs D[71:0] BA[2:0] A[13:0] CKE0 CKE1 ODT1 CK0 120 1% CK1 PAR_IN 06/2009 BPCK0A BPCK0B BPCK1A BPCK1B : SDRAMs D45, D47, D49, D51, D53, D63, D65, D67, D69, D71 : SDRAMs D37, D39, D41, D43, D55, D57, D59, D61 : SDRAMs D44, D46, D48, D50, D52, D62, D64, D66, D68, D70 : SDRAMs D36, D38, D40, D42, D54, D56, D58, D60 BA[2:0]: SDRAMs D[53:44], D[71:62] BA[2:0]: SDRAMs D[43:36], D[61:54] A[13:0]: SDRAMs D[53:44], D[71:62] A[13:0]: SDRAMs D[43:36], D[61:54] : SDRAMs D[53:44], D[71:62] : SDRAMs D[43:36], D[61:54] : SDRAMs D[53:44], D[71:62] : SDRAMs D[43:36], D[61:54] : SDRAMs D[53:44], D[71:62] : SDRAMs D[43:36], D[61:54] CKE1: SDRAMs D45, D47, D49, D51, D53, D63, D65, D67, D69, D71 CKE1: SDRAMs D37, D39, D41, D43, D55, D57, D59, D61 CKE0: SDRAMs D44, D46, D48, D50, D52, D62, D64, D66, D68, D70 CKE0: SDRAMs D36, D38, D40, D42, D54, D56, D58, D60 ODT1: SDRAMs D45, D47, D49, D51, D53, D63, D65, D67, D69, D71 ODT1: SDRAMs D37, D39, D41, D43, D55, D57, D59, D61 CK: SDRAMs D[53:44] CK: SDRAMs D[43:36] CK: SDRAMs D[71:62] CK: SDRAMs D[61:54] : SDRAMs D[53:44] : SDRAMs D[43:36] : SDRAMs D[71:62] : SDRAMs D[61:54] 120 5% REV 1.1 Register / PLL B BRBA[2:0]A BRBA[2:0]B BRA[13:0]A BRA[13:0]B BRCKE0A BRCKE0B BRCKE1A BRCKE1B BRODT0A BRODT0B 19 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GC72B89A0NL / NT2GC72B8PA0NL NT4GC72B4NA1NL / NT4GC72B8NA1NL / NT8GTC72B4NA1NL 1GB: 128M x 72 / 2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72 PC3-8500 / PC3-10600 Registered DDR3 SDRAM DIMM Serial Presence Detect (Part 1 of 2) [NT1GC72B89A0NL, 1GB - 1 Ranks, 128Mx8 DDR3 SDRAMs] SPD Entry Value Byte Serial PD Data Entry (Hex.) Description 0 CRC range, EEPROM bytes, bytes used 1 SPD revision 2 DRAM device type 3 Module type (form factor) 4 SDRAM Device density and banks 5 SDRAM device row and column count 6 Module minimum nominal voltage 7 Module ranks and device DQ count 8 ECC tag and module memory Bus width -BE -CG -BE -CG CRC Covers Bytes: 0~116, Total SPD Bytes: 256, SPD Bytes Used: 176, CRC Covers Bytes: 0~116, Total SPD Bytes: 256, SPD Bytes Used: 176, 92 92 Revision 1.0 Revision 1.0 10 10 DDR3 SDRAM DDR3 SDRAM 0B 0B RDIMM RDIMM 01 01 8 banks, 1Gb 8 banks, 1Gb 02 02 14 rows, 10 columns 14 rows, 10 columns 11 11 1.5 V 1.5 V 00 00 1 ranks, 8 bits 1 ranks, 8 bits 01 01 With ECC, 64bits With ECC, 64bits 0B 0B 9 Fine timebase dividend/divisor (in ps) 2.5ps 2.5ps 52 52 10 Medium timebase dividend 1ns 1ns 01 01 11 Medium timebase divisor 8ns 8ns 08 08 12 Minimum SDRAM cycle time (tCKmin) 1.875ns 1.5ns 0F 0C 13 Reserved Undefined Undefined 00 00 14 CAS latencies supported 6,7,8 6,7,8,9 1C 3C 15 CAS latencies supported Undefined Undefined 00 00 16 Minimum CAS latency time (tAAmin) 13.125ns 13.125ns 69 69 17 Minimum write recovery time (tWRmin) 15ns 15ns 78 78 18 Minimum -to- delay (tRCDmin) 13.125ns 13.125ns 69 69 19 Minimum Row Active to Row Active delay (tRRDmin) 7.5ns 6ns 3C 30 20 Minimum row Precharge delay (tRPmin) 13.125ns 13.125ns 69 69 21 Upper nibble for tRAS and tRC 1,1 1,1 11 11 22 Minimum Active-to-Precharge delay (tRASmin) 37.5ns 36ns 2C 20 23 Minimum Active-to-Active/Refresh delay (tRCmin) 50.625ns 49.125ns 95 89 24 Minimum refresh recovery delay (tRFCmin) LSB (Combo bytes 24,25) (Combo bytes 24,25) 70 70 25 Minimum refresh recovery delay (tRFCmin) MSB 110ns 110ns 03 03 26 Minimum internal Write-to-Read command delay (tWTRmin) 7.5ns 7.5ns 3C 3C 27 Minimum internal Read-to-Precharge command delay (tRTPmin) 7.5ns 7.5ns 3C 3C 28 Minimum four active window delay (tFAWmin) LSB (Combo byte 28, 29) (Combo byte 28, 29) 01 00 29 Minimum four active window delay (tFAWmin) MSB 37.5ns 30ns 2C F0 30 SDRAM device output drivers suported RZQ / 6, RZQ / 7, DLL-Off Mode Support, RZQ / 6, RZQ / 7, DLL-Off Mode Support, 83 83 31 SDRAM device thermal and refresh options Extended Temperature Range, ASR, ODTS, PASR, Extended Temperature Range, ASR, ODTS, PASR, 8D 8D 32 Module Thermal Sensor 33 SDRAM Device Type 34-59 Thermal Sensor Support Thermal Sensor Support 80 80 Standard Monolithic Device Standard Monolithic Device 00 00 Undefined Undefined -- -- Reserved 60 Module height (nominal) 29 height 30 mm 29 height 30 mm 0F 0F 61 Module thickness (Max) Back: 1 < thickness 2 mm, Front: 1 < thickness 2 mm, Back: 1 < thickness 2 mm, Front: 1 < thickness 2 mm, 11 11 62 Raw Card ID reference Raw Card A Raw Card A 00 00 63 DRAM address mapping edge connector 1 row, 1 register 1 row, 1 register 05 05 Undefined Undefined -- -- Nanya Technology Nanya Technology 830B 830B 64-116 Reserved 117-118 Module manufacture ID 119-121 Module manufacturer Information 126-127 CRC REV 1.1 06/2009 Undefined Undefined -- -- Calculated Value Calculated Value D6AC 9405 20 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GC72B89A0NL / NT2GC72B8PA0NL NT4GC72B4NA1NL / NT4GC72B8NA1NL / NT8GTC72B4NA1NL 1GB: 128M x 72 / 2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72 PC3-8500 / PC3-10600 Registered DDR3 SDRAM DIMM Serial Presence Detect (Part 2 of 2) [NT1GC72B89A0NL, 1GB - 1 Ranks, 128Mx8 DDR3 SDRAMs] SPD Entry Value Byte Serial PD Data Entry (Hex.) Description -BE -CG -BE -CG 128-145 Module part number ASCII values ASCII values -- -- 146 Module die revision Undefined Undefined 00 00 147 Module PCB revision Undefined Undefined 00 00 Nanya Technology Nanya Technology 830B 830B Manufacturer reserved Undefined Undefined -- -- Customer reserved Undefined Undefined -- -- 148-149 DRAM device manufacturer ID 150-175 176-255 Note1: NT1GC72B89A0NL-BE -> 4E54314743373242383941304E4C2D424520 NT1GC72B89A0NL-CG -> 4E54314743373242383941304E4C2D434720 REV 1.1 06/2009 21 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GC72B89A0NL / NT2GC72B8PA0NL NT4GC72B4NA1NL / NT4GC72B8NA1NL / NT8GTC72B4NA1NL 1GB: 128M x 72 / 2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72 PC3-8500 / PC3-10600 Registered DDR3 SDRAM DIMM Serial Presence Detect (Part 1 of 2) [NT2GC72B8PA0NL, 2GB - 2 Ranks, 128Mx8 DDR3 SDRAMs] SPD Entry Value Byte Serial PD Data Entry (Hex.) Description 0 CRC range, EEPROM bytes, bytes used 1 SPD revision 2 DRAM device type 3 Module type (form factor) 4 SDRAM Device density and banks 5 SDRAM device row and column count 6 Module minimum nominal voltage 7 Module ranks and device DQ count 8 ECC tag and module memory Bus width -BE -CG -BE -CG CRC Covers Bytes: 0~116, Total SPD Bytes: 256, SPD Bytes Used: 176, CRC Covers Bytes: 0~116, Total SPD Bytes: 256, SPD Bytes Used: 176, 92 92 Revision 1.0 Revision 1.0 10 10 DDR3 SDRAM DDR3 SDRAM 0B 0B RDIMM RDIMM 01 01 8 banks, 1Gb 8 banks, 1Gb 02 02 14 rows, 10 columns 14 rows, 10 columns 11 11 1.5 V 1.5 V 00 00 2 ranks, 8 bits 2 ranks, 8 bits 09 09 With ECC, 64bits With ECC, 64bits 0B 0B 9 Fine timebase dividend/divisor (in ps) 2.5ps 2.5ps 52 52 10 Medium timebase dividend 1ns 1ns 01 01 11 Medium timebase divisor 8ns 8ns 08 08 12 Minimum SDRAM cycle time (tCKmin) 1.875ns 1.5ns 0F 0C 13 Reserved Undefined Undefined 00 00 14 CAS latencies supported 6,7,8 6,7,8,9 1C 3C 15 CAS latencies supported Undefined Undefined 00 00 16 Minimum CAS latency time (tAAmin) 13.125ns 13.125ns 69 69 17 Minimum write recovery time (tWRmin) 15ns 15ns 78 78 18 Minimum -to- delay (tRCDmin) 13.125ns 13.125ns 69 69 19 Minimum Row Active to Row Active delay (tRRDmin) 7.5ns 6ns 3C 30 20 Minimum row Precharge delay (tRPmin) 13.125ns 13.125ns 69 69 21 Upper nibble for tRAS and tRC 1,1 1,1 11 11 22 Minimum Active-to-Precharge delay (tRASmin) 37.5ns 36ns 2C 20 23 Minimum Active-to-Active/Refresh delay (tRCmin) 50.625ns 49.125ns 95 89 24 Minimum refresh recovery delay (tRFCmin) LSB (Combo bytes 24,25) (Combo bytes 24,25) 70 70 25 Minimum refresh recovery delay (tRFCmin) MSB 110ns 110ns 03 03 26 Minimum internal Write-to-Read command delay (tWTRmin) 7.5ns 7.5ns 3C 3C 27 Minimum internal Read-to-Precharge command delay (tRTPmin) 7.5ns 7.5ns 3C 3C 28 Minimum four active window delay (tFAWmin) LSB (Combo byte 28, 29) (Combo byte 28, 29) 01 00 29 Minimum four active window delay (tFAWmin) MSB 37.5ns 30ns 2C F0 30 SDRAM device output drivers suported RZQ / 6, RZQ / 7, DLL-Off Mode Support, RZQ / 6, RZQ / 7, DLL-Off Mode Support, 83 83 31 SDRAM device thermal and refresh options Extended Temperature Range, ASR, ODTS, PASR, Extended Temperature Range, ASR, ODTS, PASR, 8D 8D 32 Module Thermal Sensor 33 SDRAM Device Type 34-59 Thermal Sensor Support Thermal Sensor Support 80 80 Standard Monolithic Device Standard Monolithic Device 00 00 Undefined Undefined -- -- Reserved 60 Module height (nominal) 29 height 30 mm 29 height 30 mm 0F 0F 61 Module thickness (Max) Back: 1 < thickness 2 mm, Front: 1 < thickness 2 mm, Back: 1 < thickness 2 mm, Front: 1 < thickness 2 mm, 11 11 62 Raw Card ID reference 63 DRAM address mapping edge connector 64-116 Reserved 117-118 Module manufacture ID 119-121 Module manufacturer Information 126-127 CRC REV 1.1 06/2009 Raw Card B Raw Card B 01 01 1 row, 1 register 1 row, 1 register 05 05 Undefined Undefined -- -- Nanya Technology Nanya Technology 830B 830B Undefined Undefined -- -- Calculated Value Calculated Value 24C4 666D 22 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GC72B89A0NL / NT2GC72B8PA0NL NT4GC72B4NA1NL / NT4GC72B8NA1NL / NT8GTC72B4NA1NL 1GB: 128M x 72 / 2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72 PC3-8500 / PC3-10600 Registered DDR3 SDRAM DIMM Serial Presence Detect (Part 2 of 2) [NT2GC72B8PA0NL, 2GB - 2 Ranks, 128Mx8 DDR3 SDRAMs] SPD Entry Value Byte Serial PD Data Entry (Hex.) Description -BE -CG -BE -CG 128-145 Module part number ASCII values ASCII values -- -- 146 Module die revision Undefined Undefined 00 00 147 Module PCB revision Undefined Undefined 00 00 Nanya Technology Nanya Technology 830B 830B Manufacturer reserved Undefined Undefined -- -- Customer reserved Undefined Undefined -- -- 148-149 DRAM device manufacturer ID 150-175 176-255 Note1: NT2GC72B8PA0NL-BE -> 4E54324743373242385041304E4C2D424520 NT2GC72B8PA0NL-CG -> 4E54324743373242385041304E4C2D434720 REV 1.1 06/2009 23 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GC72B89A0NL / NT2GC72B8PA0NL NT4GC72B4NA1NL / NT4GC72B8NA1NL / NT8GTC72B4NA1NL 1GB: 128M x 72 / 2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72 PC3-8500 / PC3-10600 Registered DDR3 SDRAM DIMM Serial Presence Detect (Part 1 of 2) [NT4GC72B8NA1NL, 4GB - 4 Ranks, 128Mx8 DDR3 SDRAMs] SPD Entry Value Byte Serial PD Data Entry (Hex.) Description 0 CRC range, EEPROM bytes, bytes used 1 SPD revision 2 DRAM device type 3 Module type (form factor) 4 SDRAM Device density and banks 5 SDRAM device row and column count 6 Module minimum nominal voltage 7 Module ranks and device DQ count 8 ECC tag and module memory Bus width -BE -CG -BE -CG CRC Covers Bytes: 0~116, Total SPD Bytes: 256, SPD Bytes Used: 176, CRC Covers Bytes: 0~116, Total SPD Bytes: 256, SPD Bytes Used: 176, 92 92 Revision 1.0 Revision 1.0 10 10 DDR3 SDRAM DDR3 SDRAM 0B 0B RDIMM RDIMM 01 01 8 banks, 1Gb 8 banks, 1Gb 02 02 14 rows, 10 columns 14 rows, 10 columns 11 11 1.5 V 1.5 V 00 00 4 ranks, 8 bits 4 ranks, 8 bits 19 19 With ECC, 64bits With ECC, 64bits 0B 0B 9 Fine timebase dividend/divisor (in ps) 2.5ps 2.5ps 52 52 10 Medium timebase dividend 1ns 1ns 01 01 11 Medium timebase divisor 8ns 8ns 08 08 12 Minimum SDRAM cycle time (tCKmin) 1.875ns 1.5ns 0F 0C 13 Reserved Undefined Undefined 00 00 14 CAS latencies supported 6,7,8 6,7,8,9 1C 3C 15 CAS latencies supported Undefined Undefined 00 00 16 Minimum CAS latency time (tAAmin) 13.125ns 13.125ns 69 69 17 Minimum write recovery time (tWRmin) 15ns 15ns 78 78 18 Minimum -to- delay (tRCDmin) 13.125ns 13.125ns 69 69 19 Minimum Row Active to Row Active delay (tRRDmin) 7.5ns 6ns 3C 30 20 Minimum row Precharge delay (tRPmin) 13.125ns 13.125ns 69 69 21 Upper nibble for tRAS and tRC 1,1 1,1 11 11 22 Minimum Active-to-Precharge delay (tRASmin) 37.5ns 36ns 2C 20 23 Minimum Active-to-Active/Refresh delay (tRCmin) 50.625ns 49.125ns 95 89 24 Minimum refresh recovery delay (tRFCmin) LSB (Combo bytes 24,25) (Combo bytes 24,25) 70 70 25 Minimum refresh recovery delay (tRFCmin) MSB 110ns 110ns 03 03 26 Minimum internal Write-to-Read command delay (tWTRmin) 7.5ns 7.5ns 3C 3C 27 Minimum internal Read-to-Precharge command delay (tRTPmin) 7.5ns 7.5ns 3C 3C 28 Minimum four active window delay (tFAWmin) LSB (Combo byte 28, 29) (Combo byte 28, 29) 01 00 29 Minimum four active window delay (tFAWmin) MSB 37.5ns 30ns 2C F0 30 SDRAM device output drivers suported RZQ / 6, RZQ / 7, DLL-Off Mode Support, RZQ / 6, RZQ / 7, DLL-Off Mode Support, 83 83 31 SDRAM device thermal and refresh options Extended Temperature Range, ASR, ODTS, PASR, Extended Temperature Range, ASR, ODTS, PASR, 8D 8D 32 Module Thermal Sensor 33 SDRAM Device Type 34-59 Thermal Sensor Support Thermal Sensor Support 80 80 Standard Monolithic Device Standard Monolithic Device 00 00 Undefined Undefined -- -- Reserved 60 Module height (nominal) 29 height 30 mm 29 height 30 mm 0F 0F 61 Module thickness (Max) Back: 3 < thickness 4 mm, Front: 3 < thickness 4 mm, Back: 3 < thickness 4 mm, Front: 3 < thickness 4 mm, 33 33 62 Raw Card ID reference Raw Card H Raw Card H 07 07 63 DRAM address mapping edge connector 2 rows, 1 register 2 rows, 1 register 09 09 Undefined Undefined -- -- Nanya Technology Nanya Technology 830B 830B 64-116 Reserved 117-118 Module manufacture ID 119-121 Module manufacturer Information 126-127 CRC REV 1.1 06/2009 Undefined Undefined -- -- Calculated Value Calculated Value E6F3 A45A 24 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GC72B89A0NL / NT2GC72B8PA0NL NT4GC72B4NA1NL / NT4GC72B8NA1NL / NT8GTC72B4NA1NL 1GB: 128M x 72 / 2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72 PC3-8500 / PC3-10600 Registered DDR3 SDRAM DIMM Serial Presence Detect (Part 2 of 2) [NT4GC72B8NA1NL, 4GB - 4 Ranks, 128Mx8 DDR3 SDRAMs] SPD Entry Value Byte Serial PD Data Entry (Hex.) Description -BE -CG -BE -CG 128-145 Module part number ASCII values ASCII values -- -- 146 Module die revision Undefined Undefined 00 00 147 Module PCB revision Undefined Undefined 00 00 Nanya Technology Nanya Technology 830B 830B Manufacturer reserved Undefined Undefined -- -- Customer reserved Undefined Undefined -- -- 148-149 DRAM device manufacturer ID 150-175 176-255 Note1: NT4GC72B8NA1NL-BE -> 4E54344743373242384E41314E4C2D424520 NT4GC72B8NA1NL-CG -> 4E54344743373242384E41314E4C2D434720 REV 1.1 06/2009 25 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GC72B89A0NL / NT2GC72B8PA0NL NT4GC72B4NA1NL / NT4GC72B8NA1NL / NT8GTC72B4NA1NL 1GB: 128M x 72 / 2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72 PC3-8500 / PC3-10600 Registered DDR3 SDRAM DIMM Serial Presence Detect (Part 1 of 2) [NT4GC72B4NA1NL, 4GB - 2 Ranks, 256Mx4 DDR3 SDRAMs] SPD Entry Value Byte Serial PD Data Entry (Hex.) Description 0 CRC range, EEPROM bytes, bytes used 1 SPD revision 2 DRAM device type 3 Module type (form factor) 4 SDRAM Device density and banks 5 SDRAM device row and column count 6 Module minimum nominal voltage 7 Module ranks and device DQ count 8 ECC tag and module memory Bus width -BE -CG -BE -CG CRC Covers Bytes: 0~116, Total SPD Bytes: 256, SPD Bytes Used: 176, CRC Covers Bytes: 0~116, Total SPD Bytes: 256, SPD Bytes Used: 176, 92 92 Revision 1.0 Revision 1.0 10 10 DDR3 SDRAM DDR3 SDRAM 0B 0B RDIMM RDIMM 01 01 8 banks, 1Gb 8 banks, 1Gb 02 02 14 rows, 11 columns 14 rows, 11 columns 12 12 1.5 V 1.5 V 00 00 2 ranks, 4 bits 2 ranks, 4 bits 08 08 With ECC, 64bits With ECC, 64bits 0B 0B 9 Fine timebase dividend/divisor (in ps) 2.5ps 2.5ps 52 52 10 Medium timebase dividend 1ns 1ns 01 01 11 Medium timebase divisor 8ns 8ns 08 08 12 Minimum SDRAM cycle time (tCKmin) 1.875ns 1.5ns 0F 0C 13 Reserved Undefined Undefined 00 00 14 CAS latencies supported 6,7,8 6,7,8,9 1C 3C 15 CAS latencies supported Undefined Undefined 00 00 16 Minimum CAS latency time (tAAmin) 13.125ns 13.125ns 69 69 17 Minimum write recovery time (tWRmin) 15ns 15ns 78 78 18 Minimum -to- delay (tRCDmin) 13.125ns 13.125ns 69 69 19 Minimum Row Active to Row Active delay (tRRDmin) 7.5ns 6ns 3C 30 20 Minimum row Precharge delay (tRPmin) 13.125ns 13.125ns 69 69 21 Upper nibble for tRAS and tRC 1,1 1,1 11 11 22 Minimum Active-to-Precharge delay (tRASmin) 37.5ns 36ns 2C 20 23 Minimum Active-to-Active/Refresh delay (tRCmin) 50.625ns 49.125ns 95 89 24 Minimum refresh recovery delay (tRFCmin) LSB (Combo bytes 24,25) (Combo bytes 24,25) 70 70 25 Minimum refresh recovery delay (tRFCmin) MSB 110ns 110ns 03 03 26 Minimum internal Write-to-Read command delay (tWTRmin) 7.5ns 7.5ns 3C 3C 27 Minimum internal Read-to-Precharge command delay (tRTPmin) 7.5ns 7.5ns 3C 3C 28 Minimum four active window delay (tFAWmin) LSB (Combo byte 28, 29) (Combo byte 28, 29) 01 00 29 Minimum four active window delay (tFAWmin) MSB 37.5ns 30ns 2C F0 30 SDRAM device output drivers suported RZQ / 6, RZQ / 7, DLL-Off Mode Support, RZQ / 6, RZQ / 7, DLL-Off Mode Support, 83 83 31 SDRAM device thermal and refresh options Extended Temperature Range, ASR, ODTS, PASR, Extended Temperature Range, ASR, ODTS, PASR, 8D 8D 32 Module Thermal Sensor 33 SDRAM Device Type 34-59 Thermal Sensor Support Thermal Sensor Support 80 80 Standard Monolithic Device Standard Monolithic Device 00 00 Undefined Undefined -- -- Reserved 60 Module height (nominal) 29 height 30 mm 29 height 30 mm 0F 0F 61 Module thickness (Max) Back: 3 < thickness 4 mm, Front: 3 < thickness 4 mm, Back: 3 < thickness 4 mm, Front: 3 < thickness 4 mm, 33 33 62 Raw Card ID reference 63 DRAM address mapping edge connector 64-116 Reserved 117-118 Module manufacture ID 119-121 Module manufacturer Information 126-127 CRC REV 1.1 06/2009 Raw Card E Raw Card E 04 04 2 rows, 1 register 2 rows, 1 register 09 09 Undefined Undefined -- -- Nanya Technology Nanya Technology 830B 830B Undefined Undefined -- -- Calculated Value Calculated Value D041 92E8 26 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GC72B89A0NL / NT2GC72B8PA0NL NT4GC72B4NA1NL / NT4GC72B8NA1NL / NT8GTC72B4NA1NL 1GB: 128M x 72 / 2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72 PC3-8500 / PC3-10600 Registered DDR3 SDRAM DIMM Serial Presence Detect (Part 2 of 2) [NT4GC72B4NA1NL, 4GB - 2 Ranks, 256Mx4 DDR3 SDRAMs] SPD Entry Value Byte Serial PD Data Entry (Hex.) Description -BE -CG -BE -CG 128-145 Module part number ASCII values ASCII values -- -- 146 Module die revision Undefined Undefined 00 00 147 Module PCB revision Undefined Undefined 00 00 Nanya Technology Nanya Technology 830B 830B Manufacturer reserved Undefined Undefined -- -- Customer reserved Undefined Undefined -- -- 148-149 DRAM device manufacturer ID 150-175 176-255 Note1: NT4GC72B4NA1NL-BE -> 4E54344743373242344E41314E4C2D424520 NT4GC72B4NA1NL-CG -> 4E54344743373242344E41314E4C2D434720 REV 1.1 06/2009 27 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GC72B89A0NL / NT2GC72B8PA0NL NT4GC72B4NA1NL / NT4GC72B8NA1NL / NT8GTC72B4NA1NL 1GB: 128M x 72 / 2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72 PC3-8500 / PC3-10600 Registered DDR3 SDRAM DIMM Serial Presence Detect (Part 1 of 2) [NT8GTC72B4NA1NL, 8GB - 4 Ranks, 512Mx4 DDR3 SDRAMs] SPD Entry Value Byte Serial PD Data Entry (Hex.) Description 0 CRC range, EEPROM bytes, bytes used 1 SPD revision 2 DRAM device type 3 Module type (form factor) 4 SDRAM Device density and banks 5 SDRAM device row and column count 6 Module minimum nominal voltage 7 Module ranks and device DQ count 8 ECC tag and module memory Bus width -BE -CG -BE -CG CRC Covers Bytes: 0~116, Total SPD Bytes: 256, SPD Bytes Used: 176, CRC Covers Bytes: 0~116, Total SPD Bytes: 256, SPD Bytes Used: 176, 92 92 Revision 1.0 Revision 1.0 10 10 DDR3 SDRAM DDR3 SDRAM 0B 0B RDIMM RDIMM 01 01 8 banks, 1Gb 8 banks, 1Gb 02 02 14 rows, 11 columns 14 rows, 11 columns 12 12 1.5 V 1.5 V 00 00 4 ranks, 4 bits 4 ranks, 4 bits 18 18 With ECC, 64bits With ECC, 64bits 0B 0B 9 Fine timebase dividend/divisor (in ps) 2.5ps 2.5ps 52 52 10 Medium timebase dividend 1ns 1ns 01 01 11 Medium timebase divisor 8ns 8ns 08 08 12 Minimum SDRAM cycle time (tCKmin) 1.875ns 1.5ns 0F 0C 13 Reserved Undefined Undefined 00 00 14 CAS latencies supported 6,7,8 6,7,8,9 1C 3C 15 CAS latencies supported Undefined Undefined 00 00 16 Minimum CAS latency time (tAAmin) 13.125ns 13.125ns 69 69 17 Minimum write recovery time (tWRmin) 15ns 15ns 78 78 18 Minimum -to- delay (tRCDmin) 13.125ns 13.125ns 69 69 19 Minimum Row Active to Row Active delay (tRRDmin) 7.5ns 6ns 3C 30 20 Minimum row Precharge delay (tRPmin) 13.125ns 13.125ns 69 69 21 Upper nibble for tRAS and tRC 1,1 1,1 11 11 22 Minimum Active-to-Precharge delay (tRASmin) 37.5ns 36ns 2C 20 23 Minimum Active-to-Active/Refresh delay (tRCmin) 50.625ns 49.125ns 95 89 24 Minimum refresh recovery delay (tRFCmin) LSB (Combo bytes 24,25) (Combo bytes 24,25) 70 70 25 Minimum refresh recovery delay (tRFCmin) MSB 110ns 110ns 03 03 26 Minimum internal Write-to-Read command delay (tWTRmin) 7.5ns 7.5ns 3C 3C 27 Minimum internal Read-to-Precharge command delay (tRTPmin) 7.5ns 7.5ns 3C 3C 28 Minimum four active window delay (tFAWmin) LSB (Combo byte 28, 29) (Combo byte 28, 29) 01 00 29 Minimum four active window delay (tFAWmin) MSB 37.5ns 30ns 2C F0 30 SDRAM device output drivers suported RZQ / 6, RZQ / 7, DLL-Off Mode Support, RZQ / 6, RZQ / 7, DLL-Off Mode Support, 83 83 31 SDRAM device thermal and refresh options Extended Temperature Range, ASR, ODTS, PASR, Extended Temperature Range, ASR, ODTS, PASR, 8D 8D 32 Module Thermal Sensor Thermal Sensor Support Thermal Sensor Support 80 80 33 SDRAM Device Type Dual Die Package Dual Die Package 80 80 Undefined Undefined -- -- 34-59 Reserved 60 Module height (nominal) 29 height 30 mm 29 height 30 mm 0F 0F 61 Module thickness (Max) Back: 3 < thickness 4 mm, Front: 3 < thickness 4 mm, Back: 3 < thickness 4 mm, Front: 3 < thickness 4 mm, 33 33 62 Raw Card ID reference 63 DRAM address mapping edge connector 64-116 Reserved 117-118 Module manufacture ID 119-121 Module manufacturer Information 126-127 CRC REV 1.1 06/2009 Raw Card F Raw Card F 05 05 2 rows, 2 registers 2 rows, 2 registers 0A 0A Undefined Undefined -- -- Nanya Technology Nanya Technology 830B 830B Undefined Undefined -- -- Calculated Value Calculated Value 132C 5185 28 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GC72B89A0NL / NT2GC72B8PA0NL NT4GC72B4NA1NL / NT4GC72B8NA1NL / NT8GTC72B4NA1NL 1GB: 128M x 72 / 2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72 PC3-8500 / PC3-10600 Registered DDR3 SDRAM DIMM Serial Presence Detect (Part 2 of 2) [NT8GTC72B4NA1NL, 8GB - 4 Ranks, 512Mx4 DDR3 SDRAMs] SPD Entry Value Byte Serial PD Data Entry (Hex.) Description -BE -CG -BE -CG 128-145 Module part number ASCII values ASCII values -- -- 146 Module die revision Undefined Undefined 00 00 147 Module PCB revision Undefined Undefined 00 00 Nanya Technology Nanya Technology 830B 830B Manufacturer reserved Undefined Undefined -- -- Customer reserved Undefined Undefined -- -- 148-149 DRAM device manufacturer ID 150-175 176-255 Note1: NT8GTC72B4NA1NL-BE -> 4E5438475443373242344E41314E4C2D4245 NT8GTC72B4NA1NL-CG -> 4E5438475443373242344E41314E4C2D4347 REV 1.1 06/2009 29 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GC72B89A0NL / NT2GC72B8PA0NL NT4GC72B4NA1NL / NT4GC72B8NA1NL / NT8GTC72B4NA1NL 1GB: 128M x 72 / 2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72 PC3-8500 / PC3-10600 Registered DDR3 SDRAM DIMM Environmental Requirements Symbol Parameter Rating Units Note TOPR Module Operating Temperature Range (ambient) 0 to 55 C 3 HOPR Operating Humidity (relative) 10 to 90 % 1 TSTG Storage Temperature (Plastic) -55 to 100 C 1 HSTG Storage Humidity (without condensation) 5 to 95 % 1 PBAR Barometric Pressure (operating & storage) 105 to 69 K Pascal 1, 2 Note: 1. Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only and device functional operation at or above the conditions indicated is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Up to 9850 ft. 3. The component maximum case temperature shall not exceed the value specified in the component spec. Absolute Maximum DC Ratings Symbol VDD VDDQ VIN, VOUT TSTG Rating Units Note Voltage on VDD pins relative to Vss Parameter -0.4 V ~ 1.975 V V 1, 3 Voltage on VDDQ pins relative to Vss -0.4 V ~ 1.975 V V 1, 3 Voltage on I/O pins relative to Vss -0.4 V ~ 1.975 V V 1 -55 to +100 C 1, 2 Storage Temperature Note: 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability 2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. 3. VDD and VDDQ must be within 300 mV of each other at all times;and VREF must be not greater Operating temperature Conditions Symbol TOPER Parameter Rating Units Note Normal Operating Temperature Range 0 to 85 C 1, 2 Extended Temperature Range (Optional) 85 to 95 C 1, 3 Note: 1. Operating Temperature TOPER is the case surface temperature on the center / top side of the DRAM. 2. The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported. During operation, the DRAM case temperature must be maintained between 0 to 85 C under all operating conditions 3. Some applications require operation of the DRAM in the Extended Temperature Range between 85 C and 95 C case temperature. Full specifications are supported in this range, but the following additional conditions apply: a) Refresh commands must be doubled in frequency, therefore reducing the Refresh interval tREFI to 3.9 s. It is also possible to specify a component with 1X refresh (tREFI to 7.8s) in the Extended Temperature Range. Please refer to supplier data sheet and/or the DIMM SPD for option availability. b) If Self-Refresh operation is required in the Extended Temperature Range, then it is mandatory to either use the Manual Self-Refresh mode with Extended Temperature Range capability (MR2 A6 = 0b and MR2 A7 = 1b) or enable the optional Auto Self-Refresh mode (MR2 A6 = 1b and MR2 A7 = 0b). Please refer to the supplier data sheet and/or the DIMM SPD for Auto Self-Refresh option availability, Extended Temperature Range support and tREFI requirements in the Extended Temperature Range. REV 1.1 06/2009 30 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GC72B89A0NL / NT2GC72B8PA0NL NT4GC72B4NA1NL / NT4GC72B8NA1NL / NT8GTC72B4NA1NL 1GB: 128M x 72 / 2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72 PC3-8500 / PC3-10600 Registered DDR3 SDRAM DIMM DC Electrical Characteristics and Operating Conditions Symbol VDD VDDQ Parameter Min Typ Max Units Notes Supply Voltage 1.425 1.5 1.575 V 1,2 Output Supply Voltage 1.425 1.5 1.575 V 1,2 Note: 1. Under all conditions VDDQ must be less than or equal to VDD. 2. VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together. Single-Ended AC and DC Input Levels for Command and Address Symbol Parameter VIH.CA(DC) DC Input Logic High DDR3-1066 (-BE) DDR3-1333 (-CG) Units Note VDD V 1 Min. Max. Min. Max. Vref + 0.100 VDD Vref + 0.100 VIL.CA(DC) DC Input Logic Low VSS Vref - 0.100 VSS Vref - 0.100 V 1 VIH.CA(AC) AC Input Logic High Vref + 0.175 Note 2 Vref + 0.175 Note 2 V 1, 2 VIL.CA(AC) AC Input Logic Low Note 2 Vref - 0.175 Note 2 Vref - 0.175 V 1, 2 VIH.CA(AC150) AC Input Logic High - - Vref + 0.15 Note 2 V 1, 2 VIL.CA(AC150) AC Input Logic Low - - Note 2 Vref - 0.15 V 1, 2 0.49 x VDD 0.51 x VDD 0.49 x VDD 0.51 x VDD V 3, 4 VRefCA(DC) Reference Voltage for ADD, CMD Inputs Note: 1. For input only pins except . Vref = VrefCA(DC). 2. See "Overshoot and Undershoot Specifications" in the device datasheet. 3. The ac peak noise on VRef may not allow VRef to deviate from VRefDQ(DC) by more than +/-1% VDD (for reference: approx. +/- 15 mV). 4. For reference: approx. VDD/2 +/- 15 mV. Single-Ended AC and DC Input Levels for DQ and DM Symbol Parameter DDR3-1066 (-BE) Min. DDR3-1333 (-CG) Max. Min. Max. Units Note 1 VIH.DQ(DC) DC Input Logic High Vref + 0.100 VDD Vref + 0.100 VDD V VIL.DQ(DC) DC Input Logic Low VSS Vref - 0.100 VSS Vref - 0.100 V 1 VIH.DQ(AC) AC Input Logic High Vref + 0.175 Note 2 Vref + 0.15 Note 2 V 1, 2, 5 VIL.DQ(AC) AC Input Logic Low Note 2 Vref - 0.175 Note 2 Vref - 0.15 V 1, 2, 5 0.49 x VDD 0.51 x VDD 0.49 x VDD 0.51 x VDD V 3, 4 VRefDQ(DC) Reference Voltage for DQ, DM Inputs Note: 1. For input only pins except . Vref = VrefDQ(DC). 2. See "Overshoot and Undershoot Specifications" in the device datasheet. 3. The ac peak noise on VRef may not allow VRef to deviate from VRefDQ(DC) by more than +/-1% VDD (for reference: approx. +/- 15 mV). 4. For reference: approx. VDD/2 +/- 15 mV. 5. Single-ended swing requirement for DQS, DQS# is 350 mV (peak to peak). Differential swing requirement for DQS - DQS# is 700 mV (peak to peak). REV 1.1 06/2009 31 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GC72B89A0NL / NT2GC72B8PA0NL NT4GC72B4NA1NL / NT4GC72B8NA1NL / NT8GTC72B4NA1NL 1GB: 128M x 72 / 2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72 PC3-8500 / PC3-10600 Registered DDR3 SDRAM DIMM Operating, Standby, and Refresh Currents TCASE = 0 C ~ 85 C; VDDQ = VDD = 1.5V 0.075V [1GB - 1 Rank, 128Mx8 DDR3 SDRAMs] Symbol Parameter/Condition PC3-8500 PC3-10600 (-BE) (-CG) Unit IDD0 Operating One Bank Active-Precharge Current 743 842 mA IDD1 Operating One Bank Active-Read-Precharge Current 891 990 mA IDD2P0 Precharge Power-Down Current Slow Exit 139 139 mA IDD2P1 Precharge Power-Down Current Fast Exit 297 327 mA IDD2Q Precharge Quiet Standby Current 545 594 mA IDD2N Precharge Standby Current 446 495 mA IDD3P Active Power-Down Current 327 347 mA IDD3N Active Standby Current 545 644 mA IDD4R Operating Burst Read Current 1584 1980 mA IDD4W Operating Burst Write Current 1337 1683 mA IDD5B Burst Refresh Current 1782 2228 mA 119 119 mA 2178 2574 mA PC3-8500 PC3-10600 (-BE) (-CG) IDD6 Self Refresh Current: Normal Temperature Range IDD7 Operating Bank Interleave Read Current Operating, Standby, and Refresh Currents TCASE = 0 C ~ 85 C; VDDQ = VDD = 1.5V 0.075V [2GB - 2 Ranks, 128Mx8 DDR3 SDRAMs] Symbol Unit IDD0 Operating One Bank Active-Precharge Current 1287 1485 mA IDD1 Operating One Bank Active-Read-Precharge Current 1436 1634 mA IDD2P0 Precharge Power-Down Current Slow Exit 277 277 mA IDD2P1 Precharge Power-Down Current Fast Exit 594 653 mA IDD2Q Precharge Quiet Standby Current 1089 1188 mA IDD2N Precharge Standby Current 891 990 mA IDD3P Active Power-Down Current 653 693 mA IDD3N Active Standby Current 1089 1287 mA IDD4R Operating Burst Read Current 2129 2624 mA IDD4W Operating Burst Write Current 1881 2327 mA IDD5B Burst Refresh Current 2327 2871 mA IDD6 Self Refresh Current: Normal Temperature Range 238 238 mA IDD7 Operating Bank Interleave Read Current 2723 3218 mA REV 1.1 06/2009 Parameter/Condition 32 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GC72B89A0NL / NT2GC72B8PA0NL NT4GC72B4NA1NL / NT4GC72B8NA1NL / NT8GTC72B4NA1NL 1GB: 128M x 72 / 2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72 PC3-8500 / PC3-10600 Registered DDR3 SDRAM DIMM Operating, Standby, and Refresh Currents TCASE = 0 C ~ 85 C; VDDQ = VDD = 1.5V 0.075V [4GB - 4 Ranks, 128Mx8 DDR3 SDRAMs] Symbol Parameter/Condition PC3-8500 PC3-10600 (-BE) (-CG) Unit IDD0 Operating One Bank Active-Precharge Current 2376 2772 mA IDD1 Operating One Bank Active-Read-Precharge Current 2525 2921 mA IDD2P0 Precharge Power-Down Current Slow Exit 554 554 mA IDD2P1 Precharge Power-Down Current Fast Exit 1188 1307 mA IDD2Q Precharge Quiet Standby Current 2178 2376 mA IDD2N Precharge Standby Current 1782 1980 mA IDD3P Active Power-Down Current 1307 1386 mA IDD3N Active Standby Current 2178 2574 mA IDD4R Operating Burst Read Current 3218 3911 mA IDD4W Operating Burst Write Current 2970 3614 mA IDD5B Burst Refresh Current 3416 4158 mA IDD6 Self Refresh Current: Normal Temperature Range 475 475 mA IDD7 Operating Bank Interleave Read Current 3812 4505 mA PC3-8500 PC3-10600 (-BE) (-CG) Operating, Standby, and Refresh Currents TCASE = 0 C ~ 85 C; VDDQ = VDD = 1.5V 0.075V [4GB - 2 Ranks, 256Mx4 DDR3 SDRAMs] Symbol Unit IDD0 Operating One Bank Active-Precharge Current 2574 2970 mA IDD1 Operating One Bank Active-Read-Precharge Current 2871 3267 mA IDD2P0 Precharge Power-Down Current Slow Exit 554 554 mA IDD2P1 Precharge Power-Down Current Fast Exit 1188 1307 mA IDD2Q Precharge Quiet Standby Current 2178 2376 mA IDD2N Precharge Standby Current 1782 1980 mA IDD3P Active Power-Down Current 1307 1386 mA IDD3N Active Standby Current 2178 2574 mA IDD4R Operating Burst Read Current 4257 5247 mA IDD4W Operating Burst Write Current 3762 4653 mA IDD5B Burst Refresh Current 4653 5742 mA IDD6 Self Refresh Current: Normal Temperature Range 475 475 mA IDD7 Operating Bank Interleave Read Current 5049 6039 mA REV 1.1 06/2009 Parameter/Condition 33 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GC72B89A0NL / NT2GC72B8PA0NL NT4GC72B4NA1NL / NT4GC72B8NA1NL / NT8GTC72B4NA1NL 1GB: 128M x 72 / 2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72 PC3-8500 / PC3-10600 Registered DDR3 SDRAM DIMM Operating, Standby, and Refresh Currents TCASE = 0 C ~ 85 C; VDDQ = VDD = 1.5V 0.075V [8GB - 4 Ranks, 512Mx4 (DDP) DDR3 SDRAMs] Symbol PC3-8500 PC3-10600 (-BE) (-CG) Unit IDD0 Operating One Bank Active-Precharge Current 4752 5544 mA IDD1 Operating One Bank Active-Read-Precharge Current 5049 5841 mA IDD2P0 Precharge Power-Down Current Slow Exit 1109 1109 mA IDD2P1 Precharge Power-Down Current Fast Exit 2376 2614 mA IDD2Q Precharge Quiet Standby Current 4356 4752 mA IDD2N Precharge Standby Current 3564 3960 mA IDD3P Active Power-Down Current 2614 2772 mA IDD3N Active Standby Current 4356 5148 mA IDD4R Operating Burst Read Current 6435 7821 mA IDD4W Operating Burst Write Current 5940 7227 mA IDD5B Burst Refresh Current 6831 8316 mA IDD6 Self Refresh Current: Normal Temperature Range 950 950 mA IDD7 Operating Bank Interleave Read Current 7227 8613 mA REV 1.1 06/2009 Parameter/Condition 34 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GC72B89A0NL / NT2GC72B8PA0NL NT4GC72B4NA1NL / NT4GC72B8NA1NL / NT8GTC72B4NA1NL 1GB: 128M x 72 / 2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72 PC3-8500 / PC3-10600 Registered DDR3 SDRAM DIMM Speed Bins Speed Bin CL-nRCD-nRP Parameter Symbol Internal read command to first data tAA ACT to internal read or write delay tRCD PRE command period tRP ACT to ACT or REF command period tRC ACT to PRE command period tRAS CL CWL 5 tCK(avg) 6 6 tCK(avg) 7,8 tCK(avg) 5 tCK(avg) 7 6 tCK(avg) 7,8 tCK(avg) 5 tCK(avg) 8 6 tCK(avg) 7 tCK(avg) 5,6 tCK(avg) 9 7 tCK(avg) 8 tCK(avg) Supported CL settings Supported CWL settings REV 1.1 06/2009 DDR3-1066 (-BE) 7-7-7 min max 13.125 20 13.125 13.125 50.625 37.5 9*tREFI DDR3-1333 (-CG) 9-9-9 min max 13.5 20 13.5 13.5 49.5 36 9*tREFI 2.5 3.3 Reserved Reserved Reserved 1.875 <2.5 Reserved Reserved 1.875 <2.5 Reserved Reserved Reserved Reserved 6,7,8 5,6 2.5 3.3 Reserved Reserved Reserved Reserved Reserved Reserved 1.875 <2.5 Reserved Reserved 1.5 <1.875 Reserved 6,8,9 5,6,7 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns nCK nCK 35 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GC72B89A0NL / NT2GC72B8PA0NL NT4GC72B4NA1NL / NT4GC72B8NA1NL / NT8GTC72B4NA1NL 1GB: 128M x 72 / 2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72 PC3-8500 / PC3-10600 Registered DDR3 SDRAM DIMM AC Timing Specifications for DDR3 SDRAM Devices Used on Module Symbol Clock Timing tCK(DLL_OF tCK(avg) tCH(avg) tCL(avg) tCK(abs) tCH(abs) tCL(abs) JIT(per) tJIT(per,lck) tJIT(cc) tJIT(cc,lck) tERR(2per) tERR(3per) tERR(4per) tERR(5per) tERR(6per) tERR(7per) tERR(8per) tERR(9per) tERR(10per) tERR(11per) tERR(12per) DDR3-1066 (-BE) min max Parameter Minimum Clock Cycle Time (DLL off mode) Average Clock Period(Refer to "Standard Speed Average high pulse width Average low pulse width Absolute Clock Period Absolute high pulse width Absolute low pulse width Clock Period Jitter Clock Period Jitter during DLL locking period Cycle to Clcyle Period Jitter Cycle to Cycle Period Jitter Cumulative error accross 2 cycles Cumulative error accross 3 cycles Cumulative error accross 4cycles Cumulative error accross 5cycles Cumulative error accross 6 cycles Cumulative error accross 7 cycles Cumulative error accross 8 cycles Cumulative error accross 9 cycles Cumulative error accross 10 cycles Cumulative error accross 11 cycles Cumulative error accross 12 cycles tERR(nper) Cumulative error accross n=13,14,..,49,50 cycles Data Timing tDQSQ tQH tLZ(DQ) tHZ(DQ) DQS, DQS to DQ skew per group, per access DQ output hold time from DQS, DQS DQ low-impedence time from CK / DQ high-impedence time from CK / Data Setup time to DQS, DQS referenced to tDS(base) Vih(ac)/ Vil(ac) levels Data Hold time to DQS, DQS referenced to Vih(dc)/ tDH(base) Vil(dc) levels Data Strobe Timing tRPRE DQS, DQS differential READ Preamble tRPST DQS, DQS differential READ Postamble tQSH DQS, DQS differential output high time tQSL DQS, DQS differential output low time tWPRE DQS, DQS differential WRITE Preamble tWPST DQS, DQS differential WRITE Postamble DQS, DQS rising edge output access time from tDQSCK rising CK, tLZ(DQS) DQS, DQS low-impedance time (Referenced from DQS, DQS high-impedance time (Referenced from tHZ(DQS) RL+BL/2) tDQSL DQS, DQS differential input low pulse width tDQSH DQS, DQS differential input high pulse width tDQSS DQS, DQS rising edge to CK, rising edge DQS, DQS falling edge setup time to CK, rising tDSS edge tDSH DQS, DQS falling edge hold time to CK, rising REV 1.1 06/2009 8 - 0.47 0.53 0.47 0.53 tCK(avg)min tCK(avg)ma + x+ tJIT(per)min tJIT(per)ma 0.43 0.43 -90 90 -80 80 180 160 -132 132 -157 157 -175 175 -188 188 -200 200 -209 209 -217 217 -224 224 -231 231 -237 237 -242 242 tERR(npr)mi tERR(npr)m n = (1+ ax = (1+ 0.68In(n)) * 0.68In(n)) * tJIT(per)min tJIT(per)ma 0.38 -600 - 150 300 300 DDR3-1333 (-CG) min max 8 - 0.47 0.53 0.47 0.53 tCK(avg)min tCK(avg)ma + x+ tJIT(per)min tJIT(per)ma 0.43 0.43 -80 80 -70 70 160 140 -118 118 -140 140 -155 155 -168 168 -177 177 -186 186 -193 193 -200 200 -205 205 -210 210 -215 215 tERR(npr)mi tERR(npr)m n = (1+ ax = (1+ 0.68In(n)) * 0.68In(n)) * tJIT(per)min tJIT(per)ma 0.38 -500 - 125 250 250 Unit ns tCK(avg) tCK(avg) ps tCK(avg) tCK(avg) ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps tCK(avg) ps ps 25 30 ps 100 65 ps 0.9 0.3 0.38 0.38 0.9 0.3 - 0.9 0.3 0.4 0.4 0.9 0.3 - tCK(avg) tCK(avg) tCK(avg) tCK(avg) tCK(avg) tCK(avg) -300 300 -255 255 ps -600 300 -500 250 ps - 300 - 250 ps 0.45 0.45 -0.25 0.55 0.55 0.25 0.45 0.45 -0.25 0.55 0.55 0.25 tCK(avg) tCK(avg) tCK(avg) 0.2 - 0.2 - tCK(avg) 0.2 - 0.2 - tCK(avg) 36 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GC72B89A0NL / NT2GC72B8PA0NL NT4GC72B4NA1NL / NT4GC72B8NA1NL / NT8GTC72B4NA1NL 1GB: 128M x 72 / 2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72 PC3-8500 / PC3-10600 Registered DDR3 SDRAM DIMM Symbol DDR3-1066 (-BE) min max Parameter Command and Address Timing tDLLK DLL Locking time Internal READ command to PRECHARGE tRTP Command delay Delay from start of internal write transaction to tWTR internal read command tWR WRITE recovery time tMRD Mode Register Set command cycle time tMOD Mode Register Set command update delay tCCD CAS to CAS command delay tDAL 512 max(4nCK, 7.5ns) max(4nCK, 7.5ns) 15 4 max(12nCK, 15ns) 4 - WR + roundup (tRP/tCK(avg)) Auto Precharge write recovery + precharge time tMPRR End of MPR Read burst to MSR for MPR (exit) ACTIVE to ACTIVE command period (1k page size tRRD -x4/x8) ACTIVE to ACTIVE command period (2k page size tRRD -x16) tFAW Four activate window (1k page size - x4/x8) tFAW Four activate window (2k page size - x16) Command and Address setup time to CK, tIS(base) referenced Vih(ac) / Vil(ac) levels Command and Address hold time from CK, tIH(base) referenced Vih(ac) / Vil(ac) levels tIS(base) Commad and Address setup time to CK, AC150 referenced to Vih(ac) / Vil(ac) levels Calibration Timing tZQinit Power-up and RESET calibration time tZQoper Normal operation Full calibration time tZQCS normal operation Short calibration time Reset Timing tXPR - Exit Reset from CKE HIGH to a valid command 1 max(4nCK, 7.5ns) max(4nCK, 10ns) 37.5 50 - DDR3-1333 (-CG) min max 512 max(4nCK, 7.5ns) max(4nCK, 7.5ns) 15 4 max(12nCK, 15ns) 4 - Unit nCK - ns nCK - nCK WR + roundup (tRP/tCK(avg)) nCK 1 max(4nCK, 6ns) max(4nCK, 7.5ns) 30 45 - nCK 0 0 ns ns 125 65 ps 200 140 ps ps - - 65+125 512 256 64 - 512 256 64 - max(5nCK, tRFC(min) +10ns) - max(5nCK, tRFC(min) +10ns) - nCK nCK nCK Self RefreshTimings max(5nCK, tRFC(min) +10ns) tXSDLL Exit Self Refresh to Commands requiring a locked tDLLK(min) Minimum CKE low width for Self Refresh entry to tCKE(min)+ tCKESR exit timing 1nCK Valid Clock Requirement after Self Refresh Entry max(5nCK, tCKSRE (SRE) or Power Down Entry (PDE) 10ns) Valid Clock Requirement before Self Refresh max(5nCK, tCKSRX Exit(SRX) or Power-Down Exit (PDX) or Reset Exit 10ns) Power Down Timings Exit Power Down with DLL on to any valid max(3nCK, tXP command; Exit Precharge Power Down with DLL 7.5ns) frozen to commands not requiring a locked DLL Exit Precharge Power Down with DLL frozen to max(10nCK, tXPDLL commands requiring a locked DLL 24ns) max(3nCK, tCKE CKE minimm pulse width 5.625ns) tCPDED Command Pass disable delay 1 tPD Power Down Entry to Exit Timing tCKE(min) tACTPDEN Timing of ACT command to Power Down entry 1 tPRPDEN Timing of PRE or PREA command to Power Down 1 tRDPDEN Timing of RD/RDA command to Power Down entry RL + 4 + 1 tXS REV 1.1 06/2009 Exit Self Refresh to Commands not requiring a locked DLL - 9tREFI - max(5nCK, tRFC(min) +10ns) tDLLK(min) tCKE(min)+ 1nCK max(5nCK, 10ns) max(5nCK, 10ns) max(3nCK, 6ns) max(10nCK, 24ns) max(3nCK, 5.625ns) 1 tCKE(min) 1 1 RL + 4 + 1 - nCK - 9tREFI - nCK nCK nCK nCK 37 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GC72B89A0NL / NT2GC72B8PA0NL NT4GC72B4NA1NL / NT4GC72B8NA1NL / NT8GTC72B4NA1NL 1GB: 128M x 72 / 2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72 PC3-8500 / PC3-10600 Registered DDR3 SDRAM DIMM Symbol tWRPDEN tWRAPDEN tWRPDEN Parameter Timing of WR command to Power Down entry (BL8OTF, BL8MRS, BC4OTF) Timing of WRA command to Power Down entry (BL8OTF, BL8MRS, BC4OTF) Timing of WR command to Power Down entry (BC4MRS) Timing of WRA command to Power Down entry (BC4MRS) tREFPDEN Timing of REF command to Power Down entry tMRSPDEN Timing of MRS command to Power Down entry ODT Timings ODT high time without write command or with write tODTH4 command and BC4 tODTH8 ODT high time without write command oand BL8 Asynchronous RTT turn-on delay (Power-Down with tAONPD DLL frozen) Asynchronous RTT turn-off delay (Power Down with tAOFPD DLL frozen) tAON RTT turn-on RTT_NOM and RTT_WR turn-off time from tAOF ODTLoff reference tADC RTT dynamic change skew Write Leveling Timings First DQS/DQS rising edge after write leveling mode tWLMRD is programmed tWLDQSEN DQS/DQS delay after write leveling mode is Write leveling setup time from rising CK, CK tWLS crossing to rising DQS, DQS crossing Write leveling hold time from rising DQS, DQS tWLH crossing to rising CK, CK crossing tWLO Write leveling output delay tWLOE Write levleing output error tRFC REF command to ACT or REF command time tREFI Average period refresh interval (0CtCASE85C) tREFI Average period refresh interval (85C<tCASE95C) tWRAPDEN REV 1.1 06/2009 DDR3-1066 (-BE) min max WL + 4 + (tWR/tCK(av g)) WL + 4 + WR + 1 WL + 2 + (tWR/tCK(av g)) WL + 2 + WR + 1 1 tMOD(min) - DDR3-1333 (-CG) min max WL + 4 + (tWR/tCK(av g)) WL + 4 + WR + 1 WL + 2 + (tWR/tCK(av g)) WL + 2 + WR + 1 1 tMOD(min) - Unit nCK nCK nCK nCK nCK 4 - 4 - nCK 6 - 6 - nCK 1 9 1 9 ns 1 9 1 9 ns -300 300 -250 250 ps 0.3 0.7 0.3 0.7 tCK(avg) 0.3 0.7 0.3 0.7 tCK(avg) 40 - 40 - nCK 25 - 25 - nCK 245 - 195 - ps 245 - 195 - ps 0 0 9 2 0 0 9 2 ns ns ns us us 110 7.8 3.9 110 7.8 3.9 38 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GC72B89A0NL / NT2GC72B8PA0NL NT4GC72B4NA1NL / NT4GC72B8NA1NL / NT8GTC72B4NA1NL 1GB: 128M x 72 / 2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72 PC3-8500 / PC3-10600 Registered DDR3 SDRAM DIMM Package Dimensions [1GB - 1 Rank, 128Mx8 DDR3 SDRAMs] FRONT 133.35 +/- 0.15 3.0 (x4) Registering Clock Driver 9.50 17.30 SPD/TS 4.00 Max. Detail B Detail A 5.175 30.00 +0.5/-0.15 SIDE 47.00 71.00 5.00 1.27 +0.07/-0.10 BACK 2.50 Detail B 4.00 3.80 Detail A 0.80 +/- 0.05 1.00 Pitch 1.50 +/- 0.10 Units: Millimeters Note: Device position and scale are only for reference. REV 1.1 06/2009 39 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GC72B89A0NL / NT2GC72B8PA0NL NT4GC72B4NA1NL / NT4GC72B8NA1NL / NT8GTC72B4NA1NL 1GB: 128M x 72 / 2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72 PC3-8500 / PC3-10600 Registered DDR3 SDRAM DIMM Package Dimensions [2GB - 2 Ranks, 128Mx8 DDR3 SDRAMs] FRONT 133.35 +/- 0.15 3.0 (x4) Registering Clock Driver 9.50 17.30 SPD/TS 4.00 Max. Detail B Detail A 5.175 30.00 +0.5/-0.15 SIDE 47.00 71.00 5.00 1.27 +0.07/-0.10 BACK 2.50 Detail B 4.00 3.80 Detail A 0.80 +/- 0.05 1.00 Pitch 1.50 +/- 0.10 Units: Millimeters Note: Device position and scale are only for reference. REV 1.1 06/2009 40 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GC72B89A0NL / NT2GC72B8PA0NL NT4GC72B4NA1NL / NT4GC72B8NA1NL / NT8GTC72B4NA1NL 1GB: 128M x 72 / 2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72 PC3-8500 / PC3-10600 Registered DDR3 SDRAM DIMM Package Dimensions [4GB - 2 Ranks, 256Mx4 DDR3 SDRAMs] FRONT 133.75 +/- 0.25 Max 8.5 Detail B Detail A 5.175 30.60 +/- 0.15 17.30 9.50 3.0 (x4) SIDE 47.00 71.00 5.00 1.27 +0.07/-0.10 REAR 2.50 Detail B 4.00 3.80 Detail A 0.80 +/- 0.05 1.00 Pitch 1.50 +/- 0.10 Units: Millimeters Note: Device position and scale are only for reference. REV 1.1 06/2009 41 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GC72B89A0NL / NT2GC72B8PA0NL NT4GC72B4NA1NL / NT4GC72B8NA1NL / NT8GTC72B4NA1NL 1GB: 128M x 72 / 2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72 PC3-8500 / PC3-10600 Registered DDR3 SDRAM DIMM Package Dimensions [4GB - 4 Ranks, 128Mx8 DDR3 SDRAMs] FRONT 133.75 +/- 0.25 Max 8.5 Detail B Detail A 5.175 30.60 +/- 0.15 17.30 9.50 3.0 (x4) SIDE 47.00 71.00 5.00 1.27 +0.07/-0.10 REAR 2.50 Detail B 4.00 3.80 Detail A 0.80 +/- 0.05 1.00 Pitch 1.50 +/- 0.10 Units: Millimeters Note: Device position and scale are only for reference. REV 1.1 06/2009 42 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GC72B89A0NL / NT2GC72B8PA0NL NT4GC72B4NA1NL / NT4GC72B8NA1NL / NT8GTC72B4NA1NL 1GB: 128M x 72 / 2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72 PC3-8500 / PC3-10600 Registered DDR3 SDRAM DIMM Package Dimensions [8GB - 4 Ranks, 512Mx4 (DDP) DDR3 SDRAMs] FRONT 133.75 +/- 0.25 Max 8.5 Detail B Detail A 5.175 30.60 +/- 0.15 17.30 9.50 3.0 (x4) SIDE 47.00 71.00 5.00 1.27 +0.07/-0.10 REAR 2.50 Detail B 4.00 3.80 Detail A 0.80 +/- 0.05 1.00 Pitch 1.50 +/- 0.10 Units: Millimeters Note: Device position and scale are only for reference. REV 1.1 06/2009 43 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GC72B89A0NL / NT2GC72B8PA0NL NT4GC72B4NA1NL / NT4GC72B8NA1NL / NT8GTC72B4NA1NL 1GB: 128M x 72 / 2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72 PC3-8500 / PC3-10600 Registered DDR3 SDRAM DIMM Revision Log Rev Date Modification 0.1 07/2008 Preliminary Release 1.0 09/2008 Official Release 1.1 06/2009 4GB 4Rank x8, IDD, and SPD update Nanya Technology Corporation Hwa Ya Technology Park 669 Fu Hsing 3rd Rd., Kueishan, Taoyuan, 333, Taiwan, R.O.C. Tel: +886-3-328-1688 Please visit our home page for more information: www.nanya.com Printed in Taiwan (c) 2009 REV 1.1 06/2009 44 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice.