NT1GC72B89A0NL / NT2GC72B8PA0NL
NT4GC72B4NA1NL / NT4GC72B8NA1NL / NT8GTC72B4NA1NL
1GB: 128M x 72 / 2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72
PC3-8500 / PC3-10600
Registered DDR3 SDRAM DIMM
REV 1.1 1
06/2009
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
Based on DDR3-1066/1333 128Mx8 (1GB/2GB/4GB) / 256Mx4 (4GB) / 512Mx4 (DDP) (8GB) SDRAM A-Die
Features
•Performance:
Speed Sort
PC3-8500
PC3-10600
Unit
-BE
-CG
DIMM CAS Latency
7
9
fck – Clock Frequency
533
667
MHz
tck – Clock Cycle
1.875
1.5
ns
fDQ – DQ Burst Frequency
1066
1333
Mbps
• 240-Pin Registered Dual In-Line Memory Module (RDIMM)
• 1GB/2GB/4GB: 128Mx72/256Mx72/512Mx72 DDR3 Registered
DIMM based on 128Mx8 DDR3 SDRAM A-Die devices.
• 4GB: 512Mx72 DDR3 Registered DIMM based on 256Mx4 DDR3
SDRAM A-Die devices.
• 8GB: 1Gx72 DDR3 Registered DIMM based on 512Mx4 (DDP)
DDR3 SDRAM A-Die devices.
• Intended for 533MHz/667MHz applications
• Inputs and outputs are SSTL-15 compatible
• VDD = VDDQ = 1.5V ±0.075V
• SDRAMs have 8 internal banks for concurrent operation
• Differential clock inputs
• Data is read or written on both clock edges
• DRAM DLL aligns DQ and DQS transitions with clock transitions.
• Address and control signals are fully synchronous to positive
clock edge
• Nominal and Dynamtic On-Die Termination support
• Programmable Operation:
- DIMM Latency: 6,7,8,9
- Burst Type: Sequential or Interleave
- Burst Length: BC4, BL8
- Operation: Burst Read and Write
• Two different termination values (Rtt_Nom & Rtt_WR)
• 14/10/1 (row/column/rank) Addressing for 1GB
• 14/10/2 (row/column/rank) Addressing for 2GB
• 14/10/4 (row/column/rank) Addressing for 4GB (128Mx8 Device)
• 14/11/2 (row/column/rank) Addressing for 4GB (256Mx4 Device)
• 14/11/4 (row/column/rank) Addressing for 8GB
• Extended operating temperature rage
• Auto Self-Refresh option
• Serial Presence Detect
• Gold contacts
• SDRAMs are in 78-ball BGA Package
• RoHS compliance
• Halogen free product
Description
NT1GC72B89A0NL, NT2GC72B8PA0NL, NT4GC72B8NA1NL, NT4GC72B4NA1NL and NT8GTC72B4NA1NL are 240-Pin Double Data
Rate 3 (DDR3) Synchronous DRAM Registered Dual In-Line Memory Module, organized as one rank of 128Mx72 (1GB), two ranks of
256Mx72 (2GB), two or four ranks of 512Mx72 (4GB) and four ranks of 1Gx72 (8GB) high-speed memory array. Modules use nine 128Mx8
(1GB) 78-ball BGA packaged devices, eighteen 128Mx8 (2GB) 78-ball BGA packaged devices, thirty-six 256Mx4 (4GB) 78-ball BGA
packaged devices and thirty-six 512Mx4 (DDP) (8GB) 78-ball BGA packaged devices. These DIMMs are manufactured using raw cards
developed for broad industry use as reference designs. The use of these common design files minimizes electrical variation between
suppliers. All NANYA DDR3 SDRAM DIMMs provide a high-performance, flexible 8-byte interface in a 5.25” long space-saving footprint.
The DIMM is intended for use in applications operating of 533MHz/667MHz clock speeds and achieves high-speed data transfer rates of
1066Mbps/1333Mbps. Prior to any access operation, the device latency and burst/length/operation type must be programmed into the
DIMM by address inputs A0-A13 and I/O inputs BA0~BA2 using the mode register set cycle.
The DIMM uses serial presence-detect implemented via a serial EEPROM using a standard IIC protocol. The first 128 bytes of SPD data
are programmed and locked during module assembly. The remaining 128 bytes are available for use by the customer.
NT1GC72B89A0NL / NT2GC72B8PA0NL
NT4GC72B4NA1NL / NT4GC72B8NA1NL / NT8GTC72B4NA1NL
1GB: 128M x 72 / 2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72
PC3-8500 / PC3-10600
Registered DDR3 SDRAM DIMM
REV 1.1 2
06/2009
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
Ordering Information
Part Number
Speed
Organization
Power
Leads
Note
NT1GC72B89A0NL-BE
DDR3-1066
PC3-8500
533MHz (1.875ns @ CL = 7)
128Mx72
1.5V
Gold
NT1GC72B89A0NL-CG
DDR3-1333
PC3-10600
667MHz (1.5ns @ CL = 9)
NT2GC72B8PA0NL-BE
DDR3-1066
PC3-8500
533MHz (1.875ns @ CL = 7)
256Mx72
NT2GC72B8PA0NL-CG
DDR3-1333
PC3-10600
667MHz (1.5ns @ CL = 9)
NT4GC72B4NA1NL-BE
DDR3-1066
PC3-8500
533MHz (1.875ns @ CL = 7)
512Mx72
NT4GC72B4NA1NL-CG
DDR3-1333
PC3-10600
667MHz (1.5ns @ CL = 9)
NT4GC72B8NA1NL-BE
DDR3-1066
PC3-8500
533MHz (1.875ns @ CL = 7)
NT4GC72B8NA1NL-CG
DDR3-1333
PC3-10600
667MHz (1.5ns @ CL = 9)
NT8GTC72B4NA1NL-BE
DDR3-1066
PC3-8500
533MHz (1.875ns @ CL = 7)
1Gx72
NT8GTC72B4NA1NL-CG
DDR3-1333
PC3-10600
667MHz (1.5ns @ CL = 9)
Pin Description
Pin Name
Description
Pin Name
Description
CK0, CK1
Clock Inputs, positive line
ODT0, ODT1
Active termination control lines
,
Clock Inputs, negative line
DQ0-DQ63
Data input/output
CKE0, CKE1
Clock Enable
DQS0-DQS17
Data strobes
Row Address Strobe
-
Data strobes complement
Column Address Strobe
TDQS9-TDQS17
Termination data strobes
Write Enable
-
Termination data strobes
-
Chip Selects
DM0-DM8
Data Masks
A0-A9, A11, A13
Address Inputs
CB0-CB7
ECC Check Bits
A10/AP
Address Input/Auto-Precharge
Temperature event pin
A12/
Address Input/Burst Chop
Reset pin
BA0-BA2
SDRAM Bank Address Inputs
VREFDQ , VREFCA
Input/Output Reference
SCL
Serial Presence Detect Clock Input
VDDSPD
SPD and Temp sensor power
SDA
Serial Presence Detect Data input/output
SA0, SA1, SA2
Serial Presence Detect Address Inputs
Par_In
Parity bit for the Address and Control bus
Vtt
Termination voltage
Parity error found on the Address and Control bus
VSS
Ground
NC
No Connect
VDD
Core and I/O power
NT1GC72B89A0NL / NT2GC72B8PA0NL
NT4GC72B4NA1NL / NT4GC72B8NA1NL / NT8GTC72B4NA1NL
1GB: 128M x 72 / 2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72
PC3-8500 / PC3-10600
Registered DDR3 SDRAM DIMM
REV 1.1 3
06/2009
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
DDR3 SDRAM Pin Assignment
Pin
Front
Pin
Back
Pin
Front
Pin
Back
Pin
Front
Pin
Back
Pin
Front
Pin
Back
1
VREFDQ
121
VSS
31
DQ25
151
VSS
61
A2
181
A1
91
DQ41
211
VSS
2
VSS
122
DQ4
32
VSS
152
DM3/DQS12
/TDQS12
62
VDD
182
VDD
92
VSS
212
DM5/DQS14
/TDQS14
3
DQ0
123
DQ5
33
153
NC/
/
63
NC
183
VDD
93
213
NC/
/
4
DQ1
124
VSS
34
DQS3
154
VSS
64
NC
184
CK0
94
DQS5
214
VSS
5
VSS
125
DM0/DQS9/
TDQS9
35
VSS
155
DQ30
65
VDD
185
95
VSS
215
DQ46
6
126
NC/
/
36
DQ26
156
DQ31
66
VDD
186
VDD
96
DQ42
216
DQ47
7
DQS0
127
VSS
37
DQ27
157
VSS
67
VREFCA
187
97
DQ43
217
VSS
8
VSS
128
DQ6
38
VSS
158
CB4
68
Par_In/NC
188
A0
98
VSS
218
DQ52
9
DQ2
129
DQ7
39
CB0
159
CB5
69
VDD
189
VDD
99
DQ48
219
DQ53
10
DQ3
130
VSS
40
CB1
160
VSS
70
A10/AP
190
BA1
100
DQ49
220
VSS
11
VSS
131
DQ12
41
VSS
161
DM8/DQS17
/TDQS17
71
BA0
191
VDD
101
VSS
221
DM6/DQS15
/TDQS15
12
DQ8
132
DQ13
42
162
NC/
/
72
VDD
192
102
222
NC/
/
13
DQ9
133
VSS
43
DQS8
163
VSS
73
193
103
DQS6
223
VSS
14
VSS
134
DM1/DQS10
/TDQS10
44
VSS
164
CB6
74
194
VDD
104
VSS
224
DQ54
15
135
NC/
/
45
CB2
165
CB7
75
VDD
195
ODT0
105
DQ50
225
DQ55
16
DQS1
136
VSS
46
CB3
166
VSS
76
/NC
196
A13
106
DQ51
226
VSS
17
VSS
137
DQ14
47
VSS
167
NC
77
ODT1/NC
197
VDD
107
VSS
227
DQ60
18
DQ10
138
DQ15
48
VTT/NC
168
78
VDD
198
/NC
108
DQ56
228
DQ61
19
DQ11
139
VSS
49
VTT/NC
169
CKE1/NC
79
/NC
199
VSS
109
DQ57
229
VSS
20
VSS
140
DQ20
50
CKE0
170
VDD
80
VSS
200
DQ36
110
VSS
230
DM7/DQS16
/TDQS16
21
DQ16
141
DQ21
51
VDD
171
NC
81
DQ32
201
DQ37
111
231
NC/
/
22
DQ17
142
VSS
52
BA2
172
NC
82
DQ33
202
VSS
112
DQS7
232
VSS
23
VSS
143
DM2/DQS11
/TDQS11
53
/NC
173
VDD
83
VSS
203
DM4/DQS13
/TDQS13
113
VSS
233
DQ62
24
144
NC/
/
54
VDD
174
A12/
84
204
NC/
/
114
DQ58
234
DQ63
25
DQS2
145
VSS
55
A11
175
A9
85
DQS4
205
VSS
115
DQ59
235
VSS
26
VSS
146
DQ22
56
A7
176
VDD
86
VSS
206
DQ38
116
VSS
236
VDDSPD
27
DQ18
147
DQ23
57
VDD
177
A8
87
DQ34
207
DQ39
117
SA0
237
SA1
28
DQ19
148
VSS
58
A5
178
A6
88
DQ35
208
VSS
118
SCL
238
SDA
29
VSS
149
DQ28
59
A4
179
VDD
89
VSS
209
DQ44
119
SA2
239
VSS
30
DQ24
150
DQ29
60
VDD
180
A3
90
DQ40
210
DQ45
120
VTT
240
VTT
Note: 1. CKE1, and ODT1 are for 2GB/4GB/8GB only.
2. and are for 8GB only.
3. TDQS9-TDQS17 and - are for 1GB/2GB only.
NT1GC72B89A0NL / NT2GC72B8PA0NL
NT4GC72B4NA1NL / NT4GC72B8NA1NL / NT8GTC72B4NA1NL
1GB: 128M x 72 / 2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72
PC3-8500 / PC3-10600
Registered DDR3 SDRAM DIMM
REV 1.1 4
06/2009
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
Input/Output Functional Description
Symbol
Type
Polarity
Function
CK0, CK1
,
Input
Cross
point
The system clock inputs. All address and command lines are sampled on the cross point of the
rising edge of CK and falling edge of . A Delay Locked Loop (DLL) circuit is driven from the
clock inputs and output timing for read operations is synchronized to the input clock. However,
CK1 and are terminated but not used on RDIMMs.
CKE0, CKE1
Input
Active
High
Activates the DDR3 SDRAM CK signal when high and deactivates the CK signal when low. By
deactivating the clocks, CKE low initiates the Power Down mode or the Self Refresh mode.
–
Input
Active
Low
Enable the command decoders for the associated rank of SDRAM when low and disables
decoders when high. When decoders are disabled, new commands are ignored and previous
operations continue. Other combinations of these input signals perform unique functions,
including disabling all outputs (except CKE and ODT) of the register(s) on the DIMM or accessing
internal control words in the register device(s). For modules with two registers, and operate
similarly to and for the second set of register outputs or register control words.
, ,
Input
Active
Low
When sampled at the positive rising edge of CK and falling edge of , signals , ,
define the operation to be executed by the SDRAM.
ODT0, ODT1
Input
Active
High
Asserts on-die termination for DQ, DM, DQS, and signals if enabled via the DDR3 SDRAM
mode register.
DM0 – DM8
Input
Active
High
The data write masks, associated with one data byte. In Write mode, DM operates as a byte mask
by allowing input data to be written if it is low but blocks the write operation if it is high. In Read
mode, DM lines have no effect.
DQS0 – DQS17
–
I/O
Cross
point
The data strobes, associated with one data byte, sourced with data transfers. In Write mode, the
data strobe is sourced by the controller and is centered in the data window. In Read mode, the
data strobe is sourced by the DDR3 SDRAM and is sent at the leading edge of the data window.
signals are complements, and timing is relative to the cross point of respective DQS and
. If the module is to be operated in single ended strobe mode, all signals must be tied on
the system board to VSS and DDR3 SDRAM mode registers programmed appropriately.
TDQS9 – TDQS17
–
Output
TDQS/ is applicable for x8 DRAMs only. When enabled via mode register A11=1 in MR1,
DRAM will enable the same termination resistance function on TDQS/ that is applied to
DQS/. When disabled via mode register A11=0 in MR1, DM/TDQS will provide the data
mask function is not used. X4/x16 DRAMs must disable the TDQS function via mode
register A11=0 in MR1.
BA0, BA1, BA2
Input
-
Selects which DDR3 SDRAM internal bank of four or eight is activated.
A0 – A9
A10/AP
A11
A12/
A13
Input
-
During a Bank Activate command cycle, defines the row address when sampled at the cross point
of the rising edge of CK and falling edge of . During a Read or Write command cycle, defines
the column address when sampled at the cross point of the rising edge of CK and falling edge of
. In addition to the column address, AP is used to invoke autoprecharge operation at the end of
the burst read or write cycle. If AP is high, autoprecharge is selected and BA0-BAn defines the
bank to be precharged. If AP is low, autoprecharge is disabled. During a Precharge command
cycle, AP is used in conjunction with BA0-BAn to control which bank(s) to precharge. If AP is
high, all banks will be precharged regardless of the state of BA0-BAn inputs. If AP is low, then
BA0-BAn are used to define which bank to precharge.
DQ0 – DQ63
Input
-
Data Input/Output pins.
CB0 – CB7
I/O
-
Check bits are used for ECC.
VDD, VDDSPD, VSS
Supply
-
Power supplies for core, I/O, Serial Presence Detect, Temp sensor, and ground for the module.
VREFDQ, VREFCA
Supply
-
Reference voltage for SSTL15 inputs.
SDA
I/O
-
This is a bidirectional pin used to transfer data into or out of the SPD EEPROM and temp sensor.
A resistor must be connected from the SDA bus line to VDDSPD on the system planar to act as a pull
up.
SCL
Input
-
This signal is used to clock data into and out of the SPD EEPROM and Temp sensor.
SA0 – SA2
Input
-
Address pins used to select the Serial Presence Detect and Temp sensor base address.
Output
-
The pin is reserved for use to flag critical module temperature.
Input
-
This signal resets the DDR3 SDRAM.
Par_In
Input
-
Parity bit for the Address and Control bus.
Output
-
Parity error detected on the Address and Control bus. A resistor may be connected from bus line
to VDD on the system planar to act as a pull up.
NT1GC72B89A0NL / NT2GC72B8PA0NL
NT4GC72B4NA1NL / NT4GC72B8NA1NL / NT8GTC72B4NA1NL
1GB: 128M x 72 / 2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72
PC3-8500 / PC3-10600
Registered DDR3 SDRAM DIMM
REV 1.1 5
06/2009
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
Functional Block Diagram (Part 1 of 2)
[1GB – 1 Rank, 128Mx8 DDR3 SDRAMs]
D8
Notes :
1. DQ-to-I/O wiring is shown as recommended but may be changed.
2. ZQ resistors are 240Ω±1%. For all other resistor values refer to the appropriate wiring diagram.
ZQ
VDDSPD
VTT
VREFDQ
VREFCA
VDD
SPD
D0-D8
D0-D8
D0-D8
VSS
D0-D8
DQS
DQS8
PCK0A
RCKE0A
RODT0A
A[13:0]A/
BA[2:0]A
DM8/DQS17
CB[7:0]
TDQS
DQ[7:0]
CK
CKE
ODT
A[13:0]A/
BA[2:0]A
D3
ZQDQS
DQS3
DM3/DQS12
DQ[31:24]
TDQS
DQ[7:0]
CK
CKE
ODT
A[13:0]A/
BA[2:0]A
D2
ZQDQS
DQS2
DM2/DQS11
DQ[23:16]
TDQS
DQ[7:0]
CK
CKE
ODT
A[13:0]A/
BA[2:0]A
D1
ZQDQS
DQS1
DM1/DQS10
DQ[15:8]
TDQS
DQ[7:0]
CK
CKE
ODT
A[13:0]A/
BA[2:0]A
D0
ZQDQS
DQS0
DM0/DQS9
DQ[7:0]
TDQS
DQ[7:0]
CK
CKE
ODT
A[13:0]A/
BA[2:0]A
D4
ZQDQS
DQS4
PCK0A
RCKE0B
RODT0B
A[13:0]B/
BA[2:0]B
DM4/DQS13
CB[39:32]
TDQS
DQ[7:0]
CK
CKE
ODT
A[13:0]B/
BA[2:0]B
D5
ZQDQS
DQS5
DM5/DQS14
DQ[47:40]
TDQS
DQ[7:0]
CK
CKE
ODT
A[13:0]B/
BA[2:0]B
D6
ZQDQS
DQS6
DM6/DQS15
DQ[55:48]
TDQS
DQ[7:0]
CK
CKE
ODT
A[13:0]B/
BA[2:0]B
D7
ZQDQS
DQS7
DM7/DQS16
DQ[63:56]
TDQS
DQ[7:0]
CK
CKE
ODT
A[13:0]B/
BA[2:0]B
VSS
VSS
D0-D8
SPD w/ Integrated Thermal Sensor
SCL
SCL
SDA
SA0
SA1 A0
A1
A2
SA2
NT1GC72B89A0NL / NT2GC72B8PA0NL
NT4GC72B4NA1NL / NT4GC72B8NA1NL / NT8GTC72B4NA1NL
1GB: 128M x 72 / 2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72
PC3-8500 / PC3-10600
Registered DDR3 SDRAM DIMM
REV 1.1 6
06/2009
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
Functional Block Diagram (Part 2 of 2)
[1GB – 1 Rank, 128Mx8 DDR3 SDRAMs]
Register / PLL
: SDRAMs D[3:0], D8
: SDRAMs D[7:4]
BA[2:0] RBA[2:0]A BA[2:0]: SDRAMs D[3:0], D8
RBA[2:0]B BA[2:0]: SDRAMs D[7:4]
A[13:0] RA[13:0]A A[13:0]: SDRAMs D[3:0], D8
RA[13:0]B A[13:0]: SDRAMs D[7:4]
: SDRAMs D[3:0], D8
: SDRAMs D[7:4]
: SDRAMs D[3:0], D8
: SDRAMs D[7:4]
: SDRAMs D[3:0], D8
: SDRAMs D[7:4]
CKE0 RCKE0A CKE0: SDRAMs D[3:0], D8
RCKE0B CKE0: SDRAMs D[7:4]
RODT0A ODT0: SDRAMs D[3:0], D8
RODT0B ODT0: SDRAMs D[7:4]
ODT0
CK0
PCK0A CK: SDRAMs D[3:0], D8
PCK0B CK: SDRAMs D[7:4]
: SDRAMs D[3:0], D8
: SDRAMs D[7:4]
CK1
PAR_IN
: SDRAMs D[8:0]
120Ω
±1%
120Ω
±5%
Note: S[3:2], CKE1, ODT1 are NC
(Unused register inputs ODT1 and CKE1 have a 330Ω resistor to ground)
NT1GC72B89A0NL / NT2GC72B8PA0NL
NT4GC72B4NA1NL / NT4GC72B8NA1NL / NT8GTC72B4NA1NL
1GB: 128M x 72 / 2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72
PC3-8500 / PC3-10600
Registered DDR3 SDRAM DIMM
REV 1.1 7
06/2009
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
Functional Block Diagram (Part 1 of 2)
[2GB – 2 Ranks, 128Mx8 DDR3 SDRAMs]
D8
Notes :
1. DQ-to-I/O wiring is shown as recommended but may be changed.
2. ZQ resistors are 240Ω±1%. For all other resistor values refer to the appropriate wiring diagram.
3. Unless otherwise noted, resistor values are 15Ω±5%.
4. See the wiring diagrams for all resistors associated with the command, address and control bus.
ZQ
VDDSPD
VTT
VREFDQ
VREFCA
VDD
SPD
D0-D17
D0-D17
D0-D17
VSS
D0-D17
DQS
DQS8
PCK0A
RCKE0A
RODT0A
A[13:0]A/
BA[2:0]A
DM8/DQS17
CB[7:0]
TDQS
DQ[7:0]
CK
CKE
ODT
A[13:0]A/
BA[2:0]A
D3
DQS
DQS3
DM3/DQS12
DQ[31:24]
TDQS
DQ[7:0]
CK
CKE
ODT
A[13:0]A/
BA[2:0]A
D2
DQS
DQS2
DM2/DQS11
DQ[23:16]
TDQS
DQ[7:0]
CK
CKE
ODT
A[13:0]A/
BA[2:0]A
D1
DQS
DQS1
DM1/DQS10
DQ[15:8]
TDQS
DQ[7:0]
CK
CKE
ODT
A[13:0]A/
BA[2:0]A
D0
DQS
DQS0
DM0/DQS9
DQ[7:0]
TDQS
DQ[7:0]
CK
CKE
ODT
A[13:0]A/
BA[2:0]A
VSS
D0-D17
SPD w/ Integrated Thermal Sensor
SCL
SCL
SDA
SA0
SA1 A0
A1
A2
SA2
ZQ
ZQ
ZQ
ZQ
D17
ZQ
DQS
PCK1A
RCKE1A
RODT1A
TDQS
DQ[7:0]
CK
CKE
ODT
A[13:0]A/
BA[2:0]A
D12
ZQ
DQS
TDQS
DQ[7:0]
CK
CKE
ODT
A[13:0]A/
BA[2:0]A
D11
ZQ
DQS
TDQS
DQ[7:0]
CK
CKE
ODT
A[13:0]A/
BA[2:0]A
D10
ZQ
DQS
TDQS
DQ[7:0]
CK
CKE
ODT
A[13:0]A/
BA[2:0]A
D9
ZQ
DQS
TDQS
DQ[7:0]
CK
CKE
ODT
A[13:0]A/
BA[2:0]A
D4
ZQ
DQS
DQS4
PCK0B
RCKE0B
RODT0B
A[13:0]B/
BA[2:0]B
DM4/DQS13
CB[39:32]
TDQS
DQ[7:0]
CK
CKE
ODT
A[13:0]A/
BA[2:0]A
D5
DQS
DQS5
DM5/DQS14
DQ[47:40]
TDQS
DQ[7:0]
CK
CKE
ODT
A[13:0]A/
BA[2:0]A
D6
DQS
DQS6
DM6/DQS15
DQ[55:48]
TDQS
DQ[7:0]
CK
CKE
ODT
A[13:0]A/
BA[2:0]A
D7
DQS
DQS7
DM7/DQS16
DQ[63:56]
TDQS
DQ[7:0]
CK
CKE
ODT
A[13:0]A/
BA[2:0]A
VSS
ZQ
ZQ
ZQ
D13
ZQ
DQS
PCK1B
RCKE1B
RODT1B
TDQS
DQ[7:0]
CK
CKE
ODT
A[13:0]A/
BA[2:0]A
D14
ZQ
DQS
TDQS
DQ[7:0]
CK
CKE
ODT
A[13:0]A/
BA[2:0]A
D15
ZQ
DQS
TDQS
DQ[7:0]
CK
CKE
ODT
A[13:0]A/
BA[2:0]A
D16
ZQ
DQS
TDQS
DQ[7:0]
CK
CKE
ODT
A[13:0]A/
BA[2:0]A
NT1GC72B89A0NL / NT2GC72B8PA0NL
NT4GC72B4NA1NL / NT4GC72B8NA1NL / NT8GTC72B4NA1NL
1GB: 128M x 72 / 2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72
PC3-8500 / PC3-10600
Registered DDR3 SDRAM DIMM
REV 1.1 8
06/2009
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
Functional Block Diagram (Part 2 of 2)
[2GB – 2 Ranks, 128Mx8 DDR3 SDRAMs]
Register / PLL
: SDRAMs D[3:0], D8
: SDRAMs D[7:4]
BA[2:0] RBA[2:0]A BA[2:0]: SDRAMs D[3:0], D[12:8], D17
RBA[2:0]B BA[2:0]: SDRAMs D[7:4], D[16:13]
A[13:0] RA[13:0]A A[13:0]: SDRAMs D[3:0], D[12:8], D17
RA[13:0]B A[13:0]: SDRAMs D[7:4], D[16:13]
: SDRAMs D[3:0], D[12:8], D17
: SDRAMs D[7:4], D[16:13]
: SDRAMs D[3:0], D[12:8], D17
: SDRAMs D[7:4], D[16:13]
: SDRAMs D[3:0], D[12:8], D17
: SDRAMs D[7:4], D[16:13]
CKE0 RCKE0A CKE0: SDRAMs D[3:0], D8
RCKE0B CKE0: SDRAMs D[7:4]
RODT0A ODT0: SDRAMs D[3:0], D8
RODT0B ODT0: SDRAMs D[7:4]
ODT0
CK0
PCK0A CK: SDRAMs D[3:0], D8
PCK0B CK: SDRAMs D[7:4]
: SDRAMs D[3:0], D8
: SDRAMs D[7:4]
CK1
PAR_IN
: SDRAMs D[17:0]
120Ω
±1%
120Ω
±5%
CKE1
: SDRAMs D[12:9], D17
: SDRAMs D[16:13]
RCKE1A CKE1: SDRAMs D[12:9], D17
RCKE1B CKE1: SDRAMs D[16:13]
RODT1A ODT1: SDRAMs D[12:9], D17
RODT1B ODT1: SDRAMs D[16:13]
ODT1
PCK1A CK: SDRAMs D[12:9], D17
PCK1B CK: SDRAMs D[16:13]
: SDRAMs D[12:9], D17
: SDRAMs D[16:13]
NT1GC72B89A0NL / NT2GC72B8PA0NL
NT4GC72B4NA1NL / NT4GC72B8NA1NL / NT8GTC72B4NA1NL
1GB: 128M x 72 / 2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72
PC3-8500 / PC3-10600
Registered DDR3 SDRAM DIMM
REV 1.1 9
06/2009
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
Functional Block Diagram (Part 1 of 3)
[4GB – 4 Ranks, 128Mx8 DDR3 SDRAMs]
Notes :
1. DQ-to-I/O wiring is shown as recommended but may be changed.
2. ZQ resistors are 240Ω±1%. For all other resistor values refer to the appropriate wiring diagram.
3. Unless otherwise noted, resistor values are 15Ω±5%.
4. See the wiring diagrams for all resistors associated with the command, address and control bus.
VDDSPD
VTT
VREFDQ
VREFCA
VDD
SPD
D0-D17
D0-D17
D0-D17
VSS
D0-D17
D0-D17
SPD w/ Integrated Thermal Sensor
SCL
EVENT
SCL
SDA
EVENT
SA0
SA1 A0
A1
A2
SA2
RS0
RRASA
RCASA
RWEA
PCK0A
PCK0A
RCKE0A
RODT0A
A[13:0]A/
BA[2:0]A
D7
DQS
DQS
DQS4
DQS4
DM4/DQS13
DQS13
DQ[39:32]
TDQS
TDQS
DQ[7:0]
CS
RAS
CAS
WE
CK
CK
CKE
ODT
A[13:0]A/
BA[2:0]A
D8
DQS
DQS
DQS5
DQS5
DM5/DQS14
DQS14
DQ[47:40]
TDQS
TDQS
DQ[7:0]
CS
RAS
CAS
WE
CK
CK
CKE
ODT
A[13:0]A/
BA[2:0]A
D9
DQS
DQS
DQS6
DQS6
DM6/DQS15
DQS15
DQ[55:48]
TDQS
TDQS
DQ[7:0]
CS
RAS
CAS
WE
CK
CK
CKE
ODT
A[13:0]A/
BA[2:0]A
D10
DQS
DQS
DQS7
DQS7
DM7/DQS16
DQS16
DQ[63:56]
TDQS
TDQS
DQ[7:0]
CS
RAS
CAS
WE
CK
CK
CKE
ODT
A[13:0]A/
BA[2:0]A
VSS
ZQ
ZQ
ZQ
ZQ
RS1
PCK1A
PCK1A
RCKE1A
RODT1A
D16
ZQ
DQS
DQS
TDQS
TDQS
DQ[7:0]
CS
RAS
CAS
WE
CK
CK
CKE
ODT
A[13:0]A/
BA[2:0]A
D17
ZQ
DQS
DQS
TDQS
TDQS
DQ[7:0]
CS
RAS
CAS
WE
CK
CK
CKE
ODT
A[13:0]A/
BA[2:0]A
D18
ZQ
DQS
DQS
TDQS
TDQS
DQ[7:0]
CS
RAS
CAS
WE
CK
CK
CKE
ODT
A[13:0]A/
BA[2:0]A
D19
ZQ
DQS
DQS
TDQS
TDQS
DQ[7:0]
CS
RAS
CAS
WE
CK
CK
CKE
ODT
A[13:0]A/
BA[2:0]A
D25
DQS
DQS
TDQS
TDQS
DQ[7:0]
CS
RAS
CAS
WE
CK
CK
CKE
ODT
A[13:0]A/
BA[2:0]A
D26
DQS
DQS
TDQS
TDQS
DQ[7:0]
CS
RAS
CAS
WE
CK
CK
CKE
ODT
A[13:0]A/
BA[2:0]A
D27
DQS
DQS
TDQS
TDQS
DQ[7:0]
CS
RAS
CAS
WE
CK
CK
CKE
ODT
A[13:0]A/
BA[2:0]A
ZQ
ZQ
ZQ
RS3
PCK1B
PCK1B
RCKE1B
RODT1B
D34
ZQ
DQS
DQS
TDQS
TDQS
DQ[7:0]
CS
RAS
CAS
WE
CK
CK
CKE
ODT
A[13:0]A/
BA[2:0]A
D35
ZQ
DQS
DQS
TDQS
TDQS
DQ[7:0]
CS
RAS
CAS
WE
CK
CK
CKE
ODT
A[13:0]A/
BA[2:0]A
D36
ZQ
DQS
DQS
TDQS
TDQS
DQ[7:0]
CS
RAS
CAS
WE
CK
CK
CKE
ODT
A[13:0]A/
BA[2:0]A
D28
ZQ
DQS
DQS
TDQS
TDQS
DQ[7:0]
CS
RAS
CAS
WE
CK
CK
CKE
ODT
A[13:0]A/
BA[2:0]A
D37
ZQ
DQS
DQS
TDQS
TDQS
DQ[7:0]
CS
RAS
CAS
WE
CK
CK
CKE
ODT
A[13:0]A/
BA[2:0]A
RS2
PCK1B
PCK1B
RCKE1B
RODT1B
NT1GC72B89A0NL / NT2GC72B8PA0NL
NT4GC72B4NA1NL / NT4GC72B8NA1NL / NT8GTC72B4NA1NL
1GB: 128M x 72 / 2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72
PC3-8500 / PC3-10600
Registered DDR3 SDRAM DIMM
REV 1.1 10
06/2009
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
Functional Block Diagram (Part 2 of 3)
[4GB – 4 Ranks, 128Mx8 DDR3 SDRAMs]
D6
ZQ
DQS
DQS
DQS8
RS0
RRASA
RCASA
RWEA
PCK0A
PCK0A
RCKE0A
RODT0A
A[13:0]A/
BA[2:0]A
DQS8
DM8/DQS17
DQS17
CB[7:0]
TDQS
TDQS
DQ[7:0]
CS
RAS
CAS
WE
CK
CK
CKE
ODT
A[13:0]A/
BA[2:0]A
D5
DQS
DQS
DQS3
DQS3
DM3/DQS12
DQS12
DQ[31:24]
TDQS
TDQS
DQ[7:0]
CS
RAS
CAS
WE
CK
CK
CKE
ODT
A[13:0]A/
BA[2:0]A
D4
DQS
DQS
DQS2
DQS2
DM2/DQS11
DQS11
DQ[23:16]
TDQS
TDQS
DQ[7:0]
CS
RAS
CAS
WE
CK
CK
CKE
ODT
A[13:0]A/
BA[2:0]A
D3
DQS
DQS
DQS1
DQS1
DM1/DQS10
DQS10
DQ[15:8]
TDQS
TDQS
DQ[7:0]
CS
RAS
CAS
WE
CK
CK
CKE
ODT
A[13:0]A/
BA[2:0]A
D2
DQS
DQS
DQS0
DQS0
DM0/DQS9
DQS9
DQ[7:0]
TDQS
TDQS
DQ[7:0]
CS
RAS
CAS
WE
CK
CK
CKE
ODT
A[13:0]A/
BA[2:0]A
VSS
ZQ
ZQ
ZQ
ZQ
D15
ZQ
DQS
DQS
RS1
PCK1A
PCK1A
RCKE1A
RODT1A
TDQS
TDQS
DQ[7:0]
CS
RAS
CAS
WE
CK
CK
CKE
ODT
A[13:0]A/
BA[2:0]A
D14
ZQ
DQS
DQS
TDQS
TDQS
DQ[7:0]
CS
RAS
CAS
WE
CK
CK
CKE
ODT
A[13:0]A/
BA[2:0]A
D13
ZQ
DQS
DQS
TDQS
TDQS
DQ[7:0]
CS
RAS
CAS
WE
CK
CK
CKE
ODT
A[13:0]A/
BA[2:0]A
D12
ZQ
DQS
DQS
TDQS
TDQS
DQ[7:0]
CS
RAS
CAS
WE
CK
CK
CKE
ODT
A[13:0]A/
BA[2:0]A
D11
ZQ
DQS
DQS
TDQS
TDQS
DQ[7:0]
CS
RAS
CAS
WE
CK
CK
CKE
ODT
A[13:0]A/
BA[2:0]A
D24
ZQ
DQS
DQS
TDQS
TDQS
DQ[7:0]
CS
RAS
CAS
WE
CK
CK
CKE
ODT
A[13:0]A/
BA[2:0]A
D23
DQS
DQS
TDQS
TDQS
DQ[7:0]
CS
RAS
CAS
WE
CK
CK
CKE
ODT
A[13:0]A/
BA[2:0]A
D22
DQS
DQS
TDQS
TDQS
DQ[7:0]
CS
RAS
CAS
WE
CK
CK
CKE
ODT
A[13:0]A/
BA[2:0]A
D21
DQS
DQS
TDQS
TDQS
DQ[7:0]
CS
RAS
CAS
WE
CK
CK
CKE
ODT
A[13:0]A/
BA[2:0]A
ZQ
ZQ
ZQ
D33
ZQ
DQS
DQS
RS3
PCK1B
PCK1B
RCKE1B
RODT1B
TDQS
TDQS
DQ[7:0]
CS
RAS
CAS
WE
CK
CK
CKE
ODT
A[13:0]A/
BA[2:0]A
D32
ZQ
DQS
DQS
TDQS
TDQS
DQ[7:0]
CS
RAS
CAS
WE
CK
CK
CKE
ODT
A[13:0]A/
BA[2:0]A
D31
ZQ
DQS
DQS
TDQS
TDQS
DQ[7:0]
CS
RAS
CAS
WE
CK
CK
CKE
ODT
A[13:0]A/
BA[2:0]A
D30
ZQ
DQS
DQS
TDQS
TDQS
DQ[7:0]
CS
RAS
CAS
WE
CK
CK
CKE
ODT
A[13:0]A/
BA[2:0]A
D20
ZQ
DQS
DQS
TDQS
TDQS
DQ[7:0]
CS
RAS
CAS
WE
CK
CK
CKE
ODT
A[13:0]A/
BA[2:0]A
D29
ZQ
DQS
DQS
TDQS
TDQS
DQ[7:0]
CS
RAS
CAS
WE
CK
CK
CKE
ODT
A[13:0]A/
BA[2:0]A
RS2
PCK1B
PCK1B
RCKE1B
RODT1B
NT1GC72B89A0NL / NT2GC72B8PA0NL
NT4GC72B4NA1NL / NT4GC72B8NA1NL / NT8GTC72B4NA1NL
1GB: 128M x 72 / 2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72
PC3-8500 / PC3-10600
Registered DDR3 SDRAM DIMM
REV 1.1 11
06/2009
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
Functional Block Diagram (Part 3 of 3)
[4GB – 4 Ranks, 128Mx8 DDR3 SDRAMs]
Register / PLL
S2
S3
CS0_n CS0_n: SDRAMs D[10:2]
CS1_n CS1_n: SDRAMs D[19:11]
BA[2:0]
BA[2:0]A BA[2:0]: SDRAMs D[6:2], D[15:11], D[24:20], D[33:29]
BA[2:0]B BA[2:0]: SDRAMs D[10:7], D[19:16], D[28:25], D[37:34]
A[13:0]
A[13:0]A A[13:0]: SDRAMs D[6:2], D[15:11], D[24:20], D[33:29]
A[13:0]B A[13:0]: SDRAMs D[10:7], D[19:16], D[28:25], D[37:34]
RAS
CAS
WE
RRASA RAS: SDRAMs D[6:2], D[15:11], D[24:20], D[33:29]
RRASB RAS: SDRAMs D[10:7], D[19:16], D[28:25], D[37:34]
RCASA CAS: SDRAMs D[6:2], D[15:11], D[24:20], D[33:29]
RCASB CAS: SDRAMs D[10:7], D[19:16], D[28:25], D[37:34]
RWEA WE: SDRAMs D[6:2], D[15:11], D[24:20], D[33:29]
RWEB WE: SDRAMs D[10:7], D[19:16], D[28:25], D[37:34]
CKE0
RCKE0A CKE0: SDRAMs D[6:2], D[24:20]
RCKE0B CKE0: SDRAMs D[10:7], D[28:25]
RODT0A ODT0: SDRAMs D[6:2]
RODT0B ODT0: SDRAMs D[10:7]
ODT0
CK0
CK0
PCK0A CK: SDRAMs D[6:2], D[15:11]
PCK0B CK: SDRAMs D[10:7], D[28:25]
PCK0A CK: SDRAMs D[6:2], D[15:11]
PCK0B CK: SDRAMs D[10:7], D[28:25]
CK1
CK1
PAR_IN ERR_OUT
RST: SDRAMs D[37:2]
120Ω
±1%
120Ω
±5%
RESET RST
QERR
CKE1
CS2_n CS2_n: SDRAMs D[28:20]
CS3_n CS3_n: SDRAMs D[31:29]
RCKE1A CKE1: SDRAMs D[15:11], D[33:29]
RCKE1B CKE1: SDRAMs D[19:16], D[37:34]
RODT1A ODT1: SDRAMs D[24:20]
RODT1B ODT1: SDRAMs D[28:25]
ODT1 PCK1A CK: SDRAMs D[24:20], D[33:29]
PCK1B CK: SDRAMs D[19:16], D[37:34]
PCK1A CK: SDRAMs D[24:20], D[33:29]
PCK1B CK: SDRAMs D[19:16], D[37:34]
S0
S1
NT1GC72B89A0NL / NT2GC72B8PA0NL
NT4GC72B4NA1NL / NT4GC72B8NA1NL / NT8GTC72B4NA1NL
1GB: 128M x 72 / 2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72
PC3-8500 / PC3-10600
Registered DDR3 SDRAM DIMM
REV 1.1 12
06/2009
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
Functional Block Diagram (Part 1 of 3)
[4GB – 2 Ranks, 256Mx4 DDR3 SDRAMs]
D17
DM
DQS
DQS17
PCK0A
RCKE0A
RODT0A
A[13:0]A/
BA[2:0]A
VSS
CB[7:4] DQ[3:0]
CK
CKE
ODT
A[13:0]A/
BA[2:0]A
D12
DQS
CK
CKE
ODT
A[13:0]A/
BA[2:0]A
VSS
D35
DQS
PCK1A
RCKE1A
RODT1A
CK
CKE
ODT
A[13:0]A/
BA[2:0]A
D30
DQS
CK
CKE
ODT
A[13:0]A/
BA[2:0]A
VSS
PCK0A
RCKE0A
RODT0A
A[13:0]A/
BA[2:0]A
PCK1A
RCKE1A
RODT1A
DM
DQ[3:0]
DQS12
VSS
DQ[31:28] DM
DQ[3:0] DM
DQ[3:0]
D11
DQS
CK
CKE
ODT
A[13:0]A/
BA[2:0]A
D29
DQS
CK
CKE
ODT
A[13:0]A/
BA[2:0]A
DQS11
VSS
DQ[23:20] DM
DQ[3:0] DM
DQ[3:0]
D10
DQS
CK
CKE
ODT
A[13:0]A/
BA[2:0]A
D28
DQS
CK
CKE
ODT
A[13:0]A/
BA[2:0]A
DQS10
VSS
DQ[15:12] DM
DQ[3:0] DM
DQ[3:0]
D0
DQS
CK
CKE
ODT
A[13:0]A/
BA[2:0]A
D18
DQS
CK
CKE
ODT
A[13:0]A/
BA[2:0]A
DQS0
VSS
DQ[3:0] DM
DQ[3:0] DM
DQ[3:0]
D8
DM
DQS
DQS8
VSS
CB[3:0] DQ[3:0]
CK
CKE
ODT
A[13:0]A/
BA[2:0]A
D26
DQS
CK
CKE
ODT
A[13:0]A/
BA[2:0]A
DM
DQ[3:0]
D3
DM
DQS
DQS3
VSS
CB[27:24] DQ[3:0]
CK
CKE
ODT
A[13:0]A/
BA[2:0]A
D21
DQS
CK
CKE
ODT
A[13:0]A/
BA[2:0]A
DM
DQ[3:0]
D2
DM
DQS
DQS2
VSS
CB[19:16] DQ[3:0]
CK
CKE
ODT
A[13:0]A/
BA[2:0]A
D20
DQS
CK
CKE
ODT
A[13:0]A/
BA[2:0]A
DM
DQ[3:0]
D1
DM
DQS
DQS1
VSS
CB[11:8] DQ[3:0]
CK
CKE
ODT
A[13:0]A/
BA[2:0]A
D19
DQS
CK
CKE
ODT
A[13:0]A/
BA[2:0]A
DM
DQ[3:0]
D1
DM
DQS
DQS1
VSS
CB[11:8] DQ[3:0]
CK
CKE
ODT
A[13:0]A/
BA[2:0]A
D19
DQS
CK
CKE
ODT
A[13:0]A/
BA[2:0]A
DM
DQ[3:0]
NT1GC72B89A0NL / NT2GC72B8PA0NL
NT4GC72B4NA1NL / NT4GC72B8NA1NL / NT8GTC72B4NA1NL
1GB: 128M x 72 / 2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72
PC3-8500 / PC3-10600
Registered DDR3 SDRAM DIMM
REV 1.1 13
06/2009
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
Functional Block Diagram (Part 2 of 3)
[4GB – 2 Ranks, 256Mx4 DDR3 SDRAMs]
D14
Notes :
1. DQ-to-I/O wiring is shown as recommended but may be changed.
2. ZQ pins of each SDRAM are connected to individual RZQ resistors (240Ω±1%).
3. See the wiring diagrams for resistor values.
DM
VDDSPD
VTT
VREFDQ
VREFCA
VDD
SPD
D0-D35
D0-D35
D0-D35
VSS
D0-D35
DQS
DQS14
PCK0B
RCKE0B
RODT0B
A[13:0]B/
BA[2:0]B
VSS
DQ[47:44] DQ[3:0]
CK
CKE
ODT
A[13:0]A/
BA[2:0]A
D4
DQS
CK
CKE
ODT
A[13:0]A/
BA[2:0]A
VSS
D0-D35
SPD w/ Integrated Thermal Sensor
SCL
SCL
SDA
SA0
SA1 A0
A1
A2
SA2
D22
DQS
PCK1B
RCKE1B
RODT1B
CK
CKE
ODT
A[13:0]A/
BA[2:0]A
D22
DQS
CK
CKE
ODT
A[13:0]A/
BA[2:0]A
VSS
PCK0B
RCKE0B
RODT0B
A[13:0]B/
BA[2:0]B
PCK1B
RCKE1B
RODT1B
DM
DQ[3:0]
DQS4
VSS
DQ[35:32] DM
DQ[3:0] DM
DQ[3:0]
D16
DQS
CK
CKE
ODT
A[13:0]A/
BA[2:0]A
D34
DQS
CK
CKE
ODT
A[13:0]A/
BA[2:0]A
DQS16
VSS
DQ[63:60] DM
DQ[3:0] DM
DQ[3:0]
D7
DQS
CK
CKE
ODT
A[13:0]A/
BA[2:0]A
D25
DQS
CK
CKE
ODT
A[13:0]A/
BA[2:0]A
DQS7
VSS
DQ[59:56] DM
DQ[3:0] DM
DQ[3:0]
D13
DM
DQS
DQS13
VSS
DQ[39:36] DQ[3:0]
CK
CKE
ODT
A[13:0]A/
BA[2:0]A
D31
DQS
CK
CKE
ODT
A[13:0]A/
BA[2:0]A
DM
DQ[3:0]
D5
DM
DQS
DQS5
VSS
CB[43:40] DQ[3:0]
CK
CKE
ODT
A[13:0]A/
BA[2:0]A
D23
DQS
CK
CKE
ODT
A[13:0]A/
BA[2:0]A
DM
DQ[3:0]
D15
DM
DQS
DQS15
VSS
CB[55:52] DQ[3:0]
CK
CKE
ODT
A[13:0]A/
BA[2:0]A
D33
DQS
CK
CKE
ODT
A[13:0]A/
BA[2:0]A
DM
DQ[3:0]
D6
DM
DQS
DQS6
VSS
CB[51:48] DQ[3:0]
CK
CKE
ODT
A[13:0]A/
BA[2:0]A
D24
DQS
CK
CKE
ODT
A[13:0]A/
BA[2:0]A
DM
DQ[3:0]
NT1GC72B89A0NL / NT2GC72B8PA0NL
NT4GC72B4NA1NL / NT4GC72B8NA1NL / NT8GTC72B4NA1NL
1GB: 128M x 72 / 2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72
PC3-8500 / PC3-10600
Registered DDR3 SDRAM DIMM
REV 1.1 14
06/2009
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
Functional Block Diagram (Part 3 of 3)
[4GB – 2 Ranks, 256Mx4 DDR3 SDRAMs]
Register / PLL
: SDRAMs D[3:0], D[12:8], D17
: SDRAMs D[7:4], D[16:13]
BA[2:0] RBA[2:0]A BA[2:0]: SDRAMs D[3:0], D[12:8], D[21:17], D[30:26], D35
RBA[2:0]B BA[2:0]: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31]
A[13:0] RA[13:0]A A[13:0]: SDRAMs D[3:0], D[12:8], D[21:17], D[30:26], D35
RA[13:0]B A[13:0]: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31]
: SDRAMs D[3:0], D[12:8], D[21:17], D[30:26], D35
: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31]
: SDRAMs D[3:0], D[12:8], D[21:17], D[30:26], D35
: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31]
: SDRAMs D[3:0], D[12:8], D[21:17], D[30:26], D35
: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31]
CKE0 RCKE0A CKE0: SDRAMs D[3:0], D[12:8], D17
RCKE0B CKE0: SDRAMs D[7:4], D[16:13]
RODT0A ODT0: SDRAMs D[3:0], D[12:8], D17
RODT0B ODT0: SDRAMs D[7:4], D[16:13]
ODT0
CK0
PCK0A CK: SDRAMs D[3:0], D[12:8], D17
PCK0B CK: SDRAMs D[7:4], D[16:13]
: SDRAMs D[3:0], D[12:8], D17
: SDRAMs D[7:4], D[16:13]
CK1
PAR_IN
: SDRAMs D[17:0]
120Ω
±1%
120Ω
±5%
CKE1
: SDRAMs D[21:18], D[30:26], D35
: SDRAMs D[25:22], D[34:31]
RCKE1A CKE1: SDRAMs D[21:18], D[30:26], D35
RCKE1B CKE1: SDRAMs D[25:22], D[34:31]
RODT1A ODT1: SDRAMs D[21:18], D[30:26], D35
RODT1B ODT1: SDRAMs D[25:22], D[34:31]
ODT1
PCK1A CK: SDRAMs D[21:18], D[30:26], D35
PCK1B CK: SDRAMs D[25:22], D[34:31]
: SDRAMs D[21:18], D[30:26], D35
: SDRAMs D[25:22], D[34:31]
NT1GC72B89A0NL / NT2GC72B8PA0NL
NT4GC72B4NA1NL / NT4GC72B8NA1NL / NT8GTC72B4NA1NL
1GB: 128M x 72 / 2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72
PC3-8500 / PC3-10600
Registered DDR3 SDRAM DIMM
REV 1.1 15
06/2009
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
Functional Block Diagram (Part 1 of 5)
[8GB – 4 Ranks, 512Mx4 (DDP) DDR3 SDRAMs]
D9
DM
DQS
DQS8
APCK0A
ARCKE0A
ARODT0A
ARA[13:0]A
/ARBA[2:0]A
VSS
CB[3:0] DQ[3:0]
CK
CKE
ODT
A[13:0]A/
BA[2:0]
VSS
D8
DQS
ARCKE1A
VDD
CK
CKE
ODT
A[13:0]A/
BA[2:0]
BPCK0A
BRCKE0A
BRODT1A
BRA[13:0]A
/BRBA[2:0]A
DM
DQ[3:0]
ZQ ZQVSS
VSS
D7
DM
DQS
DQS3
VSS
DQ[27:24] DQ[3:0]
CK
CKE
ODT
A[13:0]A/
BA[2:0]
D6
DQS
CK
CKE
ODT
A[13:0]A/
BA[2:0]
DM
DQ[3:0]
ZQ ZQVSS
VSS
D5
DM
DQS
DQS2
VSS
DQ[19:16] DQ[3:0]
CK
CKE
ODT
A[13:0]A/
BA[2:0]
D4
DQS
CK
CKE
ODT
A[13:0]A/
BA[2:0]
DM
DQ[3:0]
ZQ ZQVSS
VSS
D3
DM
DQS
DQS1
VSS
DQ[11:8] DQ[3:0]
CK
CKE
ODT
A[13:0]A/
BA[2:0]
D2
DQS
CK
CKE
ODT
A[13:0]A/
BA[2:0]
DM
DQ[3:0]
ZQ ZQVSS
VSS
D1
DM
DQS
DQS0
VSS
DQ[3:0] DQ[3:0]
CK
CKE
ODT
A[13:0]A/
BA[2:0]
D0
DQS
CK
CKE
ODT
A[13:0]A/
BA[2:0]
DM
DQ[3:0]
ZQ ZQVSS
VSS
D45
DM
DQS
DQ[3:0]
CK
CKE
ODT
A[13:0]A/
BA[2:0]
D44
DQS
CK
CKE
ODT
A[13:0]A/
BA[2:0]
DM
DQ[3:0]
ZQ ZQVSSVSS
D47
DM
DQS
DQ[3:0]
CK
CKE
ODT
A[13:0]A/
BA[2:0]
D46
DQS
CK
CKE
ODT
A[13:0]A/
BA[2:0]
DM
DQ[3:0]
ZQ ZQVSS
VSS
D49
DM
DQS
DQ[3:0]
CK
CKE
ODT
A[13:0]A/
BA[2:0]
D48
DQS
CK
CKE
ODT
A[13:0]A/
BA[2:0]
DM
DQ[3:0]
ZQ ZQVSSVSS
D51
DM
DQS
DQ[3:0]
CK
CKE
ODT
A[13:0]A/
BA[2:0]
D50
DQS
CK
CKE
ODT
A[13:0]A/
BA[2:0]
DM
DQ[3:0]
ZQ ZQVSS
D53
DM
DQS
DQ[3:0]
CK
CKE
ODT
A[13:0]A/
BA[2:0]
D52
DQS
CK
CKE
ODT
A[13:0]A/
BA[2:0]
DM
DQ[3:0]
ZQ ZQVSSVSS
BRCKE1A
VDD
VSS
NT1GC72B89A0NL / NT2GC72B8PA0NL
NT4GC72B4NA1NL / NT4GC72B8NA1NL / NT8GTC72B4NA1NL
1GB: 128M x 72 / 2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72
PC3-8500 / PC3-10600
Registered DDR3 SDRAM DIMM
REV 1.1 16
06/2009
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
Functional Block Diagram (Part 2 of 5)
[8GB – 4 Ranks, 512Mx4 (DDP) DDR3 SDRAMs]
D27
DM
DQS
DQS17
APCK1A
ARCKE0A
ARODT0A
ARA[13:0]A
/ARBA[2:0]A
VSS
CB[7:4] DQ[3:0]
CK
CKE
ODT
A[13:0]A/
BA[2:0]
Vtt
D26
DQS
ARCKE1A
VDD
CK
CKE
ODT
A[13:0]A/
BA[2:0]
BPCK1A
BRCKE0A
BRODT1A
BRA[13:0]A
/BRBA[2:0]A
DM
DQ[3:0]
ZQ ZQVSS
VSS
D25
DM
DQS
DQS12
VSS
DQ[31:28] DQ[3:0]
CK
CKE
ODT
A[13:0]A/
BA[2:0]
D24
DQS
CK
CKE
ODT
A[13:0]A/
BA[2:0]
DM
DQ[3:0]
ZQ ZQVSS
VSS
D23
DM
DQS
DQS11
VSS
DQ[23:20] DQ[3:0]
CK
CKE
ODT
A[13:0]A/
BA[2:0]
D22
DQS
CK
CKE
ODT
A[13:0]A/
BA[2:0]
DM
DQ[3:0]
ZQ ZQVSS
VSS
D21
DM
DQS
DQS10
VSS
DQ[15:12] DQ[3:0]
CK
CKE
ODT
A[13:0]A/
BA[2:0]
D20
DQS
CK
CKE
ODT
A[13:0]A/
BA[2:0]
DM
DQ[3:0]
ZQ ZQVSS
VSS
D19
DM
DQS
DQS9
VSS
DQ[7:4] DQ[3:0]
CK
CKE
ODT
A[13:0]A/
BA[2:0]
D18
DQS
CK
CKE
ODT
A[13:0]A/
BA[2:0]
DM
DQ[3:0]
ZQ ZQVSS
VSS
D63
DM
DQS
DQ[3:0]
CK
CKE
ODT
A[13:0]A/
BA[2:0]
D62
DQS
CK
CKE
ODT
A[13:0]A/
BA[2:0]
DM
DQ[3:0]
ZQ ZQVSSVSS
D65
DM
DQS
DQ[3:0]
CK
CKE
ODT
A[13:0]A/
BA[2:0]
D64
DQS
CK
CKE
ODT
A[13:0]A/
BA[2:0]
DM
DQ[3:0]
ZQ ZQVSS
VSS
D67
DM
DQS
DQ[3:0]
CK
CKE
ODT
A[13:0]A/
BA[2:0]
D66
DQS
CK
CKE
ODT
A[13:0]A/
BA[2:0]
DM
DQ[3:0]
ZQ ZQVSSVSS
D69
DM
DQS
DQ[3:0]
CK
CKE
ODT
A[13:0]A/
BA[2:0]
D68
DQS
CK
CKE
ODT
A[13:0]A/
BA[2:0]
DM
DQ[3:0]
ZQ ZQVSS
D71
DM
DQS
DQ[3:0]
CK
CKE
ODT
A[13:0]A/
BA[2:0]
D70
DQS
CK
CKE
ODT
A[13:0]A/
BA[2:0]
DM
DQ[3:0]
ZQ ZQVSSVSS
BRCKE1A
VDD
VSS
NT1GC72B89A0NL / NT2GC72B8PA0NL
NT4GC72B4NA1NL / NT4GC72B8NA1NL / NT8GTC72B4NA1NL
1GB: 128M x 72 / 2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72
PC3-8500 / PC3-10600
Registered DDR3 SDRAM DIMM
REV 1.1 17
06/2009
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
Functional Block Diagram (Part 3 of 5)
[8GB – 4 Ranks, 512Mx4 (DDP) DDR3 SDRAMs]
D11
DM
DQS
DQS4
APCK0B
ARCKE0B
ARODT0B
ARA[13:0]B
/ARBA[2:0]B
VSS
DQ[35:32] DQ[3:0]
CK
CKE
ODT
A[13:0]A/
BA[2:0]
Vtt
D10
DQS
ARCKE1B
VDD
CK
CKE
ODT
A[13:0]A/
BA[2:0]
BPCK0B
BRCKE0B
BRODT1B
BRA[13:0]B
/BRBA[2:0]B
DM
DQ[3:0]
ZQ ZQVSS
VSS
D13
DM
DQS
DQS5
VSS
DQ[43:40] DQ[3:0]
CK
CKE
ODT
A[13:0]A/
BA[2:0]
D12
DQS
CK
CKE
ODT
A[13:0]A/
BA[2:0]
DM
DQ[3:0]
ZQ ZQVSS
VSS
D15
DM
DQS
DQS6
VSS
DQ[51:48] DQ[3:0]
CK
CKE
ODT
A[13:0]A/
BA[2:0]
D14
DQS
CK
CKE
ODT
A[13:0]A/
BA[2:0]
DM
DQ[3:0]
ZQ ZQVSS
VSS
D17
DM
DQS
DQS7
VSS
DQ[59:56] DQ[3:0]
CK
CKE
ODT
A[13:0]A/
BA[2:0]
D16
DQS
CK
CKE
ODT
A[13:0]A/
BA[2:0]
DM
DQ[3:0]
ZQ ZQVSS
VSS
D43
DM
DQS
DQ[3:0]
CK
CKE
ODT
A[13:0]A/
BA[2:0]
D42
DQS
CK
CKE
ODT
A[13:0]A/
BA[2:0]
DM
DQ[3:0]
ZQ ZQVSSVSS
D41
DM
DQS
DQ[3:0]
CK
CKE
ODT
A[13:0]A/
BA[2:0]
D40
DQS
CK
CKE
ODT
A[13:0]A/
BA[2:0]
DM
DQ[3:0]
ZQ ZQVSS
VSS
D39
DM
DQS
DQ[3:0]
CK
CKE
ODT
A[13:0]A/
BA[2:0]
D38
DQS
CK
CKE
ODT
A[13:0]A/
BA[2:0]
DM
DQ[3:0]
ZQ ZQVSSVSS
D37
DM
DQS
DQ[3:0]
CK
CKE
ODT
A[13:0]A/
BA[2:0]
D36
DQS
CK
CKE
ODT
A[13:0]A/
BA[2:0]
DM
DQ[3:0]
ZQ ZQVSS
BRCKE1B
VDD
VSS
NT1GC72B89A0NL / NT2GC72B8PA0NL
NT4GC72B4NA1NL / NT4GC72B8NA1NL / NT8GTC72B4NA1NL
1GB: 128M x 72 / 2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72
PC3-8500 / PC3-10600
Registered DDR3 SDRAM DIMM
REV 1.1 18
06/2009
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
Functional Block Diagram (Part 4 of 5)
[8GB – 4 Ranks, 512Mx4 (DDP) DDR3 SDRAMs]
D29
DM
DQS
DQS13
APCK1B
ARCKE0B
ARODT0B
ARA[13:0]B
/ARBA[2:0]B
VSS
DQ[39:36] DQ[3:0]
CK
CKE
ODT
A[13:0]A/
BA[2:0]
Vtt
D28
DQS
ARCKE1B
VDD
CK
CKE
ODT
A[13:0]A/
BA[2:0]
BPCK1B
BRCKE0B
BRODT1B
BRA[13:0]B
/BRBA[2:0]B
DM
DQ[3:0]
ZQ ZQVSS
VSS
D31
DM
DQS
DQS14
VSS
DQ[47:44] DQ[3:0]
CK
CKE
ODT
A[13:0]A/
BA[2:0]
D30
DQS
CK
CKE
ODT
A[13:0]A/
BA[2:0]
DM
DQ[3:0]
ZQ ZQVSS
VSS
D33
DM
DQS
DQS15
VSS
DQ[55:52] DQ[3:0]
CK
CKE
ODT
A[13:0]A/
BA[2:0]
D32
DQS
CK
CKE
ODT
A[13:0]A/
BA[2:0]
DM
DQ[3:0]
ZQ ZQVSS
VSS
D35
DM
DQS
DQS16
VSS
DQ[63:60] DQ[3:0]
CK
CKE
ODT
A[13:0]A/
BA[2:0]
D34
DQS
CK
CKE
ODT
A[13:0]A/
BA[2:0]
DM
DQ[3:0]
ZQ ZQVSS
VSS
D61
DM
DQS
DQ[3:0]
CK
CKE
ODT
A[13:0]A/
BA[2:0]
D60
DQS
CK
CKE
ODT
A[13:0]A/
BA[2:0]
DM
DQ[3:0]
ZQ ZQVSSVSS
D59
DM
DQS
DQ[3:0]
CK
CKE
ODT
A[13:0]A/
BA[2:0]
D58
DQS
CK
CKE
ODT
A[13:0]A/
BA[2:0]
DM
DQ[3:0]
ZQ ZQVSS
VSS
D57
DM
DQS
DQ[3:0]
CK
CKE
ODT
A[13:0]A/
BA[2:0]
D56
DQS
CK
CKE
ODT
A[13:0]A/
BA[2:0]
DM
DQ[3:0]
ZQ ZQVSSVSS
D55
DM
DQS
DQ[3:0]
CK
CKE
ODT
A[13:0]A/
BA[2:0]
D54
DQS
CK
CKE
ODT
A[13:0]A/
BA[2:0]
DM
DQ[3:0]
ZQ ZQVSS
BRCKE1B
VDD
VSS
Notes :
1. DQ-to-I/O wiring is may be changed within a nibble.
2, Resistor values are 15Ω±5%.
2. ZQ resistors are 240Ω±1%.
3. See the wiring diagrams for resistor values.
VDDSPD
VTT
VREFDQ
VREFCA
VDD
SPD
D0-D71
D0-D71
D0-D71
VSS
D0-D71
D0-D71
SPD w/ Integrated Thermal Sensor
SCL
SCL
SDA
SA0
SA1 A0
A1
A2
SA2
NT1GC72B89A0NL / NT2GC72B8PA0NL
NT4GC72B4NA1NL / NT4GC72B8NA1NL / NT8GTC72B4NA1NL
1GB: 128M x 72 / 2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72
PC3-8500 / PC3-10600
Registered DDR3 SDRAM DIMM
REV 1.1 19
06/2009
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
Functional Block Diagram (Part 5 of 5)
[8GB – 4 Ranks, 512Mx4 (DDP) DDR3 SDRAMs]
Register / PLL A
: SDRAMs D1, D3, D5, D7, D9, D19, D21, D23, D25, D27
: SDRAMs D11, D13, D15, D17, D29, D31, D33, D35
BA[2:0] ARBA[2:0]A BA[2:0]: SDRAMs D[9:0], D[27:18]
ARBA[2:0]B BA[2:0]: SDRAMs D[17:10], D[35:28]
A[13:0] ARA[13:0]A A[13:0]: SDRAMs D[9:0], D[27:18]
ARA[13:0]B A[13:0]: SDRAMs D[17:10], D[35:28]
: SDRAMs D[9:0], D[27:18]
: SDRAMs D[17:10], D[35:28]
: SDRAMs D[9:0], D[27:18]
: SDRAMs D[17:10], D[35:28]
: SDRAMs D[9:0], D[27:18]
: SDRAMs D[17:10], D[35:28]
CKE0 ARCKE0A CKE1: SDRAMs D1, D3, D5, D7, D9, D19, D21, D23, D25, D27
ARCKE0B CKE1: SDRAMs D11, D13, D15, D17, D29, D31, D33, D35
ARODT0A ODT1: SDRAMs D1, D3, D5, D7, D9, D19, D21, D23, D25, D27
ARODT0B ODT1: SDRAMs D11, D13, D15, D17, D29, D31, D33, D35
ODT0
CK0
APCK0A CK: SDRAMs D[9:0]
APCK0B CK: SDRAMs D[17:10]
: SDRAMs D[9:0]
: SDRAMs D[17:10]
CK1
PAR_IN
: SDRAMs D[71:0]
120Ω
±1%
120Ω
±5%
CKE1
: SDRAMs D0, D2, D4, D6, D8, D18, D20, D22, D24, D26
: SDRAMs D10, D12, D14, D16, D28, D30, D32, D34
ARCKE1A CKE0: SDRAMs D0, D2, D4, D6, D8, D18, D20, D22, D24, D26
ARCKE1B CKE0: SDRAMs D10, D12, D14, D16, D28, D30, D32, D34
APCK1A CK: SDRAMs D[27:18]
APCK1B CK: SDRAMs D[35:28]
: SDRAMs D[27:18]
: SDRAMs D[35:28]
Register / PLL B
BA[2:0]
A[13:0]
CKE0
CK0
CK1
PAR_IN
120Ω
±1%
120Ω
±5%
CKE1
ODT1
: SDRAMs D45, D47, D49, D51, D53, D63, D65, D67, D69, D71
: SDRAMs D37, D39, D41, D43, D55, D57, D59, D61
BRBA[2:0]A BA[2:0]: SDRAMs D[53:44], D[71:62]
BRBA[2:0]B BA[2:0]: SDRAMs D[43:36], D[61:54]
BRA[13:0]A A[13:0]: SDRAMs D[53:44], D[71:62]
BRA[13:0]B A[13:0]: SDRAMs D[43:36], D[61:54]
: SDRAMs D[53:44], D[71:62]
: SDRAMs D[43:36], D[61:54]
: SDRAMs D[53:44], D[71:62]
: SDRAMs D[43:36], D[61:54]
: SDRAMs D[53:44], D[71:62]
: SDRAMs D[43:36], D[61:54]
BRCKE0A CKE1: SDRAMs D45, D47, D49, D51, D53, D63, D65, D67, D69, D71
BRCKE0B CKE1: SDRAMs D37, D39, D41, D43, D55, D57, D59, D61
BRODT0A ODT1: SDRAMs D45, D47, D49, D51, D53, D63, D65, D67, D69, D71
BRODT0B ODT1: SDRAMs D37, D39, D41, D43, D55, D57, D59, D61
BPCK0A CK: SDRAMs D[53:44]
BPCK0B CK: SDRAMs D[43:36]
: SDRAMs D[53:44]
: SDRAMs D[43:36]
: SDRAMs D44, D46, D48, D50, D52, D62, D64, D66, D68, D70
: SDRAMs D36, D38, D40, D42, D54, D56, D58, D60
BRCKE1A CKE0: SDRAMs D44, D46, D48, D50, D52, D62, D64, D66, D68, D70
BRCKE1B CKE0: SDRAMs D36, D38, D40, D42, D54, D56, D58, D60
BPCK1A CK: SDRAMs D[71:62]
BPCK1B CK: SDRAMs D[61:54]
: SDRAMs D[71:62]
: SDRAMs D[61:54]
NT1GC72B89A0NL / NT2GC72B8PA0NL
NT4GC72B4NA1NL / NT4GC72B8NA1NL / NT8GTC72B4NA1NL
1GB: 128M x 72 / 2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72
PC3-8500 / PC3-10600
Registered DDR3 SDRAM DIMM
REV 1.1 20
06/2009
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
-BE -CG -BE -CG
0 CRC range, EEPROM bytes, bytes used
CRC Covers Bytes: 0~116,
Total SPD Bytes: 256,
SPD Bytes Used: 176,
CRC Covers Bytes: 0~116,
Total SPD Bytes: 256,
SPD Bytes Used: 176,
92 92
1 SPD revision Revision 1.0 Revision 1.0 10 10
2 DRAM device type DDR3 SDRAM DDR3 SDRAM 0B 0B
3 Module type (form factor) RDIMM RDIMM 01 01
4 SDRAM Device density and banks 8 banks, 1Gb 8 banks, 1Gb 02 02
5 SDRAM device row and column count 14 rows, 10 columns 14 rows, 10 columns 11 11
6 Module minimum nominal voltage 1.5 V 1.5 V 00 00
7 Module ranks and device DQ count 1 ranks, 8 bits 1 ranks, 8 bits 01 01
8 ECC tag and module memory Bus width With ECC, 64bits With ECC, 64bits 0B 0B
9 Fine timebase dividend/divisor (in ps) 2.5ps 2.5ps 52 52
10 Medium timebase dividend 1ns 1ns 01 01
11 Medium timebase divisor 8ns 8ns 08 08
12 Minimum SDRAM cycle time (tCKmin) 1.875ns 1.5ns 0F 0C
13 Reserved Undefined Undefined 00 00
14 CAS latencies supported 6,7,8 6,7,8,9 1C 3C
15 CAS latencies supported Undefined Undefined 00 00
16 Minimum CAS latency time (tAAmin) 13.125ns 13.125ns 69 69
17 Minimum write recovery time (tWRmin) 15ns 15ns 78 78
18 Minimum -to- delay (tRCDmin) 13.125ns 13.125ns 69 69
19 Minimum Row Active to Row Active delay (tRRDmin) 7.5ns 6ns 3C 30
20 Minimum row Precharge delay (tRPmin) 13.125ns 13.125ns 69 69
21 Upper nibble for tRAS and tRC 1,1 1,1 11 11
22 Minimum Active-to-Precharge delay (tRASmin) 37.5ns 36ns 2C 20
23 Minimum Active-to-Active/Refresh delay (tRCmin) 50.625ns 49.125ns 95 89
24 Minimum refresh recovery delay (tRFCmin) LSB (Combo bytes 24,25) (Combo bytes 24,25) 70 70
25 Minimum refresh recovery delay (tRFCmin) MSB 110ns 110ns 03 03
26 Minimum internal Write-to-Read command delay (tWTRmin) 7.5ns 7.5ns 3C 3C
27 Minimum internal Read-to-Precharge command delay (tRTPmin) 7.5ns 7.5ns 3C 3C
28 Minimum four active window delay (tFAWmin) LSB (Combo byte 28, 29) (Combo byte 28, 29) 01 00
29 Minimum four active window delay (tFAWmin) MSB 37.5ns 30ns 2C F0
30 SDRAM device output drivers suported
RZQ / 6,
RZQ / 7,
DLL-Off Mode Support,
RZQ / 6,
RZQ / 7,
DLL-Off Mode Support,
83 83
31 SDRAM device thermal and refresh options
Extended Temperature Range,
ASR,
ODTS,
PASR,
Extended Temperature Range,
ASR,
ODTS,
PASR,
8D 8D
32 Module Thermal Sensor Thermal Sensor Support Thermal Sensor Support 80 80
33 SDRAM Device Type Standard Monolithic Device Standard Monolithic Device 00 00
34-59 Reserved Undefined Undefined -- --
60 Module height (nominal) 29 ＜ height ≦ 30 mm 29 ＜ height ≦ 30 mm 0F 0F
61 Module thickness (Max)
Back: 1 < thickness ≤ 2 mm,
Front: 1 < thickness ≤ 2 mm,
Back: 1 < thickness ≤ 2 mm,
Front: 1 < thickness ≤ 2 mm,
11 11
62 Raw Card ID reference Raw Card A Raw Card A 00 00
63 DRAM address mapping edge connector 1 row, 1 register 1 row, 1 register 05 05
64-116 Reserved Undefined Undefined -- --
117-118 Module manufacture ID Nanya Technology Nanya Technology 830B 830B
119-121 Module manufacturer Information Undefined Undefined -- --
126-127 CRC Calculated Value Calculated Value D6AC 9405
Serial Presence Detect (Part 1 of 2) [NT1GC72B89A0NL, 1GB – 1 Ranks, 128Mx8 DDR3 SDRAMs]
Byte
Description
SPD Entry Value
Serial PD Data Entry (Hex.)
NT1GC72B89A0NL / NT2GC72B8PA0NL
NT4GC72B4NA1NL / NT4GC72B8NA1NL / NT8GTC72B4NA1NL
1GB: 128M x 72 / 2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72
PC3-8500 / PC3-10600
Registered DDR3 SDRAM DIMM
REV 1.1 21
06/2009
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
-BE -CG -BE -CG
128-145 Module part number ASCII values ASCII values -- --
146 Module die revision Undefined Undefined 00 00
147 Module PCB revision Undefined Undefined 00 00
148-149 DRAM device manufacturer ID Nanya Technology Nanya Technology 830B 830B
150-175 Manufacturer reserved Undefined Undefined -- --
176-255 Customer reserved Undefined Undefined -- --
Note1:
NT1GC72B89A0NL-BE -> 4E54314743373242383941304E4C2D424520
NT1GC72B89A0NL-CG -> 4E54314743373242383941304E4C2D434720
Serial Presence Detect (Part 2 of 2) [NT1GC72B89A0NL, 1GB – 1 Ranks, 128Mx8 DDR3 SDRAMs]
Byte
Description
SPD Entry Value
Serial PD Data Entry (Hex.)
NT1GC72B89A0NL / NT2GC72B8PA0NL
NT4GC72B4NA1NL / NT4GC72B8NA1NL / NT8GTC72B4NA1NL
1GB: 128M x 72 / 2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72
PC3-8500 / PC3-10600
Registered DDR3 SDRAM DIMM
REV 1.1 22
06/2009
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
-BE -CG -BE -CG
0 CRC range, EEPROM bytes, bytes used
CRC Covers Bytes: 0~116,
Total SPD Bytes: 256,
SPD Bytes Used: 176,
CRC Covers Bytes: 0~116,
Total SPD Bytes: 256,
SPD Bytes Used: 176,
92 92
1 SPD revision Revision 1.0 Revision 1.0 10 10
2 DRAM device type DDR3 SDRAM DDR3 SDRAM 0B 0B
3 Module type (form factor) RDIMM RDIMM 01 01
4 SDRAM Device density and banks 8 banks, 1Gb 8 banks, 1Gb 02 02
5 SDRAM device row and column count 14 rows, 10 columns 14 rows, 10 columns 11 11
6 Module minimum nominal voltage 1.5 V 1.5 V 00 00
7 Module ranks and device DQ count 2 ranks, 8 bits 2 ranks, 8 bits 09 09
8 ECC tag and module memory Bus width With ECC, 64bits With ECC, 64bits 0B 0B
9 Fine timebase dividend/divisor (in ps) 2.5ps 2.5ps 52 52
10 Medium timebase dividend 1ns 1ns 01 01
11 Medium timebase divisor 8ns 8ns 08 08
12 Minimum SDRAM cycle time (tCKmin) 1.875ns 1.5ns 0F 0C
13 Reserved Undefined Undefined 00 00
14 CAS latencies supported 6,7,8 6,7,8,9 1C 3C
15 CAS latencies supported Undefined Undefined 00 00
16 Minimum CAS latency time (tAAmin) 13.125ns 13.125ns 69 69
17 Minimum write recovery time (tWRmin) 15ns 15ns 78 78
18 Minimum -to- delay (tRCDmin) 13.125ns 13.125ns 69 69
19 Minimum Row Active to Row Active delay (tRRDmin) 7.5ns 6ns 3C 30
20 Minimum row Precharge delay (tRPmin) 13.125ns 13.125ns 69 69
21 Upper nibble for tRAS and tRC 1,1 1,1 11 11
22 Minimum Active-to-Precharge delay (tRASmin) 37.5ns 36ns 2C 20
23 Minimum Active-to-Active/Refresh delay (tRCmin) 50.625ns 49.125ns 95 89
24 Minimum refresh recovery delay (tRFCmin) LSB (Combo bytes 24,25) (Combo bytes 24,25) 70 70
25 Minimum refresh recovery delay (tRFCmin) MSB 110ns 110ns 03 03
26 Minimum internal Write-to-Read command delay (tWTRmin) 7.5ns 7.5ns 3C 3C
27 Minimum internal Read-to-Precharge command delay (tRTPmin) 7.5ns 7.5ns 3C 3C
28 Minimum four active window delay (tFAWmin) LSB (Combo byte 28, 29) (Combo byte 28, 29) 01 00
29 Minimum four active window delay (tFAWmin) MSB 37.5ns 30ns 2C F0
30 SDRAM device output drivers suported
RZQ / 6,
RZQ / 7,
DLL-Off Mode Support,
RZQ / 6,
RZQ / 7,
DLL-Off Mode Support,
83 83
31 SDRAM device thermal and refresh options
Extended Temperature Range,
ASR,
ODTS,
PASR,
Extended Temperature Range,
ASR,
ODTS,
PASR,
8D 8D
32 Module Thermal Sensor Thermal Sensor Support Thermal Sensor Support 80 80
33 SDRAM Device Type Standard Monolithic Device Standard Monolithic Device 00 00
34-59 Reserved Undefined Undefined -- --
60 Module height (nominal) 29 ＜ height ≦ 30 mm 29 ＜ height ≦ 30 mm 0F 0F
61 Module thickness (Max)
Back: 1 < thickness ≤ 2 mm,
Front: 1 < thickness ≤ 2 mm,
Back: 1 < thickness ≤ 2 mm,
Front: 1 < thickness ≤ 2 mm,
11 11
62 Raw Card ID reference Raw Card B Raw Card B 01 01
63 DRAM address mapping edge connector 1 row, 1 register 1 row, 1 register 05 05
64-116 Reserved Undefined Undefined -- --
117-118 Module manufacture ID Nanya Technology Nanya Technology 830B 830B
119-121 Module manufacturer Information Undefined Undefined -- --
126-127 CRC Calculated Value Calculated Value 24C4 666D
Serial Presence Detect (Part 1 of 2) [NT2GC72B8PA0NL, 2GB – 2 Ranks, 128Mx8 DDR3 SDRAMs]
Byte
Description
SPD Entry Value
Serial PD Data Entry (Hex.)
NT1GC72B89A0NL / NT2GC72B8PA0NL
NT4GC72B4NA1NL / NT4GC72B8NA1NL / NT8GTC72B4NA1NL
1GB: 128M x 72 / 2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72
PC3-8500 / PC3-10600
Registered DDR3 SDRAM DIMM
REV 1.1 23
06/2009
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
-BE -CG -BE -CG
128-145 Module part number ASCII values ASCII values -- --
146 Module die revision Undefined Undefined 00 00
147 Module PCB revision Undefined Undefined 00 00
148-149 DRAM device manufacturer ID Nanya Technology Nanya Technology 830B 830B
150-175 Manufacturer reserved Undefined Undefined -- --
176-255 Customer reserved Undefined Undefined -- --
Note1:
NT2GC72B8PA0NL-BE -> 4E54324743373242385041304E4C2D424520
NT2GC72B8PA0NL-CG -> 4E54324743373242385041304E4C2D434720
Serial Presence Detect (Part 2 of 2) [NT2GC72B8PA0NL, 2GB – 2 Ranks, 128Mx8 DDR3 SDRAMs]
Byte
Description
SPD Entry Value
Serial PD Data Entry (Hex.)
NT1GC72B89A0NL / NT2GC72B8PA0NL
NT4GC72B4NA1NL / NT4GC72B8NA1NL / NT8GTC72B4NA1NL
1GB: 128M x 72 / 2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72
PC3-8500 / PC3-10600
Registered DDR3 SDRAM DIMM
REV 1.1 24
06/2009
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
-BE -CG -BE -CG
0 CRC range, EEPROM bytes, bytes used
CRC Covers Bytes: 0~116,
Total SPD Bytes: 256,
SPD Bytes Used: 176,
CRC Covers Bytes: 0~116,
Total SPD Bytes: 256,
SPD Bytes Used: 176,
92 92
1 SPD revision Revision 1.0 Revision 1.0 10 10
2 DRAM device type DDR3 SDRAM DDR3 SDRAM 0B 0B
3 Module type (form factor) RDIMM RDIMM 01 01
4 SDRAM Device density and banks 8 banks, 1Gb 8 banks, 1Gb 02 02
5 SDRAM device row and column count 14 rows, 10 columns 14 rows, 10 columns 11 11
6 Module minimum nominal voltage 1.5 V 1.5 V 00 00
7 Module ranks and device DQ count 4 ranks, 8 bits 4 ranks, 8 bits 19 19
8 ECC tag and module memory Bus width With ECC, 64bits With ECC, 64bits 0B 0B
9 Fine timebase dividend/divisor (in ps) 2.5ps 2.5ps 52 52
10 Medium timebase dividend 1ns 1ns 01 01
11 Medium timebase divisor 8ns 8ns 08 08
12 Minimum SDRAM cycle time (tCKmin) 1.875ns 1.5ns 0F 0C
13 Reserved Undefined Undefined 00 00
14 CAS latencies supported 6,7,8 6,7,8,9 1C 3C
15 CAS latencies supported Undefined Undefined 00 00
16 Minimum CAS latency time (tAAmin) 13.125ns 13.125ns 69 69
17 Minimum write recovery time (tWRmin) 15ns 15ns 78 78
18 Minimum -to- delay (tRCDmin) 13.125ns 13.125ns 69 69
19 Minimum Row Active to Row Active delay (tRRDmin) 7.5ns 6ns 3C 30
20 Minimum row Precharge delay (tRPmin) 13.125ns 13.125ns 69 69
21 Upper nibble for tRAS and tRC 1,1 1,1 11 11
22 Minimum Active-to-Precharge delay (tRASmin) 37.5ns 36ns 2C 20
23 Minimum Active-to-Active/Refresh delay (tRCmin) 50.625ns 49.125ns 95 89
24 Minimum refresh recovery delay (tRFCmin) LSB (Combo bytes 24,25) (Combo bytes 24,25) 70 70
25 Minimum refresh recovery delay (tRFCmin) MSB 110ns 110ns 03 03
26 Minimum internal Write-to-Read command delay (tWTRmin) 7.5ns 7.5ns 3C 3C
27 Minimum internal Read-to-Precharge command delay (tRTPmin) 7.5ns 7.5ns 3C 3C
28 Minimum four active window delay (tFAWmin) LSB (Combo byte 28, 29) (Combo byte 28, 29) 01 00
29 Minimum four active window delay (tFAWmin) MSB 37.5ns 30ns 2C F0
30 SDRAM device output drivers suported
RZQ / 6,
RZQ / 7,
DLL-Off Mode Support,
RZQ / 6,
RZQ / 7,
DLL-Off Mode Support,
83 83
31 SDRAM device thermal and refresh options
Extended Temperature Range,
ASR,
ODTS,
PASR,
Extended Temperature Range,
ASR,
ODTS,
PASR,
8D 8D
32 Module Thermal Sensor Thermal Sensor Support Thermal Sensor Support 80 80
33 SDRAM Device Type Standard Monolithic Device Standard Monolithic Device 00 00
34-59 Reserved Undefined Undefined -- --
60 Module height (nominal) 29 ＜ height ≦ 30 mm 29 ＜ height ≦ 30 mm 0F 0F
61 Module thickness (Max)
Back: 3 < thickness ≤ 4 mm,
Front: 3 < thickness ≤ 4 mm,
Back: 3 < thickness ≤ 4 mm,
Front: 3 < thickness ≤ 4 mm,
33 33
62 Raw Card ID reference Raw Card H Raw Card H 07 07
63 DRAM address mapping edge connector 2 rows, 1 register 2 rows, 1 register 09 09
64-116 Reserved Undefined Undefined -- --
117-118 Module manufacture ID Nanya Technology Nanya Technology 830B 830B
119-121 Module manufacturer Information Undefined Undefined -- --
126-127 CRC Calculated Value Calculated Value E6F3 A45A
Serial Presence Detect (Part 1 of 2) [NT4GC72B8NA1NL, 4GB – 4 Ranks, 128Mx8 DDR3 SDRAMs]
Byte
Description
SPD Entry Value
Serial PD Data Entry (Hex.)
NT1GC72B89A0NL / NT2GC72B8PA0NL
NT4GC72B4NA1NL / NT4GC72B8NA1NL / NT8GTC72B4NA1NL
1GB: 128M x 72 / 2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72
PC3-8500 / PC3-10600
Registered DDR3 SDRAM DIMM
REV 1.1 25
06/2009
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
-BE -CG -BE -CG
128-145 Module part number ASCII values ASCII values -- --
146 Module die revision Undefined Undefined 00 00
147 Module PCB revision Undefined Undefined 00 00
148-149 DRAM device manufacturer ID Nanya Technology Nanya Technology 830B 830B
150-175 Manufacturer reserved Undefined Undefined -- --
176-255 Customer reserved Undefined Undefined -- --
Note1:
NT4GC72B8NA1NL-BE -> 4E54344743373242384E41314E4C2D424520
NT4GC72B8NA1NL-CG -> 4E54344743373242384E41314E4C2D434720
Serial Presence Detect (Part 2 of 2) [NT4GC72B8NA1NL, 4GB – 4 Ranks, 128Mx8 DDR3 SDRAMs]
Byte
Description
SPD Entry Value
Serial PD Data Entry (Hex.)
NT1GC72B89A0NL / NT2GC72B8PA0NL
NT4GC72B4NA1NL / NT4GC72B8NA1NL / NT8GTC72B4NA1NL
1GB: 128M x 72 / 2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72
PC3-8500 / PC3-10600
Registered DDR3 SDRAM DIMM
REV 1.1 26
06/2009
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
-BE -CG -BE -CG
0 CRC range, EEPROM bytes, bytes used
CRC Covers Bytes: 0~116,
Total SPD Bytes: 256,
SPD Bytes Used: 176,
CRC Covers Bytes: 0~116,
Total SPD Bytes: 256,
SPD Bytes Used: 176,
92 92
1 SPD revision Revision 1.0 Revision 1.0 10 10
2 DRAM device type DDR3 SDRAM DDR3 SDRAM 0B 0B
3 Module type (form factor) RDIMM RDIMM 01 01
4 SDRAM Device density and banks 8 banks, 1Gb 8 banks, 1Gb 02 02
5 SDRAM device row and column count 14 rows, 11 columns 14 rows, 11 columns 12 12
6 Module minimum nominal voltage 1.5 V 1.5 V 00 00
7 Module ranks and device DQ count 2 ranks, 4 bits 2 ranks, 4 bits 08 08
8 ECC tag and module memory Bus width With ECC, 64bits With ECC, 64bits 0B 0B
9 Fine timebase dividend/divisor (in ps) 2.5ps 2.5ps 52 52
10 Medium timebase dividend 1ns 1ns 01 01
11 Medium timebase divisor 8ns 8ns 08 08
12 Minimum SDRAM cycle time (tCKmin) 1.875ns 1.5ns 0F 0C
13 Reserved Undefined Undefined 00 00
14 CAS latencies supported 6,7,8 6,7,8,9 1C 3C
15 CAS latencies supported Undefined Undefined 00 00
16 Minimum CAS latency time (tAAmin) 13.125ns 13.125ns 69 69
17 Minimum write recovery time (tWRmin) 15ns 15ns 78 78
18 Minimum -to- delay (tRCDmin) 13.125ns 13.125ns 69 69
19 Minimum Row Active to Row Active delay (tRRDmin) 7.5ns 6ns 3C 30
20 Minimum row Precharge delay (tRPmin) 13.125ns 13.125ns 69 69
21 Upper nibble for tRAS and tRC 1,1 1,1 11 11
22 Minimum Active-to-Precharge delay (tRASmin) 37.5ns 36ns 2C 20
23 Minimum Active-to-Active/Refresh delay (tRCmin) 50.625ns 49.125ns 95 89
24 Minimum refresh recovery delay (tRFCmin) LSB (Combo bytes 24,25) (Combo bytes 24,25) 70 70
25 Minimum refresh recovery delay (tRFCmin) MSB 110ns 110ns 03 03
26 Minimum internal Write-to-Read command delay (tWTRmin) 7.5ns 7.5ns 3C 3C
27 Minimum internal Read-to-Precharge command delay (tRTPmin) 7.5ns 7.5ns 3C 3C
28 Minimum four active window delay (tFAWmin) LSB (Combo byte 28, 29) (Combo byte 28, 29) 01 00
29 Minimum four active window delay (tFAWmin) MSB 37.5ns 30ns 2C F0
30 SDRAM device output drivers suported
RZQ / 6,
RZQ / 7,
DLL-Off Mode Support,
RZQ / 6,
RZQ / 7,
DLL-Off Mode Support,
83 83
31 SDRAM device thermal and refresh options
Extended Temperature Range,
ASR,
ODTS,
PASR,
Extended Temperature Range,
ASR,
ODTS,
PASR,
8D 8D
32 Module Thermal Sensor Thermal Sensor Support Thermal Sensor Support 80 80
33 SDRAM Device Type Standard Monolithic Device Standard Monolithic Device 00 00
34-59 Reserved Undefined Undefined -- --
60 Module height (nominal) 29 ＜ height ≦ 30 mm 29 ＜ height ≦ 30 mm 0F 0F
61 Module thickness (Max)
Back: 3 < thickness ≤ 4 mm,
Front: 3 < thickness ≤ 4 mm,
Back: 3 < thickness ≤ 4 mm,
Front: 3 < thickness ≤ 4 mm,
33 33
62 Raw Card ID reference Raw Card E Raw Card E 04 04
63 DRAM address mapping edge connector 2 rows, 1 register 2 rows, 1 register 09 09
64-116 Reserved Undefined Undefined -- --
117-118 Module manufacture ID Nanya Technology Nanya Technology 830B 830B
119-121 Module manufacturer Information Undefined Undefined -- --
126-127 CRC Calculated Value Calculated Value D041 92E8
Serial Presence Detect (Part 1 of 2) [NT4GC72B4NA1NL, 4GB – 2 Ranks, 256Mx4 DDR3 SDRAMs]
Byte
Description
SPD Entry Value
Serial PD Data Entry (Hex.)
NT1GC72B89A0NL / NT2GC72B8PA0NL
NT4GC72B4NA1NL / NT4GC72B8NA1NL / NT8GTC72B4NA1NL
1GB: 128M x 72 / 2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72
PC3-8500 / PC3-10600
Registered DDR3 SDRAM DIMM
REV 1.1 27
06/2009
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
-BE -CG -BE -CG
128-145 Module part number ASCII values ASCII values -- --
146 Module die revision Undefined Undefined 00 00
147 Module PCB revision Undefined Undefined 00 00
148-149 DRAM device manufacturer ID Nanya Technology Nanya Technology 830B 830B
150-175 Manufacturer reserved Undefined Undefined -- --
176-255 Customer reserved Undefined Undefined -- --
Note1:
NT4GC72B4NA1NL-BE -> 4E54344743373242344E41314E4C2D424520
NT4GC72B4NA1NL-CG -> 4E54344743373242344E41314E4C2D434720
Serial Presence Detect (Part 2 of 2) [NT4GC72B4NA1NL, 4GB – 2 Ranks, 256Mx4 DDR3 SDRAMs]
Byte
Description
SPD Entry Value
Serial PD Data Entry (Hex.)
NT1GC72B89A0NL / NT2GC72B8PA0NL
NT4GC72B4NA1NL / NT4GC72B8NA1NL / NT8GTC72B4NA1NL
1GB: 128M x 72 / 2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72
PC3-8500 / PC3-10600
Registered DDR3 SDRAM DIMM
REV 1.1 28
06/2009
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
-BE -CG -BE -CG
0 CRC range, EEPROM bytes, bytes used
CRC Covers Bytes: 0~116,
Total SPD Bytes: 256,
SPD Bytes Used: 176,
CRC Covers Bytes: 0~116,
Total SPD Bytes: 256,
SPD Bytes Used: 176,
92 92
1 SPD revision Revision 1.0 Revision 1.0 10 10
2 DRAM device type DDR3 SDRAM DDR3 SDRAM 0B 0B
3 Module type (form factor) RDIMM RDIMM 01 01
4 SDRAM Device density and banks 8 banks, 1Gb 8 banks, 1Gb 02 02
5 SDRAM device row and column count 14 rows, 11 columns 14 rows, 11 columns 12 12
6 Module minimum nominal voltage 1.5 V 1.5 V 00 00
7 Module ranks and device DQ count 4 ranks, 4 bits 4 ranks, 4 bits 18 18
8 ECC tag and module memory Bus width With ECC, 64bits With ECC, 64bits 0B 0B
9 Fine timebase dividend/divisor (in ps) 2.5ps 2.5ps 52 52
10 Medium timebase dividend 1ns 1ns 01 01
11 Medium timebase divisor 8ns 8ns 08 08
12 Minimum SDRAM cycle time (tCKmin) 1.875ns 1.5ns 0F 0C
13 Reserved Undefined Undefined 00 00
14 CAS latencies supported 6,7,8 6,7,8,9 1C 3C
15 CAS latencies supported Undefined Undefined 00 00
16 Minimum CAS latency time (tAAmin) 13.125ns 13.125ns 69 69
17 Minimum write recovery time (tWRmin) 15ns 15ns 78 78
18 Minimum -to- delay (tRCDmin) 13.125ns 13.125ns 69 69
19 Minimum Row Active to Row Active delay (tRRDmin) 7.5ns 6ns 3C 30
20 Minimum row Precharge delay (tRPmin) 13.125ns 13.125ns 69 69
21 Upper nibble for tRAS and tRC 1,1 1,1 11 11
22 Minimum Active-to-Precharge delay (tRASmin) 37.5ns 36ns 2C 20
23 Minimum Active-to-Active/Refresh delay (tRCmin) 50.625ns 49.125ns 95 89
24 Minimum refresh recovery delay (tRFCmin) LSB (Combo bytes 24,25) (Combo bytes 24,25) 70 70
25 Minimum refresh recovery delay (tRFCmin) MSB 110ns 110ns 03 03
26 Minimum internal Write-to-Read command delay (tWTRmin) 7.5ns 7.5ns 3C 3C
27 Minimum internal Read-to-Precharge command delay (tRTPmin) 7.5ns 7.5ns 3C 3C
28 Minimum four active window delay (tFAWmin) LSB (Combo byte 28, 29) (Combo byte 28, 29) 01 00
29 Minimum four active window delay (tFAWmin) MSB 37.5ns 30ns 2C F0
30 SDRAM device output drivers suported
RZQ / 6,
RZQ / 7,
DLL-Off Mode Support,
RZQ / 6,
RZQ / 7,
DLL-Off Mode Support,
83 83
31 SDRAM device thermal and refresh options
Extended Temperature Range,
ASR,
ODTS,
PASR,
Extended Temperature Range,
ASR,
ODTS,
PASR,
8D 8D
32 Module Thermal Sensor Thermal Sensor Support Thermal Sensor Support 80 80
33 SDRAM Device Type Dual Die Package Dual Die Package 80 80
34-59 Reserved Undefined Undefined -- --
60 Module height (nominal) 29 ＜ height ≦ 30 mm 29 ＜ height ≦ 30 mm 0F 0F
61 Module thickness (Max)
Back: 3 < thickness ≤ 4 mm,
Front: 3 < thickness ≤ 4 mm,
Back: 3 < thickness ≤ 4 mm,
Front: 3 < thickness ≤ 4 mm,
33 33
62 Raw Card ID reference Raw Card F Raw Card F 05 05
63 DRAM address mapping edge connector 2 rows, 2 registers 2 rows, 2 registers 0A 0A
64-116 Reserved Undefined Undefined -- --
117-118 Module manufacture ID Nanya Technology Nanya Technology 830B 830B
119-121 Module manufacturer Information Undefined Undefined -- --
126-127 CRC Calculated Value Calculated Value 132C 5185
Serial Presence Detect (Part 1 of 2) [NT8GTC72B4NA1NL, 8GB – 4 Ranks, 512Mx4 DDR3 SDRAMs]
Byte
Description
SPD Entry Value
Serial PD Data Entry (Hex.)
NT1GC72B89A0NL / NT2GC72B8PA0NL
NT4GC72B4NA1NL / NT4GC72B8NA1NL / NT8GTC72B4NA1NL
1GB: 128M x 72 / 2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72
PC3-8500 / PC3-10600
Registered DDR3 SDRAM DIMM
REV 1.1 29
06/2009
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
-BE -CG -BE -CG
128-145 Module part number ASCII values ASCII values -- --
146 Module die revision Undefined Undefined 00 00
147 Module PCB revision Undefined Undefined 00 00
148-149 DRAM device manufacturer ID Nanya Technology Nanya Technology 830B 830B
150-175 Manufacturer reserved Undefined Undefined -- --
176-255 Customer reserved Undefined Undefined -- --
Note1:
NT8GTC72B4NA1NL-BE -> 4E5438475443373242344E41314E4C2D4245
NT8GTC72B4NA1NL-CG -> 4E5438475443373242344E41314E4C2D4347
Serial Presence Detect (Part 2 of 2) [NT8GTC72B4NA1NL, 8GB – 4 Ranks, 512Mx4 DDR3 SDRAMs]
Byte
Description
SPD Entry Value
Serial PD Data Entry (Hex.)
NT1GC72B89A0NL / NT2GC72B8PA0NL
NT4GC72B4NA1NL / NT4GC72B8NA1NL / NT8GTC72B4NA1NL
1GB: 128M x 72 / 2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72
PC3-8500 / PC3-10600
Registered DDR3 SDRAM DIMM
REV 1.1 30
06/2009
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
Environmental Requirements
Symbol
Parameter
Rating
Units
Note
TOPR
Module Operating Temperature Range (ambient)
0 to 55
°C
3
HOPR
Operating Humidity (relative)
10 to 90
%
1
TSTG
Storage Temperature (Plastic)
-55 to 100
°C
1
HSTG
Storage Humidity (without condensation)
5 to 95
%
1
PBAR
Barometric Pressure (operating & storage)
105 to 69
K Pascal
1, 2
Note:
1. Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only and device functional
operation at or above the conditions indicated is not implied. Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
2. Up to 9850 ft.
3. The component maximum case temperature shall not exceed the value specified in the component spec.
Absolute Maximum DC Ratings
Symbol
Parameter
Rating
Units
Note
VDD
Voltage on VDD pins relative to Vss
-0.4 V ~ 1.975 V
V
1, 3
VDDQ
Voltage on VDDQ pins relative to Vss
-0.4 V ~ 1.975 V
V
1, 3
VIN, VOUT
Voltage on I/O pins relative to Vss
-0.4 V ~ 1.975 V
V
1
TSTG
Storage Temperature
-55 to +100
°C
1, 2
Note:
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability
2. Storage Temperature is the case surface temperature on the center/top side of the DRAM.
3. VDD and VDDQ must be within 300 mV of each other at all times;and VREF must be not greater
Operating temperature Conditions
Symbol
Parameter
Rating
Units
Note
TOPER
Normal Operating Temperature Range
0 to 85
°C
1, 2
Extended Temperature Range (Optional)
85 to 95
°C
1, 3
Note:
1. Operating Temperature TOPER is the case surface temperature on the center / top side of the DRAM.
2. The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported. During operation, the
DRAM case temperature must be maintained between 0 to 85 °C under all operating conditions
3. Some applications require operation of the DRAM in the Extended Temperature Range between 85 °C and 95 °C case temperature. Full
specifications are supported in this range, but the following additional conditions apply:
a) Refresh commands must be doubled in frequency, therefore reducing the Refresh interval tREFI to 3.9 μs. It is also possible to specify
a component with 1X refresh (tREFI to 7.8μs) in the Extended Temperature Range. Please refer to supplier data sheet and/or the
DIMM SPD for option availability.
b) If Self-Refresh operation is required in the Extended Temperature Range, then it is mandatory to either use the Manual Self-Refresh
mode with Extended Temperature Range capability (MR2 A6 = 0b and MR2 A7 = 1b) or enable the optional Auto Self-Refresh mode
(MR2 A6 = 1b and MR2 A7 = 0b). Please refer to the supplier data sheet and/or the DIMM SPD for Auto Self-Refresh option
availability, Extended Temperature Range support and tREFI requirements in the Extended Temperature Range.
NT1GC72B89A0NL / NT2GC72B8PA0NL
NT4GC72B4NA1NL / NT4GC72B8NA1NL / NT8GTC72B4NA1NL
1GB: 128M x 72 / 2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72
PC3-8500 / PC3-10600
Registered DDR3 SDRAM DIMM
REV 1.1 31
06/2009
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
DC Electrical Characteristics and Operating Conditions
Symbol
Parameter
Min
Typ
Max
Units
Notes
VDD
Supply Voltage
1.425
1.5
1.575
V
1,2
VDDQ
Output Supply Voltage
1.425
1.5
1.575
V
1,2
Note:
1. Under all conditions VDDQ must be less than or equal to VDD.
2. VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together.
Single-Ended AC and DC Input Levels for Command and Address
Symbol
Parameter
DDR3-1066 (-BE)
DDR3-1333 (-CG)
Units
Note
Min.
Max.
Min.
Max.
VIH.CA(DC)
DC Input Logic High
Vref + 0.100
VDD
Vref + 0.100
VDD
V
1
VIL.CA(DC)
DC Input Logic Low
VSS
Vref - 0.100
VSS
Vref - 0.100
V
1
VIH.CA(AC)
AC Input Logic High
Vref + 0.175
Note 2
Vref + 0.175
Note 2
V
1, 2
VIL.CA(AC)
AC Input Logic Low
Note 2
Vref - 0.175
Note 2
Vref - 0.175
V
1, 2
VIH.CA(AC150)
AC Input Logic High
-
-
Vref + 0.15
Note 2
V
1, 2
VIL.CA(AC150)
AC Input Logic Low
-
-
Note 2
Vref - 0.15
V
1, 2
VRefCA(DC)
Reference Voltage for
ADD, CMD Inputs
0.49 x VDD
0.51 x VDD
0.49 x VDD
0.51 x VDD
V
3, 4
Note:
1. For input only pins except . Vref = VrefCA(DC).
2. See “Overshoot and Undershoot Specifications” in the device datasheet.
3. The ac peak noise on VRef may not allow VRef to deviate from VRefDQ(DC) by more than +/-1% VDD (for reference: approx. +/- 15 mV).
4. For reference: approx. VDD/2 +/- 15 mV.
Single-Ended AC and DC Input Levels for DQ and DM
Symbol
Parameter
DDR3-1066 (-BE)
DDR3-1333 (-CG)
Units
Note
Min.
Max.
Min.
Max.
VIH.DQ(DC)
DC Input Logic High
Vref + 0.100
VDD
Vref + 0.100
VDD
V
1
VIL.DQ(DC)
DC Input Logic Low
VSS
Vref - 0.100
VSS
Vref - 0.100
V
1
VIH.DQ(AC)
AC Input Logic High
Vref + 0.175
Note 2
Vref + 0.15
Note 2
V
1, 2, 5
VIL.DQ(AC)
AC Input Logic Low
Note 2
Vref - 0.175
Note 2
Vref - 0.15
V
1, 2, 5
VRefDQ(DC)
Reference Voltage for
DQ, DM Inputs
0.49 x VDD
0.51 x VDD
0.49 x VDD
0.51 x VDD
V
3, 4
Note:
1. For input only pins except . Vref = VrefDQ(DC).
2. See “Overshoot and Undershoot Specifications” in the device datasheet.
3. The ac peak noise on VRef may not allow VRef to deviate from VRefDQ(DC) by more than +/-1% VDD (for reference: approx. +/- 15 mV).
4. For reference: approx. VDD/2 +/- 15 mV.
5. Single-ended swing requirement for DQS, DQS# is 350 mV (peak to peak). Differential swing requirement for DQS - DQS# is 700 mV
(peak to peak).
NT1GC72B89A0NL / NT2GC72B8PA0NL
NT4GC72B4NA1NL / NT4GC72B8NA1NL / NT8GTC72B4NA1NL
1GB: 128M x 72 / 2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72
PC3-8500 / PC3-10600
Registered DDR3 SDRAM DIMM
REV 1.1 32
06/2009
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
Operating, Standby, and Refresh Currents
TCASE = 0 °C ~ 85 °C; VDDQ = VDD = 1.5V ± 0.075V [1GB – 1 Rank, 128Mx8 DDR3 SDRAMs]
Symbol
Parameter/Condition
PC3-8500
(-BE)
PC3-10600
(-CG)
Unit
IDD0
Operating One Bank Active-Precharge Current
743
842
mA
IDD1
Operating One Bank Active-Read-Precharge Current
891
990
mA
IDD2P0
Precharge Power-Down Current Slow Exit
139
139
mA
IDD2P1
Precharge Power-Down Current Fast Exit
297
327
mA
IDD2Q
Precharge Quiet Standby Current
545
594
mA
IDD2N
Precharge Standby Current
446
495
mA
IDD3P
Active Power-Down Current
327
347
mA
IDD3N
Active Standby Current
545
644
mA
IDD4R
Operating Burst Read Current
1584
1980
mA
IDD4W
Operating Burst Write Current
1337
1683
mA
IDD5B
Burst Refresh Current
1782
2228
mA
IDD6
Self Refresh Current: Normal Temperature Range
119
119
mA
IDD7
Operating Bank Interleave Read Current
2178
2574
mA
Operating, Standby, and Refresh Currents
TCASE = 0 °C ~ 85 °C; VDDQ = VDD = 1.5V ± 0.075V [2GB – 2 Ranks, 128Mx8 DDR3 SDRAMs]
Symbol
Parameter/Condition
PC3-8500
(-BE)
PC3-10600
(-CG)
Unit
IDD0
Operating One Bank Active-Precharge Current
1287
1485
mA
IDD1
Operating One Bank Active-Read-Precharge Current
1436
1634
mA
IDD2P0
Precharge Power-Down Current Slow Exit
277
277
mA
IDD2P1
Precharge Power-Down Current Fast Exit
594
653
mA
IDD2Q
Precharge Quiet Standby Current
1089
1188
mA
IDD2N
Precharge Standby Current
891
990
mA
IDD3P
Active Power-Down Current
653
693
mA
IDD3N
Active Standby Current
1089
1287
mA
IDD4R
Operating Burst Read Current
2129
2624
mA
IDD4W
Operating Burst Write Current
1881
2327
mA
IDD5B
Burst Refresh Current
2327
2871
mA
IDD6
Self Refresh Current: Normal Temperature Range
238
238
mA
IDD7
Operating Bank Interleave Read Current
2723
3218
mA
NT1GC72B89A0NL / NT2GC72B8PA0NL
NT4GC72B4NA1NL / NT4GC72B8NA1NL / NT8GTC72B4NA1NL
1GB: 128M x 72 / 2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72
PC3-8500 / PC3-10600
Registered DDR3 SDRAM DIMM
REV 1.1 33
06/2009
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
Operating, Standby, and Refresh Currents
TCASE = 0 °C ~ 85 °C; VDDQ = VDD = 1.5V ± 0.075V [4GB – 4 Ranks, 128Mx8 DDR3 SDRAMs]
Symbol
Parameter/Condition
PC3-8500
(-BE)
PC3-10600
(-CG)
Unit
IDD0
Operating One Bank Active-Precharge Current
2376
2772
mA
IDD1
Operating One Bank Active-Read-Precharge Current
2525
2921
mA
IDD2P0
Precharge Power-Down Current Slow Exit
554
554
mA
IDD2P1
Precharge Power-Down Current Fast Exit
1188
1307
mA
IDD2Q
Precharge Quiet Standby Current
2178
2376
mA
IDD2N
Precharge Standby Current
1782
1980
mA
IDD3P
Active Power-Down Current
1307
1386
mA
IDD3N
Active Standby Current
2178
2574
mA
IDD4R
Operating Burst Read Current
3218
3911
mA
IDD4W
Operating Burst Write Current
2970
3614
mA
IDD5B
Burst Refresh Current
3416
4158
mA
IDD6
Self Refresh Current: Normal Temperature Range
475
475
mA
IDD7
Operating Bank Interleave Read Current
3812
4505
mA
Operating, Standby, and Refresh Currents
TCASE = 0 °C ~ 85 °C; VDDQ = VDD = 1.5V ± 0.075V [4GB – 2 Ranks, 256Mx4 DDR3 SDRAMs]
Symbol
Parameter/Condition
PC3-8500
(-BE)
PC3-10600
(-CG)
Unit
IDD0
Operating One Bank Active-Precharge Current
2574
2970
mA
IDD1
Operating One Bank Active-Read-Precharge Current
2871
3267
mA
IDD2P0
Precharge Power-Down Current Slow Exit
554
554
mA
IDD2P1
Precharge Power-Down Current Fast Exit
1188
1307
mA
IDD2Q
Precharge Quiet Standby Current
2178
2376
mA
IDD2N
Precharge Standby Current
1782
1980
mA
IDD3P
Active Power-Down Current
1307
1386
mA
IDD3N
Active Standby Current
2178
2574
mA
IDD4R
Operating Burst Read Current
4257
5247
mA
IDD4W
Operating Burst Write Current
3762
4653
mA
IDD5B
Burst Refresh Current
4653
5742
mA
IDD6
Self Refresh Current: Normal Temperature Range
475
475
mA
IDD7
Operating Bank Interleave Read Current
5049
6039
mA
NT1GC72B89A0NL / NT2GC72B8PA0NL
NT4GC72B4NA1NL / NT4GC72B8NA1NL / NT8GTC72B4NA1NL
1GB: 128M x 72 / 2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72
PC3-8500 / PC3-10600
Registered DDR3 SDRAM DIMM
REV 1.1 34
06/2009
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
Operating, Standby, and Refresh Currents
TCASE = 0 °C ~ 85 °C; VDDQ = VDD = 1.5V ± 0.075V [8GB – 4 Ranks, 512Mx4 (DDP) DDR3 SDRAMs]
Symbol
Parameter/Condition
PC3-8500
(-BE)
PC3-10600
(-CG)
Unit
IDD0
Operating One Bank Active-Precharge Current
4752
5544
mA
IDD1
Operating One Bank Active-Read-Precharge Current
5049
5841
mA
IDD2P0
Precharge Power-Down Current Slow Exit
1109
1109
mA
IDD2P1
Precharge Power-Down Current Fast Exit
2376
2614
mA
IDD2Q
Precharge Quiet Standby Current
4356
4752
mA
IDD2N
Precharge Standby Current
3564
3960
mA
IDD3P
Active Power-Down Current
2614
2772
mA
IDD3N
Active Standby Current
4356
5148
mA
IDD4R
Operating Burst Read Current
6435
7821
mA
IDD4W
Operating Burst Write Current
5940
7227
mA
IDD5B
Burst Refresh Current
6831
8316
mA
IDD6
Self Refresh Current: Normal Temperature Range
950
950
mA
IDD7
Operating Bank Interleave Read Current
7227
8613
mA
NT1GC72B89A0NL / NT2GC72B8PA0NL
NT4GC72B4NA1NL / NT4GC72B8NA1NL / NT8GTC72B4NA1NL
1GB: 128M x 72 / 2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72
PC3-8500 / PC3-10600
Registered DDR3 SDRAM DIMM
REV 1.1 35
06/2009
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
Speed Bins
Symbol min max min max
tAA 13.125 20 13.5 20 ns
tRCD 13.125 -13.5 -ns
tRP 13.125 -13.5 -ns
tRC 50.625 -49.5 -ns
tRAS 37.5 9*tREFI 36 9*tREFI ns
CL CWL
5 tCK(avg) 2.5 3.3 2.5 3.3 ns
6 tCK(avg) ns
7,8 tCK(avg) ns
5 tCK(avg) ns
6 tCK(avg) 1.875 <2.5 ns
7,8 tCK(avg) ns
5 tCK(avg) ns
6 tCK(avg) 1.875 <2.5 1.875 <2.5 ns
7 tCK(avg) ns
5,6 tCK(avg) ns
7 tCK(avg) 1.5 <1.875 ns
8 tCK(avg) ns
nCK
nCK
Supported CL settings
Reserved
Reserved
7-7-7
Supported CWL settings
DDR3-1066 (-BE)
CL-nRCD-nRP
6,7,8
5,6
DDR3-1333 (-CG)
9-9-9
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
6,8,9
5,6,7
Reserved
Reserved
ACT to ACT or REF command period
ACT to PRE command period
Parameter
Internal read command to first data
ACT to internal read or write delay
PRE command period
Unit
Speed Bin
6
7
8
9
NT1GC72B89A0NL / NT2GC72B8PA0NL
NT4GC72B4NA1NL / NT4GC72B8NA1NL / NT8GTC72B4NA1NL
1GB: 128M x 72 / 2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72
PC3-8500 / PC3-10600
Registered DDR3 SDRAM DIMM
REV 1.1 36
06/2009
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
AC Timing Specifications for DDR3 SDRAM Devices Used on Module
Unit
min max min max
Clock Timing
tCK(DLL_OF
Minimum Clock Cycle Time (DLL off mode) 8 - 8 - ns
tCK(avg)
Average Clock Period(Refer to "Standard Speed
tCH(avg) Average high pulse width 0.47 0.53 0.47 0.53 tCK(avg)
tCL(avg) Average low pulse width 0.47 0.53 0.47 0.53 tCK(avg)
tCK(abs) Absolute Clock Period
tCK(avg)min
+
tJIT(per)min
tCK(avg)ma
x +
tJIT(per)ma
tCK(avg)min
+
tJIT(per)min
tCK(avg)ma
x +
tJIT(per)ma
ps
tCH(abs) Absolute high pulse width 0.43 -0.43 -tCK(avg)
tCL(abs) Absolute low pulse width 0.43 -0.43 -tCK(avg)
JIT(per) Clock Period Jitter -90 90 -80 80 ps
tJIT(per,lck) Clock Period Jitter during DLL locking period -80 80 -70 70 ps
tJIT(cc) Cycle to Clcyle Period Jitter ps
tJIT(cc,lck) Cycle to Cycle Period Jitter ps
tERR(2per) Cumulative error accross 2 cycles -132 132 -118 118 ps
tERR(3per) Cumulative error accross 3 cycles -157 157 -140 140 ps
tERR(4per) Cumulative error accross 4cycles -175 175 -155 155 ps
tERR(5per) Cumulative error accross 5cycles -188 188 -168 168 ps
tERR(6per) Cumulative error accross 6 cycles -200 200 -177 177 ps
tERR(7per) Cumulative error accross 7 cycles -209 209 -186 186 ps
tERR(8per) Cumulative error accross 8 cycles -217 217 -193 193 ps
tERR(9per) Cumulative error accross 9 cycles -224 224 -200 200 ps
tERR(10per) Cumulative error accross 10 cycles -231 231 -205 205 ps
tERR(11per) Cumulative error accross 11 cycles -237 237 -210 210 ps
tERR(12per) Cumulative error accross 12 cycles -242 242 -215 215 ps
tERR(nper) Cumulative error accross n=13,14,..,49,50 cycles
tERR(npr)mi
n = (1+
0.68In(n)) *
tJIT(per)min
tERR(npr)m
ax = (1+
0.68In(n)) *
tJIT(per)ma
tERR(npr)mi
n = (1+
0.68In(n)) *
tJIT(per)min
tERR(npr)m
ax = (1+
0.68In(n)) *
tJIT(per)ma
ps
Data Timing
tDQSQ DQS, DQS to DQ skew per group, per access - 150 -125 ps
tQH DQ output hold time from DQS, DQS 0.38 -0.38 -tCK(avg)
tLZ(DQ) DQ low-impedence time from CK / -600 300 -500 250 ps
tHZ(DQ) DQ high-impedence time from CK / -300 -250 ps
tDS(base)
Data Setup time to DQS, DQS referenced to
Vih(ac)/ Vil(ac) levels
25 30 ps
tDH(base)
Data Hold time to DQS, DQS referenced to Vih(dc)/
Vil(dc) levels
100 65 ps
Data Strobe Timing
tRPRE DQS, DQS differential READ Preamble 0.9 -0.9 -tCK(avg)
tRPST DQS, DQS differential READ Postamble 0.3 -0.3 -tCK(avg)
tQSH DQS, DQS differential output high time 0.38 -0.4 -tCK(avg)
tQSL DQS, DQS differential output low time 0.38 -0.4 -tCK(avg)
tWPRE DQS, DQS differential WRITE Preamble 0.9 -0.9 -tCK(avg)
tWPST DQS, DQS differential WRITE Postamble 0.3 -0.3 -tCK(avg)
tDQSCK
DQS, DQS rising edge output access time from
rising CK,
-300 300 -255 255 ps
tLZ(DQS)
DQS, DQS low-impedance time (Referenced from
-600 300 -500 250 ps
tHZ(DQS)
DQS, DQS high-impedance time (Referenced from
RL+BL/2)
-300 -250 ps
tDQSL DQS, DQS differential input low pulse width 0.45 0.55 0.45 0.55 tCK(avg)
tDQSH DQS, DQS differential input high pulse width 0.45 0.55 0.45 0.55 tCK(avg)
tDQSS DQS, DQS rising edge to CK, rising edge -0.25 0.25 -0.25 0.25 tCK(avg)
tDSS
DQS, DQS falling edge setup time to CK, rising
edge
0.2 -0.2 - tCK(avg)
tDSH
DQS, DQS falling edge hold time to CK, rising
0.2 -0.2 -tCK(avg)
Symbol
Parameter
140
DDR3-1066 (-BE)
DDR3-1333 (-CG)
180
160
160
NT1GC72B89A0NL / NT2GC72B8PA0NL
NT4GC72B4NA1NL / NT4GC72B8NA1NL / NT8GTC72B4NA1NL
1GB: 128M x 72 / 2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72
PC3-8500 / PC3-10600
Registered DDR3 SDRAM DIMM
REV 1.1 37
06/2009
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
Unit
min max min max
Command and Address Timing
tDLLK DLL Locking time 512 -512 -nCK
tRTP
Internal READ command to PRECHARGE
Command delay
max(4nCK,
7.5ns)
-
max(4nCK,
7.5ns)
-
tWTR
Delay from start of internal write transaction to
internal read command
max(4nCK,
7.5ns)
-
max(4nCK,
7.5ns)
-
tWR WRITE recovery time 15 -15 -ns
tMRD Mode Register Set command cycle time 4 - 4 - nCK
tMOD Mode Register Set command update delay
max(12nCK,
15ns)
-
max(12nCK,
15ns)
-
tCCD CAS to CAS command delay 4 - 4 - nCK
tDAL Auto Precharge write recovery + precharge time nCK
tMPRR End of MPR Read burst to MSR for MPR (exit) 1 - 1 - nCK
tRRD
ACTIVE to ACTIVE command period (1k page size
-x4/x8)
max(4nCK,
7.5ns)
-
max(4nCK,
6ns)
-
tRRD
ACTIVE to ACTIVE command period (2k page size
-x16)
max(4nCK,
10ns)
-
max(4nCK,
7.5ns)
-
tFAW Four activate window (1k page size - x4/x8) 37.5 -30 0ns
tFAW Four activate window (2k page size - x16) 50 -45 0ns
tIS(base)
Command and Address setup time to CK,
referenced Vih(ac) / Vil(ac) levels
125 65 ps
tIH(base)
Command and Address hold time from CK,
referenced Vih(ac) / Vil(ac) levels
200 140 ps
tIS(base)
AC150
Commad and Address setup time to CK,
referenced to Vih(ac) / Vil(ac) levels
- - 65+125 ps
Calibration Timing
tZQinit Power-up and RESET calibration time 512 -512 -nCK
tZQoper Normal operation Full calibration time 256 -256 -nCK
tZQCS normal operation Short calibration time 64 -64 -nCK
Reset Timing
tXPR Exit Reset from CKE HIGH to a valid command
max(5nCK,
tRFC(min)
+10ns)
-
max(5nCK,
tRFC(min)
+10ns)
-
Self RefreshTimings
tXS
Exit Self Refresh to Commands not requiring a
locked DLL
max(5nCK,
tRFC(min)
+10ns)
-
max(5nCK,
tRFC(min)
+10ns)
-
tXSDLL
Exit Self Refresh to Commands requiring a locked
tDLLK(min) - tDLLK(min) - nCK
tCKESR
Minimum CKE low width for Self Refresh entry to
exit timing
tCKE(min)+
1nCK
-
tCKE(min)+
1nCK
-
tCKSRE
Valid Clock Requirement after Self Refresh Entry
(SRE) or Power Down Entry (PDE)
max(5nCK,
10ns)
-
max(5nCK,
10ns)
-
tCKSRX
Valid Clock Requirement before Self Refresh
Exit(SRX) or Power-Down Exit (PDX) or Reset Exit
max(5nCK,
10ns)
-
max(5nCK,
10ns)
-
Power Down Timings
tXP
Exit Power Down with DLL on to any valid
command; Exit Precharge Power Down with DLL
frozen to commands not requiring a locked DLL
max(3nCK,
7.5ns)
-
max(3nCK,
6ns)
-
tXPDLL
Exit Precharge Power Down with DLL frozen to
commands requiring a locked DLL
max(10nCK,
24ns)
-
max(10nCK,
24ns)
-
tCKE CKE minimm pulse width
max(3nCK,
5.625ns)
-
max(3nCK,
5.625ns)
-
tCPDED Command Pass disable delay 1 - 1 - nCK
tPD Power Down Entry to Exit Timing tCKE(min) 9tREFI tCKE(min) 9tREFI
tACTPDEN Timing of ACT command to Power Down entry 1 - 1 - nCK
tPRPDEN
Timing of PRE or PREA command to Power Down
1 - 1 - nCK
tRDPDEN Timing of RD/RDA command to Power Down entry RL + 4 + 1 - RL + 4 + 1 - nCK
WR + roundup
(tRP/tCK(avg))
WR + roundup
(tRP/tCK(avg))
DDR3-1333 (-CG)
Symbol
Parameter
DDR3-1066 (-BE)
NT1GC72B89A0NL / NT2GC72B8PA0NL
NT4GC72B4NA1NL / NT4GC72B8NA1NL / NT8GTC72B4NA1NL
1GB: 128M x 72 / 2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72
PC3-8500 / PC3-10600
Registered DDR3 SDRAM DIMM
REV 1.1 38
06/2009
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
Unit
min max min max
tWRPDEN
Timing of WR command to Power Down entry
(BL8OTF, BL8MRS, BC4OTF)
WL + 4 +
(tWR/tCK(av
g))
-
WL + 4 +
(tWR/tCK(av
g))
- nCK
tWRAPDEN
Timing of WRA command to Power Down entry
(BL8OTF, BL8MRS, BC4OTF)
WL + 4 +
WR + 1
-
WL + 4 +
WR + 1
- nCK
tWRPDEN
Timing of WR command to Power Down entry
(BC4MRS)
WL + 2 +
(tWR/tCK(av
g))
-
WL + 2 +
(tWR/tCK(av
g))
- nCK
tWRAPDEN
Timing of WRA command to Power Down entry
(BC4MRS)
WL + 2 +
WR + 1
-
WL + 2 +
WR + 1
- nCK
tREFPDEN Timing of REF command to Power Down entry 1 - 1 - nCK
tMRSPDEN Timing of MRS command to Power Down entry tMOD(min) - tMOD(min) -
ODT Timings
tODTH4
ODT high time without write command or with write
command and BC4
4 - 4 - nCK
tODTH8 ODT high time without write command oand BL8 6 - 6 - nCK
tAONPD
Asynchronous RTT turn-on delay (Power-Down with
DLL frozen)
1 9 1 9 ns
tAOFPD
Asynchronous RTT turn-off delay (Power Down with
DLL frozen)
1 9 1 9 ns
tAON RTT turn-on -300 300 -250 250 ps
tAOF
RTT_NOM and RTT_WR turn-off time from
ODTLoff reference
0.3 0.7 0.3 0.7 tCK(avg)
tADC RTT dynamic change skew 0.3 0.7 0.3 0.7 tCK(avg)
Write Leveling Timings
tWLMRD
First DQS/DQS rising edge after write leveling mode
is programmed
40 -40 - nCK
tWLDQSEN
DQS/DQS delay after write leveling mode is
25 -25 -nCK
tWLS
Write leveling setup time from rising CK, CK
crossing to rising DQS, DQS crossing
245 -195 -ps
tWLH
Write leveling hold time from rising DQS, DQS
crossing to rising CK, CK crossing
245 -195 -ps
tWLO Write leveling output delay 0 9 0 9 ns
tWLOE Write levleing output error 0 2 0 2 ns
tRFC REF command to ACT or REF command time ns
tREFI Average period refresh interval (0°C≤tCASE≤85°C) us
tREFI Average period refresh interval (85°C<tCASE≤95°C) us
7.8
3.9
110
7.8
3.9
DDR3-1333 (-CG)
110
Symbol
Parameter
DDR3-1066 (-BE)
NT1GC72B89A0NL / NT2GC72B8PA0NL
NT4GC72B4NA1NL / NT4GC72B8NA1NL / NT8GTC72B4NA1NL
1GB: 128M x 72 / 2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72
PC3-8500 / PC3-10600
Registered DDR3 SDRAM DIMM
REV 1.1 39
06/2009
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
Package Dimensions
[1GB – 1 Rank, 128Mx8 DDR3 SDRAMs]
FRONT
1.50 +/- 0.10
Detail A Detail B
0.80 +/- 0.05
BACK
3.80
4.00
1.00 Pitch
Detail A
9.50
133.35 +/- 0.15
Units: Millimeters
30.00 +0.5/-0.15
SIDE
4.00 Max.
1.27 +0.07/-0.10
17.30
5.175 47.00
Detail B
71.00
5.00
2.50
3.0 (x4)
SPD/TS
Registering
Clock
Driver
Note: Device position and scale are only for reference.
NT1GC72B89A0NL / NT2GC72B8PA0NL
NT4GC72B4NA1NL / NT4GC72B8NA1NL / NT8GTC72B4NA1NL
1GB: 128M x 72 / 2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72
PC3-8500 / PC3-10600
Registered DDR3 SDRAM DIMM
REV 1.1 40
06/2009
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
Package Dimensions
[2GB – 2 Ranks, 128Mx8 DDR3 SDRAMs]
FRONT
1.50 +/- 0.10
Detail A Detail B
0.80 +/- 0.05
BACK
3.80
4.00
1.00 Pitch
Detail A
9.50
133.35 +/- 0.15
Units: Millimeters
30.00 +0.5/-0.15
SIDE
4.00 Max.
1.27 +0.07/-0.10
17.30
5.175 47.00
Detail B
71.00
5.00
2.50
3.0 (x4)
SPD/TS
Registering
Clock
Driver
Note: Device position and scale are only for reference.
NT1GC72B89A0NL / NT2GC72B8PA0NL
NT4GC72B4NA1NL / NT4GC72B8NA1NL / NT8GTC72B4NA1NL
1GB: 128M x 72 / 2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72
PC3-8500 / PC3-10600
Registered DDR3 SDRAM DIMM
REV 1.1 41
06/2009
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
Package Dimensions
[4GB – 2 Ranks, 256Mx4 DDR3 SDRAMs]
FRONT
1.50 +/- 0.10
Detail A Detail B
0.80 +/- 0.05
REAR
3.80
4.00
1.00 Pitch
133.75 +/- 0.25
Units: Millimeters
30.60 +/- 0.15
SIDE
1.27 +0.07/-0.10
2.50
Max 8.5
3.0 (x4)
47.00 5.00
Detail A Detail B
71.00
9.50
17.30
5.175
Note: Device position and scale are only for reference.
NT1GC72B89A0NL / NT2GC72B8PA0NL
NT4GC72B4NA1NL / NT4GC72B8NA1NL / NT8GTC72B4NA1NL
1GB: 128M x 72 / 2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72
PC3-8500 / PC3-10600
Registered DDR3 SDRAM DIMM
REV 1.1 42
06/2009
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
Package Dimensions
[4GB – 4 Ranks, 128Mx8 DDR3 SDRAMs]
FRONT
1.50 +/- 0.10
Detail A Detail B
0.80 +/- 0.05
REAR
3.80
4.00
1.00 Pitch
133.75 +/- 0.25
Units: Millimeters
30.60 +/- 0.15
SIDE
1.27 +0.07/-0.10
2.50
Max 8.5
3.0 (x4)
47.00 5.00
Detail A Detail B
71.00
9.50
17.30
5.175
Note: Device position and scale are only for reference.
NT1GC72B89A0NL / NT2GC72B8PA0NL
NT4GC72B4NA1NL / NT4GC72B8NA1NL / NT8GTC72B4NA1NL
1GB: 128M x 72 / 2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72
PC3-8500 / PC3-10600
Registered DDR3 SDRAM DIMM
REV 1.1 43
06/2009
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
Package Dimensions
[8GB – 4 Ranks, 512Mx4 (DDP) DDR3 SDRAMs]
FRONT
1.50 +/- 0.10
Detail A Detail B
0.80 +/- 0.05
REAR
3.80
4.00
1.00 Pitch
133.75 +/- 0.25
Units: Millimeters
30.60 +/- 0.15
SIDE
1.27 +0.07/-0.10
2.50
Max 8.5
3.0 (x4)
47.00 5.00
Detail A Detail B
71.00
9.50
17.30
5.175
Note: Device position and scale are only for reference.
NT1GC72B89A0NL / NT2GC72B8PA0NL
NT4GC72B4NA1NL / NT4GC72B8NA1NL / NT8GTC72B4NA1NL
1GB: 128M x 72 / 2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72
PC3-8500 / PC3-10600
Registered DDR3 SDRAM DIMM
REV 1.1 44
06/2009
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
Revision Log
Rev
Date
Modification
0.1
07/2008
Preliminary Release
1.0
09/2008
Official Release
1.1
06/2009
4GB 4Rank x8, IDD, and SPD update
Nanya Technology Corporation
Hwa Ya Technology Park 669
Fu Hsing 3rd Rd., Kueishan,
Taoyuan, 333, Taiwan, R.O.C.
Tel: +886-3-328-1688
Please visit our home page for more information: www.nanya.com
Printed in Taiwan
© 2009
