LTC4359
1
Rev D
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TYPICAL APPLICATION
FEATURES DESCRIPTION
Ideal Diode Controller with
Reverse Input Protection
The LT C
®
4359 is a positive high voltage ideal diode control-
ler that drives an external N-channel MOSFET to replace
a Schottky diode. It controls the forward-voltage drop
across the MOSFET to ensure smooth current delivery
without oscillation even at light loads. If a power source
fails or is shorted, a fast turn-off minimizes reverse cur-
rent transients. A shutdown mode is available to reduce
the quiescent current to 9μA for load switch and 14µA for
ideal diode applications.
When used in high current diode applications, the LTC4359
reduces power consumption, heat dissipation, voltage loss
and PC board area. With its wide operating voltage range,
the ability to withstand reverse input voltage, and high
temperature rating, the LTC4359 satisfies the demanding
requirements of both automotive and telecom applications.
The LTC4359 also easily ORs power sources in systems
with redundant supplies.
12V, 20A Automotive Reverse-Battery Protection Power Dissipation vs Load Current
APPLICATIONS
n Reduces Power Dissipation by Replacing a Power
Schottky Diode
n Wide Operating Voltage Range: 4V to 80V
n Reverse Input Protection to – 40V
n Low 9µA Shutdown Current
n Low 150μA Operating Current
n Smooth Switchover without Oscillation
n Controls Single or Back-to-Back N-Channel MOSFETs
n Available in 6-Pin (2mm × 3mm) DFN, 8-Lead MSOP
and 8-Lead SO Packages
n Automotive Battery Protection
n Redundant Power Supplies
n Supply Holdup
n Telecom Infrastructure
n Computer Systems/Servers
n Solar Systems All registered trademarks and trademarks are the property of their respective owners.
4359 TA01
LTC4359
VSS
SHDN
IN SOURCE OUT
47nF
1k
GATE
BSC028N06NS
SMAT70A
70V
SMAJ24A
24V
VIN
12V
VOUT
TO LOAD
CURRENT (A)
0
POWER DISSIPATION (W)
4
8
6
20
4359 TA01a
2
0510 15
10
SCHOTTKY DIODE (SBG2040CT)
POWER
SAVED
MOSFET (BSC028N06NS)
LTC4359
2
Rev D
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ABSOLUTE MAXIMUM RATINGS
IN, SOURCE, SHDN ................................... –40V to 100V
OUT (Note 3) ................................................–2V to 100V
IN – OUT ..................................................–100V to 100V
IN – SOURCE .................................................–1V to 80V
GATE – SOURCE (Note 4) .........................–0.3V to +10V
(Notes 1, 2)
TOP VIEW
VSS
SHDN
IN
OUT
GATE
SOURCE
DCB PACKAGE
6-LEAD (2mm × 3mm) PLASTIC DFN
TJMAX = 150°C, θJA = 64°C/W
EXPOSED PAD (PIN 7) PCB VSS CONNECTION OPTIONAL
4
5
7
6
3
2
11
2
3
4
GATE
SOURCE
NC
IN
8
7
6
5
OUT
NC
VSS
SHDN
TOP VIEW
MS8 PACKAGE
8-LEAD PLASTIC MSOP
TJMAX = 150°C, θJA = 163°C/W
1
2
3
4
8
7
6
5
TOP VIEW
OUT
NC
VSS
SHDN
GATE
SOURCE
NC
IN
S8 PACKAGE
8-LEAD PLASTIC SO
TJMAX = 150°C, θJA = 130°C/W
PIN CONFIGURATION
ORDER INFORMATION
Operating Ambient Temperature Range
LTC4359C ................................................ 0°C to 70°C
LTC4359I ............................................. −40°C to 85°C
LTC4359H .......................................... −40°C to 125°C
Storage Temperature Range .................. −65°C to 150°C
Lead Temperature (Soldering, 10 sec)
MS, SO Packages ............................................. 300°C
TAPE AND REEL (MINI) TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC4359CDCB#TRMPBF LTC4359CDCB#TRPBF LFKF 6-Lead (2mm × 3mm) Plastic DFN 0°C to 70°C
LTC4359IDCB#TRMPBF LTC4359IDCB#TRPBF LFKF 6-Lead (2mm × 3mm) Plastic DFN –40°C to 85°C
LTC4359HDCB#TRMPBF LTC4359HDCB#TRPBF LFKF 6-Lead (2mm × 3mm) Plastic DFN –40°C to 125°C
TUBE TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC4359CMS8#PBF LTC4359CMS8#TRPBF LTFKD 8-Lead Plastic MSOP 0°C to 70°C
LTC4359IMS8#PBF LTC4359IMS8#TRPBF LTFKD 8-Lead Plastic MSOP –40°C to 85°C
LTC4359HMS8#PBF LTC4359HMS8#TRPBF LTFKD 8-Lead Plastic MSOP –40°C to 125°C
LTC4359CS8#PBF LTC4359CS8#TRPBF 4359 8-Lead Plastic SO 0°C to 70°C
LTC4359IS8#PBF LTC4359IS8#TRPBF 4359 8-Lead Plastic SO –40°C to 85°C
LTC4359HS8#PBF LTC4359HS8#TRPBF 4359 8-Lead Plastic SO –40°C to 125°C
Consult ADI Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through
designated sales channels with #TRMPBF suffix.
http://www.linear.com/product/LTC4359#orderinfo
LTC4359
3
Rev D
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Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2. All currents into pins are positive; all voltages are referenced to
VSS unless otherwise specified.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VIN Operating Supply Range l4 80 V
IIN IN Current IN = 12V
IN = OUT = 12V, SHDN = 0V
IN = OUT = 24V, SHDN = 0V
IN = −40V
l
l
l
l
0
150
9
15
–15
200
20
30
–40
µA
µA
µA
µA
IOUT OUT Current IN = 12V, In Regulation
IN = 12V, ∆VSD = −1V
IN = OUT = 12V, SHDN = 0V
IN = OUT = 24V, SHDN = 0V
OUT = 12V, IN = SHDN = 0V
l
l
l
l
l
3
5
120
0.8
0.8
6
7.5
220
3
3
12
µA
µA
µA
µA
µA
ISOURCE SOURCE Current IN = 12V, ∆VSD = −1V
IN = SOURCE = 12V, SHDN = 0V
SOURCE = –40V
l
l
l
1
–0.4
150
4
–0.8
200
15
–1.5
µA
µA
mA
∆VGATE Gate Drive (GATE–SOURCE) IN = 4V, IGATE = 0, −1µA
IN = 8V to 80V; IGATE = 0, –1µA
l
l
4.5
10
5.5
12
15
15
V
V
∆VSD Source-Drain Regulation Voltage (IN –OUT) ∆VGATE = 2.5V l20 30 45 mV
IGATE(UP) Gate Pull-Up Current GATE = IN, ∆VSD = 0.1V l–6 –10 –14 µA
IGATE(DOWN) Gate Pull-Down Current Fault Condition, ∆VGATE = 5V, ∆VSD = −1V
Shutdown Mode, ∆VGATE = 5V, ∆VSD = 0.7V
l
l
70
0.6
130 180 mA
mA
tOFF Gate Turn-Off Delay Time ∆VSD = 0.1V to −1V, ∆VGATE < 2V,
CGATE = 0pF
l0.3 0.5 µs
tON Gate Turn-On Delay Time IN = 12V, SOURCE = OUT = 0V, SHDN = 0V to 2V
∆VGATE > 4.5V, CGATE = 0pF
200 µs
VSHDN(TH) SHDN Pin Input Threshold IN = 4V to 80V l0.6 1.2 2 V
VSHDN(FLT) SHDN Pin Float Voltage IN = 4V to 80V l0.6 1.75 2.5 V
ISHDN SHDN Pin Current SHDN = 0.5V, LTC4359I, LTC4359C
SHDN = 0.5V, LTC4359H
SHDN = −40V
Maximum Allowable Leakage, VIN = 4V
l
l
l
–1
–0.5
–0.4
–3
–3
–0.8
100
–5
–5
–1.5
µA
µA
mA
nA
VSOURCE(TH) Reverse SOURCE Threshold for GATE Off GATE = 0V, IGATE(DOWN) = 1mA l–0.9 –1.8 –2.7 V
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C, IN = 12V, SOURCE = IN, unless otherwise noted.
Note 3. An internal clamp limits the OUT pin to a minimum of 100V above
VSS. Driving this pin with more current than 1mA may damage the device.
Note 4. An internal clamp limits the GATE pin to a minimum of 10V above
IN or 100V above VSS. Driving this pin to voltages beyond the clamp may
damage the device.
ELECTRICAL CHARACTERISTICS
LTC4359
4
Rev D
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TYPICAL PERFORMANCE CHARACTERISTICS
OUT Current
vs Forward Voltage Drop
SOURCE Current
vs Forward Voltage Drop
Total Negative Current
vs Negative Input Voltage
Gate Current
vs Forward Voltage Drop Gate Drive vs Gate Current
Gate Turn-Off Time
vs GATE Capacitance
IN Current in Regulation IN Current in Shutdown SOURCE Current in Shutdown
VIN (V)
0
I
IN
(µA)
100
150
80
4359 G01
50
020 40 60
200
VIN (V)
0
I
IN
(µA)
30
40
80
4359 G02
20
10
020 40 60
50
TA = –40°C
TA = 25°C
TA = 85°C
TA = 125°C
IN = SOURCE = OUT
SHDN = 0V
VSOURCE (V)
0
I
SOURCE
(µA)
6
8
80
4359 G03
4
2
020 40 60
10
TA = –40°C
TA = 25°C
TA = 85°C
TA = 125°C
IN = SOURCE = OUT
SHDN = 0V
∆VSD (V)
–1
I
OUT
(µA)
80
120
1
4359 G04
40
0–0.5 00.5
160
VIN = 4V
VIN = 12V
VIN = 48V
∆VSD (V)
–1
I
SOURCE
(µA)
50
0
150
100
1
4359 G05
–50 –0.5 00.5
200
VSOURCE = 4V
VSOURCE > 12V
IN = SOURCE
VOLTAGE (V)
0
IN
SOURCE
SHDN
–1
–1.5
4359 G06
–0.5
0
–10 –20 –30
IN = SOURCE= SHDN
∆VSD (mV)
–50
I
GATE
(µA)
10
0
–10
–20
150
4359 G07
20
30
40
050 100
VIN = VSOURCE = 12V
VGATE = VIN +2.5V
IGATE (µA)
0
∆V
GATE
(V)
10
–10
4359 G08
5
0–5
–15
15
IN = SOURCE
VIN = 4V
VIN = 8V
VIN > 12V
CGATE (nF)
0
t
OFF
(ns)
400
600
8
4359 G09
200
0246
10
800
VIN = 12V
∆VSD = 0.1V –1V
LTC4359
5
Rev D
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PIN FUNCTIONS
Exposed Pad (DCB Package Only): Exposed pad may be
left open or connected to VSS.
GATE: Gate Drive Output. The GATE pin pulls high, enhanc-
ing the N-channel MOSFET when the load current creates
more than 30mV of voltage drop across the MOSFET.
When the load current is small, the gate is actively driven
to maintain 30mV across the MOSFET. If reverse current
flows, a fast pull-down circuit connects the GATE to the
SOURCE pin within 0.3μs, turning off the MOSFET.
IN: Voltage Sense and Supply Voltage. IN is the anode of
the ideal diode. The voltage sensed at this pin is used to
control the MOSFET gate.
NC (MS8 and S8 Packages): No Connection. Not internally
connected.
OUT: Drain Voltage Sense. OUT is the cathode of the ideal
diode and the common output when multiple LTC4359s
are configured as an ideal diode-OR. It connects either di-
rectly or through a 2k resistor to the drain of the N-channel
MOSFET
. The voltage sensed at this pin is used to control
the MOSFET gate.
SHDN: Shutdown Control Input. The LTC4359 can be
shut down to a low current mode by pulling the SHDN
pin below 0.6V. Pulling this pin above 2V or disconnect-
ing it allows an internal 2.6μA current source to turn the
part on. Maintain board leakage to less than 100nA for
proper operation. The SHDN pin can be pulled up to 100V
or down to –40V with respect to VSS without damage. If
the shutdown feature is not used, connect SHDN to IN.
SOURCE: Source Connection. SOURCE is the return path
of the gate fast pull-down. Connect this pin as close as
possible to the source of the external N-channel MOSFET.
VSS: Supply Voltage Return and Device Ground.
TYPICAL PERFORMANCE CHARACTERISTICS
Gate Turn-Off Time
vs Initial Overdrive
Gate Turn-Off Time
vs Final Overdrive
Load Current
vs Forward Voltage Drop
VINITIAL (V)
0
t
PD
(ns)
150
200
1
4359 G10
100
50
0
0.50.25 0.75
VIN = 12V
∆VSD = VINITIAL –1V
VFINAL (V)
0
t
PD
(ns)
1500
–1
4359 G11
1000
500
0
–0.5–0.25 –0.75
VIN = 12V
∆VSD = 45mV VFINAL
∆VSD (mV)
0
CURRENT (A)
10
100
4359 G12
8
2
4
6
0
5025 75
FDMS86101
FDB3632
FDS3732
LTC4359
6
Rev D
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BLOCK DIAGRAM
OPERATION
The LTC4359 controls an external N-channel MOSFET to
form an ideal diode. The GATE amplifier (see Block Dia-
gram) senses across IN and OUT and drives the gate of the
MOSFET to regulate the forward voltage to 30mV. As the
load current increases, GATE is driven higher until a point
is reached where the MOSFET is fully on. Further increases
in load current result in a forward drop of RDS(ON)• ILOAD.
If the load current is reduced, the GATE amplifier drives
the MOSFET gate lower to maintain a 30mV drop. If the
input voltage is reduced to a point where a forward drop
of 30mV cannot be supported, the GATE amplifier drives
the MOSFET off.
In the event of a rapid drop in input voltage, such as an
input short-circuit fault or negative-going voltage spike,
reverse current temporarily flows through the MOSFET.
This current is provided by any load capacitance and by
other supplies or batteries that feed the output in diode-
OR applications.
4359 BD
CHARGE PUMP
TYP. 500kHz
SHUTDOWN
–+
–
+
FPD
COMP
GATE
AMP
30mV30mV
IN
2.6µA
SOURCE
SHDN
GATE
Q1
–1.7V
OUT
V
OUT
V
IN
VSS
IN
+
–+
–
–
+
NEGATIVE
COMP
The FPD COMP (Fast Pull-Down Comparator) quickly
responds to this condition by turning the MOSFET off in
300ns, thus minimizing the disturbance to the output bus.
The IN, SOURCE, GATE and SHDN pins are protected
against reverse inputs of up to –40V. The NEGATIVE COMP
detects negative input potentials at the SOURCE pin and
quickly pulls GATE to SOURCE, turning off the MOSFET
and isolating the load from the negative input.
When pulled low the SHDN pin turns off most of the
internal circuitry, reducing the quiescent current to 9µA
and holding the MOSFET off. The SHDN pin may be either
driven high or left open to enable the LTC4359. If left
open, an internal 2.6µA current source pulls SHDN high.
In applications where Q1 is replaced with back-to-back
MOSFETs, the SHDN pin serves as an on/off control for
the forward path, as well as enabling the diode function.
LTC4359
7
Rev D
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Blocking diodes are commonly placed in series with supply
inputs for the purpose of ORing redundant power sources
and protecting against supply reversal. The LTC4359
replaces diodes in these applications with a MOSFET to
reduce both the voltage drop and power loss associated
with a passive solution. The curve shown on page 1 illus-
trates the dramatic improvement in power loss achieved in
a practical application. This represents significant savings
in board area by greatly reducing power dissipation in the
pass device. At low input voltages, the improvement in
forward voltage loss is readily appreciated where head-
room is tight, as shown in Figure2.
The LTC4359 operates from 4V to 80V and withstands
an absolute maximum range of –40V to 100V without
damage. In automotive applications the LTC4359 operates
through load dump, cold crank and two-battery jumps,
and it survives reverse battery connections while also
protecting the load.
A 12V/20A ideal diode application is shown in Figure1.
Several external components are included in addition to
the MOSFET, Q1. Ideal diodes, like their nonideal coun-
terparts, exhibit a behavior known as reverse recovery.
In combination with parasitic or intentionally introduced
inductances, reverse recovery spikes may be generated by
an ideal diode during commutation. D1, D2 and R1 protect
against these spikes which might otherwise exceed the
LTC4359’s –40V to 100V survival rating. COUT also plays
a role in absorbing reverse recovery energy. Spikes and
protection schemes are discussed in detail in the Input
Short-Circuit Faults section.
APPLICATIONS INFORMATION
It is important to note that the SHDN pin, while disabling
the LTC4359 and reducing its current consumption to
9µA, does not disconnect the load from the input since
Q1’s body diode is ever-present. A second MOSFET is
required for load switching applications.
MOSFET Selection
All load current passes through an external MOSFET, Q1.
The important characteristics of the MOSFET are on-
resistance, RDS(ON), the maximum drain-source voltage,
BVDSS, and the gate threshold voltage VGS(TH).
Gate drive is compatible with 4.5V logic-level MOSFETs
over the entire operating range of 4V to 80V. In applications
above 8V, standard 10V threshold MOSFETs may be used.
An internal clamp limits the gate drive to 15V maximum
between the GATE and SOURCE pins. For 24V and higher
applications, an external Zener clamp (D4) must be added
between GATE and SOURCE to not exceed the MOSFET’s
VGS(MAX) during input shorts.
The maximum allowable drain-source voltage, BVDSS, must
be higher than the power supply voltage. If the input is
grounded, the full supply voltage will appear across the
MOSFET. If the input is reversed, and the output is held
up by a charged capacitor, battery or power supply, the
sum of the input and output voltages will appear across
the MOSFET and BVDSS > OUT + |VIN |.
Figure1. 12V/20A Ideal Diode with Reverse Input Protection
4359 F01
LTC4359
VSS
SHDN
IN SOURCE
Q1
BSC028N06NS
COUT
47nF
R1
1k
GATE
D1
SMAT70A
70V
D2
SMAJ24A
24V
VIN
12V
V
OUT
12V
20A
OUT
Figure2. Forward Voltage Drop Comparison
Between MOSFET and Schottky Diode
VOLTAGE (V)
0
CURRENT (A)
10
15
0.5
4359 F02
5
00.20.1 0.3 0.4
20
MOSFET
(BSC028N06NS)
SCHOTTKY DIODE
(SBG2040CT)
LTC4359
8
Rev D
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APPLICATIONS INFORMATION
The MOSFET’s on-resistance, RDS(ON), directly affects
the forward voltage drop and power dissipation. Desired
forward voltage drop should be less than that of a diode
for reduced power dissipation; 100mV is a good starting
point. Choose a MOSFET which has:
RDS(ON) <
Forward Voltage Drop
ILOAD
The resulting power dissipation is
Pd = (ILOAD)2 • RDS(ON)
Shutdown Mode
In shutdown, the LTC4359 pulls GATE low to SOURCE,
turning off the MOSFET and reducing its current consump-
tion to 9µA. Shutdown does not interrupt forward current
flow, a path is still present through Q1’s body diode, as
shown in Figure1. A second MOSFET is needed to block
the forward path; see the section Load Switching and
Inrush Control. When enabled the LTC4359 operates as
an ideal diode. If shutdown is not needed, connect SHDN
to IN. SHDN may be driven with a 3.3V or 5V logic sig-
nal, or with an open drain or collector. To assert SHDN
low, the pull down must sink at least 5µA at 500mV. To
enable the part, SHDN must be pulled up to at least 2V.
If SHDN is driven with an open drain, open collector or
switch contact, an internal pull-up current of 2.6µA (1µA
minimum) asserts SHDN high and enables the LTC4359.
If leakage from SHDN to ground cannot be maintained at
less than 100nA, add a pull-up resistor to >2V to assure
turn on. The self-driven open circuit voltage is limited
internally to 2.5V. When floating, the impedance is high
and SHDN is subject to capacitive coupling from nearby
clock lines or traces exhibiting high dV/dt. Bypass SHDN
to VSS with 10nF to eliminate injection. Figure 3a is the
simplest way to control the shutdown pin. Since the control
signal ground is different from the SHDN pin reference,
VSS, there could be momentary glitches on SHDN during
transients. Figures 3b and 3c are alternative solutions
that level-shift the control signal and eliminate glitches.
Figure 3a. SHDN Control
Figure 3b. Transistor SHDN Control
Figure 4c. Opto-Isolator SHDN Control
4359 F03a
LTC4359
1kVN2222LL
VSS
SHDN
OFFON
4359 F03b
LTC4359
1k
240k 100k
100k240k
48V
2N5551
VSS
SHDN
IN
ON
OFF
2N5401
4359 F03c
LTC4359
1k
2MΩ
1MΩ
MOC
207M
2k
48V
VSS
SHDN IN
OFFON
Input Short-Circuit Faults
The dynamic behavior of an active, ideal diode entering
reverse bias is most accurately characterized by a delay
followed by a period of reverse recovery. During the delay
phase some reverse current is built up, limited by parasitic
resistances and inductances. During the reverse recovery
LTC4359
9
Rev D
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phase, energy stored in the parasitic inductances is trans-
ferred to other elements in the circuit. Current slew rates
during reverse recovery may reach 100A/µs or higher.
High slew rates coupled with parasitic inductances in
series with the input and output paths may cause poten-
tially destructive transients to appear at the IN, SOURCE
and OUT pins of the LTC4359 during reverse recovery.
A zero impedance short-circuit directly across the input
and ground is especially troublesome because it permits
the highest possible reverse current to build up during
the delay phase. When the MOSFET finally interrupts the
reverse current, the LTC4359 IN and SOURCE pins experi-
ence a negative voltage spike, while the OUT pin spikes in
the positive direction.
To prevent damage to the LTC4359 under conditions
of input short-circuit, protect the IN, SOURCE and OUT
pins as shown in Figure4. The IN and SOURCE pins are
protected by clamping to the VSS pin with two TransZorbs
or TVS. For input voltages 24V and greater, D4 is needed
to protect the MOSFET’s gate oxide during input short-
circuit conditions. Negative spikes, seen after the MOSFET
turns off during an input short, are clamped by D2, a 24V
TVS. D2 allows reverse inputs to 24V while keeping the
MOSFET off and is not required if reverse-input protection
is not needed. D1, a 70V TVS, protects IN and SOURCE in
the positive direction during load steps and overvoltage
conditions. OUT can be protected by an output capacitor,
COUT of at least 1.5µF, a TVS across the MOSFET or by
the MOSFET’s avalanche breakdown. Care must be taken
if the MOSFET’s avalanche breakdown is used to protect
the OUT pin. The MOSFET’s BVDSS must be sufficiently
lower than 100V, and the MOSFET’s avalanche energy rat-
ing must be ample enough to absorb the inductive energy.
If a TVS across the MOSFET or the MOSFET avalanche
is used to protect the OUT pin, COUT can be reduced to
47nF. COUT and R1 preserve the fast turn off time when
output parasitic inductance causes the IN and OUT volt-
ages to drop quickly.
Reverse Input Protection
In the case of a reverse input where negative voltage is
present on the input, the components D1, D2 and R1
protect the LTC4359. With reverse inputs more negative
than D2’s breakdown voltage (24V), current flows from
system ground through R1. For applications that must
withstand reverse inputs much greater than –24V such
that R1’s power dissipation is unacceptable, it may be
replaced by a diode. If reverse input protection and fast
turn off time are not required, R1 can be removed and VSS
connected to system ground.
APPLICATIONS INFORMATION
Figure4. Reverse Recovery Produces Inductive Spikes at the IN, SOURCE and OUT Pins.
The Polarity of Step Recovery Is Shown Across Parasitic Inductances
4359 F04
LTC4359
VSS
SHDN
IN SOURCE OUT
R1
1k
GATE
Q1
FDMS86101
REVERSE RECOVERY CURRENT
INPUT PARASITIC
INDUCTANCE
+ –
D4
DDZ9699T
12V
VIN VOUT
COUT
≥1.5µF
CLOAD
INPUT
SHORT
OUTPUT PARASITIC
INDUCTANCE
+ –
D1
SMAT70A
70V
D2
SMAJ24A
24V
LTC4359
10
Rev D
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Figure10 shows a +48V application with reverse input
protection where D5 is used instead of R1 to eliminate
the power dissipation and system ground current when the
input reverses to –48V. With –48V input and OUT powered
by another supply or held up by output capacitance, D2
(5.1V) and D3 (75V) prevent the LTC4359’s OUT–IN pins
from exceeding the 100V absolute maximum rating. R2
limits the current into D1, D2 and D3 during a reverse input.
Paralleling Supplies
Multiple LTC4359s can be used to combine the outputs of
two or more supplies for redundancy or for droop sharing,
as shown in Figure5. For redundant supplies, the supply
with the highest output voltage sources most or all of the
load current. If this supply’s output is quickly shorted to
ground while delivering load current, the flow of current
temporarily reverses and flows backwards through the
LTC4359’s MOSFET. The LTC4359 senses this reverse
current and activates a fast pull-down to quickly turn off
the MOSFET.
APPLICATIONS INFORMATION
LTC4359
VSS
IN
D2A
SMAJ24CA
24V
OUT COUTA
1.5µF
COUTB
1.5µF
GATE
Q1A
FDMS86101 12V
10A
BUS
R1A
1k
LTC4359
VSS
IN
SOURCE
SHDN
SOURCE OUTGATE
Q1B
FDMS86101
PSA
VINA = 12V
RTNA
PSB
VINB = 12V
RTNB
D2B
SMAJ24CA
24V
4359 F05
R1B
1k
SHDN
Figure5. Redundant Power Supplies
If the other, initially lower, supply was not delivering any
load current at the time of the fault, the output falls until
the body diode of its ORing MOSFET conducts. Meanwhile,
the LTC4359 charges the MOSFET gate with 10µA until
the forward drop is reduced to 30mV. If this supply was
sharing load current at the time of the fault, its associated
ORing MOSFET was already driven partially on. In this case,
the LTC4359 will simply drive the MOSFET gate harder in
an effort to maintain a drop of 30mV.
Droop sharing can be accomplished if both power supply
output voltages and output impedances are nearly equal.
The 30mV regulation technique ensures smooth load
sharing between outputs without oscillation. The degree
of sharing is a function of MOSFET RDS(ON), the output
impedance of the supplies and their initial output voltages.
Load Switching and Inrush Control
By adding a second MOSFET as shown in Figure6, the
LTC4359 can be used to control power flow in the for-
ward direction while retaining ideal diode behavior in the
reverse direction. The body diodes of Q1 and Q2 prohibit
ON OFF
4359 F06
LTC4359
VSS
IN OUT
SHDN
GATESOURCE
Q1
FDMS86101
R4
10k
C1
10nF
VIN
28V
Q2
FQA140N10
R3
10Ω
VOUT
28V
10A
CLOAD
COUT
1.5µF
R1
1k
D4
DDZ9699T
12V
D1
SMAJ58A
58V
D2
SMAJ24A
24V
Figure6. 28V Load Switch and Ideal
Diode with Reverse Input Protection
LTC4359
11
Rev D
For more information www.analog.com
APPLICATIONS INFORMATION
current flow when the MOSFETs are off. Q1 serves as the
ideal diode, while Q2 acts as a switch to control forward
power flow. On/off control is provided by the SHDN pin,
and C1 and R4 may be added if inrush control is desired.
When SHDN is driven high and provided VIN >VOUT + 30mV,
GATE sources 10µA and gradually charges C1, pulling up
both MOSFET gates. Q2 operates as a source follower and
IINRUSH =
10µA • C
LOAD
C1
If VIN <VOUT + 30mV, the LTC4359 will be activated but
holds Q1 and Q2 off until the input exceeds the output by
30mV. In this way normal diode behavior of the circuit is
preserved, but with soft starting when the diode turns on.
When SHDN is pulled low, GATE pulls the MOSFET gates
down quickly to SOURCE turning off both forward and
reverse paths, and the input current is reduced to 9µA.
While C1 and R4 may be omitted if soft starting is not
needed, R3 is necessary to prevent MOSFET parasitic
oscillations and must be placed close to Q2.
Layout Considerations
Connect the IN, SOURCE and OUT pins as close as possible
to the MOSFET source and drain pins. Keep the traces to
the MOSFET wide and short to minimize resistive losses as
shown in Figure 7. Place surge suppressors and necessary
transient protection components close to the LTC4359
using short lead lengths.
For the DFN package, pin spacing may be a concern at
voltages greater than 30V. Check creepage and clearance
guidelines to determine if this is an issue. To increase the
effective pin spacing between high voltage and ground pins,
leave the exposed pad connection open. Use no-clean flux
to minimize PCB contamination.
Figures 8 through 18 show typical applications of the
LTC4359.
Figure 7a. Layout, DCB6 Package
Figure 7b. Layout, MS8/S8 Package
Figure8. 1.2V Diode–OR
4359 F07a
S
S
S
G
1
2
3
4
8
7
6
5
D
D
D
D
VIN
OUT
LTC4359
GATE
IN
DCB6
4
5
7
6
3
2
1
VOUT
SOURCE
MOSFET
LTC4359
S
S
S
G
1
2
3
4
8
7
6
5
D
D
D
D
MOSFET
GATE
IN
SOURCE
OUT
MS8/S8 4359 F07b
VIN VOUT
LTC4359
VSS
IN OUTGATE
Q1A
BSC011N03LS
–12V
–12V
VOUT
1.2V
20A
R1A
1k
SOURCE
VINA
1.2V
CLOAD
COUTA
47nF
LTC4359
VSS
IN OUTGATE
Q1B
BSC011N03LS
4359 F08
R1B
1k
SOURCE
VINB
1.2V
COUTB
47nF
LTC4359
12
Rev D
For more information www.analog.com
TYPICAL APPLICATIONS
Figure9. Lossless Solar Panel Isolation
Figure10. 48V Ideal Diode with Reverse Input Protection
4359 F09
LTC4359
VSS
SHDN
IN SOURCE OUTGATE
Q1
Si4874DY
+12V
BATTERY LOAD
SHUNT
REGULATOR
100W
SOLAR
PANEL
4359 F10
LTC4359
VSS
SHDN
IN SOURCE OUTGATE
Q1
IPB200N25N3G
D6
SMCJ150A
150V
R2
2k
VIN
48V
VOUT
48V
10A
CLOAD
COUT
47nF
D1
SMAT70A
70V
D2
MMSZ5231B
5.1V
D3
BZG03C75
75V
D5
S1B
D4
DDZ9699T
12V
LTC4359
13
Rev D
For more information www.analog.com
TYPICAL APPLICATIONS
Figure11. 200V Ideal Diode
4359 F11
LTC4359
10M
D4
DDZ9699T
VSS
SHDN
IN SOURCE OUTGATE
Q1
IPB200N25N3G
Q3*
BSS126
*DEPLETION MODE
TRANSISTOR
1k
ES1D 0.47µF
VIN
200V
VOUT
200V
7A
CLOAD
10nF
D1
DDZ9699
12V
D3
DDZ9702
15V
R1
200k
Figure12. 12V Load Switch and Ideal
Diode with Reverse Input Protection
4359 F12
LTC4359
VSS
SHDN
IN SOURCE OUTGATE
Q1
BSC028N06NS
Q2
BSC028N06NS
R1
1k
VIN
12V
VOUT
12V
10A
CLOAD
COUT
47nF
D2
SMAJ24CA
24V
D3
S1B
R3
10Ω
R4
10k
C1
10nF
ON
OFF
LTC4359
14
Rev D
For more information www.analog.com
Figure14. 24V Ideal Diode with Reverse Input Protection
Figure15. 48V Ideal Diode without Reverse Input Protection
Figure13. 12V Load Switch and Ideal
Diode with Precise Undervoltage Lockout
TYPICAL APPLICATIONS
4359 F13
LTC4359
LTC1540
VSS
SHDN
IN SOURCE GATE OUT
COUT
1.5µF
OUTPUT
Q2
BSC028N06NS
Q1
BSC028N06NS
12V INPUT
2M
R1
1k
8.2M
UV = 10.8V
1M
GND
OUT
10V
DDZ9697T
D2
SMAJ24CA
24V
+
–
V–
IN+
IN–
HYST
REF
4359 F14
LTC4359
VSS
SHDN
IN SOURCE OUTGATE
Q1
FDMS86101
VIN
24V
VOUT
24V
10A
COUT
1.5µF
D1
SMAT70A
70V
D2
SMAJ24A
24V
R1
1k
D4
DDZ9699T
12V
4359 F15
LTC4359
VSS
SHDN
IN SOURCE OUTGATE
Q1
FDMS86101
VIN
48V
VOUT
48V
10A
COUT
47nF
D1
SMAT70A
70V
R1
1k
D4
DDZ9699T
12V
D6
SMAT70A
70V
LTC4359
15
Rev D
For more information www.analog.com
TYPICAL APPLICATIONS
LTC4359
VSS
SHDN
IN SOURCE OUT
R1
1k
GATE
SMAJ58A
58V
Q1
BSC028N06NS FDD16AN08A0 10mΩ 4A OUTPUT
(CLAMPED AT 16V)
10Ω
D2
SMAJ24A
24V
D1
SMAT70A
70V
VIN
12V
4359 F17
LT4363
GND
SHDN
UV
OV
VCC GATE OUT
FB
ENOUT
F LT
SNS
TMR
0.1µF
22µF
COUT
47nF
57.6k
4.99k
–27V TO 60V DC SURVIVAL
–40V TO 100V TRANSIENT SURVIVAL
Figure17. Overvoltage Protector and Ideal Diode Blocks Reverse Input Voltage
Figure16. Diode-OR with Selectable Power
Supply Feeds and Reverse Input Protection
LTC4359
VSS
IN OUTGATE
Q1A
FDMS86101
D4A
DDZ9699T
12V
VOUT
28V
10A
R1A
1k
R1B
1k
LTC4359
VSS
IN
SOURCE
SHDN
SOURCE OUTGATE
Q1B
FDMS86101
Q2A
FQA140N10
D1A
SMAJ58A
58V
D2A
SMAJ24A
24V
D1B
SMAJ58A
58V
D2B
SMAJ24A
24V
Q2B
FQA140N10
R5B*
100k
*DECREASES GATE RAMP TIME BY BIASING SOURCEX NEAR VINX
100k PATH TO VOUT IF VOUT < VINX
VINA
28V
VINB
28V
CLOAD
COUTA
1.5µF
COUTB
1.5µF
4359 F16
D4B
DDZ9699T
12V
ONOFF
ONOFF SHDN
R5A*
100k
LTC4359
16
Rev D
For more information www.analog.com
PACKAGE DESCRIPTION
3.00 ±0.10
(2 SIDES)
2.00 ±0.10
(2 SIDES)
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (TBD)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
0.40 ±0.10
BOTTOM VIEW—EXPOSED PAD
1.65 ±0.10
(2 SIDES)
0.75 ±0.05
R = 0.115
TYP
R = 0.05
TYP
1.35 ±0.10
(2 SIDES)
1
3
64
PIN 1 BAR
TOP MARK
(SEE NOTE 6)
0.200 REF
0.00 – 0.05
(DCB6) DFN 0405
0.25 ±0.05
0.50 BSC
PIN 1 NOTCH
R0.20 OR 0.25
× 45° CHAMFER
0.25 ±0.05
1.35 ±0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
1.65 ±0.05
(2 SIDES)
2.15 ±0.05
0.70 ±0.05
3.55 ±0.05
PACKAGE
OUTLINE
0.50 BSC
DCB Package
6-Lead Plastic DFN (2mm × 3mm)
(Reference LTC DWG # 05-08-1715 Rev A)
DCB Package
6-Lead Plastic DFN (2mm × 3mm)
(Reference LTC DWG # 05-08-1715 Rev A)
Please refer to http://www.linear.com/product/LTC4359#packaging for the most recent package drawings.
LTC4359
17
Rev D
For more information www.analog.com
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/product/LTC4359#packaging for the most recent package drawings.
MSOP (MS8) 0213 REV G
0.53 ±0.152
(.021 ±.006)
SEATING
PLANE
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
0.18
(.007)
0.254
(.010)
1.10
(.043)
MAX
0.22 – 0.38
(.009 – .015)
TYP
0.1016 ±0.0508
(.004 ±.002)
0.86
(.034)
REF
0.65
(.0256)
BSC
0° – 6° TYP
DETAIL “A”
DETAIL “A”
GAUGE PLANE
1 2 34
4.90 ±0.152
(.193 ±.006)
8765
3.00 ±0.102
(.118 ±.004)
(NOTE 3)
3.00 ±0.102
(.118 ±.004)
(NOTE 4)
0.52
(.0205)
REF
5.10
(.201)
MIN
3.20 – 3.45
(.126 – .136)
0.889 ±0.127
(.035 ±.005)
RECOMMENDED SOLDER PAD LAYOUT
0.42 ± 0.038
(.0165 ±.0015)
TYP
0.65
(.0256)
BSC
MS8 Package
8-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1660 Rev G)
LTC4359
18
Rev D
For more information www.analog.com
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/product/LTC4359#packaging for the most recent package drawings.
.016 – .050
(0.406 – 1.270)
.010 – .020
(0.254 – 0.508)× 45°
0°– 8° TYP
.008 – .010
(0.203 – 0.254)
SO8 REV G 0212
.053 – .069
(1.346 – 1.752)
.014 – .019
(0.355 – 0.483)
TYP
.004 – .010
(0.101 – 0.254)
.050
(1.270)
BSC
1234
.150 – .157
(3.810 – 3.988)
NOTE 3
8765
.189 – .197
(4.801 – 5.004)
NOTE 3
.228 – .244
(5.791 – 6.197)
.245
MIN .160 ±.005
RECOMMENDED SOLDER PAD LAYOUT
.045 ±.005
.050 BSC
.030
±.005
TYP
INCHES
(MILLIMETERS)
NOTE:
1. DIMENSIONS IN
2. DRAWING NOT TO SCALE
3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)
4. PIN 1 CAN BE BEVEL EDGE OR A DIMPLE
S8 Package
8-Lead Plastic Small Outline (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1610 Rev G)
LTC4359
19
Rev D
For more information www.analog.com
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER
A 08/13 Corrected SHDN pull-up current from 2µA to 2.6µA
Updated Figure11
5, 6, 7, 8
12
B 05/14 Pin Configuration, updated TJMAX to 150°C from 125°C
Added specification, Gate Turn-On Delay Time (tON)
Figure16, added R5A and R5B resistors
2
3
14
C 09/17 Updated specification limit for OUT current at IN = 12V, ∆VSD = −1V
Added section titled Reverse Input Protection
3
9, 10
D 04/18 Added 8-lead SO package 1, 2, 18
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
LTC4359
20
Rev D
For more information www.analog.com
ANALOG DEVICES, INC. 2012-2018
D16846-0-4/18(D)
www.analog.com
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TYPICAL APPLICATION
PART NUMBER DESCRIPTION COMMENTS
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and Monitor
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Figure18. Input Diode for Supply Hold-Up on Plug-In Card
4359 F18
LTC4359
VSS
IN
SHDN
OUTGATE
FDB3632
DDZ9699T
12V
PLUG-IN CARDBACKPLANE
48V VOUT1
GND
GND
1k
CHOLDUP
1.5µF
SMAT70A
70V
SOURCE
LTC4260
Hot Swap™
CONTROLLER
+