LTC4359 Ideal Diode Controller with Reverse Input Protection FEATURES n n n n n n n n DESCRIPTION Reduces Power Dissipation by Replacing a Power Schottky Diode Wide Operating Voltage Range: 4V to 80V Reverse Input Protection to - 40V Low 9A Shutdown Current Low 150A Operating Current Smooth Switchover without Oscillation Controls Single or Back-to-Back N-Channel MOSFETs Available in 6-Pin (2mm x 3mm) DFN, 8-Lead MSOP and 8-Lead SO Packages APPLICATIONS n n n n n n Automotive Battery Protection Redundant Power Supplies Supply Holdup Telecom Infrastructure Computer Systems/Servers Solar Systems The LTC(R)4359 is a positive high voltage ideal diode controller that drives an external N-channel MOSFET to replace a Schottky diode. It controls the forward-voltage drop across the MOSFET to ensure smooth current delivery without oscillation even at light loads. If a power source fails or is shorted, a fast turn-off minimizes reverse current transients. A shutdown mode is available to reduce the quiescent current to 9A for load switch and 14A for ideal diode applications. When used in high current diode applications, the LTC4359 reduces power consumption, heat dissipation, voltage loss and PC board area. With its wide operating voltage range, the ability to withstand reverse input voltage, and high temperature rating, the LTC4359 satisfies the demanding requirements of both automotive and telecom applications. The LTC4359 also easily ORs power sources in systems with redundant supplies. All registered trademarks and trademarks are the property of their respective owners. TYPICAL APPLICATION 12V, 20A Automotive Reverse-Battery Protection 10 BSC028N06NS VOUT TO LOAD SMAT70A 70V SMAJ24A 24V IN SOURCE GATE OUT 47nF SHDN LTC4359 VSS 4359 TA01 POWER DISSIPATION (W) VIN 12V Power Dissipation vs Load Current 1k 8 SCHOTTKY DIODE (SBG2040CT) 6 POWER SAVED 4 2 MOSFET (BSC028N06NS) 0 0 5 10 CURRENT (A) 15 20 4359 TA01a Rev D Document Feedback For more information www.analog.com 1 LTC4359 ABSOLUTE MAXIMUM RATINGS (Notes 1, 2) IN, SOURCE, SHDN.................................... -40V to 100V OUT (Note 3).................................................-2V to 100V IN - OUT...................................................-100V to 100V IN - SOURCE..................................................-1V to 80V GATE - SOURCE (Note 4)..........................-0.3V to +10V Operating Ambient Temperature Range LTC4359C................................................. 0C to 70C LTC4359I.............................................. -40C to 85C LTC4359H........................................... -40C to 125C Storage Temperature Range................... -65C to 150C Lead Temperature (Soldering, 10 sec) MS, SO Packages.............................................. 300C PIN CONFIGURATION TOP VIEW 6 VSS OUT 1 GATE 2 SOURCE 3 7 TOP VIEW TOP VIEW 5 SHDN 4 IN GATE SOURCE NC IN 8 7 6 5 OUT NC VSS SHDN MS8 PACKAGE 8-LEAD PLASTIC MSOP TJMAX = 150C, JA = 163C/W DCB PACKAGE 6-LEAD (2mm x 3mm) PLASTIC DFN TJMAX = 150C, JA = 64C/W EXPOSED PAD (PIN 7) PCB VSS CONNECTION OPTIONAL ORDER INFORMATION 1 2 3 4 GATE 1 8 OUT SOURCE 2 7 NC NC 3 6 VSS IN 4 5 SHDN S8 PACKAGE 8-LEAD PLASTIC SO TJMAX = 150C, JA = 130C/W http://www.linear.com/product/LTC4359#orderinfo TAPE AND REEL (MINI) TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC4359CDCB#TRMPBF LTC4359CDCB#TRPBF LFKF 6-Lead (2mm x 3mm) Plastic DFN 0C to 70C LTC4359IDCB#TRMPBF LTC4359IDCB#TRPBF LFKF 6-Lead (2mm x 3mm) Plastic DFN -40C to 85C LTC4359HDCB#TRMPBF LTC4359HDCB#TRPBF LFKF 6-Lead (2mm x 3mm) Plastic DFN -40C to 125C TUBE TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC4359CMS8#PBF LTC4359CMS8#TRPBF LTFKD 8-Lead Plastic MSOP 0C to 70C LTC4359IMS8#PBF LTC4359IMS8#TRPBF LTFKD 8-Lead Plastic MSOP -40C to 85C LTC4359HMS8#PBF LTC4359HMS8#TRPBF LTFKD 8-Lead Plastic MSOP -40C to 125C LTC4359CS8#PBF LTC4359CS8#TRPBF 4359 8-Lead Plastic SO 0C to 70C LTC4359IS8#PBF LTC4359IS8#TRPBF 4359 8-Lead Plastic SO -40C to 85C LTC4359HS8#PBF LTC4359HS8#TRPBF 4359 8-Lead Plastic SO -40C to 125C Consult ADI Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix. 2 Rev D For more information www.analog.com LTC4359 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C, IN = 12V, SOURCE = IN, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX 80 V 150 9 15 -15 200 20 30 -40 A A A A 5 120 0.8 0.8 6 7.5 220 3 3 12 A A A A A A A mA VIN Operating Supply Range IN Current IN = 12V IN = OUT = 12V, SHDN = 0V IN = OUT = 24V, SHDN = 0V IN = -40V l l l l IOUT OUT Current IN = 12V, In Regulation IN = 12V, VSD = -1V IN = OUT = 12V, SHDN = 0V IN = OUT = 24V, SHDN = 0V OUT = 12V, IN = SHDN = 0V l l l l l ISOURCE SOURCE Current IN = 12V, VSD = -1V IN = SOURCE = 12V, SHDN = 0V SOURCE = -40V l l l 1 -0.4 150 4 -0.8 200 15 -1.5 VGATE Gate Drive (GATE-SOURCE) IN = 4V, IGATE = 0, -1A IN = 8V to 80V; IGATE = 0, -1A l l 4.5 10 5.5 12 15 15 V V VSD Source-Drain Regulation Voltage (IN -OUT) VGATE = 2.5V l 20 30 45 mV IGATE(UP) Gate Pull-Up Current GATE = IN, VSD = 0.1V l -6 -10 -14 A Fault Condition, VGATE = 5V, VSD = -1V Shutdown Mode, VGATE = 5V, VSD = 0.7V l l 70 0.6 130 180 mA mA l 0.3 0.5 s IGATE(DOWN) Gate Pull-Down Current 4 UNITS IIN l 0 3 tOFF Gate Turn-Off Delay Time VSD = 0.1V to -1V, VGATE < 2V, CGATE = 0pF tON Gate Turn-On Delay Time IN = 12V, SOURCE = OUT = 0V, SHDN = 0V to 2V VGATE > 4.5V, CGATE = 0pF VSHDN(TH) SHDN Pin Input Threshold IN = 4V to 80V l 0.6 1.2 2 VSHDN(FLT) SHDN Pin Float Voltage IN = 4V to 80V l 0.6 1.75 2.5 V ISHDN SHDN Pin Current SHDN = 0.5V, LTC4359I, LTC4359C SHDN = 0.5V, LTC4359H SHDN = -40V Maximum Allowable Leakage, VIN = 4V l l l -1 -0.5 -0.4 -3 -3 -0.8 100 -5 -5 -1.5 A A mA nA GATE = 0V, IGATE(DOWN) = 1mA l -0.9 -1.8 -2.7 V VSOURCE(TH) Reverse SOURCE Threshold for GATE Off Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2. All currents into pins are positive; all voltages are referenced to VSS unless otherwise specified. 200 s V Note 3. An internal clamp limits the OUT pin to a minimum of 100V above VSS. Driving this pin with more current than 1mA may damage the device. Note 4. An internal clamp limits the GATE pin to a minimum of 10V above IN or 100V above VSS. Driving this pin to voltages beyond the clamp may damage the device. Rev D For more information www.analog.com 3 LTC4359 TYPICAL PERFORMANCE CHARACTERISTICS IN Current in Regulation IN Current in Shutdown 200 50 100 50 30 20 TA = 125C TA = 85C TA = 25C TA = -40C 10 40 20 60 VIN (V) 0 80 0 160 200 VIN = 48V VIN = 12V VIN = 4V IOUT (A) ISOURCE (A) 0.5 VSD (V) 50 -1 4359 G04 0.5 -1 -0.5 0 1 0 800 -40 4359 G06 VIN = 12V VSD = 0.1V -1V 600 VIN = 8V tOFF (ns) VGATE (V) 20 -30 Gate Turn-Off Time vs GATE Capacitance VIN > 12V 10 -20 -10 VOLTAGE (V) IN = SOURCE 10 80 4359 G03 IN = SOURCE= SHDN 4359 G05 15 VIN = VSOURCE = 12V VGATE = VIN +2.5V 60 -1.5 Gate Drive vs Gate Current 0 IGATE (A) 0 -0.5 VSD (V) Gate Current vs Forward Voltage Drop -10 -2 100 -50 1 40 20 VSOURCE (V) IN = SOURCE 0 0 0 Total Negative Current vs Negative Input Voltage VSOURCE = 4V 40 TA = 125C TA = 85C TA = 25C TA = -40C 4359 G02 150 80 -0.5 0 80 VSOURCE > 12V -1 4 SOURCE Current vs Forward Voltage Drop 120 -20 60 VIN (V) 4359 G01 OUT Current vs Forward Voltage Drop 0 40 20 6 2 IIN + ISOURCE + ISHDN (mA) 0 IN = SOURCE = OUT SHDN = 0V 8 ISOURCE (A) IIN (A) IIN (A) IN = SOURCE = OUT SHDN = 0V 40 150 0 SOURCE Current in Shutdown 10 400 5 VIN = 4V 200 30 40 -50 0 50 100 150 VSD (mV) 0 0 -5 -10 IGATE (A) 4359 G07 4 -15 4359 G08 0 0 2 6 4 CGATE (nF) 8 10 4359 G09 Rev D For more information www.analog.com LTC4359 TYPICAL PERFORMANCE CHARACTERISTICS Gate Turn-Off Time vs Initial Overdrive 200 Gate Turn-Off Time vs Final Overdrive 1500 VIN = 12V VSD = VINITIAL -1V Load Current vs Forward Voltage Drop VIN = 12V VSD = 45mV 10 VFINAL FDB3632 CURRENT (A) tPD (ns) tPD (ns) 1000 100 500 6 4 FDS3732 50 0 FDMS86101 8 150 2 0 0.25 0.5 VINITIAL (V) 0.75 1 0 0 -0.25 -0.5 -0.75 VFINAL (V) 4359 G10 -1 4359 G11 0 0 25 50 VSD (mV) 75 100 4359 G12 PIN FUNCTIONS Exposed Pad (DCB Package Only): Exposed pad may be left open or connected to VSS. GATE: Gate Drive Output. The GATE pin pulls high, enhancing the N-channel MOSFET when the load current creates more than 30mV of voltage drop across the MOSFET. When the load current is small, the gate is actively driven to maintain 30mV across the MOSFET. If reverse current flows, a fast pull-down circuit connects the GATE to the SOURCE pin within 0.3s, turning off the MOSFET. IN: Voltage Sense and Supply Voltage. IN is the anode of the ideal diode. The voltage sensed at this pin is used to control the MOSFET gate. NC (MS8 and S8 Packages): No Connection. Not internally connected. OUT: Drain Voltage Sense. OUT is the cathode of the ideal diode and the common output when multiple LTC4359s are configured as an ideal diode-OR. It connects either directly or through a 2k resistor to the drain of the N-channel MOSFET. The voltage sensed at this pin is used to control the MOSFET gate. SHDN: Shutdown Control Input. The LTC4359 can be shut down to a low current mode by pulling the SHDN pin below 0.6V. Pulling this pin above 2V or disconnecting it allows an internal 2.6A current source to turn the part on. Maintain board leakage to less than 100nA for proper operation. The SHDN pin can be pulled up to 100V or down to - 40V with respect to VSS without damage. If the shutdown feature is not used, connect SHDN to IN. SOURCE: Source Connection. SOURCE is the return path of the gate fast pull-down. Connect this pin as close as possible to the source of the external N-channel MOSFET. VSS: Supply Voltage Return and Device Ground. Rev D For more information www.analog.com 5 LTC4359 BLOCK DIAGRAM Q1 VIN IN SOURCE VOUT GATE OUT 2.6A SHDN SHUTDOWN - + CHARGE PUMP TYP. 500kHz - + - FPD COMP + + -1.7V NEGATIVE COMP GATE AMP - + - 30mV VSS IN 30mV 4359 BD OPERATION The LTC4359 controls an external N-channel MOSFET to form an ideal diode. The GATE amplifier (see Block Diagram) senses across IN and OUT and drives the gate of the MOSFET to regulate the forward voltage to 30mV. As the load current increases, GATE is driven higher until a point is reached where the MOSFET is fully on. Further increases in load current result in a forward drop of RDS(ON)* ILOAD. If the load current is reduced, the GATE amplifier drives the MOSFET gate lower to maintain a 30mV drop. If the input voltage is reduced to a point where a forward drop of 30mV cannot be supported, the GATE amplifier drives the MOSFET off. In the event of a rapid drop in input voltage, such as an input short-circuit fault or negative-going voltage spike, reverse current temporarily flows through the MOSFET. This current is provided by any load capacitance and by other supplies or batteries that feed the output in diodeOR applications. 6 The FPD COMP (Fast Pull-Down Comparator) quickly responds to this condition by turning the MOSFET off in 300ns, thus minimizing the disturbance to the output bus. The IN, SOURCE, GATE and SHDN pins are protected against reverse inputs of up to -40V. The NEGATIVE COMP detects negative input potentials at the SOURCE pin and quickly pulls GATE to SOURCE, turning off the MOSFET and isolating the load from the negative input. When pulled low the SHDN pin turns off most of the internal circuitry, reducing the quiescent current to 9A and holding the MOSFET off. The SHDN pin may be either driven high or left open to enable the LTC4359. If left open, an internal 2.6A current source pulls SHDN high. In applications where Q1 is replaced with back-to-back MOSFETs, the SHDN pin serves as an on/off control for the forward path, as well as enabling the diode function. Rev D For more information www.analog.com LTC4359 APPLICATIONS INFORMATION The LTC4359 operates from 4V to 80V and withstands an absolute maximum range of -40V to 100V without damage. In automotive applications the LTC4359 operates through load dump, cold crank and two-battery jumps, and it survives reverse battery connections while also protecting the load. A 12V/20A ideal diode application is shown in Figure 1. Several external components are included in addition to the MOSFET, Q1. Ideal diodes, like their nonideal counterparts, exhibit a behavior known as reverse recovery. In combination with parasitic or intentionally introduced inductances, reverse recovery spikes may be generated by an ideal diode during commutation. D1, D2 and R1 protect against these spikes which might otherwise exceed the LTC4359's -40V to 100V survival rating. COUT also plays a role in absorbing reverse recovery energy. Spikes and protection schemes are discussed in detail in the Input Short-Circuit Faults section. Q1 BSC028N06NS VIN 12V VOUT 12V 20A D1 SMAT70A 70V D2 SMAJ24A 24V IN GATE SOURCE OUT COUT 47nF LTC4359 SHDN VSS R1 1k 4359 F01 Figure 1. 12V/20A Ideal Diode with Reverse Input Protection 20 MOSFET (BSC028N06NS) 15 CURRENT (A) Blocking diodes are commonly placed in series with supply inputs for the purpose of ORing redundant power sources and protecting against supply reversal. The LTC4359 replaces diodes in these applications with a MOSFET to reduce both the voltage drop and power loss associated with a passive solution. The curve shown on page 1 illustrates the dramatic improvement in power loss achieved in a practical application. This represents significant savings in board area by greatly reducing power dissipation in the pass device. At low input voltages, the improvement in forward voltage loss is readily appreciated where headroom is tight, as shown in Figure 2. 10 SCHOTTKY DIODE (SBG2040CT) 5 0 0 0.1 0.3 0.2 VOLTAGE (V) 0.4 0.5 4359 F02 Figure 2. Forward Voltage Drop Comparison Between MOSFET and Schottky Diode It is important to note that the SHDN pin, while disabling the LTC4359 and reducing its current consumption to 9A, does not disconnect the load from the input since Q1's body diode is ever-present. A second MOSFET is required for load switching applications. MOSFET Selection All load current passes through an external MOSFET, Q1. The important characteristics of the MOSFET are onresistance, RDS(ON), the maximum drain-source voltage, BVDSS, and the gate threshold voltage VGS(TH). Gate drive is compatible with 4.5V logic-level MOSFETs over the entire operating range of 4V to 80V. In applications above 8V, standard 10V threshold MOSFETs may be used. An internal clamp limits the gate drive to 15V maximum between the GATE and SOURCE pins. For 24V and higher applications, an external Zener clamp (D4) must be added between GATE and SOURCE to not exceed the MOSFET's VGS(MAX) during input shorts. The maximum allowable drain-source voltage, BVDSS, must be higher than the power supply voltage. If the input is grounded, the full supply voltage will appear across the MOSFET. If the input is reversed, and the output is held up by a charged capacitor, battery or power supply, the sum of the input and output voltages will appear across the MOSFET and BVDSS > OUT + |VIN |. Rev D For more information www.analog.com 7 LTC4359 APPLICATIONS INFORMATION The MOSFET's on-resistance, RDS(ON), directly affects the forward voltage drop and power dissipation. Desired forward voltage drop should be less than that of a diode for reduced power dissipation; 100mV is a good starting point. Choose a MOSFET which has: Forward Voltage Drop RDS(ON) < ILOAD LTC4359 SHDN 4359 F03a VN2222LL ON OFF 1k Figure 3a. SHDN Control The resulting power dissipation is 48V Pd = (ILOAD)2 * RDS(ON) 240k Shutdown Mode 100k IN In shutdown, the LTC4359 pulls GATE low to SOURCE, turning off the MOSFET and reducing its current consumption to 9A. Shutdown does not interrupt forward current flow, a path is still present through Q1's body diode, as shown in Figure 1. A second MOSFET is needed to block the forward path; see the section Load Switching and Inrush Control. When enabled the LTC4359 operates as an ideal diode. If shutdown is not needed, connect SHDN to IN. SHDN may be driven with a 3.3V or 5V logic signal, or with an open drain or collector. To assert SHDN low, the pull down must sink at least 5A at 500mV. To enable the part, SHDN must be pulled up to at least 2V. If SHDN is driven with an open drain, open collector or switch contact, an internal pull-up current of 2.6A (1A minimum) asserts SHDN high and enables the LTC4359. If leakage from SHDN to ground cannot be maintained at less than 100nA, add a pull-up resistor to >2V to assure turn on. The self-driven open circuit voltage is limited internally to 2.5V. When floating, the impedance is high and SHDN is subject to capacitive coupling from nearby clock lines or traces exhibiting high dV/dt. Bypass SHDN to VSS with 10nF to eliminate injection. Figure 3a is the simplest way to control the shutdown pin. Since the control signal ground is different from the SHDN pin reference, VSS, there could be momentary glitches on SHDN during transients. Figures 3b and 3c are alternative solutions that level-shift the control signal and eliminate glitches. 8 VSS 2N5401 LTC4359 2N5551 OFF ON 240k SHDN VSS 100k 4359 F03b 1k Figure 3b. Transistor SHDN Control 48V ON OFF 2k 1M SHDN MOC 207M 2M IN LTC4359 VSS 4359 F03c 1k Figure 4c. Opto-Isolator SHDN Control Input Short-Circuit Faults The dynamic behavior of an active, ideal diode entering reverse bias is most accurately characterized by a delay followed by a period of reverse recovery. During the delay phase some reverse current is built up, limited by parasitic resistances and inductances. During the reverse recovery Rev D For more information www.analog.com LTC4359 APPLICATIONS INFORMATION phase, energy stored in the parasitic inductances is transferred to other elements in the circuit. Current slew rates during reverse recovery may reach 100A/s or higher. High slew rates coupled with parasitic inductances in series with the input and output paths may cause potentially destructive transients to appear at the IN, SOURCE and OUT pins of the LTC4359 during reverse recovery. A zero impedance short-circuit directly across the input and ground is especially troublesome because it permits the highest possible reverse current to build up during the delay phase. When the MOSFET finally interrupts the reverse current, the LTC4359 IN and SOURCE pins experience a negative voltage spike, while the OUT pin spikes in the positive direction. To prevent damage to the LTC4359 under conditions of input short-circuit, protect the IN, SOURCE and OUT pins as shown in Figure 4. The IN and SOURCE pins are protected by clamping to the VSS pin with two TransZorbs or TVS. For input voltages 24V and greater, D4 is needed to protect the MOSFET's gate oxide during input shortcircuit conditions. Negative spikes, seen after the MOSFET turns off during an input short, are clamped by D2, a 24V TVS. D2 allows reverse inputs to 24V while keeping the MOSFET off and is not required if reverse-input protection is not needed. D1, a 70V TVS, protects IN and SOURCE in VIN INPUT PARASITIC INDUCTANCE + - the positive direction during load steps and overvoltage conditions. OUT can be protected by an output capacitor, COUT of at least 1.5F, a TVS across the MOSFET or by the MOSFET's avalanche breakdown. Care must be taken if the MOSFET's avalanche breakdown is used to protect the OUT pin. The MOSFET's BVDSS must be sufficiently lower than 100V, and the MOSFET's avalanche energy rating must be ample enough to absorb the inductive energy. If a TVS across the MOSFET or the MOSFET avalanche is used to protect the OUT pin, COUT can be reduced to 47nF. COUT and R1 preserve the fast turn off time when output parasitic inductance causes the IN and OUT voltages to drop quickly. Reverse Input Protection In the case of a reverse input where negative voltage is present on the input, the components D1, D2 and R1 protect the LTC4359. With reverse inputs more negative than D2's breakdown voltage (24V), current flows from system ground through R1. For applications that must withstand reverse inputs much greater than -24V such that R1's power dissipation is unacceptable, it may be replaced by a diode. If reverse input protection and fast turn off time are not required, R1 can be removed and VSS connected to system ground. REVERSE RECOVERY CURRENT Q1 FDMS86101 INPUT SHORT D1 SMAT70A 70V OUTPUT PARASITIC INDUCTANCE + - D4 DDZ9699T 12V IN SOURCE GATE SHDN D2 LTC4359 SMAJ24A VSS 24V VOUT CLOAD OUT R1 1k COUT 1.5F 4359 F04 Figure 4. Reverse Recovery Produces Inductive Spikes at the IN, SOURCE and OUT Pins. The Polarity of Step Recovery Is Shown Across Parasitic Inductances Rev D For more information www.analog.com 9 LTC4359 APPLICATIONS INFORMATION Figure 10 shows a +48V application with reverse input protection where D5 is used instead of R1 to eliminate the power dissipation and system ground current when the input reverses to -48V. With -48V input and OUT powered by another supply or held up by output capacitance, D2 (5.1V) and D3 (75V) prevent the LTC4359's OUT-IN pins from exceeding the 100V absolute maximum rating. R2 limits the current into D1, D2 and D3 during a reverse input. Paralleling Supplies Multiple LTC4359s can be used to combine the outputs of two or more supplies for redundancy or for droop sharing, as shown in Figure 5. For redundant supplies, the supply with the highest output voltage sources most or all of the load current. If this supply's output is quickly shorted to ground while delivering load current, the flow of current temporarily reverses and flows backwards through the LTC4359's MOSFET. The LTC4359 senses this reverse current and activates a fast pull-down to quickly turn off the MOSFET. VINA = 12V PSA Q1A FDMS86101 D2A SMAJ24CA 24V RTNA IN SOURCE GATE OUT COUTA 1.5F VSS PSB RTNB Q1B FDMS86101 D2B SMAJ24CA 24V Load Switching and Inrush Control By adding a second MOSFET as shown in Figure 6, the LTC4359 can be used to control power flow in the forward direction while retaining ideal diode behavior in the reverse direction. The body diodes of Q1 and Q2 prohibit Q2 FQA140N10 VIN 28V ON OFF Q1 FDMS86101 VOUT 28V 10A D1 SMAJ58A 58V D2 SMAJ24A 24V R1A 1k VINB = 12V Droop sharing can be accomplished if both power supply output voltages and output impedances are nearly equal. The 30mV regulation technique ensures smooth load sharing between outputs without oscillation. The degree of sharing is a function of MOSFET RDS(ON), the output impedance of the supplies and their initial output voltages. 12V 10A BUS LTC4359 SHDN If the other, initially lower, supply was not delivering any load current at the time of the fault, the output falls until the body diode of its ORing MOSFET conducts. Meanwhile, the LTC4359 charges the MOSFET gate with 10A until the forward drop is reduced to 30mV. If this supply was sharing load current at the time of the fault, its associated ORing MOSFET was already driven partially on. In this case, the LTC4359 will simply drive the MOSFET gate harder in an effort to maintain a drop of 30mV. R3 10 C1 10nF R4 10k CLOAD D4 DDZ9699T 12V IN SOURCE SHDN LTC4359 COUT 1.5F GATE OUT VSS IN SOURCE GATE OUT COUTB 1.5F LTC4359 SHDN R1 1k 4359 F06 VSS R1B 1k 4359 F05 Figure 6. 28V Load Switch and Ideal Diode with Reverse Input Protection Figure 5. Redundant Power Supplies 10 Rev D For more information www.analog.com LTC4359 APPLICATIONS INFORMATION current flow when the MOSFETs are off. Q1 serves as the ideal diode, while Q2 acts as a switch to control forward power flow. On/off control is provided by the SHDN pin, and C1 and R4 may be added if inrush control is desired. 1 S VIN 4 G When SHDN is driven high and provided VIN >VOUT + 30mV, GATE sources 10A and gradually charges C1, pulling up both MOSFET gates. Q2 operates as a source follower and VOUT D 5 GATE OUT 1 3 2 SOURCE LTC4359 7 5 4 IN 6 10A * CLOAD C1 If VIN <VOUT + 30mV, the LTC4359 will be activated but holds Q1 and Q2 off until the input exceeds the output by 30mV. In this way normal diode behavior of the circuit is preserved, but with soft starting when the diode turns on. IINRUSH = When SHDN is pulled low, GATE pulls the MOSFET gates down quickly to SOURCE turning off both forward and reverse paths, and the input current is reduced to 9A. D 8 2 S MOSFET D 7 D 6 3 S DCB6 4359 F07a Figure 7a. Layout, DCB6 Package 1 S VIN 2 S 3 S D 8 MOSFET GATE SOURCE D 6 D 5 4 G While C1 and R4 may be omitted if soft starting is not needed, R3 is necessary to prevent MOSFET parasitic oscillations and must be placed close to Q2. VOUT D 7 OUT LTC4359 IN MS8/S8 Layout Considerations Connect the IN, SOURCE and OUT pins as close as possible to the MOSFET source and drain pins. Keep the traces to the MOSFET wide and short to minimize resistive losses as shown in Figure 7. Place surge suppressors and necessary transient protection components close to the LTC4359 using short lead lengths. For the DFN package, pin spacing may be a concern at voltages greater than 30V. Check creepage and clearance guidelines to determine if this is an issue. To increase the effective pin spacing between high voltage and ground pins, leave the exposed pad connection open. Use no-clean flux to minimize PCB contamination. Figures 8 through 18 show typical applications of the LTC4359. 4359 F07b Figure 7b. Layout, MS8/S8 Package Q1A BSC011N03LS VINA 1.2V IN SOURCE GATE VOUT 1.2V 20A CLOAD OUT COUTA 47nF LTC4359 VSS R1A 1k -12V Q1B BSC011N03LS VINB 1.2V IN SOURCE GATE LTC4359 OUT COUTB 47nF VSS R1B 1k -12V 4359 F08 Figure 8. 1.2V Diode-OR Rev D For more information www.analog.com 11 LTC4359 TYPICAL APPLICATIONS Q1 Si4874DY IN 100W SOLAR PANEL SOURCE GATE OUT + SHUNT REGULATOR LTC4359 12V BATTERY LOAD SHDN VSS 4359 F09 Figure 9. Lossless Solar Panel Isolation D6 SMCJ150A 150V VIN 48V Q1 IPB200N25N3G D4 DDZ9699T 12V VOUT 48V 10A R2 2k IN SOURCE GATE OUT D1 SMAT70A 70V LTC4359 SHDN D2 MMSZ5231B VSS 5.1V D5 S1B CLOAD COUT 47nF D3 BZG03C75 75V 4359 F10 Figure 10. 48V Ideal Diode with Reverse Input Protection 12 Rev D For more information www.analog.com LTC4359 TYPICAL APPLICATIONS 1k 0.47F ES1D Q1 IPB200N25N3G VIN 200V CLOAD Q3* BSS126 D4 DDZ9699T *DEPLETION MODE TRANSISTOR 10M IN SOURCE 10nF D1 DDZ9699 12V VOUT 200V 7A GATE OUT D3 DDZ9702 15V LTC4359 SHDN VSS 4359 F11 R1 200k Figure 11. 200V Ideal Diode Q2 BSC028N06NS VIN 12V Q1 BSC028N06NS VOUT 12V 10A CLOAD C1 10nF D2 SMAJ24CA 24V OFF ON R4 10k IN R3 10 SOURCE GATE OUT LTC4359 SHDN COUT 47nF D3 S1B VSS 4359 F12 R1 1k Figure 12. 12V Load Switch and Ideal Diode with Reverse Input Protection Rev D For more information www.analog.com 13 LTC4359 TYPICAL APPLICATIONS Q2 Q1 BSC028N06NS BSC028N06NS 12V INPUT 8.2M 2M D2 SMAJ24CA 24V IN UV = 10.8V 1M SOURCE GATE OUT LTC1540 IN+ + - IN- OUTPUT COUT 1.5F LTC4359 OUT HYST SHDN VSS 4359 F13 10V DDZ9697T REF R1 1k V- GND Figure 13. 12V Load Switch and Ideal Diode with Precise Undervoltage Lockout Q1 FDMS86101 VIN 24V VOUT 24V 10A D4 DDZ9699T 12V D1 SMAT70A 70V IN SOURCE D2 SMAJ24A 24V SHDN GATE OUT COUT 1.5F LTC4359 VSS 4359 F14 R1 1k Figure 14. 24V Ideal Diode with Reverse Input Protection D6 SMAT70A 70V Q1 FDMS86101 VIN 48V VOUT 48V 10A D4 DDZ9699T 12V D1 SMAT70A 70V IN SOURCE GATE OUT COUT 47nF LTC4359 SHDN VSS R1 1k 4359 F15 Figure 15. 48V Ideal Diode without Reverse Input Protection 14 Rev D For more information www.analog.com LTC4359 TYPICAL APPLICATIONS R5A* 100k Q1A FDMS86101 Q2A FQA140N10 VINA 28V D1A SMAJ58A 58V D2A SMAJ24A 24V VOUT 28V 10A D4A DDZ9699T 12V SOURCE IN CLOAD GATE OUT COUTA 1.5F LTC4359 OFF ON SHDN VSS R1A 1k R5B* 100k Q1B FDMS86101 Q2B FQA140N10 VINB 28V D1B SMAJ58A 58V D4B DDZ9699T 12V D2B SMAJ24A 24V IN SOURCE GATE OUT COUTB 1.5F LTC4359 OFF ON SHDN VSS 4359 F16 R1B 1k *DECREASES GATE RAMP TIME BY BIASING SOURCEX NEAR VINX 100k PATH TO VOUT IF VOUT < VINX Figure 16. Diode-OR with Selectable Power Supply Feeds and Reverse Input Protection VIN 12V Q1 BSC028N06NS D1 SMAT70A 70V D2 SMAJ24A 24V FDD16AN08A0 SMAJ58A 58V IN SHDN SOURCE GATE LTC4359 OUT 57.6k SHDN OV -27V TO 60V DC SURVIVAL -40V TO 100V TRANSIENT SURVIVAL GATE SNS 22F OUT FB 4.99k LT4363 UV VSS 4A OUTPUT (CLAMPED AT 16V) 10 VCC COUT 47nF 10m GND R1 1k TMR ENOUT FLT 0.1F 4359 F17 Figure 17. Overvoltage Protector and Ideal Diode Blocks Reverse Input Voltage Rev D For more information www.analog.com 15 LTC4359 PACKAGE DESCRIPTION Please refer to http://www.linear.com/product/LTC4359#packaging for the most recent package drawings. DCB Package Package DCB 6-Lead Plastic Plastic DFN (2mm 6-Lead (2mm xx 3mm) 3mm) (ReferenceLTC LTC DWG # 05-08-1715 (Reference 05-08-1715Rev RevA)A) 0.70 0.05 3.55 0.05 1.65 0.05 (2 SIDES) 2.15 0.05 PACKAGE OUTLINE 0.25 0.05 0.50 BSC 1.35 0.05 (2 SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS R = 0.115 TYP 2.00 0.10 (2 SIDES) R = 0.05 TYP 3.00 0.10 (2 SIDES) 0.40 0.10 4 6 1.65 0.10 (2 SIDES) PIN 1 NOTCH R0.20 OR 0.25 x 45 CHAMFER PIN 1 BAR TOP MARK (SEE NOTE 6) 3 0.200 REF 0.75 0.05 1 (DCB6) DFN 0405 0.25 0.05 0.50 BSC 1.35 0.10 (2 SIDES) 0.00 - 0.05 BOTTOM VIEW--EXPOSED PAD NOTE: 1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (TBD) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 16 Rev D For more information www.analog.com LTC4359 PACKAGE DESCRIPTION Please refer to http://www.linear.com/product/LTC4359#packaging for the most recent package drawings. MS8 Package 8-Lead Plastic MSOP (Reference LTC DWG # 05-08-1660 Rev G) 0.889 0.127 (.035 .005) 5.10 (.201) MIN 3.20 - 3.45 (.126 - .136) 3.00 0.102 (.118 .004) (NOTE 3) 0.65 (.0256) BSC 0.42 0.038 (.0165 .0015) TYP 8 7 6 5 0.52 (.0205) REF RECOMMENDED SOLDER PAD LAYOUT 0.254 (.010) 3.00 0.102 (.118 .004) (NOTE 4) 4.90 0.152 (.193 .006) DETAIL "A" 0 - 6 TYP GAUGE PLANE 0.53 0.152 (.021 .006) DETAIL "A" 1 2 3 4 1.10 (.043) MAX 0.86 (.034) REF 0.18 (.007) SEATING PLANE 0.22 - 0.38 (.009 - .015) TYP 0.65 (.0256) BSC 0.1016 0.0508 (.004 .002) MSOP (MS8) 0213 REV G NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX Rev D For more information www.analog.com 17 LTC4359 PACKAGE DESCRIPTION Please refer to http://www.linear.com/product/LTC4359#packaging for the most recent package drawings. S8 Package 8-Lead Plastic Small Outline (Narrow .150 Inch) (Reference LTC DWG # 05-08-1610 Rev G) .050 BSC .189 - .197 (4.801 - 5.004) NOTE 3 .045 .005 8 .245 MIN .160 .005 .010 - .020 x 45 (0.254 - 0.508) NOTE: 1. DIMENSIONS IN .053 - .069 (1.346 - 1.752) 0- 8 TYP .014 - .019 (0.355 - 0.483) TYP INCHES (MILLIMETERS) 2. DRAWING NOT TO SCALE 3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm) 4. PIN 1 CAN BE BEVEL EDGE OR A DIMPLE 18 5 .150 - .157 (3.810 - 3.988) NOTE 3 1 RECOMMENDED SOLDER PAD LAYOUT .016 - .050 (0.406 - 1.270) 6 .228 - .244 (5.791 - 6.197) .030 .005 TYP .008 - .010 (0.203 - 0.254) 7 2 3 4 .004 - .010 (0.101 - 0.254) .050 (1.270) BSC SO8 REV G 0212 Rev D For more information www.analog.com LTC4359 REVISION HISTORY REV DATE DESCRIPTION A 08/13 Corrected SHDN pull-up current from 2A to 2.6A B 05/14 C 09/17 04/18 5, 6, 7, 8 Updated Figure 11 12 Pin Configuration, updated TJMAX to 150C from 125C 2 Added specification, Gate Turn-On Delay Time (tON) 3 Figure 16, added R5A and R5B resistors 14 Updated specification limit for OUT current at IN = 12V, VSD = -1V Added section titled Reverse Input Protection D PAGE NUMBER Added 8-lead SO package 3 9, 10 1, 2, 18 Rev D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license For is granted implication or otherwise under any patent or patent rights of Analog Devices. more by information www.analog.com 19 LTC4359 TYPICAL APPLICATION BACKPLANE PLUG-IN CARD FDB3632 48V LTC4260 Hot SwapTM CONTROLLER VOUT1 DDZ9699T 12V IN SOURCE SHDN SMAT70A 70V GATE OUT LTC4359 1.5F + CHOLDUP VSS 1k GND 4359 F18 GND Figure 18. Input Diode for Supply Hold-Up on Plug-In Card RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC4352 Ideal Diode Controller with Monitor Controls N-Channel MOSFET, 0V to 18V Operation LTC4371 Negative Voltage Diode-OR Controller and Monitor Controls Two N-Channel MOSFETs, -4.5V to >-100V Operation LTC4355 Positive Voltage Diode-OR Controller and Monitor Controls Two N-Channel MOSFETs, 0.4s Turn-Off, 80V Operation LTC4357 Positive High Voltage Ideal Diode Controller Controls Single N-Channel MOSFET, 0.5s Turn-Off, 80V Operation LTC4358 5A Ideal Diode Internal N Channel MOSFET, 9V to 26.5V Operation LT4363-1/LT4363-2 High Voltage Surge Stopper Stops High Voltage Surges, 4V to 80V, -60V Reverse Input Protection LTC4380 Low Quiescent Current Surge Stopper 8A IQ, 4V to 72V Operation, -60V Reverse Input Protection LT4256-1/LT4256-2 Positive High Voltage Hot Swap Controllers Active Current Limiting, Supplies from 10.8V to 80V Latch-Off and Automatic Retry Option LTC4260 Positive High Voltage Hot Swap Controller With I2C and ADC, Supplies from 8.5V to 80V LTC4364 Surge Stopper with Ideal Diode 4V to 80V Operation, -40V Reverse Input, -20V Reverse Output 20 Rev D D16846-0-4/18(D) www.analog.com For more information www.analog.com ANALOG DEVICES, INC. 2012-2018