7130LA55CBG - INTEGRATED DEVICE TECHNOLOGY

Integrated Device Technology, Inc.

HIGH-SPEED

1K x 8 DUAL-PORT

STATIC RAM

IDT7130SA/LA

IDT7140SA/LA

FEATURES

• High-speed access

—Military: 25/35/55/100ns (max.)

—Commercial: 25/35/55/100ns (max.)

—Commercial: 20ns 7130 in PLCC and TQFP

• Low-power operation

—IDT7130/IDT7140SA

—Active: 550mW (typ.)

—Standby: 5mW (typ.)

—IDT7130/IDT7140LA

—Active: 550mW (typ.)

—Standby: 1mW (typ.)

• MASTER IDT7130 easily expands data bus width to

16-or-more-bits using SLAVE IDT7140

• On-chip port arbitration logic (IDT7130 Only)

•

BUSY

output flag on IDT7130;

BUSY

input on IDT7140

• Interrupt flags for port-to-port communication

• Fully asynchronous operation from either port

• Battery backup operation–2V data retention (LA only)

• TTL-compatible, single 5V ±10% power supply

• Military product compliant to MIL-STD-883, Class B

• Standard Military Drawing #5962-86875

• Industrial temperature range (–40°C to +85°C) is avail-

able, tested to military electrical specifications

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

DESCRIPTION

The IDT7130/IDT7140 are high-speed 1K x 8 Dual-Port

Static RAMs. The IDT7130 is designed to be used as a

stand-alone 8-bit Dual-Port RAM or as a "MASTER" Dual-

Port RAM together with the IDT7140 "SLAVE" Dual-Port in

16-bit-or-more word width systems. Using the IDT MAS-

TER/SLAVE Dual-Port RAM approach in 16-or-more-bit

memory system applications results in full-speed, error-free

operation without the need for additional discrete logic.

Both devices provide two independent ports with sepa-

rate control, address, and I/O pins that permit independent

asynchronous access for reads or writes to any location in

memory. An automatic power down feature, controlled by

, permits the on chip circuitry of each port to enter a very

low standby power mode.

Fabricated using IDT's CMOS high-performance tech-

nology, these devices typically operate on only 550mW of

power. Low-power (LA) versions offer battery backup data

retention capability, with each Dual-Port typically consum-

ing 200µW from a 2V battery.

The IDT7130/IDT7140 devices are packaged in 48-pin

sidebraze or plastic DIPs, LCCs, or flatpacks, 52-pin PLCC,

and 64-pin TQFP and STQFP. Military grade product is

manufactured in compliance with the latest revision of MIL-

STD-883, Class B, making it ideally suited to military tem-

perature applications demanding the highest level of per-

formance and reliability.

FUNCTIONAL BLOCK DIAGRAM

6.01 1

MILITARY AND COMMERCIAL TEMPERATURE RANGES OCTOBER 1996

I/O

Control

Address

Decoder MEMORY

ARRAY

ARBITRATION

and

INTERRUPT

LOGIC

Address

Decoder

I/O

Control

BUSY

A9L

A0L

2689 drw 01

I/O0L- I/O7L

INT

BUSY

I/O0R-I/O7R

A9R

A0R

INT

(2)

(1,2) (1,2)

(2)

NOTES:

1. IDT7130 (MASTER):

BUSY

is open

drain output and requires pullup

resistor of 270Ω.

IDT7140 (SLAVE):

BUSY

is input.

2. Open drain output: requires pullup

resistor of 270Ω.

For latest information contact IDT’s web site at www.idt.com or fax-on-demand at 408-492-8391.

IDT7130SA/LA AND IDT7140SA/LA

HIGH-SPEED 1K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS MILITARY AND COMMERCIAL TEMPERATURE RANGES

6.01 2

PIN CONFIGURATIONS (1,2)

NOTES:

1. All Vcc pins must be connected to the power supply.

2. All GND pins must be connected to the ground supply.

3. This text does not indicate orientation of the actual part-marking.

INDEX

IDT7130/40

PP64-1 & PN64-1

64-PIN STQFP

64-PIN TQFP

TOP VIEW

(3)

33 I/O

N/C

I/O

N/C

I/O

N/C

2689 drw 05

N/C

BUSY

INT

N/C

GND

N/C

GND

N/C

BUSY

INT

I/O

IDT7130/40

L48-1

F48-1

48-PIN LCC/ FLATPACK

TOP VIEW (3)

INDEX

65432148 47 46 45 44 43

19 20 21 22 23 25 26 27 28 29 3024

2689 drw 03

GND

A0L

A0R

A1R

A2R

A3R

A4R

A5R

A6R

A7R

A8R

A9R

I/O7R

I/O3L

A1L

A2L

A3L

A4L

A5L

A6L

A7L

A8L

A9L

I/O0L

I/O1L

I/O2L

INT

BUSY

INT

VCC

I/O6R

I/O5R

I/O4R

I/O3R

I/O2R

I/O1R

I/O0R

I/O7L

I/O6L

I/O5L

I/O4L

IDT7130/40

J52-1

52-PIN PLCC

TOP VIEW

(3)

INDEX

N/C

GND

N/C

I/O

474849505152

234567

33323130292827262524232221

2689 drw 04

INT

BUSY

INT

I/O

148

IDT7130/

IDT7140

P48-1

C48-2

DIP

TOP

VIEW

(3)

2689 drw 02

GND

I/O

INT

BUSY

INT

I/O

6.01 3

IDT7130SA/LA AND IDT7140SA/LA

HIGH-SPEED 1K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS MILITARY AND COMMERCIAL TEMPERATURE RANGES

7130SA 7130LA

7140SA 7140LA

Symbol Parameter Test Conditions Min. Max. Max. Max. Unit

|lLl| Input Leakage VCC = 5.5V, — 10 — 5 µA

Current(1) VIN = 0V to VCCIN = GND to VCC

|lLO| Output Leakage VCC = 5.5V, — 10 — 5 µA

Current(1)

= VIH, VOUT = 0V to VCC

VOL Output Low Voltage lOL = 4mA — 0.4 — 0.4 V

(l/O0-l/O7)lOL= 16mA

VOL Open Drain Output lOL = 16mA — 0.5 — 0.5 V

Low Voltage (

BUSY

INT

)

VOH Output High Voltage lOH = -4mA 2.4 — 2.4 — V

Symbol Parameter Conditions(2) Max. Unit

CIN Input Capacitance VIN = 3dV 9 pF

COUT Output Capacitance VIN = 3dV 10 pF

2689 tbl 02

ABSOLUTE MAXIMUM RATINGS(1)

Symbol Rating Commercial Military Unit

VTERM(2) Terminal Voltage –0.5 to +7.0 –0.5 to +7.0 V

with Respect to

GND

TAOperating 0 to +70 –55 to +125 °C

Temperature

TBIAS Temperature –55 to +125 –65 to +135 °C

Under Bias

TSTG Storage –55 to +125 –65 to +150 °C

Temperature

IOUT DC Output 50 50 mA

Current

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS

may cause permanent damage to the device. This is a stress rating only

and functional operation of the device at these or any other conditions

above those indicated in the operational sections of the specification is not

implied. Exposure to absolute maximum rating conditions for extended

periods may affect reliability.

2. VTERM must not exceed Vcc + 0.5 for more than 25% of the cycle time

or 10ns maximum, and is limited to < 20mA for the period of VTERM > Vcc

+ 0.5V.

2689 tbl 01

RECOMMENDED

DC OPERATING CONDITIONS

Symbol Parameter Min. Typ. Max. Unit

VCC Supply Voltage 4.5 5.0 5.5 V

GND Supply Voltage 0 0 0 V

VIH Input High Voltage 2.2 — 6.0(2) V

VIL Input Low Voltage –0.5 — 0.8 V

NOTES:

1. VIL (min.) > -1.5V for pulse width less than 10ns.

2. VTERM must not exceed Vcc + 0.5V.

RECOMMENDED OPERATING

TEMPERATURE AND SUPPLY VOLTAGE

Ambient

Grade Temperature GND VCC

Military –55°C to +125°C 0V 5.0V ± 10%

Commercial 0°C to +70°C 0V 5.0V ± 10%

2689 tbl 03

(1)

DC ELECTRICAL CHARACTERISTICS OVER THE

OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE (VCC = 5.0V ± 10%)

NOTES:

1. This parameter is determined by device characterization but is not

production tested.

2. 3dv references the interpolated capacitance when the input and

output signals switch from 0V to 3V or from 3V to 0V.

3. 11pF max. for other packages.

2689 tbl 05

CAPACITANCE(1)

(TA = +25°C, f = 1.0MHz) TQFP ONLY(3)

NOTE: 2689 tbl 04

1. At Vcc < 2.0V leakages are undefined.

IDT7130SA/LA AND IDT7140SA/LA

HIGH-SPEED 1K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS MILITARY AND COMMERCIAL TEMPERATURE RANGES

6.01 4

DC ELECTRICAL CHARACTERISTICS OVER THE

OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(1,6) (VCC = 5.0V ± 10%)

7130X20(2) 7130X25(3) 7130X35 7130X55 7130X100

7140X25(3) 7140X35 7140X55 7140X100

Symbol Parameter Test Conditions Version Typ. Max. Typ. Max. Typ. Max. Typ.Max. Typ. Max. Unit

ICC Dynamic Operating

L and

R = VIL, MIL. SA — — 110 280 110 230 110 190 110 190 mA

Current (Both Ports Outputs open, LA — — 110 220 110 170 110 140 110 140

Active) f = fMAX(4) COM'L. SA 110 250 110 220 110 165 110 155 110 155

LA 110 200 110 170 110 120 110 110 110 110

ISB1 Standby Current

L and

R = VIH, MIL. SA — — 30 80 25 80 20 65 20 65 mA

(Both Ports - TTL f = fMAX(4) LA — — 30 60 25 60 20 45 20 45

Level Inputs) COM'L. SA 30 65 30 65 25 65 20 65 20 55

LA 30 45 30 45 25 45 20 35 20 35

ISB2 Standby Current

"A" = VIL and MIL. SA — — 65 160 50 150 40 125 40 125 mA

(One Port - TTL

"B" = VIH (7) LA — — 65 125 50 115 40 90 40 90

Level Inputs) Active Port Outputs COM'L. SA 65 165 65 150 50 125 40 110 40 110

Open, f = fMAX(4) LA 65 125 65 115 50 90 40 75 40 75

ISB3 Full Standby Current

L and MIL. SA — — 1.0 30 1.0 30 1.0 30 1.0 30 mA

(Both Ports - All

R > VCC -0.2V, LA — — 0.2 10 0.2 10 0.2 10 0.2 10

CMOS Level Inputs VIN > VCC -0.2V or COM'L. SA 1.0 15 1.0 15 1.0 15 1.0 15 1.0 15

VIN < 0.2V,f = 0(5) LA 0.2 5 0.2 5 0.2 4 0.2 4 0.2 4

ISB4 Full Standby Current

"A" < 0.2V and MIL. SA — — 60 155 45 145 40 110 40 110 mA

(One Port - All

"B" > VCC -0.2V(7) LA — — 60 115 45 105 40 85 40 80

CMOS Level Inputs) VIN > VCC -0.2V or COM'L. SA 60 155 60 145 45 110 40 100 40 95

VIN < 0.2V, LA 60 115 60 105 45 85 40 70 40 70

Active Port Outputs

Open, f = fMAX(4)

NOTES: 2689 tbl 06

1. 'X' in part numbers indicates power rating (SA or LA).

2. Com'l Only, 0°C to +70°C temperature range. PLCC and TQFP packages.

3. Not available in DIP packages.

4. At f = fMax, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using “AC TEST CONDITIONS”

of input levels of GND to 3V.

5. f = 0 means no address or control lines change. Applies only to inputs at CMOS level standby.

6. Vcc = 5V, TA=+25°C for Typ and is not production tested. Vcc DC = 100 mA (Typ.)

7. Port "A" may be either left or right port. Port "B" is opposite from port "A".

Symbol Parameter Min. Typ.(1) Max. Unit

VDR VCC for Data Retention 2.0 — — V

ICCDR Data Retention Current — 100 4000 µA

— 100 1500 µA

tCDR Chip Deselect to Data 0 — — ns

Retention Time

tROperation Recovery tRC ——ns

Time

DATA RETENTION CHARACTERISTICS (LA Version Only)

lDT7130LA/IDT7140LA

Mil.

Com’l.

VCC = 2.0V,

> VCC -0.2V

VIN > VCC -0.2V or VIN < 0.2V

(3)

Test Conditions

2689 tbl 07

(2)

NOTES:

1. VCC = 2V, TA = +25°C, and is not production tested.

2. tRC = Read Cycle Time

3. This parameter is guaranteed but not production tested.

6.01 5

IDT7130SA/LA AND IDT7140SA/LA

HIGH-SPEED 1K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS MILITARY AND COMMERCIAL TEMPERATURE RANGES

1250Ω

(*100pF for 55 and

100ns versions)

30pF*

775Ω

DATA

OUT

1250Ω

775Ω5pF*

DATA

OUT

2689 drw 07

270Ω

30pF*

BUSY

INT

100pF for 55 and 100ns versions

DATA RETENTION WAVEFORM

AC TEST CONDITIONS

Input Pulse Levels

Input Rise/Fall Times

Input Timing Reference Levels

Output Reference Levels

Output Load

GND to 3.0V

5ns

1.5V

Figures 1, 2, and 3

2689 tbl 08

4.5V 4.5V

DATA RETENTION MODE

CDR

2.0V

2692 drw 06

≥

Figure 3.

BUSYBUSY

BUSY

and

INTINT

INT

AC Output Test Load

Figure 1. Output Test Load Figure 2. Output Test Load

(for tHZ, tLZ, tWZ, and tOW)

* including scope and jig

IDT7130SA/LA AND IDT7140SA/LA

HIGH-SPEED 1K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS MILITARY AND COMMERCIAL TEMPERATURE RANGES

6.01 6

AC ELECTRICAL CHARACTERISTICS OVER THE

OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(3)

7130X20(2) 7130X25(5) 7130X35 7130X55 7130X100

7140X25(5) 7140X35 7140X55 7140X100

Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit

Read Cycle

tRC Read Cycle Time 20 — 25 — 35 — 55 — 100 — ns

tAA Address Access Time — 20 — 25 — 35 — 55 — 100 ns

tACE Chip Enable Access Time — 20 — 25 — 35 — 55 — 100 ns

tAOE Output Enable Access Time 11 — 12 — 20 — 25 — 40 ns

tOH Output Hold From Address Change 3 — 3 — 3 — 3 — 10 — ns

tLZ Output Low-Z Time(1,4) 0— 0 — 0 — 5 — 5 —ns

HZ Output High-Z Time(1,4) — 10 — 10 — 15 — 25 — 40 ns

tPU Chip Enable to Power Up Time(4) 0— 0 —0 — 0 — 0 —ns

PD Chip Disable to Power Down Time(4) — 20 — 25 — 35 — 50 — 50 ns

NOTES: 2689 tbl 09

1. Transition is measured ±500mV from Low or High-impedance voltage Output Test Load (Figure 2).

2. Com'l Only, 0°C to +70°C temperature range. PLCC and TQFP package.

3. “X” in part numbers indicates power rating (SA or LA).

4. This parameter is guaranteed by device characterization, but is not production tested.

5. Not available in DIP packages.

TIMING WAVEFORM OF READ CYCLE NO. 1, EITHER SIDE(1)

ADDRESS

DATA

OUT

PREVIOUS DATA VALID

DATA VALID

2689 drw 08

BDD

(2,3)

BUSY

OUT

NOTES:

1. R/

= VIH,

= VIL, and is

= VIL. Address is valid prior to the coincidental with

transition Low.

2. tBDD delay is required only in the case where the opposite port is completing a write operation to the same the

address location. For simultaneous read operations,

BUSY

has no relationship to valid output data.

3. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA, and tBDD.

6.01 7

IDT7130SA/LA AND IDT7140SA/LA

HIGH-SPEED 1K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS MILITARY AND COMMERCIAL TEMPERATURE RANGES

TIMING WAVEFORM OF READ CYCLE NO. 2, EITHER SIDE(3)

AC ELECTRICAL CHARACTERISTICS OVER THE

OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(5)

7130X20(2) 7130X25(6) 7130X35 7130X55 7130X100

7140X25(6) 7140X35 7140X55 7140X100

Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit

Write Cycle

tWC Write Cycle Time(3) 20 — 25 — 35 — 55 — 100 — ns

tEW Chip Enable to End-of-Write 15 — 20 — 30 — 40 — 90 — ns

tAW Address Valid to End-of-Write 15 — 20 — 30 — 40 — 90 — ns

tAS Address Set-up Time 0 — 0 — 0 — 0 — 0 — ns

tWP Write Pulse Width(4) 15 — 15 — 25 — 30 — 55 — ns

tWR Write Recovery Time 0 — 0 — 0 — 0 — 0 — ns

tDW Data Valid to End-of-Write 10 — 12 — 15 — 20 — 40 — ns

tHZ Output High-Z Time(1) —10 —10 —15 —25 —40 ns

DH Data Hold Time 0 — 0 — 0 — 0 — 0 — ns

tWZ Write Enabled to Output in High-Z(1) —10 —10 —15 —25 —40 ns

OW Output Active From End-of-Write(1) 0— 0— 0— 0— 0— ns

NOTES: 2689 tbl 10

1. Transition is measured ±500mV from Low or High-impedance voltage with Output Test Load (Figure 2). This parameter is guaranteed by

device characterization but is not production tested.

2. 0°C to +70°C temperature range only, PLCC and TQFP packages.

3. For MASTER/SLAVE combination, tWC = tBAA + tWP, since R/

= VIL must occur after tBAA.

4. If

is low during a R/

controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off

data to be placed on the bus for the required tDW. If

is High during a R/

controlled write cycle, this requirement does not apply and the

write pulse can be as short as the specified tWP.

5. “X” in part numbers indicates power rating (SA or LA).

6. Not available in DIP packages.

ACE

AOE

VALID DATA

50%

DATA

OUT

CURRENT

50%

2689 drw 09

(4)

(1)

(1) (2)

(2)

(4)

NOTES:

1. Timing depends on which signal is asserted last,

2. Timing depends on which signal is deaserted first,

3. R/

= VIH and the address is valid prior to or coincidental with

transition Low.

4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA, and tBDD.

IDT7130SA/LA AND IDT7140SA/LA

HIGH-SPEED 1K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS MILITARY AND COMMERCIAL TEMPERATURE RANGES

6.01 8

TIMING WAVEFORM OF WRITE CYCLE NO. 2, (

CECE

CONTROLLED TIMING)(1,5)

NOTES:

1. R/

must be High during all address transitions.

2. A write occurs during the overlap (tEW or tWP) of

= VIL and R/

= VIL.

3. tWR is measured from the earlier of

or R/

going High to the end of the write cycle.

4. During this period, the l/O pins are in the output state and input signals must not be applied.

5. If the

Low transition occurs simultaneously with or after the R/

Low transition, the outputs remain in the High-impedance state.

6. Timing depends on which enable signal (

or R/

) is asserted last.

7. This parameter is determined be device characterization, but is not production tested. Transition is measured +/- 500mV from steady state

with the Output Test Load (Figure 2).

8. If

is low during a R/

controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off

and data to be placed on the bus for the required tDW. If

is High during a R/

controlled write cycle, this requirement does not apply and

the write pulse can be as short as the specified tWP.

TIMING WAVEFORM OF WRITE CYCLE NO. 1, (R/

CONTROLLED TIMING)(1,5,8)

tWC

ADDRESS

DATAOUT

DATAIN

tAS

tOW

tDW tDH

tAW

tWP(2)

tHZ

(4) (4)

tWZ

tHZ

2689 drw 10

(6)

(7)

(3) (7)

tWR

ADDRESS

DATA

2689 drw 11

(6) (2) (3)

6.01 9

IDT7130SA/LA AND IDT7140SA/LA

HIGH-SPEED 1K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS OVER THE

OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(7)8M824S258M824S30 7132158M824S4

7130X20(1) 7130X25(9) 7130X35 7130X55 7130X100

7140X25(9) 7140X35 7140X55 7140X100

Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit

Busy Timing (For Master lDT7130 Only)

tBAA

BUSY

Access Time from Address — 20 — 20 — 20 — 30 — 50 ns

tBDA

BUSY

Disable Time from Address — 20 — 20 — 20 — 30 — 50 ns

tBAC

BUSY

Access Time from Chip Enable — 20 — 20 — 20 — 30 — 50 ns

tBDC

BUSY

Disable Time from Chip Enable — 20 — 20 — 20 — 30 — 50 ns

tWH Write Hold After

BUSY

(6) 12 — 15 — 20 — 20 — 20 — ns

tWDD Write Pulse to Data Delay(2) — 40 — 50 — 60 — 80 — 120 ns

tDDD Write Data Valid to Read Data Delay(2) — 30 — 35 — 35 — 55 — 100 ns

tAPS Arbitration Priority Set-up Time(3) 5— 5— 5 — 5—5 — ns

BDD

BUSY

Disable to Valid Data(4) — 25 — 35 — 35 — 50 — 65 ns

Busy Timing (For Slave IDT7140 Only)e 5—5—5—5—5

WB Write to

BUSY

Input(5) 0— 0— 0 — 0—0 — ns

WH Write Hold After

BUSY

(6) 12 — 15 — 20 — 20 — 20 — ns

tWDD Write Pulse to Data Delay(2) — 40 — 50 — 60 — 80 — 120 ns

tDDD Write Data Valid to Read Data Delay(2) — 30 — 35 — 35 — 55 — 100 ns

NOTES: 2689 tbl 11

1. Com'l Only, 0°C to +70°C temperature range. PLCC and TQFP packages only.

2. Port-to-port delay through RAM cells from the writing port to the reading port, refer to “Timing Waveform of Write with Port-to-Port Read and

BUSY

3. To ensure that the earlier of the two ports wins.

4. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual), or tDDD – tDW (actual).

5. To ensure that a write cycle is inhibited on port 'B' during contention on port 'A'.

6. To ensure that a write cycle is completed on port 'B' after contention on port 'A'.

7. “X” in part numbers indicates power rating (SA or LA).

8. Not available in DIP packages.

TIMING WAVEFORM OF WRITE WITH PORT-TO-PORT READ AND

BUSYBUSY

BUSY

BDD

DDD

BDA

WDD

ADDR

’B’

DATA

OUT’B’

DATA

IN’A’

ADDR

’A’

MATCH

VALID

MATCH

VALID

’A’

BUSY

’B’

APS

2689 drw 12

(1)

NOTES:

1. To ensure that the earlier of the two ports wins. tBDD is ignored for slave (IDT7140).

L =

R = VIL.

3. OE = VIL for the reading port.

4. All timing is the same for the left and right ports. Port 'A' may be either the left or right port. Port "B" is opposite from port "A".

(2,3,4)

IDT7130SA/LA AND IDT7140SA/LA

HIGH-SPEED 1K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS MILITARY AND COMMERCIAL TEMPERATURE RANGES

6.01 10

TIMING WAVEFORM OF WRITE WITH

BUSYBUSY

BUSY

(3)

BUSY

'B'

2689 drw 13

'A'

'B'

(2)

(1)

NOTES:

1. tWH must be met for both BUSY Input (IDT7140, slave) or Output (IDT7130 master).

2. BUSY is asserted on port 'B' blocking R/W'B', until BUSY'B' goes High.

3. All timing is the same for the left and right ports. Port 'A' may be either the left or right

port. Port "B" is opposite from port "A".

TIMING WAVEFORM OF BUSY ARBITRATION CONTROLLED BY

CECE

TIMING (1)

TIMING WAVEFORM OF BUSY ARBITRATION CONTROLLED BY ADDRESS MATCH TIMING (1)

NOTES:

1. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.

2. If tAPS is not satisified, the

BUSY

will be asserted on one side or the other, but there is no guarantee on which side

BUSY

will be

asserted (7130 only).

APS

ADDR

'A'

AND

'B'

ADDRESSES MATCH

BAC

BDC

'B'

'A'

BUSY

'A'

2689 drw 14

(2)

BUSY

'B'

ADDRESSES DO NOT MATCH

ADDRESSES MATCH

APS

ADDR

'A'

ADDR

'B'

2689 drw 15

(2)

BAA

BDA

6.01 11

IDT7130SA/LA AND IDT7140SA/LA

HIGH-SPEED 1K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS OVER THE

OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(2) 8M824S25 8M824S308M824S35

7130X20(1) 7130X25(3) 7130X35 7130X55 7130X100

7140X25(3) 7140X35 7140X55 7140X100

Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit

Interrupt Timing

tAS Address Set-up Time 0 — 0 — 0 — 0 — 0 — ns

tWR Write Recovery Time 0 — 0 — 0 — 0 — 0 — ns

tINS Interrupt Set Time — 20 — 25 — 25 — 45 — 60 ns

tINR Interrupt Reset Time — 20 — 25 — 25 — 45 — 60 ns

2689 tbl 12

NOTES:

1. 0°C to +70°C temperature range only, PLCC and TQFP packages.

2. “X” in part numbers indicates power rating (SA or LA).

3. Not available in DIP packages .

INTINT

INT

SET:

TIMING WAVEFORM OF INTERRUPT MODE

INTINT

INT

CLEAR:

NOTES:.

1. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.

2. See Interrupt Truth Table.

3. Timing depends on which enable signal (

or R/

) is asserted last.

4. Timing depends on which enable signal (

or R/

) is de-asserted first.

INS

ADDR

'A'

INT

'B'

INTERRUPT ADDRESS

'A'

2689 drw 16

(3)

(2)

(4)

INTERRUPT CLEAR ADDRESS

ADDR

'B'

INR

INT

'B'

2689 drw 17

(3)

IDT7130SA/LA AND IDT7140SA/LA

HIGH-SPEED 1K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS MILITARY AND COMMERCIAL TEMPERATURE RANGES

6.01 12

TRUTH TABLES

TABLE I — NON-CONTENTION

READ/WRITE CONTROL(4)

Left or Right Port(1)

CECE

CE OEOE

OEOE

D0–7 Function

X H X Z Port Disabled and in Power-

Down Mode, ISB2 or ISB4

XHX Z

R =

L = VIH, Power-Down

Mode, ISB1 or ISB3

L L X DATAIN Data on Port Written I nto Memory(2)

H L L DATAOUT Data in Memory Output on Port(3)

H L H Z High Impedance Outputs

NOTES: 2689 tbl 13

1. A0L – A10L ≠ A0R – A10R.

2. If

BUSY

= L, data is not written.

3. If

BUSY

= L, data may not be valid, see tWDD and tDDD timing.

4. 'H' = VIH, 'L' = VIL, 'X' = DON’T CARE, 'Z' = HIGH IMPEDANCE

TABLE III — ADDRESS BUSY ARBITRATION

Inputs Outputs

A0L-A9L

CECE

RA0R-A9R

BUSYBUSY

BUSY

L(1)

BUSYBUSY

BUSY

R(1) Function

NO MATCH H H Normal

MATCH H H Normal

MATCH (2) (2) Write Inhibit(3)

NOTES: 2689 tbl 15

1. Pins

BUSY

L and

BUSY

R are both outputs for IDT7130 (master). Both are

inputs for IDT7140 (slave).

BUSY

X outputs on the IDT7130 are open drain,

not push-pull outputs. On slaves the

BUSY

X input internally inhibits writes.

2. 'L' if the inputs to the opposite port were stable prior to the address and

enable inputs of this port. 'H' if the inputs to the opposite port became

stable after the address and enable inputs of this port. If tAPS is not met,

either

BUSY

L or

BUSY

R = Low will result.

BUSY

L and

BUSY

R outputs can

not be low simultaneously.

3. Writes to the left port are internally ignored when

BUSY

L outputs are

driving Low regardless of actual logic level on the pin. Writes to the right

port are internally ignored when

BUSY

R outputs are driving Low regard-

less of actual logic level on the pin.

TABLE II — INTERRUPT FLAG(1,4)

Left Port Right Port

CECE

OEOE

LA9L – A0L

INTINT

INT

LR/

CECE

OEOE

RA9L – A0R

INTINT

INT

RFunction

LLX 3FF XXXX X L

(2) Set Right

INT

R Flag

X X X X X X L L 3FF H(3) Reset Right

INT

R Flag

XXX X L

(3) L L X 3FE X Set Left

INT

L Flag

X L L 3FE H(2) X X X X X Reset Left

INT

L Flag

NOTES:2689 tbl 14

1. Assumes

BUSY

L =

BUSY

R = VIH

2. If

BUSY

L = VIL, then No Change.

3. If

BUSY

R = VIL, then No Change.

4. 'H' = HIGH,' L' = LOW,' X' = DON’T CARE

6.01 13

IDT7130SA/LA AND IDT7140SA/LA

HIGH-SPEED 1K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS MILITARY AND COMMERCIAL TEMPERATURE RANGES

FUNCTIONAL DESCRIPTION

The IDT7130/IDT7140 provides two ports with separate con-

trol, address and I/O pins that permit independent access for

reads or writes to any location in memory. The IDT7130/

IDT7140 has an automatic power down feature controlled by

. The

controls on-chip power down circuitry that permits

the respective port to go into a standby mode when not

selected (

= VIH). When a port is enabled, access to the

entire memory array is permitted.

INTERRUPTS

If the user chooses to use the interrupt function, a memory

location (mail box or message center) is assigned to each

port. The left port interrupt flag (

INT

L) is asserted when the

right port writes to memory location 3FE (HEX), where a write

is defined as the

= R/

= VIL per the Truth Table. The left

port clears the interrupt by access address location 3FE

access when

R =

R = VIL, R/

is a "don't care". Likewise,

the right port interrupt flag (

INT

R) is asserted when the left port

writes to memory location 3FF (HEX) and to clear the interrupt

flag (

INT

R), the right port must access the memory location

3FF. The message (8 bits) at 3FE or 3FF is user-defined,

since it is an addressable SRAM location. If the interrupt

function is not used, address locations 3FE and 3FF are not

used as mail boxes, but as part of the random access

memory. Refer to Table II for the interrupt operation.

BUSY LOGIC

Busy Logic provides a hardware indication that both ports of

the RAM have accessed the same location at the same time.

It also allows one of the two accesses to proceed and signals

the other side that the RAM is “Busy”. The Busy pin can then

be used to stall the access until the operation on the other side

is completed. If a write operation has been attempted from the

side that receives a busy indication, the write signal is gated

internally to prevent the write from proceeding.

The use of busy logic is not required or desirable for all

applications. In some cases it may be useful to logically OR

the busy outputs together and use any busy indication as an

interrupt source to flag the event of an illegal or illogical

operation. In slave mode the

BUSY

pin operates solely as a

write inhibit input pin. Normal operation can be programmed

by tying the

BUSY

pins High. If desired, unintended write

operations can be prevented to a port by tying the Busy pin for

that port Low.

The Busy outputs on the IDT7130 RAM (Master) are open

drain type outputs and require open drain resistors to operate.

If these RAMs are being expanded in depth, then the Busy

indication for the resulting array does not require the use of an

external AND gate.

WIDTH EXPANSION WITH BUSY LOGIC

MASTER/SLAVE ARRAYS

When expanding an RAM array in width while using busy

logic, one master part is used to decide which side of the RAM

array will receive a busy indication, and to output that indica-

tion. Any number of slaves to be addressed in the same

address range as the master, use the busy signal as a write

inhibit signal. Thus on the IDT7130/IDT7140 RAMs the Busy

pin is an output if the part is Master (IDT7130), and the Busy

pin is an input if the part is a Slave (IDT7140) as shown in

Figure 4.

If two or more master parts were used when expanding in

width, a split decision could result with one master indicating

busy on one side of the array and another master indicating

busy on one other side of the array. This would inhibit the write

operations from one port for part of a word and inhibit the write

operations from the other port for the other part of the word.

The Busy arbitration, on a Master, is based on the chip enable

and address signals only. It ignores whether an access is a

read or write. In a master/slave array, both address and chip

enable must be valid long enough for a busy flag to be output

from the master before the actual write pulse can be initiated

with either the R/

signal or the byte enables. Failure to

observe this timing can result in a glitched internal write inhibit

signal and corrupted data in the slave.

2689 drw 18

MASTER

Dual Port

RAM

BUSY

(L)

BUSY

(R)

MASTER

Dual Port

RAM

BUSY

(L)

BUSY

(R)

SLAVE

Dual Port

RAM

BUSY

(L)

BUSY

(R)

SLAVE

Dual Port

RAM

BUSY

(L)

BUSY

(R)

BUSY

DECODER

5V 5V

270Ω

Figure 4. Busy and chip enable routing for both width and depth

expansion with IDT7130 (Master) and IDT7140 (Slave) RAMs.

IDT7130SA/LA AND IDT7140SA/LA

HIGH-SPEED 1K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS MILITARY AND COMMERCIAL TEMPERATURE RANGES

6.01 14

ORDERING INFORMATION

48-pin Plastic DIP (P48-1)

48-pin Sidebraze DIP (C48-2)

52-pin PLCC (J52-1)

48-pin LCC (L48-1)

48-pin Ceramic Flatpack (F48-1)

64-pin TQFP (PN64-1)

64-pin STQFP (PP64-1)

XXXXIDT Device Type A 999 A A

Power Speed Package Process/

Temperature

Range

7130

7140

Speed in nanoseconds

8K (1K x 8-Bit) MASTER Dual-Port RAM

8K (1K x 8-Bit) SLAVE Dual-Port RAM

Commercial PLCC and TQFP Only

LCC, PLCC, and TQFP Only

2689 drw 19

Blank

BCommercial (0°C to +70°C)

Military (–55°C to +125°C)

Compliant to MIL-STD-883, Class B

L48

100

SA Low Power

Standard Power