LT5554
1
5554f
FREQUENCY (MHz)
0
SFDR (dBm/Hz)
132
130
128
126
OIP3 (dBm)
49
46
43
40
50 100 150
5554 TA01b
200
SFDR
OIP3
ROUT = 50
TYPICAL APPLICATION
FEATURES
APPLICATIONS
DESCRIPTION
Broadband Ultra Low
Distortion 7-Bit Digitally
Controlled VGA
The LT
®
5554 is a 7-bit digitally controlled programmable
gain (PG) amplifi er with 16dB gain control range. It
consists of a 50 input variable attenuator, followed by
a high linearity variable transconductance amplifi er. The
coarse 4dB input attenuator step is implemented via 2-bits
of digital control (PG5, PG6). The fi ne transconductance
amplifi er 0.125dB step within 3.875dB gain control range
is set via 5-bits digital control (PG0 to PG4). The LT5554
gain control inputs (PGx) and the STROBE input can be
directly coupled to TTL or ECL drivers. The seven parallel
gain control inputs time skew can be eliminated by using
the STROBE input positive transition.
The internal output resistor RO = 400 limits the maxi-
mum overall gain to 36dB for open outputs. The internal
circuitry of open output collectors enables the LT5554 to
be unconditionally stable over any loading conditions (in-
cluding external SAW fi lters) and provides –80dB reverse
isolation at 300MHz.
The LT5554 is internally protected during overdrive and
has an on-chip power supply regulator.
With 0.125dB step resolution and 5ns settling time, the
LT5554 is suitable in applications where continuous gain
control is required.
n 1GHz Bandwidth at all Gains
n 48dBm OIP3 at 200MHz, 2VP-P into 50,
ROUT = 100
n –88dBc IMD3 at 200MHz, 2VP-P into 50,
ROUT = 100
n 1.4nV/√Hz Input-Referred-Noise (RTI)
n 20dBm Output P1dB at 70MHz, ROUT = 130
n 2dB to 18dB Gain Range (ROUT = 50)
n 0.125dB Gain Step Size
n 30ps Group Delay Variation
n 5ns Fast Gain Settling Time
n 5ns Fast Overdrive Recovery
n –80dB Reverse Isolation
n Differential ADC Driver
n IF Sampling Receivers
n VGA IF Power Amplifi er
n 50 Driver
n Instrumentation
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other
trademarks are the property of their respective owners.
RF
INPUT
LO
0.1µF
0.1µF
CDEC
0.1µF
IF
BPF BPF ADC
IF
AMPLIFIER LT5554DEC
IN+
VCC MODE
STROBE
5554 TA01
PGx GAIN CONTROL
5V
IN–+
–
7 BITS
OIP3 and SFDR vs Frequency
LT5554
2
5554f
PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS
Supply Voltage
VCC ..........................................................................6V
Pin Voltages and Currents
OUT+, OUT– ............................................................7V
STROBE, PGx ..........................................–0.5V to VCC
ENB, MODE .............................................–0.5V to VCC
IN+, IN–, DEC ........................................... –0.5V to 4V
Operating Ambient Temperature Range
LT5554 ............................................... –40°C to +85°C
Junction Temperature ........................................... 125°C
Storage Temperature Range ................. –65°C to +150°C
(Notes 1, 2)
32 31 30 29 28 27 26 25
9 10 11 12
TOP VIEW
UH PACKAGE
32-LEAD (5mm s 5mm) PLASTIC QFN
13 14 15 16
17
18
19
20
21
22
23
24
33
8
7
6
5
4
3
2
1GND
GND
DEC
IN+
IN–
DEC
GND
GND
VCC
ENB
GND
OUT–
OUT+
GND
MODE
VCC
PG1
GND
PG2
PG3
GND
PG4
GND
GND
PG5
GND
PG6
PG0
GND
STROBE
GND
GND
TJMAX = 150°C, θJA = 34°C/W, θJC = 3°C/W
EXPOSED PAD (PIN 33) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE
LT5554IUH#PBF LT5554IUH#TRPBF 5554 32-Lead (5mm × 5mm) Plastic QFN –40°C to 85°C
Consult LTC Marketing for parts specifi ed with wider operating temperature ranges.
Consult LTC Marketing for information on non-standard lead based fi nish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifi cations, go to: http://www.linear.com/tapeandreel/
LT5554
3
5554f
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT
Dynamic Performance
BW Large Signal –3dB Bandwidth All Gain Settings (Note 7) LF – 1000 MHz
OP1dB Output 1dB Compression Point All Gain Settings, ROUT = 130, 70MHz 20 dBm
GMAmplifi er Transconductance at GMAX FIN = 100MHz 0.15 S
CMRR Common Mode Gain to Single-Ended
Output FIN = 100MHz, Figure 19 –6 dB
S12 Reverse Isolation FIN = 100MHz
FIN = 400MHz –86
–78 dB
dB
Overdrive Recovery Time 5ns Input Pulse, VOUT within ±10% 5 ns
Noise/Linearity Performance Two Tones, POUT = 4dBm/Tone (2VP-P into 50), ∆f = 200kHz
IIP3 Input Third Order Intercept Point GMAX, FIN = 200MHz
GMAX –3.875dB, FIN = 200MHz 27
30 dBm
dBm
OIP3 Output Third Order Intercept Point for
Max-Gain FIN = 100MHz
FIN = 200MHz 45
46 dBm
dBm
IMD3 Intermodulation Product for Max-Gain FIN = 100MHz
FIN = 200MHz –82
–84 dBc
dBc
OIP3 Output Third Order Intercept Point for
–3.875dB STEP FIN = 100MHz
FIN = 200MHz 44
40 dBm
dBm
OIP3 Output Third Order Intercept Point GMAX, F1 = 88MHz, F2 = 112MHz
GMAX –3.875dB, F1 = 88MHz, F2 = 112MHz 40.5
38 47
44 dBm
dBm
HD3 Third Harmonic Distortion Pout = 10dBm, FIN = 100MHz, GMAX –62 dBc
VONOISE Output Noise Noise Spectral Density GMAX, FIN = 200MHz
GMAX –3.875dB, FIN = 200MHz 10.7
7.3 nV/√Hz
nV/√Hz
NF Noise Figure GMAX, FIN = 200MHz
GMAX –3.875dB, FIN = 200MHz 10
10.5 dB
dB
RTI Input Referred Noise Spectral Density
(RMS) (Note 5) GMAX, FIN = 200MHz
GMAX –3.875dB, FIN = 200MHz 1.34
1.42 nV/√Hz
nV/√Hz
SFDR Spurious Free Dynamic Range in 1Hz
BW. GMAX, FIN = 200MHz
GMAX –3.875dB, FIN = 200MHz 128
129 dBm/Hz
dBm/Hz
Amplifi er Voltage Gain and Gain Step
GMAX Maximum Voltage and Power Gain FIN = 112MHz 15.3 17.6 19.7 dB
GMIN Minimum Voltage and Power Gain FIN = 100MHz 1.725 dB
GSTEP Gain Step Size (Note 9) Except For –4dB, –8dB, –12dB Steps
For –4dB, –8dB, –12dB Steps 0.125 0.25
0.35 dB
dB
GDERROR Group Delay Step Accuracy FIN = 100MHz 10 ps
AMPLIFIER I/O Differential IMPEDANCE
RIN Input Resistance FIN = 100MHz, GMAX to GMAX –3.875dB
FIN = 100MHz, GMAX –4dB to GMIN
43
47 Ω
Ω
CIN Input Capacitance FIN = 100MHz 2.8 pF
ROOutput Resistance FIN = 100MHz 400 Ω
COOutput Capacitance FIN = 100MHz 1.9 pF
AC ELECTRICAL CHARACTERISTICS
(ROUT = 50) Specifi cations are at TA = 25°C. VCC = 5V, VCCO = 5V,
ENB = 3V, MODE = 5V, STROBE = 2.2V, VIH = 2.2V, VIL = 0.6V, maximum gain (Notes 3, 6), (Test circuits shown in Figure 16), unless
otherwise noted.
LT5554
4
5554f
AC ELECTRICAL CHARACTERISTICS
(ROUT = 100) Specifi cations are at TA = 25°C. VCC = 5V, VCCO = 5V,
ENB = 3V, MODE = 5V, STROBE = 2.2V, VIH = 2.2V, VIL = 0.6V, maximum gain (Notes 3, 8), (Test circuits shown in Figure 16), unless
otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT
Noise/Linearity Performance Two Tones, POUT = 4dBm/Tone (2VP-P into 50), ∆f = 200kHz
IIP3 Input Third Order Intercept Point GMAX, FIN = 200MHz
GMAX –3.875dB, FIN = 200MHz 27
27 dBm
dBm
OIP3 Output Third Order Intercept Point for
Max-Gain FIN = 100MHz
FIN = 200MHz 48
48 dBm
dBm
IMD3 Intermodulation Product for Max-Gain FIN = 100MHz
FIN = 200MHz –88
–88 dBc
dBc
VONOISE Output Noise Noise Spectral Density GMAX, FIN = 200MHz
GMAX –3.875dB, FIN = 200MHz 21.4
14.5 nV/√Hz
nV/√Hz
NF Noise Figure GMAX, FIN = 200MHz
GMAX –3.875dB, FIN = 200MHz 10
10.5 dB
dB
RTI Input Referred Noise Spectral Density
(RMS) (Note 5) GMAX, FIN = 200MHz
GMAX –3.875dB, FIN = 200MHz 1.34
1.42 nV/√Hz
nV/√Hz
SFDR Spurious Free Dynamic Range in
1Hz BW. GMAX, FIN = 200MHz 128 dBm/Hz
GVMAX Maximum Voltage Gain FIN = 100MHz 23.6 dB
GPMAX Maximum Power Gain FIN = 100MHz 20.6 dB
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT
PGx and Strobe Timing Characteristics
TSU Setup Time PGx vs STROBE 0ns
THOLD Hold Time PGx vs STROBE 1ns
TPW STROBE Pulse Width 2ns
TRSTROBE Period 4ns
TLATENCY Latency Time of the Previous Gain State Output Settles within 1% 4 ns
TGLITCH Time Between Previous Stable Gain State
to Next Stable State Output Settles within 1% 5 ns
AGLITCH Max Glitch Amplitude VIN = 0 (No Signal or STROBE Transition During
Output Signal Zero Crossing) 1mV
STROBE Transition when Output Power is at
Peak + 10dBm Power 3dB
AC ELECTRICAL CHARACTERISTICS (Timing Diagram)
(ROUT = 50) Specifi cations are
at TA = 25°C. VCC = 5V, VCCO = 5V, ENB = 3V, MODE = 5V, STROBE = 3V, VIH = 2.2V, VIL = 0.6V, maximum gain (Test circuit shown in
Figure 16), unless otherwise noted.
LT5554
5
5554f
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT
Normal Operating Conditions
VCC Supply Voltage 4.75 5 5.25 V
VCCO OUT+, OUT– Output Pin DC Common Mode
Voltage (Note 4) 5 6 V
Shutdown DC Characteristics, ENB = 0.6V
VIN(BIAS) DEC, IN+, IN– Bias Voltage 2 2.15 V
IIL(PG) PGx, STR Input Current VIN = 0.6V 0 µA
IIH(PG) PGx, STR Input Current VIN = 5V 210 µA
IOUT OUT+, OUT– Current 20 µA
ICC VCC Supply Current 4 5.1 mA
Enable Input DC Characteristics
VIL(EN) ENB Input LOW Voltage Disable 0.6 V
VIH(EN) ENB Input HIGH Voltage Enable 3 VCC V
IIL(EN) ENB Input Current VIN = 0.6V 20 µA
IIH(EN) ENB Input Current VIN = 3V 70 µA
IIH(EN) ENB Input Current VIN = 5V 220 300 µA
DC ELECTRICAL CHARACTERISTICS
Specifi cations are at TA = 25°C. VCC = 5V, VCCO = 5V, ENB = 3V,
MODE = 5V, unless otherwise noted. (Note 3) (Test circuit shown in Figure 16), unless otherwise noted.
Timing Diagram
PG0, 1, 2, 3, 4, 5, 6
INPUTS
STROBE
INPUTS
5554 TD01
OUT SIGNAL
TLATENCY
TSU
STATE (i)
DATA
TRANSPARENT
DATA
LATCH
STATE (i + 1) STATE (i + 2)
THOLD TPW
TGLITCH
AC ELECTRICAL CHARACTERISTICS (Timing Diagram)
LT5554
6
5554f
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT
DEC External Capacitor Charge/Discharge CURRENT
IIH(DEC) DEC Pin Source Current VDEC = 4V 27 50 70 mA
IIL(DEC) DEC Pin Sink Current VDEC = 1.8V –70 –38 –14 mA
Mode Input Three-State DC Characteristics
VIL(MODE) MODE Input LOW Voltage for AC-Couple PGx AC-Coupled, STROBE AC-Coupled 0 0.6 V
VOPEN(MODE) MODE Input OPEN PGx AC-Coupled, STROBE DC-Coupled 1.7 OPEN 2.3 V
VIH(MODE) MODE Input HIGH Voltage PGx DC-Coupled, STROBE DC-Coupled VCC – 0.4 VCC V
IIL(MODE) MODE Input Current VMODE = 0V –42 –31 –23 µA
IIH(MODE) MODE Input Current VMODE = 5V 43 72 100 µA
PGx (MODE = VCC) and STROBE (MODE = OPEN or MODE = VCC) INPUTS for DC-Coupled
VIL Input LOW Voltage 0.6 V
VIH Input HIGH Voltage 2.2 V
IIL(DC) Input Current VIN = 0.6V 30 µA
IIH(DC) Input Current VIN = 5V 125 170 220 µA
PGx (MODE = 0V or MODE = OPEN) and STROBE (MODE = 0V) INPUTS for AC-Coupled
VIN(AC) Input Pulse Range Instantaneous Input Voltage 0 4.6 V
VIN(AC)P-P Input Pulse Amplitude Rise and Fall Time <5ns
Rise and Fall Time >80ns 600
300 mVP-P
mVP-P
VIN(AC)MAX Maximum Input Noise Amplitude No LT5554 Gain Update 100 mVP-P
IIL(AC) Input Current VIN = 0V –210 –155 –100 µA
IIH(AC) Input Current VIN = 5V 310 420 530 µA
Amplifi er DC Characteristics
VIN(DEC) DEC GMAX 1.85 2 2.25 V
VIN(BIAS) IN+, IN– Bias Voltage GMAX 1.8 2.04 2.2 V
RIN INPUT Differential Resistance GMAX
GMIN
48
50 Ω
Ω
GMAmplifi er Transconductance GMAX 0.15 S
IODC OUT+, OUT– Quiescent Current VOUT = 5V 33 47 57 mA
IOUT(OFFSET) Output Current Mismatch IN+, IN– Open 200 µA
ICC VCC Supply Current GMAX, MODE = 0V
GMIN, MODE = 0V
GMAX, MODE = 5V
GMIN, MODE = 5V
78
77
75
75
110
109
106
106
132
131
127
127
mA
mA
mA
mA
ICC(TOTAL) Total Supply Current ICC + 2 • IODC (GMAX) 200 mA
DC ELECTRICAL CHARACTERISTICS
Specifi cations are at TA = 25°C. VCC = 5V, VCCO = 5V, ENB = 3V,
MODE = 5V, unless otherwise noted. (Note 3) (Test circuit shown in Figure 16), unless otherwise noted.
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to GND ground.
Note 3: RS = RIN = 50 Input matching is assumed. PIN is the available
input power. POUT is the power into ROUT
. ROUT = RO || RLOAD is the total
output resistance at amplifi er open-collectors outputs (used in GV, GP gain
calculation). RO = 400Ω is LT5554 internal output impedance. RLOAD is
load resistance as seen at OUT+, OUT– pins.
All dBm fi gures are with respect to 50. Specifi cations refer to differential
inputs and differential outputs.
Note 4: An external power supply equal to VCCO is used for choke
inductors or center-tap transformer output interfaces. Whenever OUT+,
OUT– pins are biased via resistors, the voltage drop produced by the DC-
output current (IODC = 45mA typical) may require a larger output external
power supply. However, care must be taken not to exceed the OUT+,
OUT– absolute maximum rating when the LT5554 is disabled.
LT5554
7
5554f
FREQUENCY (MHz)
0
GAIN (dB)
20
18
16
12
8
4
14
10
6
2
0500 900300 700
5554 G01
1000400 800200 600100
Note 5: RTI (Referred-To-Input) stands for the total input-referred noise
voltage source. RTI is close to output noise voltage divided by voltage gain
(the exact equation is given in Defi nition of Specifi cation section). The
equivalent noise source eN is twice the RTI value.
Note 6: The external loading at LT5554 OUT+/OUT– pins is RLOAD = 57.
ROUT = RLOAD || RO = 50.
Note 7: The IN+, IN–, DEC pins are internally biased. The time-constant
of input coupling capacitor sets the low frequency corner (LF) at input.
The output coupling capacitors or the transformer sets the low frequency
corner (LF) at the output. The LT5554 operates internally down to DC.
Note 8: The external loading at OUT+/OUT– pins is RLOAD = 133.
ROUT = RLOAD || RO = 100.
Note 9: Depending on the actual input matching conditions and frequency
of operation, the LT5554 steps involving the input attenuator tap change
may show less than 0.125dB change. These steps are GMAX –4dB, GMAX
–8dB, GMAX –12dB, and the code is given in the Programmable Gain Table.
The LT5554 monotonic operation for 0.125dB step resolution can still be
obtained by skipping any such code with a gain error excedding 0.125dB.
TYPICAL PERFORMANCE CHARACTERISTICS
Gain vs Frequency for
0.5dB Steps, Figure 17
Differential Gain Error vs
Frequency at –40°C
Differential Gain Error vs
Frequency at 85°C
ELECTRICAL CHARACTERISTICS
(ROUT = 50) TA = 25°C. VCC = 5V, VCCO = 5V,
ENB = 3V, MODE = 5V, STROBE = 3V, VIH = 2.2V, VIL = 0.6V (Test circuit shown in Figure 16), unless otherwise noted.
FREQUENCY (MHz)
50
GAIN ERROR (dB)
0.3
0.2
0.1
0
–0.1
–0.2
5554 G02
200125 175100 15075
12dB
4dB
8dB
FREQUENCY (MHz)
50
GAIN ERROR (dB)
0.3
0.2
0.1
0
–0.1
–0.2
5554 G03
200125 175100 15075
12dB
4dB
8dB
Differential Gain Error vs
Attenuation at 50MHz
Differential Gain Error vs
Attenuation at 100MHz
Differential Gain Error vs
Attenuation at 200MHz
ATTENUATION (dB)
0
GAIN ERROR (dB)
0.3
0.2
0.1
0
–0.1
–0.2
5554 G04
–16–4 –12–8
–40°C
25°C
85°C
ATTENUATION (dB)
0
GAIN ERROR (dB)
0.3
0.2
0.1
0
–0.1
–0.2
5554 G05
–16–4 –12–8
–40°C
25°C
85°C
ATTENUATION (dB)
0
GAIN ERROR (dB)
0.3
0.2
0.1
0
–0.1
–0.2
5554 G06
–16–4 –12–8
–40°C
25°C
85°C
LT5554
8
5554f
ATTENUATION (dB)
0
GAIN ERROR (dB)
0.4
0.3
0.2
0.1
0
–0.1
5554 G08
–16–4 –12–8
–40°C
25°C
85°C
TYPICAL PERFORMANCE CHARACTERISTICS
Integral Gain Error vs
Attenuation at 50MHz
Integral Gain Error vs
Attenuation at 100MHz
Integral Gain Error vs
Attenuation at 200MHz
(ROUT = 50) TA = 25°C. VCC = 5V, VCCO = 5V,
ENB = 3V, MODE = 5V, STROBE = 3V, VIH = 2.2V, VIL = 0.6V (Test circuit shown in Figure 16), unless otherwise noted.
Maximum Gain vs Temperature POUT vs PIN at Maximum Gain POUT vs PIN at GMAX – 3.875dB
ATTENUATION (dB)
0
GAIN ERROR (dB)
0.4
0.3
0.2
0.1
0
–0.1
5554 G07
–16–4 –12–8
–40°C
25°C
85°C
ATTENUATION (dB)
0
GAIN ERROR (dB)
0.4
0.3
0.2
0.1
0
–0.1
5554 G09
–16–4 –12–8
–40°C
25°C
85°C
TEMPERATURE (°C)
–40
GMAX (dB)
18.0
17.8
17.6
17.4
17.2
17.0
5554 G10
8020 60040–20
50MHz
100MHz
200MHz
PIN (dBm)
–35
POUT (dBm)
24
16
8
0
–8
–16
5554 G11
15–5–15 5–25
70MHz
140MHz
200MHz
PIN (dBm)
–35
5554 G12
15–5–15 5–25
70MHz
140MHz
200MHz
POUT (dBm)
24
16
8
0
–8
–16
Two-Tone OIP3 vs Frequency at
Max Gain, Three Temperatures
Two-Tone IMD3 vs Frequency at
Max Gain, Three Temperatures
IIP3 vs Frequency at Max Gain,
Three Temperatures
FREQUENCY (MHz)
050
OIP3 (dBm)
49
46
43
40 100 150
5554 G13
200
–40°C
85°C
25°C
FREQUENCY (MHz)
0 50 100 150
5554 G14
200
–40°C
85°C
25°C
IMD3 (dBc)
–76
–79
–82
–85
–88
FREQUENCY (MHz)
0 50 100 150
5554 G15
200
IIP3 (dBm)
32
30
28
24
26
–40°C
85°C
25°C
(ROUT = 50) TA = 25°C. VCC = 5V, VCCO = 5V, ENB = 3V, MODE = 5V, STROBE = 3V, VIH = 2.2V, VIL = 0.6V (Test circuit shown in Figure
16) POUT = 4dBm/tone (2VP-P into 50Ω), ∆f = 200kHz, unless otherwise noted.
LT5554
9
5554f
TYPICAL PERFORMANCE CHARACTERISTICS
(ROUT = 50) TA = 25°C. VCC = 5V, VCCO = 5V,
ENB = 3V, MODE = 5V, STROBE = 3V, VIH = 2.2V, VIL = 0.6V (Test circuit shown in Figure 16) POUT = 4dBm/tone (2VP-P into 50Ω),
∆f = 200kHz, unless otherwise noted.
Two-Tone OIP3 vs Frequency for
GMAX and Critical Gain Steps
Two-Tone IMD3 vs Frequency for
GMAX and Critical Gain Steps
IIP3 vs Frequency for GMAX and
GMAX –3.875dB
Two-Tone IMD3 and OIP3 vs
Attenuation at 50MHz
Two-Tone IMD3 and OIP3 vs
Attenuation at 70MHz
FREQUENCY (MHz)
50
OIP3 (dBm)
49
46
43
40 100 150
5554 G16
200
GMAX – 15.875dB
GMAX – 12dB
GMAX – 3.875dB
GMAX
FREQUENCY (MHz)
50
IMD3 (dBc)
–70
–76
–82
–88 100 150
5554 G17
200
GMAX – 15.875dB
GMAX – 12dB
GMAX – 3.875dB
GMAX
FREQUENCY (MHz)
50
IIP3 (dBm)
32
30
28
24
26
100 150
5554 G18
200
GMAX
GMAX – 3.875dB
ATTENUATION (dB)
0 –4 –8 –12
5554 G19
–16
IMD3
OIP3
IMD3 (dBc)
–70
–74
–78
–82
–86
OIP3 (dBm)
48
46
44
42
40
ATTENUATION (dB)
0 –4 –8 –12
5554 G20
–16
IMD3
OIP3
IMD3 (dBc)
–70
–74
–78
–82
–86
OIP3 (dBm)
48
46
44
42
40
Two-Tone IMD3 and OIP3 vs
Attenuation at 100MHz
ATTENUATION (dB)
0 –4 –8 –12
5554 G21
–16
IMD3
IMD3 (dBc)
–70
–74
–78
–82
–86
OIP3 (dBm)
48
46
44
42
40
OIP3
Two-Tone IMD3 and OIP3 vs
Attenuation at 140MHz
ATTENUATION (dB)
0 –4 –8 –12
5554 G22
–16
IMD3
OIP3
IMD3 (dBc)
–70
–74
–78
–82
–86
OIP3 (dBm)
48
46
44
42
40
LT5554
10
5554f
TYPICAL PERFORMANCE CHARACTERISTICS
Two-Tone OIP3 vs Tone Power at
Min-Gain
Two-Tone OIP3 vs ROUT
, for GMAX
OIP3 vs Frequency for GMAX and
GMIN, POUT = 10dBm
(ROUT = 50) TA = 25°C. VCC = 5V, VCCO = 5V,
ENB = 3V, MODE = 5V, STROBE = 3V, VIH = 2.2V, VIL = 0.6V (Test circuit shown in Figure 16) POUT = 4dBm/tone (2VP-P into 50Ω),
∆f = 200kHz, unless otherwise noted.
Two-Tone IMD3 and OIP3 vs
Attenuation at 200MHz
ATTENUATION (dB)
0 –4 –8 –12
5554 G23
–16
IMD3
OIP3
IMD3 (dBc)
–70
–74
–78
–82
–86
OIP3 (dBm)
48
46
44
42
40
Two-Tone OIP3 vs Tone Power at
Max-Gain
OUTPUT TONE POWER (dBm)
03
OIP3 (dBm)
47
44
41
38 69
5554 G24
12
50MHz
70MHz
100MHz
140MHz
200MHz
OUTPUT TONE POWER (dBm)
03
OIP3 (dBm)
47
44
41
38 69
5554 G25
12
50MHz
70MHz
100MHz
140MHz
200MHz
FREQUENCY (MHz)
50
OIP3 (dBm)
50
35
45
40
100 150
5554 G29
200
GMAX
GMIN
Harmonic Distortion vs
Attenuation, 50MHz,
POUT = 10dBm, Figure 17
ATTENUATION (dB)
0 –4 –8 –12
5554 G27
–16
HD3
HD5
HARMONIC DISTORTION (dBc)
–70
–75
–80
–85
–90
–100
–95
–105
Two-Tone OIP3 vs VCCO, for GMAX
OUTPUT COMMON MODE VOLTAGE (V)
2
5554 G28
OIP3 (dBm)
48
45
42
36
39
3456
25MHz
70MHz
140MHz
200MHz
Two-Tone OIP3 vs VCCO, for GMAX
–3.875dB
OUTPUT COMMON MODE VOLTAGE (V)
2
5554 G30
OIP3 (dBm)
48
45
42
36
39
3456
25MHz
70MHz
140MHz
200MHz
ROUT ()
50
5554 G52
OIP3 (dBm)
50
48
44
46
75 100
25MHz
70MHz
140MHz
200MHz
LT5554
11
5554f
TYPICAL PERFORMANCE CHARACTERISTICS
(ROUT = 50) TA = 25°C. VCC = 5V, VCCO = 5V,
ENB = 3V, MODE = 5V, STROBE = 3V, VIH = 2.2V, VIL = 0.6V (Test circuit shown in Figure 16) POUT = 4dBm/tone (2VP-P into 50Ω),
∆f = 200kHz, unless otherwise noted.
Noise Figure vs Attenuation,
140MHz
Input Referred Noise vs
Attenuation, 140MHz
Output Noise Density vs
Attenuation, 140MHz
Noise Figure vs Frequency
Single-Ended Output NF vs
Frequency, Figure 18
HD3 and HD5 vs POUT
for GMAX, Figure 17
HD3 vs Frequency for GMAX and
GMIN, POUT = 10dBm, Figure 17
HD5 vs Frequency for GMAX and
GMIN, POUT = 10dBm, Figure 17
HARMONIC DISTORTION (dBc)
–50
–68
–80
–62
–74
–56
FREQUENCY (MHz)
50 100 150
5554 G31
200
GMAX
GMIN
HARMONIC DISTORTION (dBc)
–70
–88
–100
–82
–94
–76
FREQUENCY (MHz)
50 100 150
5554 G32
200
GMAX
GMIN
OUTPUT POWER (dBm)
7
HARMONIC DISTORTION (dBc)
–40
–60
–75
–80
–70
–65
–55
–50
–45
10 13
5554 G33
16
70MHz
140MHz
HD3 HD3
HD5
HD5
FREQUENCY (MHz)
0
5554 G34
NF (dB)
20
15
10
0
5
200 400 600 800
GMAX
GMAX –3.875
GMAX
GMAX –3.875
FREQUENCY (MHz)
0 200 400 600
5554 G35
800
NF (dB)
20
15
10
0
5
ATTENUATION (dB)
0
NF (dB)
25
20
15
10
5
0
5554 G36
–16–4 –12–8
ATTENUATION (dB)
0
RTI (nV/
√Hz
)
6
4
2
0
5554 G37
–16–4 –12–8
ATTENUATION (dB)
0
VONOISE (nV/
√Hz
)
12
9
6
3
0
5554 G38
–16–4 –12–8
(ROUT = 50) TA = 25°C. VCC = 5V, VCCO = 5V, ENB = 3V, MODE = 5V, STROBE = 3V, VIH = 2.2V, VIL = 0.6V (Test circuit shown in Figure 16),
maximum gain, unless otherwise noted.
LT5554
12
5554f
ATTENUATION (dB)
0
VIN(BIAS) (V)
2.2
2.1
2.0
5554 G42
–16–4 –12–8
–40°C
85°C
25°C
ATTENUATION (dB)
0
CURRENT (mA)
215
208
200
185
193
5554 G40
–16–4 –12–8
–40°C
85°C
25°C
TYPICAL PERFORMANCE CHARACTERISTICS
Single-Ended Output Current vs
Attenuation Total ICC Current vs Attenuation
ICC Shutdown Current vs VCC,
ENB = 0.6V
( ROUT = 50) TA = 25°C. VCC = 5V, VCCO = 5V,
ENB = 3V, MODE = 5V, STROBE = 3V, VIH = 2.2V, VIL = 0.6V (Test circuit shown in Figure 16), maximum gain, unless otherwise noted.
VIN(BIAS) vs Attenuation
ATTENUATION (dB)
0
CURRENT (mA)
98
96
94
92
5554 G39
–16–4 –12–8
–40°C
85°C
25°C
VCC (V)
4.7
CURRENT (mA)
5
4
1
2
3
0
5554 G41
5.54.9 5.35.1
–40°C
85°C
25°C
LT5554
13
5554f
PIN FUNCTIONS
GND (Pins 1, 2, 7, 8, 10, 13, 15, 16, 19, 22, 25, 26, 28,
31): Ground Pins.
DEC (Pins 3, 6): Decoupling Pin for the Internal DC Bias
Voltage for the Differential Inputs, IN+ and IN–. It is also
connected to the ‘virtual ground’ of the input resistive
attenuator. Capacitive de-coupling to ground is recom-
mended in order to preserve linearity performance when
IN+, IN– inputs are driven with up to 3dB imbalance.
IN+ (Pin 4): Positive Signal Input Pin with Internal DC
Bias to 2V.
IN– (Pin 5): Negative Signal Input Pin with Internal DC
Bias to 2V.
PG5 (Pin 9): 4dB Step Amplifi er Programmable Gain Con-
trol Input Pin. Input levels are controlled by MODE pin.
PG6 (Pin 11): 8dB Step Amplifi er Programmable Gain
Control Input Pin. Input levels are controlled by the
MODE pin.
PG0 (Pin 12): 0.125dB Step Amplifi er Programmable
Gain Control Input Pin. Input levels are controlled by
MODE pin.
STROBE (Pin 14): Strobe Pin for the Programmable Gain
Control Inputs (PGx). With STROBE in Low-state, the
Amplifi er Gain is not changed by PGx state changes (latch
mode). With STROBE in High-state, the Amplifi er Gain is
asynchronously set by PGx inputs transitions (transpar-
ent-mode). A positive STROBE transition updates the
PGx state. Low-state and High-state depends on MODE
pin level (Table1).
VCC (Pins 17, 24): Power Supply Pins. These pins are
internally connected together.
MODE (Pin 18): PGx and STROBE Functionality and Level
Control Pin. When MODE is higher than VCC – 0.4V, the
PGx and STROBE are DC-coupled. When the MODE pin
is lower than 0.6V, the PGx and STROBE are AC-coupled.
2dB-Step Response (PG4)
120MHz Signal
8dB-Step Response (PG6)
120MHz Signal
8dB-Step Response (PG6)
120MHz Pulse Signal
TYPICAL PERFORMANCE CHARACTERISTICS
(ROUT = 50) TA = 25°C. VCC = 5V, VCCO = 5V,
ENB = 3V, MODE = 5V, STROBE = 3V, VIH = 2.2V, VIL = 0.6V (Test circuit shown in Figure 16), maximum gain, unless otherwise noted.
8dB-Step (PG6) 120MHz Pulse
Signal for 8dB Overdrive
8dB-Step (PG6) 120MHz
Sinusoidal Signal for 2dB
Overdrive
8dB-Step (PG6) 120MHz
Sinusoidal Signal for 8dB
Overdrive
MODE = HIGH
1V/DIV
5554 G49
5ns/DIV
MODE = HIGH
1V/DIV
5554 G50
5ns/DIV
MODE = HIGH
1V/DIV
5554 G51
10ns/DIV
MODE = HIGH
0.1V/DIV
5554 G46
10ns/DIV
MODE = HIGH
0.1V/DIV
5554 G47
10ns/DIV
MODE = HIGH
0.2V/DIV
5554 G48
5ns/DIV
LT5554
14
5554f
PIN FUNCTIONS
When the MODE pin is left open, the PGx inputs are AC-
couple and the STROBE input is DC-coupled.
In DC-coupled mode, the PGx and STROBE inputs levels are
0.6V and 2.2V. In AC-coupled mode, the PGx and STROBE
inputs are driven with 0.6VP-P minimum amplitude (with
rise and fall time <5ns) regardless the DC voltage level. A
positive transition sets a High-state. A negative transition
sets a Low-state (for PGx and STROBE inputs).
OUT+ (Pin 20): Positive Amplifi er Output Pin. A transformer
with a center tap tied to VCC or a choke inductor is recom-
mended to conduct the DC quiescent current.
OUT– (Pin 21): Negative Amplifi er Output Pin. A transformer
with a center tap tied to VCC or a choke inductor is recom-
mended to conduct the DC quiescent current.
ENB (Pin 23): Enable Pin for Amplifi er. When the ENB
input voltage is higher than 3V, the amplifi er is turned on.
When the ENB input voltage is less than or equal to 0.6V,
the amplifi er is turned off.
PG4 (Pin 27): 2dB Step Amplifi er Programmable Gain Con-
trol Input Pin. Input levels are controlled by MODE pin.
PG3 (Pin 29): 1dB Step Amplifi er Programmable Gain Con-
trol Input Pin. Input levels are controlled by MODE pin.
PG2 (Pin 30): 0.5dB Step Amplifi er Programmable Gain Con-
trol Input Pin. Input levels are controlled by MODE pin.
PG1 (Pin 32): 0.25dB Step Amplifi er Programmable
Gain Control Input Pin. Input levels are controlled by
MODE pin.
EXPOSED PAD (Pin 33): Ground. This pin must be sol-
dered to the printed circuit board ground plane for good
heat dissipation.
BLOCK DIAGRAM
Figure 1. Functional Block Diagram
VOLTAGE
REGULATOR
AND BIAS
AMPLIFIER
DEC
GND
(15 PINS)
RO
400
5554 BD
ENABLE
CONTROL
IN+OUT–
OUT+
IN–
DEC
VCC VCC ENB
MODE
STROBE
LOGIC
TRANSCONDUCTANCE
GAIN LOGIC
0.125dB STEPS
3.875dB RANGE
ATTENUATOR
GAIN LOGIC
4dB STEPS
12dB RANGE
PG4 PG3PG6 PG5 MODE STROBE PG2 PG1 PG0
ATTENUATOR RIN+
25
RIN–
25
23
21
32302927
14
18911
6
5
4
3
12
20
2417
LT5554
15
5554f
FUNCTIONAL CHARACTERISTICS
Programmable Gain Table
STATE PG0 PG1 PG2 PG3 PG4 PG5 PG6
ATTENUATION
Step Relative to Max Gain GAIN STATE NAME
N Step Size in dB dB
0.125 0.25 0.5 1 2 4 8 (N – 127) • 0.125dB
127HHHHHHH 0.00dB GMAX (Max Gain)
126LHHHHHH –0.125dB GMAX –0.125dB
125HLHHHHH –0.250dB GMAX –0.25dB
124LLHHHHH –0.375dB GMAX –0.375dB
123 H H L H H H H –0.500dB GMAX –0.5dB
122 L H L H H H H –0.625dB GMAX –0.625dB
121 H L L H H H H –0.750dB GMAX –0.75dB
120 L L L H H H H –0.875dB
119 H H H L H H H –1.00dB GMAX –1dB
118 L H H L H H H –1.125dB GMAX –1.125dB
…
112 L L L L H H H –1.875dB GMAX –1.875dB
111 H H H H L H H –2.00dB GMAX –2dB
…
104 L L L H L H H –2.875dB GMAX –2.875dB
103 H H H L L H H –3.00dB GMAX –3dB
…
96 L L L L L H H –3.875dB GMAX –3.875dB
95 H H H H H L H –4.00dB GMAX –4dB
…
64 L L L L L L H –7.875dB GMAX –7.875dB
63 HHHHHHL –8.00dB GMAX –8dB
…
32 L L L L L H L –11.875dB GMAX –11.875dB
31 HHHHHLL –12.000dB GMAX –12dB
…
8 L L L H L L L –14.875dB GMAX –14.875dB
7 HHHLLLL –15.000dB GMAX –15dB
6 LHHLLLL –15.125dB GMAX –15.125dB
5 HLHLLLL –15.250dB GMAX –15.25dB
4 LLHLLLL –15.375dB GMAX –15.375dB
3 HHLLLLL –15.500dB GMAX –15.5dB
2 L H L L L L L –15.625dB GMAX –15.625dB
1 H L L L L L L –15.750dB GMAX –15.75dB
0 LLLLLLL –15.875dB GMIN (Min Gain)
LT5554
16
5554f
DEFINITION OF SPECIFICATIONS
Amplifi er Impedance and Gain Defi nitions
(Differential)
RS Input source resistor. Input matching is assumed:
R
S = RIN
RIN LT5554 input resistance (internal, 50)
CIN LT5554 input capacitance (internal)
RO LT5554 output resistance (internal, 400)
CO LT5554 output capacitance (internal)
RLOAD Load resistance as seen by LT5554
output pins
CLOAD Load capacitance as seen by LT5554
output pins
ROUT Total output resistance at LT5554 open-collec-
tors outputs (used in GV, GP gain calculation):
R
OUT = RO || RLOAD
COUT Total output capacitance at LT5554 output
(used in gain calculation):
C
OUT = CLOAD + CO
GM LT5554 differential transconductance:
G=
I
V
MOUT
IN
GV LT5554 differential voltage gain:
GV
VGR
VOUT
IN M OUT
=⎛
⎝
⎜⎞
⎠
⎟=
()
20 20log log • in dB
GP LT5554 differential power gain:
G
P = 10log(RIN • GM2 • ROUT) in dB
PIN Power available at LT5554 input, RS = RIN =
50 input matching:
P
V
RmW
IN
IN
IN
=
⎛
⎝
⎜⎞
⎠
⎟
()
⎛
⎝
⎜
⎜
⎜
⎜
⎜
⎞
⎠
⎟
⎟
⎟
⎟
⎟
10 2
1
2
log •in dBm
V is peak value
IN
,
-
POUT Total power delivered by LT5554 open-collec-
tor outputs:
P
V
RmW
OUT
OUT
OUT
=
⎛
⎝
⎜⎞
⎠
⎟
()
⎛
⎝
⎜
⎜
⎜
⎜
⎜
⎞
⎠
⎟
⎟
10 2
1
2
log •⎟⎟
⎟
⎟
OUT
in dBm
V is peak value
,
-
Figure 2. Output Equivalent Circuit and Impedance Defi nitions
INTERNAL EXTERNAL
5554 F02
OUT+
OUT–
CLOAD
CO
1.9pF
IDC
RO
400
RO
400
IOUT = GM • VIN
ROUT
RLOAD
ROUT
RLOAD
VOUT = IOUT • ROUT
LT5554
17
5554f
Circuit Operation
The LT5554 is a high dynamic range programmable-gain
amplifi er. It consists of the following sections:
• An input variable attenuator with 50Ω input imped-
ance (four 4dB steps, controlled by PG5, PG6 inputs)
• A differential programmable transconductance ampli-
fi er (32 steps, 0.125dB each controlled by PG0, PG1,
PG2, PG3, PG4 inputs)
• Programmable logic blocks
• Internal bias (voltage regulators)
• Enable/disable circuit
• Overdrive protection circuit
Noise Defi nitions for 50 Matched Input
eRS Source resistor RMS noise voltage:
ekTRforR
enV
Hz
RS S S
RS
2450
09
==
=
••• ; ,
.
Ω
eN Equivalent short-circuit input RMS noise voltage
source
iN Equivalent open-circuit input RMS noise current
source
vN Equivalent total input RMS noise voltage
source:
v
N2 = eN2 + iN2 • RS2 (RS = 50)
RTI Referred-to-input LT5554 noise voltage:
RTI = (e +e +i •R ) =v
2
RS2N2N2S2
N
2
VONOISE LT5554 output noise voltage:
V=RTI+
e
2•10
ONOISE 2RS
2GV
⎛
⎝
⎜⎞
⎠
⎟
⎛
⎝
⎜
⎜
⎞
⎠
⎟
⎟
220
⎛
⎝
⎜⎞
⎠
⎟
NF Noise fi gure in dB according to any of the fol-
lowing equations:
NF
eiR
e
NN S
RS
=+
+
()
⎛
⎝
⎜
⎜
⎞
⎠
⎟
⎟=
+
10 1
10 1
22 2
2
log
•
log VV
e
RTI
e
N
RS RS
2
2
2
2
10 1
2
⎛
⎝
⎜⎞
⎠
⎟=+
⎛
⎝
⎜⎞
⎠
⎟
⎛
⎝
⎜
⎜
⎜
⎜
log
⎞⎞
⎠
⎟
⎟
⎟
⎟
Linearity Defi nitions for 50 Matched Input
IMD3[dBc] Third-order intermodulation product
(negative value)
IIP3[dBm]
IIP3 = P (per-tone) – IMD3
2
IN
SFDR[dBm/Hz]
SFDR = 2
3• 174+IIP3–NF
⎛
⎝
⎜⎞
⎠
⎟
()
OIP3[dBm]
OIP P IMD IIP G
OUT P
33
23==+–
APPLICATIONS INFORMATION
DEFINITION OF SPECIFICATIONS
Since no internal feedback network is used between ampli-
fi er outputs and inputs, the LT5554 is able to offer:
• Unconditional stability for I/O reactive loading such
as fi lters (no isolation output resistors required)
• High reverse isolation
The LT5554 is a class-A transconductance amplifi er. An
input signal voltage is fi rst converted to an output cur-
rent via the LT5554 internal GM. And then, the output load
(ROUT) converts the output current into an output voltage.
ROUT sets the LT5554 gain and output noise fl oor. However,
the SFDR performance is almost independent of ROUT for
values of 25Ω to 100Ω.
LT5554
18
5554f
APPLICATIONS INFORMATION
The PGx gain control inputs and STROBE input can be
confi gured to be either DC coupled or AC coupled depend-
ing on MODE pin level. The LT5554 gain control inputs
can be connected without external components to a wide
range of user control interfaces.
The LT5554 has internal overdrive protection circuitry.
The recovery time from a short duration (less than 5ns)
overdrive pulse is 5ns.
Input Interface
The DC voltage level at the IN+, IN– inputs are internally
biased to about 2V when the part is either enabled or
disabled. The best linearity performance is achieved when
an input imbalance is less than 2dB.
Two typical Input connection circuits are shown in Figures
3 and 4.
An input source with 50Ω (5%) is required for best gain
error performance.
This buffer is also connected to the input resistive attenua-
tor network. The DEC pin is a ‘virtual ground’ and typically
connected to an external capacitor CDEC (Figures 3 and
4). When CDEC is used, the LT5554 will have same input
attenuation for both differential mode and common mode
signals. The DEC pin de-coupling capacitor improves the
common mode AC performance even when the differential
IN+, IN– inputs are imbalanced by 3dB.
The DEC pin can be used as a voltage reference for external
circuitry when DC input coupling is desired.
Output Interface
The output interface must conduct the DC current of about
45mA to the amplifi er outputs (OUT+ OUT–). Two interface
examples are shown in Figures 5 and 6.
A wide band ADC voltage interface is shown in Figure
5 where L1 and L2 are choke inductors. For a narrow
band application, a band pass fi lter can be placed at the
LT5554’s outputs.
Figure 3. Input Capacitively-Coupled to a Differential Source
Figure 4. Input Transformer-Coupled to Single-Ended Source
Figure 5. Differential Output Interface
Figure 6. Single-Ended Matched Output Interface
LT5554
VSRC
RSRC
50
5554 F04
DEC
IN+
IN–OUT+
OUT–
25
25
CDEC
0.1µF
••
LT5554
5554 F03
DEC
IN+
IN–OUT+
OUT–
C1
25
C2 25
CDEC
0.1µF
VSRC
RSRC/2
25
RSRC/2
25
••
•
LT5554
5554 F06
DEC
IN+
IN–OUT+
OUT–
ZO
50
C5
R6
205
R5
205
RO
400
RO
400
ROUT
100
RLOAD
133
VCCO
5V
MAX GAIN:
GV = 24dB
GP = 21dB MAX GAIN INTO ZO:
GP = 18dB
T2
4:1
Decouple (DEC) Input
The DEC pin provides the DC voltage level for differential
inputs IN+, IN– via an internal buffer, which is able to fast
charge/discharge the LT5554 input coupling capacitors
with about 30mA sourcing or sinking current capability.
LT5554
CHOKE
INDUCTORS
5554 F05
DEC
IN+
IN–OUT+
OUT–
C5
C6
C4
C3
RO
400
RO
400
RSADC
100
ROUT
100
RLOAD
133
VCCO
5V
L1 L2
MAX GAIN:
GV = 24dB
GP = 18dB
ADC
BIAS
R1
66.5
R2
66.5
ADC
LT5554
19
5554f
APPLICATIONS INFORMATION
The differential outputs can also be converted to single-
ended 50Ω load using a center-tap transformer interface
shown in Figure 6 and Figure 16.
The internal 400Ω differential resistor (RO) sets the output
impedance and the maximum voltage gain (GMAX) to 36dB
when outputs OUT+, OUT– are open.
Figure 7 shows the Voltage and Power Gains as a func-
tion of ROUT
, which is the total output loading at the open
collector amplifi er output including the internal resistor
RO = 400Ω.
Voltage clipping will occur with ROUT >140Ω, in which case
the instantaneous voltage at each OUT+ and OUT– outputs
is either <2V or >8V.
The output OP1dB = 20dBm can be achieved when ROUT =
130Ω. In this case, the LT5554 outputs reach both current
and voltage limiting for maximum output power.
Gain Control Interface
The MODE pin selects the interface to the LT5554 gain
control pins.
The PGx and STROBE control inputs can be confi gured
to be either DC-coupled (for TTL interface) or AC-coupled
(for ECL or low-voltage CMOS interfaces).
In addition, the STROBE input can be driven such that the
LT5554 gain state is updated asynchronously (PGx latch
control in transparent-mode) or controlled by positive
STROBE transition (PGx latch control in strobed-mode).
There are several options available for coupling type and
latch control which are given in the following tables:
Table1. MODE Input Options
MODE
(State)
COUPLING TYPE
PGx (Latch Control)STROBE PGx
LOW AC Positive
Transition AC Strobe
OPEN DC >2.2V AC Transparent
OPEN 0.6 to 2.2V AC Strobe
HIGH DC >2.2V DC Transparent
HIGH 0.6 to 2.2V DC Strobe
Table2. MODE Input Levels
MODE
(State)
MODE
(Min Level)
MODE
(Max Level)
LOW 0 0.6V
OPEN 1.5V 2.5V
HIGH VCC – 0.4V VCC
Alternatively, the MODE pin can be left open (2V
internal).
Figure 7. Maximum Voltage and Power Gain vs ROUT
The gain vs ROUT relationship is given by the following
equations:
G
V = 20log(GM • ROUT) in dB
G
P = 10log(RIN • GM2 • ROUT) in dB
Where RIN = 50 and GM = 0.15 siemens at GMAX
For wide band applications, the amplifi er bandwidth can
be extended by inductive peaking technique. The inductor
in series with the LT5554 outputs (OUT+ OUT–) can have
a value up to some tens of nH depending on ROUT value
and board capacitance.
The current limiting will occur with ROUT <140Ω, in which
case the instantaneous signal current at the output exceeds
IODC = 45mA.
ROUT ()
10
MAXIMUM GAIN (dB)
36
30
24
18
12
6
0100 40050
5554 F07
1000
VOLTAGE GAIN
POWER GAIN
LT5554
20
5554f
All seven PGx gain control inputs and STROBE input can
be confi gured as DC-coupled or ac-coupled. Accordingly,
there are two basic equivalent schematics (shown in Figures
8 and 9) depending on MODE input choice (Table1).
Each PGx input circuit shown in Figures 8 and 9 is fol-
lowed by a transparent latch controlled by the STROBE
input level (Table 1).
The DC-coupled interface is shown in Figure 8. DC levels for
PGx inputs and STROBE input are VIL <0.6V, VIH >2.2V.
The AC-coupled interface is shown in Figure 9. The PGx
inputs and STROBE input state is decided by a signal
transition rather than signal level.
A HIGH-state is set by positive transitions. A LOW-state is
set by negative transitions. The PGx and STROBE inputs
appear as capacitive coupled inputs. The DC voltage (0V
to VCC range) presented on any PGx or STROBE input is
shifted to the internal 1.4V level by the additional circuit
shown in Figure 9. Each PGx and STROBE input has an
independent shift circuit such that each input can have a
different DC voltage.
Each PGx input has a parallel R-C (R1 = 20k, C1 = 2pF)
with a 40ns time constant. The STROBE input circuit has
R1 = 20k C1 = 3pF and 60ns time constant. An minimum
amplitude of 0.6VP-P is required to trip the PGx and STROBE
inputs to an appropriate state when the signal period is
less than input time constant. The circuit shown in Figure 8
converts the single-ended external signal to an internal
differential signal. Consequently, when the input is idle for
more than the input time constant, a 0.3VP-P transition
will still trigger the gain control state change. All control
inputs have 200mV hysteresis to insure stable logic levels
when the input noise level is less than 100mVP-P.
For transparent latch control, the amplifi er gain will be
updated directly with any PGx input state changes. If
different PGx inputs have an (external) time skew greater
than 1ns, then a noticeable amplifi er output glitch can
occur. The strobe latch control is recommended to avoid
this amplifi er output glitch.
It is not necessary to double buffer the PGx inputs since
the LT5554 has good internal isolation from the PGx inputs
to the amplifi er output to any type of external gain control
circuit without external components.
If LT5554 is powered up or enabled in latch mode, the
LT5554 gain initial gain is indeterminate. If the minimum
gain state is desired at power up, it is recommended to
set the transparent-mode with all PGx inputs low.
Figure 8. DC-Coupled PGx and STROBE Equivalent Inputs
(Simplifi ed Schematic)
Figure 9. AC-Coupled PGx and STROBE Equivalent Inputs
(Simplifi ed Schematic)
APPLICATIONS INFORMATION
5554 F08
OUT+
OUT–
INPUT
VCC
IDC
I1
200µA
V1
1.4V
R3
1.5k
R2
1.5k
Q1
Q3
Q2
R4
20k
R1
20k
C1
2pF
DC-COUPLED
5554 F09
OUT+
OUT–
INPUT
VCC
IDC
I1
200µA
V1
1.4V
IDC
AC-COUPLED
I2
IDCI3
R3
1.5k
R2
1.5k
Q1
Q3
Q2
R4
20k
R1
20k
C1
2pF
LT5554
21
5554f
Gain Step Accuracy
LT5554 internal input signal coupling to the transcon-
ductance amplifi er inputs across the 4dB step attenuator
increases with frequency. The gain step error is higher
when the LT5554 gain update changes the input attenua-
tor tap (PG5, PG6 transitions) and this error is frequency
dependent.
Gain error is ‘compressive’, effectively reducing LT5554
gain range. Therefore, it is possible to skip one gain
APPLICATIONS INFORMATION
code whenever PG5, PG6 transitions are involved in or-
der to preserve high-frequency monotonic behavior for
0.125dB steps.
Linearity and Noise Performance Throughout the
Gain Range
The LT5554’s Noise and Linearity performance across
the 16dB gain range at 100MHz with ROUT = 100 and
RSADC = 50 is shown in Figures 10 through 13.
ATTENUATION (dB)
0
RTI AND VONOISE (nV/
√Hz
)
12
6
9
3
0
NF (dB)
24
18
12
6
0
–4 –8 –12
5554 F10
–16
RTI
NF
VONOISE
Figure 10. Noise, 140MHz, ROUT = 50
ATTENUATION (dB)
0 –4 –8 –12
5554 F12
–16
IMD3
IMD3 (dBc)
–70
–74
–78
–82
–86
OIP3 (dBm)
48
46
44
42
40
OIP3
Figure 12. Linearity, 70MHz, ROUT = 50, 4dBm/Tone
ATTENUATION (dB)
0 –4 –8 –12
5554 F11
–16
IIP3 (dBc)
44
34
39
29
24
SFDR (dBm/Hz)
136
132
128
124
120
SFDR
IIP3
Figure 11. Noise, 140MHz, ROUT = 50
ATTENUATION (dB)
0 –4 –8 –12
5554 F12
–16
IMD3
IMD3 (dBc)
–70
–74
–78
–82
–86
OIP3 (dBm)
48
46
44
42
40
OIP3
Figure 13. Linearity, 140MHz, ROUT = 50, 4dBm/Tone
LT5554
22
5554f
APPLICATIONS INFORMATION
The LT5554 Noise and Linearity performance throughout
the 16dB gain range has an obvious discontinuity at every
4dB gain step. The noise fi gure is fairly constant from 0dB
(Maximum Gain) to –3.875dB attenuation when the gain is
decreased by lowering the amplifi er transconductance. And
then, the NF increases by 4dB when the input attenuator
is switched to –4dB attenuation while the amplifi er gain
is switched back to maximum transconductance. This
pattern repeats for each 4dB gain step change.
SECOND ORDER HARMONIC DISTORTION
Balanced differential inputs and outputs are important
for achieving excellent second order harmonic distortion
(HD2) of the LT5554. When confi gured in single-ended
input and output interfaces, therefore, the single-ended
to differential conversion at the input and differential to
single-ended conversion at the output will have signifi cant
impact on the HD2 performance.
Figure 14, for example, shows the desirable singe-ended
input and output confi guration using external transformers
for the single-ended to differential conversion and differ-
ential to single-ended conversion. To assure a good HD2
performance, R5 and R6 should also be matched to better
than 1% or use these two resistors with 1% component
tolerance. In this case, the HD2 can be as good as -80dBc
when the output power is 10dBm at 140MHz.
When the single-ended input is not converted into well
balanced inputs to LT5554, the HD2 performance will
be degraded. For instance, when the T1 transformer is
improperly rotated by 90 degrees as shown in Figure 15,
the imbalance of the differential input signals will result in
14dB degradation in HD2. It is also important to split the
differential R7 resistor into two single-ended R5 and R6
resistors at the outputs to reduce the imbalance of the T2
transformer. If not, 3dB degradation in HD2 performance
can also be observed.
The HD2 performance can be further improved by mounting
a capacitor from IN+ to ground (a few pF) and a capaci-
tor from OUT– to ground. For narrow band applications,
these capacitors cancels to some degree the T1 and T2
imbalance as shown in Figure 15.
For optimum HD2 performance, fully differential input and
output interfaces to the LT5554 part are recommended.
Figure 15. Not Recommended Single-Ended Input and Output
Confi guration, HD2 = –63dBc at 10dBm, 140MHz
Figure 14. Recommended Single-Ended Input and Output
Confi guration, HD2 = –80dBc at 10dBm, 140MHz
••
IN+
IN–
T1
1:1
ETC1-1-13
C5
1µF
••
•
LT5554
5554 F14
OUT+
OUT–
R5
68.1
R6
68.1
RO
400
VCCO = 5V
VCC = 5V
T2
TC2-1T
C3
0.1µF
C4
0.1µF
DEC
50
IN+
IN–
T1
1:1
ETC1-1-13
C5
1µF
••
•
LT5554
5554 F15
OUT+
OUT–
R7
134
RO
400
DEC
50
VCCO = 5V
VCC = 5V
T2
TC2-1T
C3
0.1µF
C4
0.1µF
C1
47nF
C2
47nF
••
LT5554
23
5554f
Figure 16. Single-Ended Transformer Test Board (Simplifi ed Schematic)
••
IN+
IN–
T1
1:1
ETC1-1-13
MACOM
J1
50 J3
50
C5
1µF
••
•
LT5554
1, 3, 5, 7 9
5554 F16
OUT+
OUT–
C9
0.1µF
C3
0.1µF
R6
68.1
R5
68.1
RO
400
RIN
50
RO
400
VCC = 5V
VCCO = 5V
RLOAD
57.1
OUTPUT
MATCHING
T2
TC2-1T
2:1
C18
0.1µF
C19
4.7µF
C8
0.1µF
C4
0.1µF
11
VCC VDEC ENB
13
PG0
PG0
15
PG1
17
PG2
19
PG3
21
PG4
23
PG5
25
PG6
27
STROBE
29
VPG
31
MODE
33, 35, 37, 38 2, 4, ...40
J5, 40 PINS
SMT-TB
VCCO
R20
10k
PG1
R21
10k
PG2
R22
10k
PG3
R23
10k
PG4
R24
10k
PG5
R25
10k
PG6
R26
10k
ROUT = 50
APPLICATIONS INFORMATION
Layout Considerations
Attention must be paid to the printed circuit board layout
to avoid output pin to input pin signal coupling (external
feedback). The evaluation board layout is a good example.
The exposed backside pad on the LT5554 package must be
soldered to PCB ground plane for thermal considerations.
Characterization Test Circuits
The LT5554’s typical performance data are on the test
circuits shown in Figures 16, 17 and 18 which are simpli-
fi ed schematics of the evaluation board schematic from
Figure 21.
The transformer board from Figure 16 was used for char-
acterization as a function of ROUT
. For each ROUT option,
The T2 transformer model and the matching resistors R5,
R6 values are given in Table 3. The T2 transformer total
matching resistance is RMATCH = RO || (R5 + R6) (part
LT5554 internal, and part on board R5 and R6).
Table 3. Transformer Board ROUT Options
ROUT (Ω) 50 75 100
T2 (Mini-Circuits) TC2-1T TC3-1T TC4-1W
NLOAD Ratio 234
RLOAD (Ω) 57.1 92.3 133.3
R5, R6 (Ω) 68.1 124 205
GP_BOARD (dB) 13.2 16 17.2
IL(T2) at
200MHz (dB) –0.6 –0.65 –1
LT5554
24
5554f
APPLICATIONS INFORMATION
Figure 17. Single Ended Test Board (Simplifi ed Schematic)
The LT5554 output power POUT was obtained by adding
3dB for matching-loss and the transformer loss IL(T2) in
Table 3 to the board output power at J3 connector. The
transformer insertion loss (frequency and temperature
dependent) has been included in characterization.
The output power matching is required when LT5554
drives a 50 transmission line as shown on the evalua-
tion board.
When LT5554 drives local (on-board) loads such that
an ADC part, output power matching is not required and
OIP3 is defi ned based on POUT, total power at LT5554
open collector outputs.
Figure 17 shows the evaluation board for wide-band
characterization at ROUT = 50, where the insertion loss
of the output balun is about –1dB at 1GHz. Several ROUT
options are given in Table 4 as well as the output padding
insertion-loss and required VCCO for 5V on LT5554 outputs.
The LT5554 output power at open collector outputs is:
P
OUT = PWR(J3) + IL(T2) + 3dB + ILPAD
Table 4. Balun Board ROUT Options
ROUT () 25 36 50 71 100
R3, R4 () 0 6.49 15.4 30.1 53.6
R5, R6 () 28.7 28.7 28 28 28
ILPAD 0 1.88 3.66 5.76 8.08
VCCO (V) 6.29 6.57 6.96 7.61 8.66
The differential-output board from Figure 18 was used
for ROUT = 50 wide-band characterization of the LT5554
single-ended outputs.
Both Figure 17 and Figure 18 boards VCCO was shifted
up with the voltage drop on R5, R6 produced by 45mA
output DC current such that OUT+, OUT– DC bias voltage
is still 5V. The LT5554 part should be always enabled when
VCCO >6V. If disabled, the VCCO will be applied at OUT+,
OUT– exceeding the absolute maximum 6V limit with
possible LT5554 failure.
••
T2
1:1
ETC1-1-13
IN+
IN–
J1
50
J3
50
C5
1µF
LT5554
1, 3, 5, 7 9
5554 F17
OUT+
OUT–
C9
0.1µF
C3
0.1µF
R6
28
RO
400
RIN
50
RO
400
RLOAD
57.1
50
MATCHING
C18
0.1µF
C19
4.7µF
C8
0.1µF
C4
0.1µF
11
VCC VDEC ENB
13
PG0
PG0
15
PG1
17
PG2
19
PG3
21
PG4
23
PG5
25
PG6
27
STROBE
29
VPG
31
MODE
33, 35, 37, 38 2, 4, ...40
J5, 40 PINS
SMT-TB
VCCO
R20
10k
PG1
R21
10k
PG2
R22
10k
PG3
R23
10k
PG4
R24
10k
PG5
R25
10k
PG6
R26
10k
ROUT = 50
R5
28
R3
15.4
R4
15.4
VCC = 5V
VCCO = 7V
••
T1
1:1
ETC1-1-13
MACOM
LT5554
25
5554f
APPLICATIONS INFORMATION
Figure 18. Wideband Differential Output Test Board (Simplifi ed Schematic)
Common mode characterization for the LT5554 was per-
formed with input circuit shown in Figure 19.
Figure 19. Common Mode Input Interface
source is applied at J6 connector and 50Ω terminated by
R16 and R33 resistors. C66 decouple R33 to ground while
C16 provides DC-decoupling between referenced to ground
pulse source and the PG6 DC-voltage. A supply connected
to PG6 turret will set the PG6 DC-voltage in 0V to 5V range.
All other (untested) PGx DC-voltage can be independently
be applied at VPG turret decoupled by C88.
Strobe-mode operation is tested with a pulse source ap-
plied at J7 connector as shown in Figure 20.
Applying similar modifi cations around J2 and J4 connec-
tors shown in Figure 21, other PGx inputs can be evaluated.
As described in Table 1 and Table 2, the MODE pin will
select the desired state.
J3
50
J33
50
IN+
IN–
J1
50
C5
1µF
LT5554
1, 3, 5, 7 9
5554 F18
OUT+
OUT–
C9
0.1µF
C3
0.1µF
R6
66.5
RO
400
RIN
50
RO
400
RLOAD
57
100
MATCHING
C18
0.1µF
C19
4.7µF
C8
0.1µF
C4
0.1µF
11
VCC VDEC ENB
13
PG0
PG0
15
PG1
17
PG2
19
PG3
21
PG4
23
PG5
25
PG6
27
STROBE
29
VPG
31
MODE
33, 35, 37, 38 2, 4, ...40
J5, 40 PINS
SMT-TB
VCCO
R20
10k
PG1
R21
10k
PG2
R22
10k
PG3
R23
10k
PG4
R24
10k
PG5
R25
10k
PG6
R26
10k
ROUT = 50
R5
66.5 C10
47nF
C12
47nF
VCC = 5V
VCCO = 8V
ENB = 5V
••
T1
1:1
ETC1-1-13
MACOM
CDEC
47nF
LT5554
DEC
IN+
IN–+
–
OUT+
OUT–
25
25
25
C1
47nF
J1
50
5554 F19
Timing characterization and AC-coupled gain control inputs
are tested on evaluation board. The required circuit modi-
fi cations are shown in the Figure 20 simplifi ed schematic
and detailed below for PG6 (8dB step). The PG6 pulse
LT5554
26
5554f
Figure 20. Timing Test for PG6 and STROBE (Simplifi ed Schematic)
J6 J7
VDEC
32
PG1
31
GND
30
PG2
29
PG3
PG1
PG2 PG3
28
GND
27
PG4
PG4
26
GND
25
GND
9
PG5
PG5
10
GND
11
PG6
12
PG0
PG6 PG0
13
GND
14
STROBE
STROBE
15
GND
16
GND
1GND
2GND
3DEC
4IN+
5IN–
6DEC
7GND
8GND
24
VCC VCC
23
ENB ENABLE
22
GND
21
OUT–
20
OUT+
19
GND
18
MODE MODE
17
VCC
LT5554
C6
47nF
C8
0.1µF
C5
1µF
C17
47nF
C28
47nF
R17
100
R33
100
R34
100
R27
0
R22
10k
R23
10k
R29
0
R30
0
R32
0
R26
10k
R20
10k
R25
10k
C16
47nF
R16
100
R21
10k
R24
10k
R28
0
R31
0
R8
0
5554 F20
C4
0.1µF
C27
47nF
C88
47nF
VPG
APPLICATIONS INFORMATION
Evaluation Board
Figure 21 shows the schematic of the LT5554 evaluation
board. Transformer T2 is TC2-1T and resistor R5 + R6 =
134 (ROUT = 50 GP(J3) = 13.2dB). The silkscreen and
layout are shown in Figures 22 through Figure 27. The
board control J5 edge connector (40PINS SMT-TB) allows
easy access to LT5554 component pins. Alternatively or
combined with J5, 14 test points (turrets) for signals and
two for GND are also available. The board is powered with
a single supply in 4.75V to 5.25V at VCC and VCCO (either
J5 connector or turrets). Connecting the ENABLE pin to
VCC supply enables the LT5554 part. PGx gain control
and STROBE inputs will have TTL levels (DC-coupled)
when MODE = 5V (same power supply). To set LT5554 for
maximum gain (GMAX) in transparent-mode, all seven PGx
and STROBE can be connected to 5V supply. Alternatively,
a 2.2V power supply at VPG pin and STROBE turret will
set same GMAX state.
J1 (input) and J3 (output) are the default board signal
ports for evaluation with 50Ω single ended test system. For
differential evaluation, the board J11 and J33 connectors
must be reconfi gured.
LT5554
27
5554f
J6
J7
J1
5554 F21
VDEC
PG0
VPG
11913 15 17 19 21 23 25 27 29 31
VDEC ENB PG0 PG1 PG2
31 5 7
VCC VCC VCC VCC
3533 37 39
1210 14 16 18 20 22 24 26 28 30 3242 6 8 3634 38 40
VCCO VCCO VCCO VCCO
PG3 PG4 PG5 PG6 STROBE VPG MODE
VDEC ENB PG0 PG1 PG2
VCC VCCO
PG3 PG4 PG5 PG6 STROBE VPG MODE
J5, 40 PINS
SMT-TB
R20
10k
PG1
R21
10k
PG2
R22
10k
PG3
R23
10k
PG4
R24
10k
PG5
R25
10k
PG6
R26
10k
C27
0.1µF
C21
0.1µF
C22
0.1µF
C23
0.1µF
C24
0.1µF
C25
0.1µF
C26
0.1µF
••
•
T2
TC2-1T
2:1
32
PG1
31
GND
30
PG2
29
PG3
PG1
PG2 PG3
28
GND
27
PG4
PG4
26
GND
25
GND
9
PG5
PG5
10
GND
11
PG6
12
PG0
PG6 PG0
13
GND
14
STROBE
STROBE
15
GND
16
GND
1GND
2GND
3DEC
4IN+
5IN–
6DEC
7GND
8GND
24
VCC VCC
VCCO
23
ENB ENABLE
22
GND
21
OUT–
20
OUT+
19
GND
18
MODE MODE MINI-
CIRCUITS
17
VCC
LT5554
NOT
MOUNTED
J3
J33
C3
0.1µF
C18
0.1µF
C19
4.7µF
R7
NC
R3
0
R4
0
R2
0
OUT–
IN+
OUT+
R6
681
R5
68.1
C6
47nF
C8
0.1µF
NOT
MOUNTED
NOT MOUNTED
NOT MOUNTED
NOT MOUNTED
NOT MOUNTED
J11 IN–
C5
1µF
C17
47nF
R17
R33
0
R34
0
R27
0
R1
0
R29
0
R30
0
R32
0
NOT MOUNTED
NOT MOUNTED
C16
47nF
NOT MOUNTED
C15
47nF
R16
J2
NOT MOUNTED R28
0
NOT MOUNTED
NOT MOUNTED
C12
47nF
NOT MOUNTED NOT MOUNTED
C11
47nF
R12
J4
NOT MOUNTED
NOT MOUNTED C21 THROUGH C27 ARE NOT MOUNTED
NOT MOUNTED
C13
47nF
C14
47nF
R14
R31
0
R8
0 C4
••
T1
1:1
ETC1-1-13
MACOM
C9
0.1µF
APPLICATIONS INFORMATION
Figure 21. Evaluation Circuit Schematic
LT5554
28
5554f
APPLICATIONS INFORMATION
Figure 22. Top Side
Figure 23. Inner Layer 2 GND
LT5554
29
5554f
APPLICATIONS INFORMATION
Figure 24. Inner Layer 3 Power
Figure 25. Bottom Side
LT5554
30
5554f
APPLICATIONS INFORMATION
Figure 27. Silkscreen Bottom
Figure 26. Silkscreen Top
LT5554
31
5554f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
PACKAGE DESCRIPTION
UH Package
32-Lead Plastic QFN (5mm × 5mm)
(Reference LTC DWG # 05-08-1693 Rev D)
5.00 ± 0.10
(4 SIDES)
NOTE:
1. DRAWING PROPOSED TO BE A JEDEC PACKAGE OUTLINE
M0-220 VARIATION WHHD-(X) (TO BE APPROVED)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
PIN 1
TOP MARK
(NOTE 6)
0.40 ± 0.10
31
1
2
32
BOTTOM VIEW—EXPOSED PAD
3.50 REF
(4-SIDES)
3.45 ± 0.10
3.45 ± 0.10
0.75 ± 0.05 R = 0.115
TYP
0.25 ± 0.05
(UH32) QFN 0406 REV D
0.50 BSC
0.200 REF
0.00 – 0.05
0.70 ±0.05
3.50 REF
(4 SIDES)
4.10 ±0.05
5.50 ±0.05
0.25 ± 0.05
PACKAGE OUTLINE
0.50 BSC
RECOMMENDED SOLDER PAD LAYOUT
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
PIN 1 NOTCH R = 0.30 TYP
OR 0.35 × 45° CHAMFER
R = 0.05
TYP
3.45 ± 0.05
3.45 ± 0.05
LT5554
32
5554f
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2008
LT 0708 • PRINTED IN USA
RELATED PARTS
PART NUMBER DESCRIPTION COMMENTS
Infrastructure
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LT5517 40MHz to 900MHz Quadrature Demodulator 21dBm IIP3, Integrated LO Quadrature Generator
LT5518 1.5GHz to 2.4GHz High Linearity Direct Quadrature
Modulator 22.8dBm OIP3 at 2GHz, –158.2dBm/Hz Noise Floor, 50 Single-Ended RF and
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Single-Ended LO and RF Ports Operation
LT5520 1.3GHz to 2.3GHz High Linearity Upconverting Mixer 15.9dBm IIP3 at 1.9GHz, Integrated RF Output Transformer with 50 Matching,
Single-Ended LO and RF Ports Operation
LT5521 10MHz to 3700MHz High Linearity Upconverting Mixer 24.2dBm IIP3 at 1.95GHz, NF = 12.5dB, 3.15V to 5.25V Supply, Single-Ended LO
Port Operation
LT5522 600 MHz to 2.7GHz High Signal Level
Downconverting Mixer 4.5V to 5.25V Supply, 25dBm IIP3 at 900MHz, NF = 12.5dB, 50 Single-Ended
RF and LO Ports
LT5524 Low Power, Low Distortion ADC Driver with Digitally
Programmable Gain 450MHz Bandwidth, 40dBm OIP3, 4.5dB to 27dB Gain Control
LT5525 High Linearity, Low Power Downconverting Mixer Single-Ended 50 RF and LO Ports, 17.6dBm IIP3 at 1900MHz, ICC = 28A
LT5526 High Linearity, Low Power Downconverting Mixer 3V to 5.3V Supply, 16.5dBm IIP3, 100kHz to 2GHz RF, NF = 11dB,
ICC = 28mA, –65dBm LO-RF Leakage
LT5527 400MHz to 3.7GHz High Signal Level
Downconverting Mixer IIP3 = 23.5dBm and NF = 12.5dBm at 1900MHz, 4.5V to 5.25V Supply,
ICC = 78mA, Conversion Gain = 2dB
LT5528 1.5GHz to 2.4GHz High Linearity Direct Quadrature
Modulator 21.8dBm OIP3 at 2GHz, –159.3dBm/Hz Noise Floor, 50, 0.5VDC Baseband
Interface, 4-Channel W-CDMA ACPR = –66dBc at 2.14GHz
LT5557 400MHz to 3.8GHz, 3.3V High Signal Level
Downconverting Mixer IIP3 = 23.7dBm at 2600MHz, 23.5dBm at 3600MHz, ICC = 82A at 3.3V
LT5560 Ultra-Low Power Active Mixer 10mA Supply Current, 10dBm IIP3, 10dB NF, Usable as Up- or Down-Converter.
LT5568 700MHz to 1050MHz High Linearity Direct Quadrature
Modulator 22.9dBm OIP3 at 850MHz, –160.3dBm/Hz Noise Floor, 50, 0.5VDC Baseband
Interface, 3-Ch CDMA2000 ACPR = –71.4dBc at 850MHz
LT5572 1.5GHz to 2.5GHz High Linearity Direct Quadrature
Modulator 21.6dBm OIP3 at 2GHz, –158.6dBm/Hz Noise Floor, High-Ohmic 0.5VDC
Baseband Interface, 4-Ch W-CDMA ACPR = –67.7dBc at 2.14GHz
LT5575 800MHz to 2.7GHz High Linearity Direct Conversion
I/Q Demodulator 50, Single-Ended RF and LO Inputs. 28dBm IIP3 at 900MHz, 13.2dBm P1dB,
0.04dB I/Q Gain Mismatch, 0.4° I/Q Phase Mismatch
LT5579 1.5GHz to 3.8GHz High Linearity Upconverting Mixer 27.3dBm OIP3 at 2.14GHz, 9.9dB Noise Floor, 2.6dB Conversion Gain, –35dBm
LO Leakage
RF Power Detectors
LTC
®
5505 RF Power Detectors with >40dB Dynamic Range 300MHz to 3GHz, Temperature Compensated, 2.7V to 6V Supply
LTC5507 100kHz to 1000MHz RF Power Detector 100kHz to 1GHz, Temperature Compensated, 2.7 to 6V Supply
LTC5508 300MHz to 7GHz RF Power Detector 44dB Dynamic Range, Temperature Compensated, SC70 Package
LTC5509 300MHz to 3GHz RF Power Detector 36dB Dynamic Range, Low Power Consumption, SC70 Package
LTC5530 300MHz to 7GHz Precision RF Power Detector Precision VOUT Offset Control, Shutdown, Adjustable Gain
LTC5531 300MHz to 7GHz Precision RF Power Detector Precision VOUT Offset Control, Shutdown, Adjustable Offset
LTC5532 300MHz to 7GHz Precision RF Power Detector Precision VOUT Offset Control, Adjustable Gain and Offset
LT5534 50MHz to 3GHz Log RF Power Detector with 60dB
Dynamic Range ±1dB Output Variation over Temperature, 38ns Response Time, Log Linear
Response
LTC5536 Precision 600Mhz to 7GHz RF Power Detector with
Fast Comparator Output 25ns Response Time, Comparator Reference Input, Latch Enable Input, –26dBm
to 12dBm Input Range
LT5537 Wide Dynamic Range Log RF/IF Detector Low Frequency to 1GHz, 83dB Log Linear Dynamic Range
LT5538 3.8GHz Wide Dynamic Range Log Detector 75dB Dynamic Range, ±1dB Output Variation Over Temperature
LT5570 2.7GHz RMS Power Detector Fast Responding, up to 60dB Dynamic Range, ±0.3dB Accuracy Over
Temperature
