LT5554 Broadband Ultra Low Distortion 7-Bit Digitally Controlled VGA DESCRIPTION FEATURES n n n n n n n n n n n 1GHz Bandwidth at all Gains 48dBm OIP3 at 200MHz, 2VP-P into 50, ROUT = 100 -88dBc IMD3 at 200MHz, 2VP-P into 50, ROUT = 100 1.4nV/Hz Input-Referred-Noise (RTI) 20dBm Output P1dB at 70MHz, ROUT = 130 2dB to 18dB Gain Range (ROUT = 50) 0.125dB Gain Step Size 30ps Group Delay Variation 5ns Fast Gain Settling Time 5ns Fast Overdrive Recovery -80dB Reverse Isolation The LT(R)5554 is a 7-bit digitally controlled programmable gain (PG) amplifier with 16dB gain control range. It consists of a 50 input variable attenuator, followed by a high linearity variable transconductance amplifier. The coarse 4dB input attenuator step is implemented via 2-bits of digital control (PG5, PG6). The fine transconductance amplifier 0.125dB step within 3.875dB gain control range is set via 5-bits digital control (PG0 to PG4). The LT5554 gain control inputs (PGx) and the STROBE input can be directly coupled to TTL or ECL drivers. The seven parallel gain control inputs time skew can be eliminated by using the STROBE input positive transition. The internal output resistor RO = 400 limits the maximum overall gain to 36dB for open outputs. The internal circuitry of open output collectors enables the LT5554 to be unconditionally stable over any loading conditions (including external SAW filters) and provides -80dB reverse isolation at 300MHz. APPLICATIONS n n n n n Differential ADC Driver IF Sampling Receivers VGA IF Power Amplifier 50 Driver Instrumentation The LT5554 is internally protected during overdrive and has an on-chip power supply regulator. L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. With 0.125dB step resolution and 5ns settling time, the LT5554 is suitable in applications where continuous gain control is required. TYPICAL APPLICATION OIP3 and SFDR vs Frequency 132 VCC MODE IF BPF RF INPUT DEC IN- LO - 0.1F CDEC 0.1F LT5554 BPF ADC + 7 BITS PGx GAIN CONTROL 130 46 OIP3 OIP3 (dBm) IN+ SFDR (dBm/Hz) 0.1F IF AMPLIFIER 49 ROUT = 50 5V 128 43 5554 TA01 SFDR STROBE 126 0 50 100 150 FREQUENCY (MHz) 40 200 5554 TA01b 5554f 1 LT5554 ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION (Notes 1, 2) GND GND PG4 GND PG3 PG2 PG1 GND TOP VIEW Supply Voltage VCC..........................................................................6V Pin Voltages and Currents OUT+, OUT- ............................................................7V STROBE, PGx..........................................-0.5V to VCC ENB, MODE.............................................-0.5V to VCC IN+, IN-, DEC ........................................... -0.5V to 4V Operating Ambient Temperature Range LT5554 ............................................... -40C to +85C Junction Temperature ........................................... 125C Storage Temperature Range................. -65C to +150C 32 31 30 29 28 27 26 25 GND 1 24 VCC GND 2 23 ENB DEC 3 22 GND IN+ 4 IN- 5 DEC 6 19 GND GND 7 18 MODE GND 8 17 VCC 21 OUT- 33 20 OUT+ GND GND STROBE GND PG0 PG6 PG5 GND 9 10 11 12 13 14 15 16 UH PACKAGE 32-LEAD (5mm s 5mm) PLASTIC QFN TJMAX = 150C, JA = 34C/W, JC = 3C/W EXPOSED PAD (PIN 33) IS GND, MUST BE SOLDERED TO PCB ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE LT5554IUH#PBF LT5554IUH#TRPBF 5554 32-Lead (5mm x 5mm) Plastic QFN -40C to 85C Consult LTC Marketing for parts specified with wider operating temperature ranges. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 5554f 2 LT5554 AC ELECTRICAL CHARACTERISTICS (ROUT = 50) Specifications are at TA = 25C. VCC = 5V, VCCO = 5V, ENB = 3V, MODE = 5V, STROBE = 2.2V, VIH = 2.2V, VIL = 0.6V, maximum gain (Notes 3, 6), (Test circuits shown in Figure 16), unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT Dynamic Performance BW Large Signal -3dB Bandwidth All Gain Settings (Note 7) LF - 1000 MHz OP1dB Output 1dB Compression Point All Gain Settings, ROUT = 130, 70MHz 20 dBm GM Amplifier Transconductance at GMAX FIN = 100MHz 0.15 S CMRR Common Mode Gain to Single-Ended Output FIN = 100MHz, Figure 19 -6 dB S12 Reverse Isolation FIN = 100MHz FIN = 400MHz -86 -78 dB dB Overdrive Recovery Time 5ns Input Pulse, VOUT within 10% 5 ns Noise/Linearity Performance Two Tones, POUT = 4dBm/Tone (2VP-P into 50), f = 200kHz IIP3 Input Third Order Intercept Point GMAX, FIN = 200MHz GMAX -3.875dB, FIN = 200MHz 27 30 dBm dBm OIP3 Output Third Order Intercept Point for Max-Gain FIN = 100MHz FIN = 200MHz 45 46 dBm dBm IMD3 Intermodulation Product for Max-Gain FIN = 100MHz FIN = 200MHz -82 -84 dBc dBc OIP3 Output Third Order Intercept Point for -3.875dB STEP FIN = 100MHz FIN = 200MHz 44 40 dBm dBm OIP3 Output Third Order Intercept Point GMAX, F1 = 88MHz, F2 = 112MHz GMAX -3.875dB, F1 = 88MHz, F2 = 112MHz 47 44 dBm dBm HD3 Third Harmonic Distortion Pout = 10dBm, FIN = 100MHz, GMAX -62 dBc VONOISE Output Noise Noise Spectral Density GMAX, FIN = 200MHz GMAX -3.875dB, FIN = 200MHz 10.7 7.3 nV/Hz nV/Hz NF Noise Figure GMAX, FIN = 200MHz GMAX -3.875dB, FIN = 200MHz 10 10.5 dB dB RTI Input Referred Noise Spectral Density (RMS) (Note 5) GMAX, FIN = 200MHz GMAX -3.875dB, FIN = 200MHz 1.34 1.42 nV/Hz nV/Hz SFDR Spurious Free Dynamic Range in 1Hz BW. GMAX, FIN = 200MHz GMAX -3.875dB, FIN = 200MHz 128 129 dBm/Hz dBm/Hz 40.5 38 Amplifier Voltage Gain and Gain Step GMAX Maximum Voltage and Power Gain FIN = 112MHz 15.3 17.6 19.7 dB GMIN Minimum Voltage and Power Gain FIN = 100MHz 1.725 GSTEP Gain Step Size (Note 9) Except For -4dB, -8dB, -12dB Steps For -4dB, -8dB, -12dB Steps 0.125 0.25 0.35 dB dB GDERROR Group Delay Step Accuracy FIN = 100MHz 10 ps 43 47 dB AMPLIFIER I/O Differential IMPEDANCE RIN Input Resistance FIN = 100MHz, GMAX to GMAX -3.875dB FIN = 100MHz, GMAX -4dB to GMIN CIN Input Capacitance FIN = 100MHz 2.8 pF RO Output Resistance FIN = 100MHz 400 CO Output Capacitance FIN = 100MHz 1.9 pF 5554f 3 LT5554 AC ELECTRICAL CHARACTERISTICS (ROUT = 100) Specifications are at TA = 25C. VCC = 5V, VCCO = 5V, ENB = 3V, MODE = 5V, STROBE = 2.2V, VIH = 2.2V, VIL = 0.6V, maximum gain (Notes 3, 8), (Test circuits shown in Figure 16), unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT Noise/Linearity Performance Two Tones, POUT = 4dBm/Tone (2VP-P into 50), f = 200kHz IIP3 Input Third Order Intercept Point GMAX, FIN = 200MHz GMAX -3.875dB, FIN = 200MHz 27 27 dBm dBm OIP3 Output Third Order Intercept Point for Max-Gain FIN = 100MHz FIN = 200MHz 48 48 dBm dBm IMD3 Intermodulation Product for Max-Gain FIN = 100MHz FIN = 200MHz -88 -88 dBc dBc VONOISE Output Noise Noise Spectral Density GMAX, FIN = 200MHz GMAX -3.875dB, FIN = 200MHz 21.4 14.5 nV/Hz nV/Hz NF Noise Figure GMAX, FIN = 200MHz GMAX -3.875dB, FIN = 200MHz 10 10.5 dB dB RTI Input Referred Noise Spectral Density (RMS) (Note 5) GMAX, FIN = 200MHz GMAX -3.875dB, FIN = 200MHz 1.34 1.42 nV/Hz nV/Hz SFDR Spurious Free Dynamic Range in 1Hz BW. GMAX, FIN = 200MHz 128 dBm/Hz GVMAX Maximum Voltage Gain FIN = 100MHz 23.6 dB GPMAX Maximum Power Gain FIN = 100MHz 20.6 dB AC ELECTRICAL CHARACTERISTICS (Timing Diagram) (ROUT = 50) Specifications are at TA = 25C. VCC = 5V, VCCO = 5V, ENB = 3V, MODE = 5V, STROBE = 3V, VIH = 2.2V, VIL = 0.6V, maximum gain (Test circuit shown in Figure 16), unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT PGx and Strobe Timing Characteristics TSU Setup Time PGx vs STROBE 0 ns THOLD Hold Time PGx vs STROBE 1 ns TPW STROBE Pulse Width 2 ns TR STROBE Period 4 ns TLATENCY Latency Time of the Previous Gain State Output Settles within 1% 4 ns TGLITCH Time Between Previous Stable Gain State to Next Stable State Output Settles within 1% 5 ns AGLITCH Max Glitch Amplitude VIN = 0 (No Signal or STROBE Transition During Output Signal Zero Crossing) 1 mV STROBE Transition when Output Power is at Peak + 10dBm Power 3 dB 5554f 4 LT5554 AC ELECTRICAL CHARACTERISTICS (Timing Diagram) Timing Diagram PG0, 1, 2, 3, 4, 5, 6 INPUTS TSU THOLD STROBE INPUTS DATA TRANSPARENT TPW DATA LATCH TGLITCH TLATENCY OUT SIGNAL STATE (i) STATE (i + 1) STATE (i + 2) 5554 TD01 DC ELECTRICAL CHARACTERISTICS Specifications are at TA = 25C. VCC = 5V, VCCO = 5V, ENB = 3V, MODE = 5V, unless otherwise noted. (Note 3) (Test circuit shown in Figure 16), unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT 4.75 5 5.25 V 5 6 V 2 2.15 Normal Operating Conditions VCC Supply Voltage VCCO OUT+, OUT- Output Pin DC Common Mode (Note 4) Voltage Shutdown DC Characteristics, ENB = 0.6V VIN(BIAS) DEC, IN+, IN- Bias Voltage IIL(PG) PGx, STR Input Current VIN = 0.6V IIH(PG) PGx, STR Input Current VIN = 5V IOUT OUT+, OUT- Current ICC VCC Supply Current V 0 A 210 A 4 20 A 5.1 mA 0.6 V VCC V 20 A Enable Input DC Characteristics VIL(EN) ENB Input LOW Voltage Disable VIH(EN) ENB Input HIGH Voltage Enable 3 IIL(EN) ENB Input Current VIN = 0.6V IIH(EN) ENB Input Current VIN = 3V 70 IIH(EN) ENB Input Current VIN = 5V 220 A 300 A 5554f 5 LT5554 DC ELECTRICAL CHARACTERISTICS Specifications are at TA = 25C. VCC = 5V, VCCO = 5V, ENB = 3V, MODE = 5V, unless otherwise noted. (Note 3) (Test circuit shown in Figure 16), unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT DEC External Capacitor Charge/Discharge CURRENT IIH(DEC) DEC Pin Source Current VDEC = 4V 27 50 70 mA IIL(DEC) DEC Pin Sink Current VDEC = 1.8V -70 -38 -14 mA 0.6 V 2.3 V Mode Input Three-State DC Characteristics VIL(MODE) MODE Input LOW Voltage for AC-Couple PGx AC-Coupled, STROBE AC-Coupled 0 VOPEN(MODE) MODE Input OPEN PGx AC-Coupled, STROBE DC-Coupled 1.7 OPEN VIH(MODE) MODE Input HIGH Voltage PGx DC-Coupled, STROBE DC-Coupled VCC - 0.4 VCC IIL(MODE) MODE Input Current VMODE = 0V -42 -31 -23 A V IIH(MODE) MODE Input Current VMODE = 5V 43 72 100 A 0.6 V 30 A 220 A 4.6 V PGx (MODE = VCC) and STROBE (MODE = OPEN or MODE = VCC) INPUTS for DC-Coupled VIL Input LOW Voltage VIH Input HIGH Voltage IIL(DC) Input Current VIN = 0.6V IIH(DC) Input Current VIN = 5V 2.2 125 V 170 PGx (MODE = 0V or MODE = OPEN) and STROBE (MODE = 0V) INPUTS for AC-Coupled VIN(AC) Input Pulse Range Instantaneous Input Voltage 0 VIN(AC)P-P Input Pulse Amplitude Rise and Fall Time <5ns Rise and Fall Time >80ns VIN(AC)MAX Maximum Input Noise Amplitude No LT5554 Gain Update IIL(AC) Input Current VIN = 0V -210 -155 -100 A IIH(AC) Input Current VIN = 5V 310 420 530 A V 600 300 mVP-P mVP-P 100 mVP-P Amplifier DC Characteristics VIN(DEC) DEC GMAX 1.85 2 2.25 VIN(BIAS) IN+, IN- Bias Voltage GMAX 1.8 2.04 2.2 RIN INPUT Differential Resistance GMAX GMIN GM Amplifier Transconductance GMAX IODC OUT+, OUT- Quiescent Current VOUT = 5V IOUT(OFFSET) Output Current Mismatch IN+, IN- Open ICC VCC Supply Current GMAX, MODE = 0V GMIN, MODE = 0V GMAX, MODE = 5V GMIN, MODE = 5V ICC(TOTAL) Total Supply Current ICC + 2 * IODC (GMAX) Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltage values are with respect to GND ground. Note 3: RS = RIN = 50 Input matching is assumed. PIN is the available input power. POUT is the power into ROUT. ROUT = RO || RLOAD is the total output resistance at amplifier open-collectors outputs (used in GV, GP gain calculation). RO = 400 is LT5554 internal output impedance. RLOAD is 48 50 0.15 33 47 78 77 75 75 110 109 106 106 S 57 mA 132 131 127 127 mA mA mA mA 200 200 V A mA load resistance as seen at OUT+, OUT- pins. All dBm figures are with respect to 50. Specifications refer to differential inputs and differential outputs. Note 4: An external power supply equal to VCCO is used for choke inductors or center-tap transformer output interfaces. Whenever OUT+, OUT- pins are biased via resistors, the voltage drop produced by the DCoutput current (IODC = 45mA typical) may require a larger output external power supply. However, care must be taken not to exceed the OUT+, OUT- absolute maximum rating when the LT5554 is disabled. 5554f 6 LT5554 ELECTRICAL CHARACTERISTICS Note 5: RTI (Referred-To-Input) stands for the total input-referred noise voltage source. RTI is close to output noise voltage divided by voltage gain (the exact equation is given in Definition of Specification section). The equivalent noise source eN is twice the RTI value. Note 6: The external loading at LT5554 OUT+/OUT- pins is RLOAD = 57. ROUT = RLOAD || RO = 50. Note 7: The IN+, IN-, DEC pins are internally biased. The time-constant of input coupling capacitor sets the low frequency corner (LF) at input. The output coupling capacitors or the transformer sets the low frequency corner (LF) at the output. The LT5554 operates internally down to DC. Note 8: The external loading at OUT+/OUT- pins is RLOAD = 133. ROUT = RLOAD || RO = 100. Note 9: Depending on the actual input matching conditions and frequency of operation, the LT5554 steps involving the input attenuator tap change may show less than 0.125dB change. These steps are GMAX -4dB, GMAX -8dB, GMAX -12dB, and the code is given in the Programmable Gain Table. The LT5554 monotonic operation for 0.125dB step resolution can still be obtained by skipping any such code with a gain error excedding 0.125dB. TYPICAL PERFORMANCE CHARACTERISTICS (ROUT = 50) TA = 25C. VCC = 5V, VCCO = 5V, ENB = 3V, MODE = 5V, STROBE = 3V, VIH = 2.2V, VIL = 0.6V (Test circuit shown in Figure 16), unless otherwise noted. Gain vs Frequency for 0.5dB Steps, Figure 17 Differential Gain Error vs Frequency at -40C 20 Differential Gain Error vs Frequency at 85C 0.3 0.3 0.2 0.2 18 16 12dB 12 10 8 6 12dB 0.1 GAIN ERROR (dB) GAIN ERROR (dB) GAIN (dB) 14 4dB 8dB 0 -0.1 4 0.1 4dB 8dB 0 -0.1 2 0 -0.2 0 100 200 300 400 500 600 700 800 900 1000 FREQUENCY (MHz) 50 75 100 125 150 FREQUENCY (MHz) 5554 G01 -0.1 -0.2 0.3 0.1 0 -0.1 0 -4 -8 -12 ATTENUATION (dB) -16 5554 G04 100 125 150 FREQUENCY (MHz) -0.2 175 200 -40C 25C 85C 0.2 GAIN ERROR (dB) 0 75 Differential Gain Error vs Attenuation at 200MHz -40C 25C 85C 0.2 GAIN ERROR (dB) GAIN ERROR (dB) 0.3 0.1 50 5554 G03 Differential Gain Error vs Attenuation at 100MHz -40C 25C 85C 0.2 -0.2 200 5554 G02 Differential Gain Error vs Attenuation at 50MHz 0.3 175 0.1 0 -0.1 0 -4 -8 -12 ATTENUATION (dB) -16 5554 G05 -0.2 0 -4 -8 -12 ATTENUATION (dB) -16 5554 G06 5554f 7 LT5554 TYPICAL PERFORMANCE CHARACTERISTICS (ROUT = 50) TA = 25C. VCC = 5V, VCCO = 5V, ENB = 3V, MODE = 5V, STROBE = 3V, VIH = 2.2V, VIL = 0.6V (Test circuit shown in Figure 16), unless otherwise noted. Integral Gain Error vs Attenuation at 50MHz 0.2 0.1 0.1 0.1 -4 -8 -12 ATTENUATION (dB) -0.1 -16 0 0 -4 -8 -12 ATTENUATION (dB) 5554 G07 24 200MHz 17.4 17.2 -20 0 20 40 60 TEMPERATURE (C) -8 -12 ATTENUATION (dB) -16 8 0 8 0 -8 -16 -35 80 70MHz 140MHz 200MHz 16 -8 17.0 -40 -4 POUT vs PIN at GMAX - 3.875dB 24 POUT (dBm) POUT (dBm) 100MHz 0 5554 G09 70MHz 140MHz 200MHz 16 50MHz 17.6 -0.1 POUT vs PIN at Maximum Gain Maximum Gain vs Temperature 17.8 -16 5554 G08 18.0 GMAX (dB) 0.2 0 0 -40C 25C 85C 0.3 0.2 0 -0.1 0.4 -40C 25C 85C 0.3 GAIN ERROR (dB) 0.3 GAIN ERROR (dB) 0.4 -40C 25C 85C Integral Gain Error vs Attenuation at 200MHz GAIN ERROR (dB) 0.4 Integral Gain Error vs Attenuation at 100MHz -25 -15 -5 PIN (dBm) 5 5554 G10 -16 -35 15 -25 -15 -5 PIN (dBm) 5554 G11 5 15 5554 G12 (ROUT = 50) TA = 25C. VCC = 5V, VCCO = 5V, ENB = 3V, MODE = 5V, STROBE = 3V, VIH = 2.2V, VIL = 0.6V (Test circuit shown in Figure 16) POUT = 4dBm/tone (2VP-P into 50), f = 200kHz, unless otherwise noted. Two-Tone OIP3 vs Frequency at Max Gain, Three Temperatures Two-Tone IMD3 vs Frequency at Max Gain, Three Temperatures 49 IIP3 vs Frequency at Max Gain, Three Temperatures -76 32 85C 85C -79 30 IMD3 (dBc) OIP3 (dBm) -40C 25C -40C IIP3 (dBm) 25C 46 -82 25C 28 -40C 43 -85 26 85C 40 0 50 100 150 FREQUENCY (MHz) 200 5554 G13 -88 0 50 100 150 FREQUENCY (MHz) 200 5554 G14 24 0 50 100 150 FREQUENCY (MHz) 200 5554 G15 5554f 8 LT5554 TYPICAL PERFORMANCE CHARACTERISTICS (ROUT = 50) TA = 25C. VCC = 5V, VCCO = 5V, ENB = 3V, MODE = 5V, STROBE = 3V, VIH = 2.2V, VIL = 0.6V (Test circuit shown in Figure 16) POUT = 4dBm/tone (2VP-P into 50), f = 200kHz, unless otherwise noted. Two-Tone OIP3 vs Frequency for GMAX and Critical Gain Steps Two-Tone IMD3 vs Frequency for GMAX and Critical Gain Steps 49 IIP3 vs Frequency for GMAX and GMAX -3.875dB 32 -70 GMAX - 3.875dB GMAX - 12dB -76 IMD3 (dBc) OIP3 (dBm) GMAX GMAX - 15.875dB 43 GMAX - 3.875dB -82 GMAX - 3.875dB IIP3 (dBm) 46 30 GMAX - 15.875dB GMAX GMAX 28 26 GMAX - 12dB 200 100 150 FREQUENCY (MHz) -88 24 50 200 100 150 FREQUENCY (MHz) 5554 G16 50 100 150 FREQUENCY (MHz) 200 5554 G18 5554 G17 Two-Tone IMD3 and OIP3 vs Attenuation at 50MHz Two-Tone IMD3 and OIP3 vs Attenuation at 70MHz -70 48 -70 -74 46 -74 46 -78 44 -78 44 48 OIP3 IMD3 IMD3 -82 -86 0 -4 -8 -12 ATTENUATION (dB) 42 -82 40 -16 -86 OIP3 (dBm) OIP3 (dBm) IMD3 (dBc) OIP3 IMD3 (dBc) 42 0 -4 -8 -12 ATTENUATION (dB) 5554 G19 40 -16 5554 G20 Two-Tone IMD3 and OIP3 vs Attenuation at 100MHz Two-Tone IMD3 and OIP3 vs Attenuation at 140MHz -70 48 -70 48 OIP3 -74 46 OIP3 -82 42 -74 46 -78 44 -82 42 IMD3 -86 0 -4 -8 -12 ATTENUATION (dB) OIP3 (dBm) 44 OIP3 (dBm) -78 IMD3 (dBc) 50 IMD3 (dBc) 40 IMD3 40 -16 5554 G21 -86 0 -4 -8 -12 ATTENUATION (dB) 40 -16 5554 G22 5554f 9 LT5554 TYPICAL PERFORMANCE CHARACTERISTICS (ROUT = 50) TA = 25C. VCC = 5V, VCCO = 5V, ENB = 3V, MODE = 5V, STROBE = 3V, VIH = 2.2V, VIL = 0.6V (Test circuit shown in Figure 16) POUT = 4dBm/tone (2VP-P into 50), f = 200kHz, unless otherwise noted. Two-Tone IMD3 and OIP3 vs Attenuation at 200MHz Two-Tone OIP3 vs Tone Power at Max-Gain -70 48 Two-Tone OIP3 vs Tone Power at Min-Gain 47 47 44 44 IMD3 44 OIP3 (dBm) -78 OIP3 50MHz 70MHz 100MHz 140MHz 200MHz 42 0 -4 40 -16 -8 -12 ATTENUATION (dB) 38 50MHz 70MHz 100MHz 140MHz 200MHz 41 41 -82 -86 OIP3 (dBm) 46 OIP3 (dBm) IMD3 (dBc) -74 0 38 6 9 3 OUTPUT TONE POWER (dBm) 5554 G23 12 0 3 6 9 OUTPUT TONE POWER (dBm) 5554 G25 5554 G24 Two-Tone OIP3 vs ROUT, for GMAX Two-Tone OIP3 vs VCCO, for GMAX -3.875dB Two-Tone OIP3 vs VCCO, for GMAX 50 12 48 48 45 45 OIP3 (dBm) OIP3 (dBm) OIP3 (dBm) 48 42 42 46 44 25MHz 70MHz 140MHz 200MHz 50 75 ROUT () 100 39 36 2 3 4 5 OUTPUT COMMON MODE VOLTAGE (V) 6 36 25MHz 70MHz 140MHz 200MHz 2 3 4 5 OUTPUT COMMON MODE VOLTAGE (V) 5554 G28 5554 G52 Harmonic Distortion vs Attenuation, 50MHz, POUT = 10dBm, Figure 17 6 5554 G30 OIP3 vs Frequency for GMAX and GMIN, POUT = 10dBm 50 -70 -75 -80 45 HD3 -85 OIP3 (dBm) HARMONIC DISTORTION (dBc) 39 25MHz 70MHz 140MHz 200MHz -90 GMIN 40 -95 GMAX -100 HD5 -105 35 0 -4 -8 -12 ATTENUATION (dB) -16 5554 G27 50 100 150 FREQUENCY (MHz) 200 5554 G29 5554f 10 LT5554 TYPICAL PERFORMANCE CHARACTERISTICS (ROUT = 50) TA = 25C. VCC = 5V, VCCO = 5V, ENB = 3V, MODE = 5V, STROBE = 3V, VIH = 2.2V, VIL = 0.6V (Test circuit shown in Figure 16) POUT = 4dBm/tone (2VP-P into 50), f = 200kHz, unless otherwise noted. HD3 vs Frequency for GMAX and GMIN, POUT = 10dBm, Figure 17 HD5 vs Frequency for GMAX and GMIN, POUT = 10dBm, Figure 17 -70 -56 HARMONIC DISTORTION (dBc) HARMONIC DISTORTION (dBc) -50 GMAX -62 GMIN -68 -74 -80 50 100 150 FREQUENCY (MHz) -76 -82 GMIN -88 -94 -100 200 GMAX 50 100 150 FREQUENCY (MHz) 200 5554 G31 5554 G32 (ROUT = 50) TA = 25C. VCC = 5V, VCCO = 5V, ENB = 3V, MODE = 5V, STROBE = 3V, VIH = 2.2V, VIL = 0.6V (Test circuit shown in Figure 16), maximum gain, unless otherwise noted. HD3 and HD5 vs POUT for GMAX, Figure 17 -40 -50 20 15 HD3 HD5 -60 NF (dB) -55 15 GMAX -3.875 GMAX -3.875 HD3 NF (dB) HARMONIC DISTORTION (dBc) 20 70MHz 140MHz -45 Single-Ended Output NF vs Frequency, Figure 18 Noise Figure vs Frequency GMAX 10 GMAX 10 -65 -70 5 -75 -80 5 HD5 7 10 13 OUTPUT POWER (dBm) 0 16 0 200 400 600 FREQUENCY (MHz) 5554 G33 0 800 0 200 400 600 FREQUENCY (MHz) 5554 G34 Noise Figure vs Attenuation, 140MHz 5554 G35 Input Referred Noise vs Attenuation, 140MHz 25 800 Output Noise Density vs Attenuation, 140MHz 6 12 20 15 10 VONOISE (nV/Hz) RTI (nV/Hz) NF (dB) 9 4 2 3 5 0 6 0 -4 -8 -12 ATTENUATION (dB) -16 5554 G36 0 0 -4 -8 -12 ATTENUATION (dB) -16 5554 G37 0 0 -4 -8 -12 ATTENUATION (dB) -16 5554 G38 5554f 11 LT5554 TYPICAL PERFORMANCE CHARACTERISTICS ( ROUT = 50) TA = 25C. VCC = 5V, VCCO = 5V, ENB = 3V, MODE = 5V, STROBE = 3V, VIH = 2.2V, VIL = 0.6V (Test circuit shown in Figure 16), maximum gain, unless otherwise noted. Single-Ended Output Current vs Attenuation Total ICC Current vs Attenuation 98 215 85C 208 96 CURRENT (mA) CURRENT (mA) -40C 25C 85C 94 25C 200 193 92 0 -4 -8 -12 ATTENUATION (dB) 185 -16 -40C 0 -4 -8 -12 ATTENUATION (dB) 5554 G39 -16 5554 G40 ICC Shutdown Current vs VCC, ENB = 0.6V VIN(BIAS) vs Attenuation 5 2.2 85C 4 VIN(BIAS) (V) CURRENT (mA) -40C 3 25C 2 -40C 2.1 85C 25C 1 0 4.7 4.9 5.1 VCC (V) 5.3 5.5 5554 G41 2.0 0 -4 -8 -12 ATTENUATION (dB) -16 5554 G42 5554f 12 LT5554 TYPICAL PERFORMANCE CHARACTERISTICS (ROUT = 50) TA = 25C. VCC = 5V, VCCO = 5V, ENB = 3V, MODE = 5V, STROBE = 3V, VIH = 2.2V, VIL = 0.6V (Test circuit shown in Figure 16), maximum gain, unless otherwise noted. 2dB-Step Response (PG4) 120MHz Signal 8dB-Step Response (PG6) 120MHz Signal 0.1V/DIV 8dB-Step Response (PG6) 120MHz Pulse Signal 0.1V/DIV 10ns/DIV 0.2V/DIV 5554 G46 10ns/DIV 5554 G47 5ns/DIV MODE = HIGH MODE = HIGH MODE = HIGH 8dB-Step (PG6) 120MHz Pulse Signal for 8dB Overdrive 8dB-Step (PG6) 120MHz Sinusoidal Signal for 2dB Overdrive 8dB-Step (PG6) 120MHz Sinusoidal Signal for 8dB Overdrive 1V/DIV 1V/DIV 5ns/DIV MODE = HIGH 5554 G48 1V/DIV 5554 G49 5ns/DIV MODE = HIGH 5554 G50 10ns/DIV 5554 G51 MODE = HIGH PIN FUNCTIONS GND (Pins 1, 2, 7, 8, 10, 13, 15, 16, 19, 22, 25, 26, 28, 31): Ground Pins. DEC (Pins 3, 6): Decoupling Pin for the Internal DC Bias Voltage for the Differential Inputs, IN+ and IN-. It is also connected to the `virtual ground' of the input resistive attenuator. Capacitive de-coupling to ground is recommended in order to preserve linearity performance when IN+, IN- inputs are driven with up to 3dB imbalance. IN+ (Pin 4): Positive Signal Input Pin with Internal DC Bias to 2V. IN- (Pin 5): Negative Signal Input Pin with Internal DC Bias to 2V. PG5 (Pin 9): 4dB Step Amplifier Programmable Gain Control Input Pin. Input levels are controlled by MODE pin. PG6 (Pin 11): 8dB Step Amplifier Programmable Gain Control Input Pin. Input levels are controlled by the MODE pin. PG0 (Pin 12): 0.125dB Step Amplifier Programmable Gain Control Input Pin. Input levels are controlled by MODE pin. STROBE (Pin 14): Strobe Pin for the Programmable Gain Control Inputs (PGx). With STROBE in Low-state, the Amplifier Gain is not changed by PGx state changes (latch mode). With STROBE in High-state, the Amplifier Gain is asynchronously set by PGx inputs transitions (transparent-mode). A positive STROBE transition updates the PGx state. Low-state and High-state depends on MODE pin level (Table1). VCC (Pins 17, 24): Power Supply Pins. These pins are internally connected together. MODE (Pin 18): PGx and STROBE Functionality and Level Control Pin. When MODE is higher than VCC - 0.4V, the PGx and STROBE are DC-coupled. When the MODE pin is lower than 0.6V, the PGx and STROBE are AC-coupled. 5554f 13 LT5554 PIN FUNCTIONS When the MODE pin is left open, the PGx inputs are ACcouple and the STROBE input is DC-coupled. When the ENB input voltage is less than or equal to 0.6V, the amplifier is turned off. In DC-coupled mode, the PGx and STROBE inputs levels are 0.6V and 2.2V. In AC-coupled mode, the PGx and STROBE inputs are driven with 0.6VP-P minimum amplitude (with rise and fall time <5ns) regardless the DC voltage level. A positive transition sets a High-state. A negative transition sets a Low-state (for PGx and STROBE inputs). PG4 (Pin 27): 2dB Step Amplifier Programmable Gain Control Input Pin. Input levels are controlled by MODE pin. PG3 (Pin 29): 1dB Step Amplifier Programmable Gain Control Input Pin. Input levels are controlled by MODE pin. PG2 (Pin 30): 0.5dB Step Amplifier Programmable Gain Control Input Pin. Input levels are controlled by MODE pin. OUT+ (Pin 20): Positive Amplifier Output Pin. A transformer with a center tap tied to VCC or a choke inductor is recommended to conduct the DC quiescent current. PG1 (Pin 32): 0.25dB Step Amplifier Programmable Gain Control Input Pin. Input levels are controlled by MODE pin. OUT- (Pin 21): Negative Amplifier Output Pin. A transformer with a center tap tied to VCC or a choke inductor is recommended to conduct the DC quiescent current. EXPOSED PAD (Pin 33): Ground. This pin must be soldered to the printed circuit board ground plane for good heat dissipation. ENB (Pin 23): Enable Pin for Amplifier. When the ENB input voltage is higher than 3V, the amplifier is turned on. BLOCK DIAGRAM GND (15 PINS) 17 VCC VCC 24 ENB VOLTAGE REGULATOR AND BIAS 23 ENABLE CONTROL DEC 3 RIN+ 25 ATTENUATOR IN+ OUT- 4 21 RO 400 AMPLIFIER IN- OUT+ 20 5 RIN- 25 DEC 6 ATTENUATOR GAIN LOGIC 4dB STEPS 12dB RANGE PG6 11 PG5 9 TRANSCONDUCTANCE GAIN LOGIC 0.125dB STEPS 3.875dB RANGE MODE STROBE LOGIC MODE 18 STROBE 14 PG4 27 PG3 29 PG2 30 PG1 32 PG0 12 5554 BD Figure 1. Functional Block Diagram 5554f 14 LT5554 FUNCTIONAL CHARACTERISTICS Programmable Gain Table STATE PG0 PG1 PG2 N PG3 PG4 PG5 PG6 Step Size in dB 0.125 0.25 0.5 1 ATTENUATION Step Relative to Max Gain GAIN STATE NAME dB 2 4 8 (N - 127) * 0.125dB 127 H H H H H H H 0.00dB GMAX (Max Gain) 126 L H H H H H H -0.125dB GMAX -0.125dB 125 H L H H H H H -0.250dB GMAX -0.25dB 124 L L H H H H H -0.375dB GMAX -0.375dB 123 H H L H H H H -0.500dB GMAX -0.5dB 122 L H L H H H H -0.625dB GMAX -0.625dB 121 H L L H H H H -0.750dB GMAX -0.75dB 120 L L L H H H H -0.875dB 119 H H H L H H H -1.00dB GMAX -1dB 118 L H H L H H H -1.125dB GMAX -1.125dB 112 L L L L H H H -1.875dB GMAX -1.875dB 111 H H H H L H H -2.00dB GMAX -2dB 104 L L L H L H H -2.875dB GMAX -2.875dB 103 H H H L L H H -3.00dB GMAX -3dB 96 L L L L L H H -3.875dB GMAX -3.875dB 95 H H H H H L H -4.00dB GMAX -4dB ... ... ... ... 64 L L L L L L H -7.875dB GMAX -7.875dB 63 H H H H H H L -8.00dB GMAX -8dB ... 32 L L L L L H L -11.875dB GMAX -11.875dB 31 H H H H H L L -12.000dB GMAX -12dB ... 8 L L L H L L L -14.875dB GMAX -14.875dB 7 H H H L L L L -15.000dB GMAX -15dB 6 L H H L L L L -15.125dB GMAX -15.125dB 5 H L H L L L L -15.250dB GMAX -15.25dB 4 L L H L L L L -15.375dB GMAX -15.375dB 3 H H L L L L L -15.500dB GMAX -15.5dB 2 L H L L L L L -15.625dB GMAX -15.625dB 1 H L L L L L L -15.750dB GMAX -15.75dB 0 L L L L L L L -15.875dB GMIN (Min Gain) 5554f 15 LT5554 DEFINITION OF SPECIFICATIONS Amplifier Impedance and Gain Definitions (Differential) RS GV GP RIN LT5554 input resistance (internal, 50) CIN LT5554 input capacitance (internal) RO LT5554 output resistance (internal, 400) CO LT5554 output capacitance (internal) RLOAD Load resistance as seen by LT5554 output pins CLOAD Load capacitance as seen by LT5554 output pins ROUT Total output resistance at LT5554 open-collectors outputs (used in GV, GP gain calculation): PIN VIN is peak - value POUT Total output capacitance at LT5554 output (used in gain calculation): Total power delivered by LT5554 open-collector outputs: V 2 OUT 2 POUT = 10 log in dBm, ROUT * 1mW ) ( LT5554 differential transconductance: GM = Power available at LT5554 input, RS = RIN = 50 input matching: V 2 IN 2 PIN = 10 log in dBm, RIN * 1mW ) ( COUT = CLOAD + CO GM LT5554 differential power gain: GP = 10log(RIN * GM2 * ROUT) in dB ROUT = RO || RLOAD COUT V GV = 20 log OUT = 20 log (GM * ROUT ) in dB VIN Input source resistor. Input matching is assumed: RS = RIN LT5554 differential voltage gain: IOUT VIN VOUT is peak - value INTERNAL EXTERNAL OUT+ IOUT = GM * VIN IDC CO 1.9pF RO 400 ROUT RLOAD RO 400 OUT- CLOAD VOUT = IOUT * ROUT 5554 F02 RLOAD ROUT Figure 2. Output Equivalent Circuit and Impedance Definitions 5554f 16 LT5554 DEFINITION OF SPECIFICATIONS NF Noise Definitions for 50 Matched Input eRS Source resistor RMS noise voltage: ( eN2 + iN2 * RS2 NF = 10 log 1+ eRS2 eRS2 = 4 * k * T * RS ; for RS = 50, eRS = Noise figure in dB according to any of the following equations: 0.9nV Hz ) = 1+ V 1+ RTI2 N 10 log = 10 log 2 e 2 eRS RS 2 2 eN Equivalent short-circuit input RMS noise voltage source iN Equivalent open-circuit input RMS noise current source vN Equivalent total input RMS noise voltage source: Linearity Definitions for 50 Matched Input vN2 = eN2 + iN2 * RS2 (RS = 50) IMD3[dBc] Third-order intermodulation product (negative value) IIP3[dBm] IIP3 = PIN (per-tone) - RTI Referred-to-input LT5554 noise voltage: 2 RTI = 2 2 2 (eRS + eN + iN * RS ) 2 = vN 2 VONOISE LT5554 output noise voltage: 2 20 eRS 2 RTI + * 10 2 2 SFDR[dBm/Hz] SFDR = * (174 + IIP3 - NF ) 3 GV VONOISE = IMD3 2 OIP3[dBm] OIP3 = POUT - IMD3 = IIP3 + GP 2 APPLICATIONS INFORMATION Circuit Operation The LT5554 is a high dynamic range programmable-gain amplifier. It consists of the following sections: * An input variable attenuator with 50 input impedance (four 4dB steps, controlled by PG5, PG6 inputs) * A differential programmable transconductance amplifier (32 steps, 0.125dB each controlled by PG0, PG1, PG2, PG3, PG4 inputs) * Programmable logic blocks * Internal bias (voltage regulators) * Enable/disable circuit Since no internal feedback network is used between amplifier outputs and inputs, the LT5554 is able to offer: * Unconditional stability for I/O reactive loading such as filters (no isolation output resistors required) * High reverse isolation The LT5554 is a class-A transconductance amplifier. An input signal voltage is first converted to an output current via the LT5554 internal GM. And then, the output load (ROUT) converts the output current into an output voltage. ROUT sets the LT5554 gain and output noise floor. However, the SFDR performance is almost independent of ROUT for values of 25 to 100. * Overdrive protection circuit 5554f 17 LT5554 APPLICATIONS INFORMATION The PGx gain control inputs and STROBE input can be configured to be either DC coupled or AC coupled depending on MODE pin level. The LT5554 gain control inputs can be connected without external components to a wide range of user control interfaces. The LT5554 has internal overdrive protection circuitry. The recovery time from a short duration (less than 5ns) overdrive pulse is 5ns. This buffer is also connected to the input resistive attenuator network. The DEC pin is a `virtual ground' and typically connected to an external capacitor CDEC (Figures 3 and 4). When CDEC is used, the LT5554 will have same input attenuation for both differential mode and common mode signals. The DEC pin de-coupling capacitor improves the common mode AC performance even when the differential IN+, IN- inputs are imbalanced by 3dB. The DEC pin can be used as a voltage reference for external circuitry when DC input coupling is desired. Input Interface The DC voltage level at the IN+, IN- inputs are internally biased to about 2V when the part is either enabled or disabled. The best linearity performance is achieved when an input imbalance is less than 2dB. Two typical Input connection circuits are shown in Figures 3 and 4. An input source with 50 (5%) is required for best gain error performance. RSRC/2 25 Output Interface The output interface must conduct the DC current of about 45mA to the amplifier outputs (OUT+ OUT-). Two interface examples are shown in Figures 5 and 6. A wide band ADC voltage interface is shown in Figure 5 where L1 and L2 are choke inductors. For a narrow band application, a band pass filter can be placed at the LT5554's outputs. 5V C1 IN+ OUT- C5 25 CDEC 0.1F VSRC RSRC/2 25 DEC C2 25 OUT+ DEC IN- OUT+ 5554 F03 VCCO ADC BIAS R2 C6 66.5 R1 66.5 LT5554 OUT- RO 400 IN+ L2 CHOKE INDUCTORS MAX GAIN: GV = 24dB GP = 18dB LT5554 IN- L1 C3 ADC Figure 3. Input Capacitively-Coupled to a Differential Source C4 5554 F05 IN+ RSRC 50 * VSRC * RO 400 ROUT 100 OUT- RLOAD 133 RSADC 100 25 CDEC 0.1F DEC IN- Figure 5. Differential Output Interface LT5554 25 5V OUT+ MAX GAIN: GV = 24dB GP = 21dB 5554 F04 Figure 4. Input Transformer-Coupled to Single-Ended Source Decouple (DEC) Input The DEC pin provides the DC voltage level for differential inputs IN+, IN- via an internal buffer, which is able to fast charge/discharge the LT5554 input coupling capacitors with about 30mA sourcing or sinking current capability. C5 DEC LT5554 OUT- RO 400 IN- OUT+ IN+ ROUT 100 R5 205 VCCO MAX GAIN INTO ZO: GP = 18dB T2 4:1 * * R6 205 RO 400 RLOAD 133 * ZO 50 5554 F06 Figure 6. Single-Ended Matched Output Interface 5554f 18 LT5554 APPLICATIONS INFORMATION The differential outputs can also be converted to singleended 50 load using a center-tap transformer interface shown in Figure 6 and Figure 16. Voltage clipping will occur with ROUT >140, in which case the instantaneous voltage at each OUT+ and OUT- outputs is either <2V or >8V. The internal 400 differential resistor (RO) sets the output impedance and the maximum voltage gain (GMAX) to 36dB when outputs OUT+, OUT- are open. The output OP1dB = 20dBm can be achieved when ROUT = 130. In this case, the LT5554 outputs reach both current and voltage limiting for maximum output power. Figure 7 shows the Voltage and Power Gains as a function of ROUT, which is the total output loading at the open collector amplifier output including the internal resistor RO = 400. VOLTAGE GAIN MAXIMUM GAIN (dB) 30 In addition, the STROBE input can be driven such that the LT5554 gain state is updated asynchronously (PGx latch control in transparent-mode) or controlled by positive STROBE transition (PGx latch control in strobed-mode). 24 POWER GAIN 12 There are several options available for coupling type and latch control which are given in the following tables: 6 0 The MODE pin selects the interface to the LT5554 gain control pins. The PGx and STROBE control inputs can be configured to be either DC-coupled (for TTL interface) or AC-coupled (for ECL or low-voltage CMOS interfaces). 36 18 Gain Control Interface 10 50 100 ROUT () 400 1000 5554 F07 Figure 7. Maximum Voltage and Power Gain vs ROUT The gain vs ROUT relationship is given by the following equations: GV = 20log(GM * ROUT) in dB GP = 10log(RIN * GM2 * ROUT) in dB Table1. MODE Input Options COUPLING TYPE MODE (State) STROBE PGx LOW AC Positive Transition AC Strobe OPEN DC >2.2V AC Transparent OPEN 0.6 to 2.2V AC Strobe HIGH DC >2.2V DC Transparent HIGH 0.6 to 2.2V DC Strobe PGx (Latch Control) Where RIN = 50 and GM = 0.15 siemens at GMAX For wide band applications, the amplifier bandwidth can be extended by inductive peaking technique. The inductor in series with the LT5554 outputs (OUT+ OUT-) can have a value up to some tens of nH depending on ROUT value and board capacitance. The current limiting will occur with ROUT <140, in which case the instantaneous signal current at the output exceeds IODC = 45mA. Table2. MODE Input Levels MODE (State) MODE (Min Level) MODE (Max Level) LOW 0 0.6V OPEN 1.5V 2.5V HIGH VCC - 0.4V VCC Alternatively, the MODE pin can be left open (2V internal). 5554f 19 LT5554 APPLICATIONS INFORMATION All seven PGx gain control inputs and STROBE input can be configured as DC-coupled or ac-coupled. Accordingly, there are two basic equivalent schematics (shown in Figures 8 and 9) depending on MODE input choice (Table1). Each PGx input circuit shown in Figures 8 and 9 is followed by a transparent latch controlled by the STROBE input level (Table 1). The DC-coupled interface is shown in Figure 8. DC levels for PGx inputs and STROBE input are VIL <0.6V, VIH >2.2V. VCC R2 1.5k R3 1.5k OUT+ OUT- R1 20k Q1 Q2 INPUT C1 2pF DC-COUPLED I1 200A R4 20k Q3 V1 1.4V IDC 5554 F08 Figure 8. DC-Coupled PGx and STROBE Equivalent Inputs (Simplified Schematic) I3 R3 1.5k OUT+ IDC OUT- R1 20k Q1 Q2 INPUT R4 20k Q3 C1 2pF AC-COUPLED I2 IDC I1 200A V1 1.4V IDC A HIGH-state is set by positive transitions. A LOW-state is set by negative transitions. The PGx and STROBE inputs appear as capacitive coupled inputs. The DC voltage (0V to VCC range) presented on any PGx or STROBE input is shifted to the internal 1.4V level by the additional circuit shown in Figure 9. Each PGx and STROBE input has an independent shift circuit such that each input can have a different DC voltage. Each PGx input has a parallel R-C (R1 = 20k, C1 = 2pF) with a 40ns time constant. The STROBE input circuit has R1 = 20k C1 = 3pF and 60ns time constant. An minimum amplitude of 0.6VP-P is required to trip the PGx and STROBE inputs to an appropriate state when the signal period is less than input time constant. The circuit shown in Figure 8 converts the single-ended external signal to an internal differential signal. Consequently, when the input is idle for more than the input time constant, a 0.3VP-P transition will still trigger the gain control state change. All control inputs have 200mV hysteresis to insure stable logic levels when the input noise level is less than 100mVP-P. For transparent latch control, the amplifier gain will be updated directly with any PGx input state changes. If different PGx inputs have an (external) time skew greater than 1ns, then a noticeable amplifier output glitch can occur. The strobe latch control is recommended to avoid this amplifier output glitch. VCC R2 1.5k The AC-coupled interface is shown in Figure 9. The PGx inputs and STROBE input state is decided by a signal transition rather than signal level. 5554 F09 Figure 9. AC-Coupled PGx and STROBE Equivalent Inputs (Simplified Schematic) It is not necessary to double buffer the PGx inputs since the LT5554 has good internal isolation from the PGx inputs to the amplifier output to any type of external gain control circuit without external components. If LT5554 is powered up or enabled in latch mode, the LT5554 gain initial gain is indeterminate. If the minimum gain state is desired at power up, it is recommended to set the transparent-mode with all PGx inputs low. 5554f 20 LT5554 APPLICATIONS INFORMATION Gain Step Accuracy LT5554 internal input signal coupling to the transconductance amplifier inputs across the 4dB step attenuator increases with frequency. The gain step error is higher when the LT5554 gain update changes the input attenuator tap (PG5, PG6 transitions) and this error is frequency dependent. Gain error is `compressive', effectively reducing LT5554 gain range. Therefore, it is possible to skip one gain 12 code whenever PG5, PG6 transitions are involved in order to preserve high-frequency monotonic behavior for 0.125dB steps. Linearity and Noise Performance Throughout the Gain Range The LT5554's Noise and Linearity performance across the 16dB gain range at 100MHz with ROUT = 100 and RSADC = 50 is shown in Figures 10 through 13. 24 44 18 39 136 132 12 NF 3 IIP3 (dBc) 6 34 6 29 0 -16 24 128 0 0 -4 -8 -12 ATTENUATION (dB) 124 IIP3 RTI 0 SFDR (dBm/Hz) SFDR NF (dB) RTI AND VONOISE (nV/Hz) VONOISE 9 -4 -8 -12 ATTENUATION (dB) 5554 F10 120 -16 5554 F11 Figure 10. Noise, 140MHz, ROUT = 50 Figure 11. Noise, 140MHz, ROUT = 50 -70 48 -70 46 -74 46 -78 44 42 48 IMD3 (dBc) -78 44 -82 42 -82 40 -16 -86 IMD3 -86 0 -4 -8 -12 ATTENUATION (dB) OIP3 (dBm) OIP3 (dBm) IMD3 (dBc) OIP3 OIP3 -74 IMD3 5554 F12 Figure 12. Linearity, 70MHz, ROUT = 50, 4dBm/Tone 0 -4 -8 -12 ATTENUATION (dB) 40 -16 5554 F12 Figure 13. Linearity, 140MHz, ROUT = 50, 4dBm/Tone 5554f 21 LT5554 APPLICATIONS INFORMATION Balanced differential inputs and outputs are important for achieving excellent second order harmonic distortion (HD2) of the LT5554. When configured in single-ended input and output interfaces, therefore, the single-ended to differential conversion at the input and differential to single-ended conversion at the output will have significant impact on the HD2 performance. Figure 14, for example, shows the desirable singe-ended input and output configuration using external transformers for the single-ended to differential conversion and differential to single-ended conversion. To assure a good HD2 performance, R5 and R6 should also be matched to better VCC = 5V C4 0.1F IN+ T1 1:1 * R5 68.1 * ETC1-1-13 IN- C5 1F LT5554 IN+ T1 1:1 C1 47nF ETC1-1-13 C2 47nF C5 1F T2 TC2-1T OUT- DEC 50 IN- VCCO = 5V LT5554 RO 400 OUT+ R7 134 C3 0.1F * * * 5554 F15 Figure 15. Not Recommended Single-Ended Input and Output Configuration, HD2 = -63dBc at 10dBm, 140MHz The HD2 performance can be further improved by mounting a capacitor from IN+ to ground (a few pF) and a capacitor from OUT- to ground. For narrow band applications, these capacitors cancels to some degree the T1 and T2 imbalance as shown in Figure 15. T2 TC2-1T R6 68.1 RO 400 OUT+ VCC = 5V C4 0.1F VCCO = 5V OUT- DEC 50 When the single-ended input is not converted into well balanced inputs to LT5554, the HD2 performance will be degraded. For instance, when the T1 transformer is improperly rotated by 90 degrees as shown in Figure 15, the imbalance of the differential input signals will result in 14dB degradation in HD2. It is also important to split the differential R7 resistor into two single-ended R5 and R6 resistors at the outputs to reduce the imbalance of the T2 transformer. If not, 3dB degradation in HD2 performance can also be observed. * SECOND ORDER HARMONIC DISTORTION than 1% or use these two resistors with 1% component tolerance. In this case, the HD2 can be as good as -80dBc when the output power is 10dBm at 140MHz. * The LT5554 Noise and Linearity performance throughout the 16dB gain range has an obvious discontinuity at every 4dB gain step. The noise figure is fairly constant from 0dB (Maximum Gain) to -3.875dB attenuation when the gain is decreased by lowering the amplifier transconductance. And then, the NF increases by 4dB when the input attenuator is switched to -4dB attenuation while the amplifier gain is switched back to maximum transconductance. This pattern repeats for each 4dB gain step change. C3 0.1F * * * 5554 F14 For optimum HD2 performance, fully differential input and output interfaces to the LT5554 part are recommended. Figure 14. Recommended Single-Ended Input and Output Configuration, HD2 = -80dBc at 10dBm, 140MHz 5554f 22 LT5554 APPLICATIONS INFORMATION Layout Considerations The transformer board from Figure 16 was used for characterization as a function of ROUT. For each ROUT option, The T2 transformer model and the matching resistors R5, R6 values are given in Table 3. The T2 transformer total matching resistance is RMATCH = RO || (R5 + R6) (part LT5554 internal, and part on board R5 and R6). Attention must be paid to the printed circuit board layout to avoid output pin to input pin signal coupling (external feedback). The evaluation board layout is a good example. The exposed backside pad on the LT5554 package must be soldered to PCB ground plane for thermal considerations. Table 3. Transformer Board ROUT Options Characterization Test Circuits ROUT () The LT5554's typical performance data are on the test circuits shown in Figures 16, 17 and 18 which are simplified schematics of the evaluation board schematic from Figure 21. T2 (Mini-Circuits) 50 75 100 TC2-1T TC3-1T TC4-1W 2 3 4 57.1 92.3 133.3 NLOAD Ratio RLOAD () R5, R6 () 68.1 124 205 GP_BOARD (dB) 13.2 16 17.2 IL(T2) at 200MHz (dB) -0.6 -0.65 -1 J5, 40 PINS SMT-TB 1, 3, 5, 7 9 11 VCC VDEC ENB 13 15 17 R20 10k C4 0.1F J1 50 C8 0.1F PG0 23 IN- R22 10k PG1 RIN 50 * ETC1-1-13 MACOM 21 R21 10k IN+ T1 1:1 * 19 25 27 29 PG0 PG1 PG2 PG3 PG4 PG5 PG6 STROBE R23 10k PG2 R24 10k PG3 R5 68.1 OUT- R25 10k PG4 PG6 C19 4.7F OUTPUT MATCHING OUT+ ROUT = 50 RLOAD 57.1 R6 68.1 2, 4, ...40 VCCO C3 0.1F RO 400 RO 400 33, 35, 37, 38 MODE R26 10k PG5 LT5554 C5 1F 31 VPG C9 0.1F C18 0.1F * * J3 50 * T2 TC2-1T 2:1 5554 F16 VCC = 5V VCCO = 5V Figure 16. Single-Ended Transformer Test Board (Simplified Schematic) 5554f 23 LT5554 APPLICATIONS INFORMATION The LT5554 output power POUT was obtained by adding 3dB for matching-loss and the transformer loss IL(T2) in Table 3 to the board output power at J3 connector. The transformer insertion loss (frequency and temperature dependent) has been included in characterization. Table 4. Balun Board ROUT Options The output power matching is required when LT5554 drives a 50 transmission line as shown on the evaluation board. VCCO (V) ROUT () 25 36 50 71 100 R3, R4 () 0 6.49 15.4 30.1 53.6 R5, R6 () 28.7 28.7 28 28 28 0 1.88 3.66 5.76 8.08 6.29 6.57 6.96 7.61 8.66 ILPAD The differential-output board from Figure 18 was used for ROUT = 50 wide-band characterization of the LT5554 single-ended outputs. When LT5554 drives local (on-board) loads such that an ADC part, output power matching is not required and OIP3 is defined based on POUT, total power at LT5554 open collector outputs. Both Figure 17 and Figure 18 boards VCCO was shifted up with the voltage drop on R5, R6 produced by 45mA output DC current such that OUT+, OUT- DC bias voltage is still 5V. The LT5554 part should be always enabled when VCCO >6V. If disabled, the VCCO will be applied at OUT+, OUT- exceeding the absolute maximum 6V limit with possible LT5554 failure. Figure 17 shows the evaluation board for wide-band characterization at ROUT = 50, where the insertion loss of the output balun is about -1dB at 1GHz. Several ROUT options are given in Table 4 as well as the output padding insertion-loss and required VCCO for 5V on LT5554 outputs. The LT5554 output power at open collector outputs is: POUT = PWR(J3) + IL(T2) + 3dB + ILPAD J5, 40 PINS SMT-TB 1, 3, 5, 7 9 11 VCC VDEC ENB 13 15 17 R20 10k J1 50 21 R21 10k PG0 C4 0.1F 19 23 25 R22 10k PG1 R23 10k PG2 R24 10k PG3 C8 0.1F * RIN 50 * IN- ETC1-1-13 MACOM 29 R25 10k PG4 PG5 R5 28 LT5554 RO 400 R6 28 OUT+ ROUT = 50 33, 35, 37, 38 MODE 2, 4, ...40 VCCO PG6 C9 0.1F C18 0.1F C19 4.7F R3 15.4 OUT- C5 1F 31 VPG R26 10k C3 0.1F IN+ T1 1:1 27 PG0 PG1 PG2 PG3 PG4 PG5 PG6 STROBE J3 50 T2 1:1 50 MATCHING R4 15.4 RLOAD RO 400 57.1 * * ETC1-1-13 5554 F17 VCC = 5V VCCO = 7V Figure 17. Single Ended Test Board (Simplified Schematic) 5554f 24 LT5554 APPLICATIONS INFORMATION J5, 40 PINS SMT-TB 1, 3, 5, 7 9 11 VCC VDEC ENB 13 15 17 R20 10k J1 50 21 R21 10k 23 R22 10k PG1 PG0 C4 0.1F 19 25 27 R23 10k PG2 R24 10k PG3 PG4 C8 0.1F * R5 66.5 LT5554 RO 400 IN- R6 66.5 OUT+ C5 1F ETC1-1-13 MACOM R25 10k 33, 35, 37, 38 MODE 2, 4, ...40 VCCO R26 10k PG5 PG6 C9 0.1F C18 0.1F C19 4.7F J3 50 OUT- RIN 50 * 31 VPG C3 0.1F IN+ T1 1:1 29 PG0 PG1 PG2 PG3 PG4 PG5 PG6 STROBE ROUT = 50 RO 400 RLOAD 57 100 MATCHING C10 47nF J33 50 C12 47nF 5554 F18 VCC = 5V VCCO = 8V ENB = 5V Figure 18. Wideband Differential Output Test Board (Simplified Schematic) Common mode characterization for the LT5554 was performed with input circuit shown in Figure 19. C1 47nF J1 50 25 IN+ 25 25 DEC IN- CDEC 47nF OUT- - LT5554 + OUT+ 5554 F19 Figure 19. Common Mode Input Interface Timing characterization and AC-coupled gain control inputs are tested on evaluation board. The required circuit modifications are shown in the Figure 20 simplified schematic and detailed below for PG6 (8dB step). The PG6 pulse source is applied at J6 connector and 50 terminated by R16 and R33 resistors. C66 decouple R33 to ground while C16 provides DC-decoupling between referenced to ground pulse source and the PG6 DC-voltage. A supply connected to PG6 turret will set the PG6 DC-voltage in 0V to 5V range. All other (untested) PGx DC-voltage can be independently be applied at VPG turret decoupled by C88. Strobe-mode operation is tested with a pulse source applied at J7 connector as shown in Figure 20. Applying similar modifications around J2 and J4 connectors shown in Figure 21, other PGx inputs can be evaluated. As described in Table 1 and Table 2, the MODE pin will select the desired state. 5554f 25 LT5554 APPLICATIONS INFORMATION R22 10k R21 10k R23 10k PG1 PG2 PG4 PG3 R28 0 R29 0 32 R8 0 1 2 3 30 29 R31 0 28 27 25 GND GND GND ENB DEC GND IN+ - 8 26 PG4 VCC 5 7 C4 0.1F GND 4 6 LT5554 IN 24 21 + 20 DEC GND GND MODE GND VCC ENABLE 22 OUT - OUT VCC 23 19 18 17 C8 0.1F PG5 GND PG6 PG0 GND STROBE GND GND C5 1F R16 100 31 R30 0 PG1 GND PG2 PG3 GND VDEC VPG C88 47nF R24 10k 9 C16 47nF 10 R32 0 11 12 R33 100 13 14 15 R27 R34 0 100 C17 47nF 16 MODE C6 47nF R17 100 J6 J7 PG5 R25 10k PG6 C27 47nF PG0 C28 47nF R26 10k R20 10k 5554 F20 STROBE Figure 20. Timing Test for PG6 and STROBE (Simplified Schematic) Evaluation Board Figure 21 shows the schematic of the LT5554 evaluation board. Transformer T2 is TC2-1T and resistor R5 + R6 = 134 (ROUT = 50 GP(J3) = 13.2dB). The silkscreen and layout are shown in Figures 22 through Figure 27. The board control J5 edge connector (40PINS SMT-TB) allows easy access to LT5554 component pins. Alternatively or combined with J5, 14 test points (turrets) for signals and two for GND are also available. The board is powered with a single supply in 4.75V to 5.25V at VCC and VCCO (either J5 connector or turrets). Connecting the ENABLE pin to VCC supply enables the LT5554 part. PGx gain control and STROBE inputs will have TTL levels (DC-coupled) when MODE = 5V (same power supply). To set LT5554 for maximum gain (GMAX) in transparent-mode, all seven PGx and STROBE can be connected to 5V supply. Alternatively, a 2.2V power supply at VPG pin and STROBE turret will set same GMAX state. J1 (input) and J3 (output) are the default board signal ports for evaluation with 50 single ended test system. For differential evaluation, the board J11 and J33 connectors must be reconfigured. 5554f 26 LT5554 APPLICATIONS INFORMATION 2 4 6 8 10 12 14 VCC VCC VCC VCC VDEC ENB 1 3 5 7 9 11 16 20 22 24 26 28 30 32 34 PG0 PG1 PG2 PG3 PG4 PG5 PG6 STROBE VPG MODE 13 VDEC ENB 18 15 17 19 21 23 25 27 29 31 36 35 C11 47nF R20 10k C14 47nF R31 0 R28 0 NOT MOUNTED J4 PG2 PG3 NOT MOUNTED C12 47nF NOT MOUNTED R12 NOT MOUNTED R8 0 VDEC NOT MOUNTED T1 1:1 26 PG4 24 OUT- 21 5 IN- OUT+ 20 GND MODE GND VCC 10 11 12 13 14 15 ENABLE R33 0 C16 47nF NOT MOUNTED R27 0 PG6 PG0 R34 0 STROBE C17 47nF C25 0.1F R3 0 PG5 PG6 C27 0.1F C26 0.1F T2 - TC2-1T OUT 2:1 * * R7 NC OUT+ 18 MODE C6 47nF 17 C8 0.1F R4 0 J33 MINICIRCUITS R6 681 C9 0.1F J3 * 19 16 NOT MOUNTED NOT MOUNTED PG4 R26 10k R5 68.1 22 PG5 GND PG6 PG0 GND STROBE GND GND 9 C24 0.1F R25 10k C19 4.7F VCC 23 IN+ GND C23 0.1F PG3 C3 0.1F C4 VCC DEC C22 0.1F PG2 R24 10k VCCO GND GND GND LT5554 PG1 R23 10k C21 THROUGH C27 ARE NOT MOUNTED 25 4 C5 1F NOT MOUNTED 27 ENB 8 R16 28 GND 7 NOT MOUNTED 29 DEC 6 ETC1-1-13 MACOM 30 R22 10k R14 GND 3 * 31 PG0 NOT MOUNTED NOT MOUNTED PG1 GND PG2 PG3 GND 1 2 R1 0 C13 47nF R21 10k C21 0.1F NOT MOUNTED R30 0 R29 0 32 J11 39 VPG PG4 J2 IN- 37 VCCO NOT MOUNTED * J5, 40 PINS SMT-TB PG0 PG1 PG2 PG3 PG4 PG5 PG6 STROBE VPG MODE PG1 IN+ 40 VCCO VCCO VCCO VCCO 33 VCC J1 38 C18 0.1F R2 0 NOT MOUNTED 5554 F21 R17 NOT MOUNTED NOT MOUNTED J7 J6 C15 47nF R32 0 PG5 Figure 21. Evaluation Circuit Schematic 5554f 27 LT5554 APPLICATIONS INFORMATION Figure 22. Top Side Figure 23. Inner Layer 2 GND 5554f 28 LT5554 APPLICATIONS INFORMATION Figure 24. Inner Layer 3 Power Figure 25. Bottom Side 5554f 29 LT5554 APPLICATIONS INFORMATION Figure 26. Silkscreen Top Figure 27. Silkscreen Bottom 5554f 30 LT5554 PACKAGE DESCRIPTION UH Package 32-Lead Plastic QFN (5mm x 5mm) (Reference LTC DWG # 05-08-1693 Rev D) 0.70 0.05 5.50 0.05 4.10 0.05 3.50 REF (4 SIDES) 3.45 0.05 3.45 0.05 PACKAGE OUTLINE 0.25 0.05 0.50 BSC RECOMMENDED SOLDER PAD LAYOUT APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 5.00 0.10 (4 SIDES) BOTTOM VIEW--EXPOSED PAD 0.75 0.05 R = 0.05 TYP 0.00 - 0.05 PIN 1 NOTCH R = 0.30 TYP OR 0.35 x 45 CHAMFER R = 0.115 TYP 31 32 0.40 0.10 PIN 1 TOP MARK (NOTE 6) 1 2 3.50 REF (4-SIDES) 3.45 0.10 3.45 0.10 (UH32) QFN 0406 REV D 0.200 REF NOTE: 1. DRAWING PROPOSED TO BE A JEDEC PACKAGE OUTLINE M0-220 VARIATION WHHD-(X) (TO BE APPROVED) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 0.25 0.05 0.50 BSC 5554f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 31 LT5554 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS Infrastructure LT5514 Ultralow Distortion, IF Amplifier/ADC Driver with Digitally Controlled Gain 850MHz Bandwidth, 47 dBm OIP3 at 100MHz, 10.5dB to 33dB Gain Control Range LT5517 40MHz to 900MHz Quadrature Demodulator 21dBm IIP3, Integrated LO Quadrature Generator LT5518 1.5GHz to 2.4GHz High Linearity Direct Quadrature Modulator 22.8dBm OIP3 at 2GHz, -158.2dBm/Hz Noise Floor, 50 Single-Ended RF and LO Ports, 4-Channel W-CDMA ACPR = -64dBc at 2.14GHz LT5519 0.7GHz to 1.4GHz High Linearity Upconverting Mixer 17.1dBm IIP3 at 1GHz, Integrated RF Output Transformer with 50 Matching, Single-Ended LO and RF Ports Operation LT5520 1.3GHz to 2.3GHz High Linearity Upconverting Mixer 15.9dBm IIP3 at 1.9GHz, Integrated RF Output Transformer with 50 Matching, Single-Ended LO and RF Ports Operation LT5521 10MHz to 3700MHz High Linearity Upconverting Mixer 24.2dBm IIP3 at 1.95GHz, NF = 12.5dB, 3.15V to 5.25V Supply, Single-Ended LO Port Operation LT5522 600 MHz to 2.7GHz High Signal Level Downconverting Mixer 4.5V to 5.25V Supply, 25dBm IIP3 at 900MHz, NF = 12.5dB, 50 Single-Ended RF and LO Ports LT5524 Low Power, Low Distortion ADC Driver with Digitally Programmable Gain 450MHz Bandwidth, 40dBm OIP3, 4.5dB to 27dB Gain Control LT5525 High Linearity, Low Power Downconverting Mixer Single-Ended 50 RF and LO Ports, 17.6dBm IIP3 at 1900MHz, ICC = 28A LT5526 High Linearity, Low Power Downconverting Mixer 3V to 5.3V Supply, 16.5dBm IIP3, 100kHz to 2GHz RF, NF = 11dB, ICC = 28mA, -65dBm LO-RF Leakage LT5527 400MHz to 3.7GHz High Signal Level Downconverting Mixer IIP3 = 23.5dBm and NF = 12.5dBm at 1900MHz, 4.5V to 5.25V Supply, ICC = 78mA, Conversion Gain = 2dB LT5528 1.5GHz to 2.4GHz High Linearity Direct Quadrature Modulator 21.8dBm OIP3 at 2GHz, -159.3dBm/Hz Noise Floor, 50, 0.5VDC Baseband Interface, 4-Channel W-CDMA ACPR = -66dBc at 2.14GHz LT5557 400MHz to 3.8GHz, 3.3V High Signal Level Downconverting Mixer IIP3 = 23.7dBm at 2600MHz, 23.5dBm at 3600MHz, ICC = 82A at 3.3V LT5560 Ultra-Low Power Active Mixer 10mA Supply Current, 10dBm IIP3, 10dB NF, Usable as Up- or Down-Converter. LT5568 700MHz to 1050MHz High Linearity Direct Quadrature Modulator 22.9dBm OIP3 at 850MHz, -160.3dBm/Hz Noise Floor, 50, 0.5VDC Baseband Interface, 3-Ch CDMA2000 ACPR = -71.4dBc at 850MHz LT5572 1.5GHz to 2.5GHz High Linearity Direct Quadrature Modulator 21.6dBm OIP3 at 2GHz, -158.6dBm/Hz Noise Floor, High-Ohmic 0.5VDC Baseband Interface, 4-Ch W-CDMA ACPR = -67.7dBc at 2.14GHz LT5575 800MHz to 2.7GHz High Linearity Direct Conversion I/Q Demodulator 50, Single-Ended RF and LO Inputs. 28dBm IIP3 at 900MHz, 13.2dBm P1dB, 0.04dB I/Q Gain Mismatch, 0.4 I/Q Phase Mismatch LT5579 1.5GHz to 3.8GHz High Linearity Upconverting Mixer 27.3dBm OIP3 at 2.14GHz, 9.9dB Noise Floor, 2.6dB Conversion Gain, -35dBm LO Leakage RF Power Detectors LTC(R)5505 RF Power Detectors with >40dB Dynamic Range LTC5507 100kHz to 1000MHz RF Power Detector 100kHz to 1GHz, Temperature Compensated, 2.7 to 6V Supply LTC5508 300MHz to 7GHz RF Power Detector 44dB Dynamic Range, Temperature Compensated, SC70 Package LTC5509 300MHz to 3GHz RF Power Detector 36dB Dynamic Range, Low Power Consumption, SC70 Package LTC5530 300MHz to 7GHz Precision RF Power Detector Precision VOUT Offset Control, Shutdown, Adjustable Gain LTC5531 300MHz to 7GHz Precision RF Power Detector Precision VOUT Offset Control, Shutdown, Adjustable Offset LTC5532 300MHz to 7GHz Precision RF Power Detector Precision VOUT Offset Control, Adjustable Gain and Offset LT5534 50MHz to 3GHz Log RF Power Detector with 60dB Dynamic Range 1dB Output Variation over Temperature, 38ns Response Time, Log Linear Response LTC5536 Precision 600Mhz to 7GHz RF Power Detector with Fast Comparator Output 25ns Response Time, Comparator Reference Input, Latch Enable Input, -26dBm to 12dBm Input Range LT5537 Wide Dynamic Range Log RF/IF Detector Low Frequency to 1GHz, 83dB Log Linear Dynamic Range LT5538 3.8GHz Wide Dynamic Range Log Detector 75dB Dynamic Range, 1dB Output Variation Over Temperature LT5570 2.7GHz RMS Power Detector Fast Responding, up to 60dB Dynamic Range, 0.3dB Accuracy Over Temperature 300MHz to 3GHz, Temperature Compensated, 2.7V to 6V Supply 5554f 32 Linear Technology Corporation LT 0708 * PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 FAX: (408) 434-0507 www.linear.com (c) LINEAR TECHNOLOGY CORPORATION 2008