Low Skew, 1-to-2 Differential-to-LVCMOS/LVTTL Fanout Buffer GENERAL DESCRIPTION FEATURES The 83026I-01 is a low skew, 1-to-2 Differential-to-LVCMOS/LVTTL Fanout Buffer. The differential input can accept most differential signal types (LVPECL, LVDS, LVHSTL, HCSL and SSTL) and translate to two single-ended LVCMOS/LVTTL outputs. The small 8-lead SOIC footprint makes this device ideal for use in applications with limited board space. * Two LVCMOS / LVTTL outputs 83026I-01 Data Sheet * Differential CLK, nCLK input pair * CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL * Maximum output frequency: 350MHz * Output skew: 15ps (maximum) * Part-to-part skew: 600ps (maximum) * Additive phase jitter, RMS: 0.03ps (typical) * Small 8 lead SOIC package saves board space * 3.3V core, 3.3V, 2.5V or 1.8V output operating supply * -40C to 85C ambient operating temperature * Available in lead-free RoHS (6) package BLOCK DIAGRAM PIN ASSIGNMENT VDD CLK nCLK OE Q0 CLK nCLK 1 2 3 4 8 7 6 5 VDDO Q0 Q1 GND 83026I-01 Q1 8-Lead SOIC 3.8mm x 4.8mm, x 1.47mm package body M Package Top View OE VDD CLK nCLK OE 1 2 3 4 8 7 6 5 VDDO Q0 Q1 GND 83026I-01 8-Lead TSSOP 4.40mm x 3.0mm x 0.925mm package body G Package Top View (c)2015 Integrated Device Technology, Inc 1 December 15, 2015 83026I-01 Data Sheet TABLE 1. PIN DESCRIPTIONS Number Name Type Description 1 VDD Power 2 CLK Input 3 nCLK Input 4 OE Input 5 GND Power Power supply ground. 6 Q1 Output Clock output. LVCMOS / LVTTL interface levels. 7 Q0 Output Clock output. LVCMOS / LVTTL interface levels. 8 VDDO Power Output supply pin. Positive supply pin. Pulldown Non-inverting differential clock input. Pullup/ Inverting differential clock input. VDD/2 default when left floating. Pulldown Output enable. When HIGH, outputs are enabled. When LOW, outputs are in Pullup High Impedance State. LVCMOS / LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN Input Capacitance CPD Power Dissipation Capacitance (per output) RPULLUP Input Pullup Resistor RPULLDOWN Input Pulldown Resistor Test Conditions Minimum Typical Maximum Units VDD, VDDO = 3.465V 17 pF VDD = 3.465V, VDDO = 2.625V 16 pF 4 VDD = 3.465V, VDDO = 1.95V Output Impedance ROUT pF 15 pF 51 k 51 k VDD, VDDO = 3.3V 7 VDD = 3.3V, VDDO = 2.5V 8 VDD = 3.3V, VDDO = 1.8V 10 TABLE 3. CONTROL FUNCTION TABLE Input Outputs OE Q0, Q1 0 HiZ 1 Active (c)2015 Integrated Device Technology, Inc 2 December 15, 2015 83026I-01 Data Sheet ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5 V Outputs, VO -0.5V to VDDO + 0.5V NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Package Thermal Impedance, JA 8 Lead SOIC 112.7C/W (0 lfpm) 8 Lead TSSOP 101.7C/W (0 lfpm) Storage Temperature, TSTG -65C to 150C TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V 5%, VDDO = 1.71V TO 3.465V, TA = -40C TO 85C Symbol Parameter VDD Positive Supply Voltage VDDO Test Conditions Minimum Typical Maximum Units 3.135 3.3 3.465 V 3.135 3.3 3.465 V 2.375 2.5 2.625 V 1.71 1.8 1.89 V Output Supply Voltage IDD Power Supply Current 10 mA IDDO Output Supply Current 3 mA TABLE 3B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = 3.3V 5%, VDDO = 2.375V TO 3.465V, TA = -40C TO 85C Symbol Parameter Test Conditions VIH Input High Voltage OE VIL Input Low Voltage OE IIH Input High Current OE VDD = VIN = 3.465V IIL Input Low Current OE VDD = 3.465V, VIN = 0V -150 A VDDO = 3.135V 2.6 V VDDO = 2.375V 1.8 VOH Output High Voltage; NOTE 1 VOL Output Low Voltage; NOTE 1 Minimum Typical Maximum Units 2 VDD + 0.3 V -0.3 0.8 V 5 A V 0.5 V NOTE 1: Outputs terminated with 50 to VDDO/2. See Parameter Measurement Information section, "Output Load Test Circuit" diagrams. TABLE 3C. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = 3.3V 5%, VDDO = 1.8V 5%, TA = -40C TO 85C Symbol Parameter Test Conditions VIH Input High Voltage OE VIL Input Low Voltage OE Minimum Typical Maximum Units 2 VDD + 0.3 V -0.3 0.8 V IIH Input High Current OE VDD = VIN = 3.465V IIL Input Low Current OE VDD = 3.465V, VIN = 0V -150 A VOH Output High Voltage IOH = -100A VDDO - 0.2 V IOH = -2mA VDDO - 0.45 VOL Output Low Voltage (c)2015 Integrated Device Technology, Inc 5 A V IOL = 100A 0.2 V IOL = 2mA 0.45 V 3 December 15, 2015 83026I-01 Data Sheet TABLE 3D. DIFFERENTIAL DC CHARACTERISTICS, VDD = 3.3V 5%, VDDO = 1.71V TO 3.465V, TA = -40C TO 85C Symbol Parameter Test Conditions IIH Input High Current IIL Input Low Current VPP Peak-to-Peak Input Voltage; NOTE 1 VCMR Common Mode Input Voltage; NOTE 2, 3 Minimum Typical Maximum Units nCLK VIN = VDD = 3.465V 150 A CLK VIN = VDD = 3.465V 150 A nCLK VIN = 0V, VDD = 3.465V -150 A CLK VIN = 0V, VDD = 3.465V -5 A 0.15 1.3 V GND + 0.5 VDD - 0.85 V NOTE 1: VPP can exceed 1.3V provided that there is sufficient offset level to keep VIL > 0V. NOTE 2: For single ended applications, the maximum input voltage for CLK, nCLK is VDD + 0.3V. NOTE 3: Common mode voltage is defined as VIH. TABLE 4A. AC CHARACTERISTICS, VDD = 3.3V 5%, VDDO = 3.3V 5%, TA = -40C TO 85C Symbol Parameter fMAX Output Frequency tPD Propagation Delay; NOTE 1 2.5 ns tsk(o) Output Skew; NOTE 2, 4 15 ps tsk(pp) Part-to-Part Skew; NOTE 3, 4 900 ps tjit Buffer Additive Phase Jitter, RMS, refer to Additive Phase Jitter Section tR / t F Output Rise/Fall Time odc Output Duty Cycle Test Conditions 350MHz Minimum 1.3 Typical 1.9 Maximum Units 350 MHz 0.03 ps 20% to 80% 150 800 ps 66MHz 48 52 % 67MHz 166MHz 45 55 % 167MHz 350MHz 40 60 % NOTE 1: Measured from the differential input crossing point to VDDO/2 of the output. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2. NOTE 4: This parameter is defined in accordance with JEDEC Standard 6. (c)2015 Integrated Device Technology, Inc 4 December 15, 2015 83026I-01 Data Sheet TABLE 4B. AC CHARACTERISTICS, VDD = 3.3V 5%, VDDO = 2.5V 5%, TA = -40C TO 85C Symbol Parameter fMAX Output Frequency tPD Propagation Delay; NOTE 1 tsk(o) tsk(pp) tjit Buffer Additive Phase Jitter, RMS, refer to Additive Phase Jitter Section t R / tF Output Rise/Fall Time odc Maximum Units 350 MHz 2.6 ns Output Skew; NOTE 2, 4 15 ps Part-to-Part Skew; NOTE 3, 4 750 ps Output Duty Cycle Test Conditions 350MHz Minimum 1.5 Typical 2.0 0.03 ps 20% to 80% 150 800 ps 66MHz 48 52 % 67MHz 166MHz 46 54 % 167MHz 350MHz 40 60 % NOTE 1: Measured from the differential input crossing point to VDDO/2 of the output. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. TABLE 4C. AC CHARACTERISTICS, VDD = 3.3V 5%, VDDO = 1.8V 5%, TA = -40C TO 85C Symbol Parameter fMAX Output Frequency tPD Propagation Delay; NOTE 1 tsk(o) tsk(pp) tjit Buffer Additive Phase Jitter, RMS, refer to Additive Phase Jitter Section t R / tF Output Rise/Fall Time odc Maximum Units 350 MHz 3.1 ns Output Skew; NOTE 2, 4 15 ps Part-to-Part Skew; NOTE 3, 4 600 ps Output Duty Cycle Test Conditions 350MHz Minimum 1.9 Typical 2.5 0.03 ps 20% to 80% 200 900 ps 66MHz 48 52 % 67MHz 166MHz 43 57 % 167MHz 350MHz 40 60 % NOTE 1: Measured from the differential input crossing point to VDDO/2 of the output. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. (c)2015 Integrated Device Technology, Inc 5 December 15, 2015 83026I-01 Data Sheet ADDITIVE PHASE JITTER 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot. The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in the 0 -10 Input/Output Additive Phase Jitter at 155.52MHz -20 = 0.03ps typical -30 -40 -50 SSB PHASE NOISE dBc/HZ -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 1k 10k 100k 1M 10M 100M OFFSET FROM CARRIER FREQUENCY (HZ) device meets the noise floor of what is shown, but can actually be lower. The phase noise is dependant on the input source and measurement equipment. As with most timing specifications, phase noise measurements have issues. The primary issue relates to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. This is illustrated above. The (c)2015 Integrated Device Technology, Inc 6 December 15, 2015 83026I-01 Data Sheet PARAMETER MEASUREMENT INFORMATION 3.3VCORE/3.3V OUTPUT LOAD AC TEST CIRCUIT 3.3VCORE/2.5V OUTPUT LOAD AC TEST CIRCUIT 3.3VCORE/1.8V OUTPUT LOAD AC TEST CIRCUIT DIFFERENTIAL INPUT LEVEL OUTPUT SKEW PART-TO-PART SKEW (c)2015 Integrated Device Technology, Inc 7 December 15, 2015 83026I-01 Data Sheet PROPAGATION DELAY OUTPUT RISE/FALL TIME OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD (c)2015 Integrated Device Technology, Inc 8 December 15, 2015 83026I-01 Data Sheet APPLICATION INFORMATION WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT RECOMMENDATIONS FOR UNUSED OUTPUT PINS OUTPUTS: LVCMOS OUTPUTS All unused LVCMOS output can be left floating. We recommend that there is no trace attached. (c)2015 Integrated Device Technology, Inc 9 December 15, 2015 83026I-01 Data Sheet DIFFERENTIAL CLOCK INPUT INTERFACE The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 2A to 2E show interface examples for the CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 2A, the input termination applies for LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation. 3.3V 3.3V 3.3V 1.8V Zo = 50 Ohm CLK Zo = 50 Ohm CLK Zo = 50 Ohm nCLK Zo = 50 Ohm LVPECL nCLK HiPerClockS Input LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R1 50 HiPerClockS Input R2 50 R2 50 R3 50 FIGURE 2A. CLK/nCLK INPUT DRIVEN BY LVHSTL DRIVER FIGURE 2B. CLK/nCLK INPUT DRIVEN BY 3.3V LVPECL DRIVER 3.3V 3.3V 3.3V 3.3V R3 125 3.3V R4 125 Zo = 50 Ohm Zo = 50 Ohm LVDS_Driv er CLK CLK R1 100 Zo = 50 Ohm nCLK LVPECL R1 84 FIGURE 2C. HiPerClockS Input nCLK Receiv er Zo = 50 Ohm R2 84 CLK/nCLK INPUT DRIVEN BY 3.3V LVPECL DRIVER FIGURE 2D. CLK/nCLK INPUT DRIVEN BY 3.3V LVDS DRIVER 3.3V 3.3V 3.3V LVPECL Zo = 50 Ohm C1 Zo = 50 Ohm C2 R3 125 R4 125 CLK nCLK R5 100 - 200 R6 100 - 200 R1 84 HiPerClockS Input R2 84 R5,R6 locate near the driver pin. FIGURE 2E. CLK/nCLK INPUT DRIVEN BY 3.3V LVPECL DRIVER WITH AC COUPLE (c)2015 Integrated Device Technology, Inc 10 December 15, 2015 83026I-01 Data Sheet SCHEMATIC EXAMPLE Figure 3 shows an application schematic example of 83026I-01. The 83026I-01 CLK/nCLK input can directly accepts various types of differential signal. In this example, the input is driven by an LVDS driver. The 83026I-01 outputs are LVCMOS drivers. In this example, series termination approach is shown. Additional termination approaches are shown in the LVCMOS Termination Application Note. VDD 3.3V R3 1K Zo = 50 Ohm VDD R4 100 1 2 3 4 VDD CLK nCLK OE VDDO Q0 Q1 GND VDDO 8 7 6 5 R1 43 Zo = 50 Ohm LVCMOS C2 0.1u LVDS U1 ICS83026I-01 C1 0.1u Zo = 50 Ohm Zo = 50 Ohm VDD=3.3V R2 43 VDDO= 3.3V, 2.5V or 1.8V LVCMOS FIGURE 3. 83026I-01 SCHEMATIC EXAMPLE RELIABILITY INFORMATION TABLE 5A. JAVS. AIR FLOW TABLE FOR 8 LEAD SOIC JA by Velocity (Linear Feet per Minute) 0 Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 153.3C/W 112.7C/W 200 500 128.5C/W 103.3C/W 115.5C/W 97.1C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TABLE5B. JAVS. AIR FLOW TABLE FOR 8 LEAD TSSOP JA by Velocity (Linear Feet per Minute) Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 101.7C/W 90.5C/W 89.8C/W TRANSISTOR COUNT The transistor count for ICS83026I-0I is: 260 (c)2015 Integrated Device Technology, Inc 11 December 15, 2015 83026I-01 Data Sheet PACKAGE OUTLINE - SUFFIX M FOR 8 LEAD SOIC PACKAGE OUTLINE - G SUFFIX FOR 8 LEAD TSSOP TABLE 6A. PACKAGE DIMENSIONS SYMBOL TABLE 6B. PACKAGE DIMENSIONS Millimeters MINIMUM N SYMBOL MAXIMUM 8 Millimeters Minimum N Maximum 8 A 1.35 1.75 A -- 1.20 A1 0.10 0.25 A1 0.05 0.15 B 0.33 0.51 A2 0.80 1.05 C 0.19 0.25 b 0.19 0.30 D 4.80 5.00 c 0.09 0.20 E 3.80 4.00 D 2.90 3.10 e 1.27 BASIC E 6.40 BASIC H 5.80 6.20 E1 h 0.25 0.50 e L 0.40 1.27 L 0.45 0.75 0 8 0 8 aaa -- 0.10 Reference Document: JEDEC Publication 95, MS-012 4.30 4.50 0.65 BASIC Reference Document: JEDEC Publication 95, MO-153 (c)2015 Integrated Device Technology, Inc 12 December 15, 2015 83026I-01 Data Sheet TABLE 7. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature 83026BMI-01LF 026BI01L 8 lead "Lead Free" SOIC Tube -40C to +85C 83026BMI-01LFT 026BI01L 8 lead "Lead Free" SOIC Tape and Reel -40C to +85C 83026BGI-01LF BI01L 8 lead "Lead Free" TSSOP Tube -40C to +85C 83026BGI-01LFT BI01L 8 lead "Lead Free" TSSOP Tape and Reel -40C to +85C (c)2015 Integrated Device Technology, Inc 13 December 15, 2015 83026I-01 Data Sheet REVISION HISTORY SHEET Rev Table T7 A A A A T3C T7 Page Description of Change Date 1 3 11 12 13 Added 8 Lead TSSOP package to Pin Assignment. Absolute Maximum Ratings - added 8 Lead TSSOP to Package Thermal Impedance. Added 8 Lead TSSOP Reliability Information table. Added 8 Lead TSSOP Package Outline and Package Dimensions. Ordering Information Table - added 8 Lead TSSOP ordering information. 6/25/04 6 Additive Phase Jitter - corrected X axis on plot. 8/2/05 3 LVCMOS DC Characteristics - corrected Test Conditions for IIH and IIL. 8/12/05 1 9 13 Features Section - added lead-free bullet Added Recommendations for Unused Output Pins. Ordering Information Table - added lead-free part number, marking, and note. 1/16/06 Ordering Information Table - added lead-free marking 10/22/07 A T7 13 A T7 13 15 A T7 1 13 Updated datasheet's header/footer with IDT from ICS. Removed ICS prefix from Part/Order Number column. Added Contact Page. Removed the ICS prefix on part numbers. Features Section - removed reference to leaded packages. Ordering Information - removed 2500 from Tape and Reel. Removed LF note below the table. Updated datasheet header and footer (c)2015 Integrated Device Technology, Inc 14 8/4/10 12/15/15 December 15, 2015 83026I-01 Data Sheet Corporate Headquarters 6024 Silver Creek Valley Road San Jose, CA 95138 USA www.IDT.com Sales 1-800-345-7015 or 408-284-8200 Fax: 408-284-2775 www.IDT.com/go/sales Tech Support www.idt.com/go/support DISCLAIMER Integrated Device Technology, Inc. (IDT) reserves the right to modify the products and/or specifications described herein at any time, without notice, at IDT's sole discretion. Performance specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. 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