TPS2030−Q1, TPS2031−Q1, TPS2032−Q1, TPS2033−Q1, TPS2034−Q1
POWER-DISTRIBUTION SWITCHES
SGLS298B − SEPTEMBER 2005 − REVISED JUNE 2008
1
TI.COM
DQualified for Automotive Applications
D33-mΩ (5-V Input) High-Side MOSFET
Switch
DShort-Circuit and Thermal Protection
DOvercurrent Logic Output
DOperating Range . . . 2.7 V to 5.5 V
DLogic-Level Enable Input
DTypical Rise Time . . . 6.1 ms
DUndervoltage Lockout
DMaximum Standby Supply
Current ...10 µA
DNo Drain-Source Back-Gate Diode
DAvailable in 8-pin SOIC Package
DAmbient Temperature Range, −40°C to 85°C
D2-kV Human-Body-Model, 200-V
Machine-Model ESD Protection
DUL Listed − File No. E169910
description
The TPS203x family of power distribution switches is intended for applications where heavy capacitive loads
and short circuits are likely to be encountered. These devices are 50-mΩ N-channel MOSFET high-side power
switches. The switch is controlled by a logic enable compatible with 5-V logic and 3-V logic. Gate drive is
provided by an internal charge pump designed to control the power-switch rise times and fall times to minimize
current surges during switching. The charge pump requires no external components and allows operation from
supplies as low as 2.7 V.
When the output load exceeds the current-limit threshold or a short is present, the TPS203x limits the output
current to a safe level by switching into a constant-current mode, pulling the overcurrent (OC) logic output low.
When continuous heavy overloads and short circuits increase the power dissipation in the switch, causing the
junction temperature to rise, a thermal protection circuit shuts off the switch to prevent damage. Recovery from
a thermal shutdown is automatic once the device has cooled sufficiently. Internal circuitry ensures the switch
remains off until valid input voltage is present.
The TPS203x devices differ only in short-circuit current threshold. The TPS2030 limits at 0.3-A load, the
TPS2031 at 0.9-A load, the TPS2032 at 1.5-A load, the TPS2033 at 2.2-A load, and the TPS2034 at 3-A load
(see Available Options). The TPS203x is available in an 8-pin small-outline integrated-circuit (SOIC) package
and in an 8-pin dual in-line (DIP) package and operates over a junction temperature range of − 40°C to 125°C.
TPS201xA
TPS202x
TPS203x
33 mΩ, single 0.2 A − 2 A
0.2 A − 2 A
0.2 A − 2 A
TPS2014
TPS2015
TPS2041
TPS2051
TPS2045
TPS2055
80 mΩ, single 600 mA
1 A
500 mA
500 mA
250 mA
250 mA
GENERAL SWITCH CATALOG
TPS2042
TPS2052
TPS2046
TPS2056
80 mΩ, dual 500 mA
500 mA
250 mA
250 mA
TPS2100/1
260 mΩ
IN1 500 mA
IN2 10 mA
OUT
IN1
IN2 TPS2102/3/4/5
IN1 500 mA
IN2 100 mA
1.3 Ω
TPS2043
TPS2053
TPS2047
TPS2057
80 mΩ, triple
500 mA
500 mA
250 mA
250 mA
TPS2044
TPS2054
TPS2048
TPS2058
80 mΩ, quad
500 mA
500 mA
250 mA
250 mA
Copyright 2008 Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
2
3
4
8
7
6
5
GND
IN
IN
EN
OUT
OUT
OUT
OC
D PACKAGE
(TOP VIEW)
TPS2030−Q1, TPS2031−Q1, TPS2032−Q1, TPS2033−Q1, TPS2034−Q1
POWER-DISTRIBUTION SWITCHES
SGLS298B − SEPTEMBER 2005 − REVISED JUNE 2008
2TI.COM
AVAILABLE OPTIONS{
RECOMMENDED
MAXIMUM CONTINUOUS
TYPICAL SHORT-CIRCUIT PACKAGED DEVICES}
TAENABLE MAXIMUM CONTINUOUS
LOAD CURRENT
(A)
TYPICAL
SHORT-CIRCUIT
CURRENT LIMIT AT 25°C
(A)
SMALL OUTLINE
(D)§
0.2 0.3 TPS2030IDRQ1
0.6 0.9 TPS2031IDRQ1
−40°C to 85°CActive high 1 1.5 TPS2032IDRQ1
40 C
to
85 C
Active
high
1.5 2.2 TPS2033IDRQ1
2 3 TPS2034IDRQ1
†For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at http://www.ti.com.
‡Package drawings, thermal data, and symbolization are available at http://www.ti.com/packaging.
§The D package is available taped and reeled. Add an R suffix to device type (e.g., TPS2030IDRQ1)
Product Preview
TPS2030 functional block diagram
OUT
OC
IN
EN
GND
Current
Limit
Driver
UVLO
Charge
Pump
CS
Thermal
Sense
Power Switch
†
†Current Sense
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME NO. I/O DESCRIPTION
EN 4 I Enable input. Logic high turns on power switch.
GND 1 I Ground
IN 2, 3 IInput voltage
OC 5 O Overcurrent. Logic output active low
OUT 6, 7, 8 OPower-switch output
TPS2030−Q1, TPS2031−Q1, TPS2032−Q1, TPS2033−Q1, TPS2034−Q1
POWER-DISTRIBUTION SWITCHES
SGLS298B − SEPTEMBER 2005 − REVISED JUNE 2008
3
TI.COM
detailed description
power switch
The power switch is an N-channel MOSFET with a maximum on-state resistance of 50 mΩ (VI(IN) = 5 V).
Configured as a high-side switch, the power switch prevents current flow from OUT to IN and IN to OUT when
disabled.
charge pump
An internal charge pump supplies power to the driver circuit and provides the necessary voltage to pull the gate
of the MOSFET above the source. The charge pump operates from input voltages as low as 2.7 V and requires
very little supply current.
driver
The driver controls the gate voltage of the power switch. To limit large current surges and reduce the associated
electromagnetic interference (EMI) produced, the driver incorporates circuitry that controls the rise times and
fall times of the output voltage. The rise and fall times are typically in the 2-ms to 9-ms range.
enable (EN)
The logic enable disables the power switch, the bias for the charge pump, driver, and other circuitry to reduce
the supply current to less than 10 µA when a logic low is present on EN . A logic high input on EN restores bias
to the drive and control circuits and turns the power on. The enable input is compatible with both TTL and CMOS
logic levels.
overcurrent (OC)
The OC open drain output is asserted (active low) when an overcurrent or overtemperature condition is
encountered. The output remains asserted until the overcurrent or overtemperature condition is removed.
current sense
A sense FET monitors the current supplied to the load. The sense FET measures current more efficiently than
conventional resistance methods. When an overload or short circuit is encountered, the current-sense circuitry
sends a control signal to the driver. The driver, in turn, reduces the gate voltage and drives the power FET into
its saturation region, which switches the output into a constant current mode and holds the current constant
while varying the voltage on the load.
thermal sense
An internal thermal-sense circuit shuts off the power switch when the junction temperature rises to
approximately 140°C. Hysteresis is built into the thermal sense circuit. After the device has cooled
approximately 20°C, the switch turns back on. The switch continues to cycle off and on until the fault is removed.
undervoltage lockout
A voltage sense circuit monitors the input voltage. When the input voltage is below approximately 2 V, a control
signal turns off the power switch.
TPS2030−Q1, TPS2031−Q1, TPS2032−Q1, TPS2033−Q1, TPS2034−Q1
POWER-DISTRIBUTION SWITCHES
SGLS298B − SEPTEMBER 2005 − REVISED JUNE 2008
4TI.COM
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Input voltage range, VI(IN) (see Note 1) −0.3 V to 6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, VO(OUT) (see Note 1) −0.3 V to VI(IN) + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range,VI(EN) −0.3 V to 6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, IO(OUT) internally limited. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total power dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating virtual junction temperature range, TJ−40°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature soldering 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . .
Electrostatic discharge (ESD) protection: Human body model 2 kV. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Machine model 200V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Charged device model (CDM) 750 V. . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltages are with respect to GND.
DISSIPATION RATING TABLE
PACKAGE TA ≤ 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
D725 mW 5.8 mW/°C464 mW 377 mW
recommended operating conditions
MIN MAX UNIT
Input voltage
VI(IN) 2.7 5.5 V
Input voltage VI(EN) 0 5.5 V
TPS2030 0 0.2
TPS2031 0 0.6
Continuous output current, IOTPS2032 0 1 A
Continuous
output
current,
IO
TPS2033 0 1.5
A
TPS2034 0 2
Operating virtual junction temperature, TJ−40 125 °C
TPS2030−Q1, TPS2031−Q1, TPS2032−Q1, TPS2033−Q1, TPS2034−Q1
POWER-DISTRIBUTION SWITCHES
SGLS298B − SEPTEMBER 2005 − REVISED JUNE 2008
5
TI.COM
electrical characteristics over recommended operating junction temperature range, VI(IN)= 5.5 V,
IO = rated current, EN = 5 V, TJ = −405C to 1255C (unless otherwise noted)
power switch
PARAMETER TEST CONDITIONS†MIN TYP MAX UNIT
TJ = 25°C, IO = 1.8 A}33 36
VI(IN) = 5 V, TJ = 85°C, IO = 1.8 A}38 46
I(IN)
TJ = 125°C, IO = 1.8 A}44 50
TJ = 25°C, IO = 1.8 A}37 41
VI(IN) = 3.3 V, TJ = 85°C, IO = 1.8 A}43 52
Static drain source on state resistance
I(IN)
TJ = 125°C, IO = 1.8 A}51 61
mΩ
rDS(on) Static drain-source on-state resistance TJ = 25°C, IO = 0.18 A 30 34 mΩ
VI(IN) = 5 V, TJ = 85°C, IO = 0.18 A 35 50
I(IN)
TJ = 125°C, IO = 0.18 A 39 55
TJ = 25°C, IO = 0.18 A 33 37
VI(IN) = 3.3 V, TJ = 85°C, IO = 0.18 A 39 55
I(IN)
TJ = 125°C, IO = 0.18 A 44 66
Rise time output
VI(IN) = 5.5 V,
CL = 1 µF,
TJ = 25°C,
RL = 10 Ω6.1
ms
trRise time, output VI(IN) = 2.7 V,
CL = 1 µF,
TJ = 25°C,
RL = 10 Ω8.6
ms
Fall time output
VI(IN) = 5.5 V,
CL = 1 µF,
TJ = 25°C,
RL = 10 Ω3.4
ms
tfFall time, output VI(IN) = 2.7 V,
CL = 1 µF,
TJ = 25°C,
RL = 10 Ω3
ms
†Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account separately.
‡Not production tested
enable input (EN)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIH High-level input voltage 2.7 V ≤ VI(IN) ≤ 5.5 V 2 V
V
Low level input voltage
4.5 V ≤ VI(IN) ≤ 5.5 V 0.8
V
VIL Low-level input voltage 2.7 V ≤ VI(IN) ≤ 4.5 V 0.5 V
IIInput current EN = 0 V or EN = VI(IN) −0.5 0.5 µA
ton Turnon time CL = 100 µF, R L = 10 Ω20
ms
toff Turnoff time CL = 100 µF, R L = 10 Ω40 ms
current limit
PARAMETER TEST CONDITIONS†MIN TYP MAX UNIT
TPS2030 0.22 0.3 0.4
TJ
=
25
°
C, VI
=
5.5 V,
TPS2031 0.66 0.9 1.1
IOS Short-circuit output current
T
J =
25°C
,
V
I =
5
.
5
V
,
OUT connected to GND, TPS2032 1.1 1.5 1.8 A
IOS
Short circuit
output
current
OUT
connected
to
GND,
Device enable into short circuit TPS2033 1.65 2.2 2.7
A
TPS2034 2.2 3 3.8
†Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account separately.
TPS2030−Q1, TPS2031−Q1, TPS2032−Q1, TPS2033−Q1, TPS2034−Q1
POWER-DISTRIBUTION SWITCHES
SGLS298B − SEPTEMBER 2005 − REVISED JUNE 2008
6TI.COM
electrical characteristics over recommended operating junction temperature range, VI(IN)= 5.5 V,
IO = rated current, EN = 5 V, TA = −405C to 1255C (unless otherwise noted) (continued)
supply current
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Supply current low level output
No Load on OUT
TJ = 25°C 0.3 1
A
Supply current, low-level output No Load on OUT EN = 0 −40°C ≤ TJ ≤ 125°C 10 µA
Supply current high level output
No Load on OUT
EN V
TJ = 25°C 58 75
A
Supply current, high-level output No Load on OUT EN = VI(IN) −40°C ≤ TJ ≤ 125°C 75 100 µA
Leakage current OUT connected to ground EN = 0 −40°C ≤ TJ ≤ 125°C 10 µA
undervoltage lockout
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Low-level input voltage 2 2.5 V
Hysteresis TJ = 25°C 100 mV
overcurrent (OC)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Output low voltage IO = 10 mA, VOL(OC)0.5 V
Off-state current†VO = 5 V, VO = 3.3 V 1µA
†Specified by design, not production tested.
TPS2030−Q1, TPS2031−Q1, TPS2032−Q1, TPS2033−Q1, TPS2034−Q1
POWER-DISTRIBUTION SWITCHES
SGLS298B − SEPTEMBER 2005 − REVISED JUNE 2008
7
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PARAMETER MEASUREMENT INFORMATION
RL CL
OUT
trtf
90% 90%
10%
10%
50% 50%
90%
10%
VO(OUT)
VI(EN)
VO(OUT)
VOLTAGE WAVEFORMS
TEST CIRCUIT
ton toff
Figure 1. Test Circuit and Voltage Waveforms
Table of Timing Diagrams
FIGURE
Turnon Delay and Rise TIme 2
Turnoff Delay and Fall Time 3
Turnon Delay and Rise TIme with 1-µF Load 4
Turnoff Delay and Rise TIme with 1-µF Load 5
Device Enabled Into Short 6
TPS2030, TPS2031, TPS2032, TPS2033, and TPS2034, Ramped Load on Enabled Device 7, 8, 9, 10,
11
TPS2034, Inrush Current 12
7.9-Ω Load Connected to an Enabled TPS2030 Device 13
3.7-Ω Load Connected to an Enabled TPS2030 Device 14
3.7-Ω Load Connected to an Enabled TPS2031 Device 15
2.6-Ω Load Connected to an Enabled TPS2031 Device 16
2.6-Ω Load Connected to an Enabled TPS2032 Device 17
1.2-Ω Load Connected to an Enabled TPS2032 Device 18
1.2-Ω Load Connected to an Enabled TPS2033 Device 19
0.9-Ω Load Connected to an Enabled TPS2033 Device 20
0.9-Ω Load Connected to an Enabled TPS2034 Device 21
0.5-Ω Load Connected to an Enabled TPS2034 Device 22
TPS2030−Q1, TPS2031−Q1, TPS2032−Q1, TPS2033−Q1, TPS2034−Q1
POWER-DISTRIBUTION SWITCHES
SGLS298B − SEPTEMBER 2005 − REVISED JUNE 2008
8TI.COM
PARAMETER MEASUREMENT INFORMATION
Figure 2. Turnon Delay and Rise Time
2468101214161820
t − Time − ms
0
VIN = 5 V
RL = 27 Ω
TA = 25°C
VO(OUT) (2 V/div)
VI(EN)
VO(OUT)
VI(EN) (5 V/div)
Figure 3. Turnoff Delay and Fall Time
2 4 6 8 10 12 14 16 18 20
t − Time − ms
VI(EN) (5 V/div)
0
VI(IN) = 5 V
RL = 27 Ω
TA = 25°C
VO(OUT) (2 V/div)
VI(EN)
VO(OUT)
Figure 4. Turnon Delay and Rise Time
With 1-µF Load
24 6 81012141618 20
t − Time − ms
VI(EN) (5 V/div)
0
VI(IN) = 5 V
CL = 1 µF
RL = 27 Ω
TA = 25°C
VO(OUT) (2 V/div)
VI(EN)
VO(OUT)
Figure 5. Turnoff Delay and Fall Time
With 1-µF Load
2468101214161820
t − Time − ms
VI(EN) (5 V/div)
0
VI(IN) = 5 V
CL = 1 µF
RL = 27 Ω
TA = 25°C
VO(OUT) (2 V/div)
VI(EN)
VO(OUT)
TPS2030−Q1, TPS2031−Q1, TPS2032−Q1, TPS2033−Q1, TPS2034−Q1
POWER-DISTRIBUTION SWITCHES
SGLS298B − SEPTEMBER 2005 − REVISED JUNE 2008
9
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PARAMETER MEASUREMENT INFORMATION
Figure 6. Device Enabled Into Short
12345678910
t − Time − ms
VI(EN) (5 V/div)
0
IO(OUT) (1 A/div)
VI(EN)
IO(OUT)
VI(IN) = 5 V
TA = 25°CTPS2034
TPS2033
TPS2032
TPS2031
TPS2030
Figure 7. TPS2030, Ramped Load on
Enabled Device
20 40 60 80 100 120 140 160 180 200
t − Time − ms
VO(OC) (5 V/div)
0
IO(OUT) (500 mA/div)
VO(OC)
IO(OUT)
VI(IN) = 5 V
TA = 25°C
Figure 8. TPS2031, Ramped Load on Enabled
Device
20 40 60 80 100 120 140 160 180 200
t − Time − ms
VO(OC) (5 V/div)
0
IO(OUT) (1 A/div)
VO(OC)
IO(OUT)
VI(IN) = 5 V
TA = 25°C
Figure 9. TPS2032, Ramped Load on
Enabled Device
20 40 60 80 100 120 140 160 180 200
t − Time − ms
VO(OC) (5 V/div)
0
IO(OUT) (1 A/div)
VO(OC)
IO(OUT)
VI(IN) = 5 V
TA = 25°C
TPS2030−Q1, TPS2031−Q1, TPS2032−Q1, TPS2033−Q1, TPS2034−Q1
POWER-DISTRIBUTION SWITCHES
SGLS298B − SEPTEMBER 2005 − REVISED JUNE 2008
10 TI.COM
PARAMETER MEASUREMENT INFORMATION
Figure 10. TPS2033, Ramped Load on
Enabled Device
20 40 60 80 100 120 140 160 180 200
t − Time − ms
VO(OC) (5 V/div)
0
IO(OUT) (1 A/div)
VO(OC)
IO(OUT)
VI(IN) = 5 V
TA = 25°C
Figure 11. TPS2034, Ramped Load on Enabled
Device
20 40 60 80 100 120 140 160 180 200
t − Time − ms
VO(OC) (5 V/div)
0
IO(OUT) (1 A/div)
VO(OC)
IO(OUT)
VI(IN) = 5 V
TA = 25°C
Figure 12. TPS2034, Inrush Current
12 3 45 6 7 8 910
t − Time − ms
0
II(IN) (500 mA/div)
VI(EN)
II(IN) RL = 10 Ω
TA = 25°C
VI(EN) (5 V/div)
470 µF
47 µF
150 µF
Figure 13. 7.9-Ω Load Connected to an Enabled
TPS2030 Device
200 400 600 800 1000 1200 1400 1600 1800 2000
t − Time − µs
VO(OC) (5 V/div)
0
IO(OUT) (200 mA/div)
VO(OC)
IO(OUT)
VI(IN) = 5 V
RL = 7.9 Ω
TA = 25°C
TPS2030−Q1, TPS2031−Q1, TPS2032−Q1, TPS2033−Q1, TPS2034−Q1
POWER-DISTRIBUTION SWITCHES
SGLS298B − SEPTEMBER 2005 − REVISED JUNE 2008
11
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PARAMETER MEASUREMENT INFORMATION
Figure 14. 3.7-Ω Load Connected to an Enabled
TPS2030 Device
50 100 150 200 250 300 350 400 450 500
t − Time − µs
VO(OC) (5 V/div)
0
IO(OUT) (500 mA/div)
VO(OC)
IO(OUT)
VI(IN) = 5 V
RL = 3.7 Ω
TA = 25°C
Figure 15. 3.7-Ω Load Connected to an Enabled
TPS2031 Device
200 400 600 800 1000 1200 1400 1600 1800 2000
t − Time − µs
VO(OC) (5 V/div)
0
IO(OUT) (1 A/div)
VO(OC)
IO(OUT)
VI(IN) = 5 V
RL = 3.7 Ω
TA = 25°C
Figure 16. 2.6-Ω Load Connected to an Enabled
TPS2031 Device
50 100 150 200 250 300 350 400 450 500
t − Time − µs
VO(OC) (5 V/div)
0
IO(OUT) (1 A/div)
VO(OC)
IO(OUT)
VI(IN) = 5 V
RL = 2.6 Ω
TA = 25°C
Figure 17. 2.6-Ω Load Connected to an Enabled
TPS2032 Device
200 400 600 800 1000 1200 1400 1600 1800 2000
t − Time − µs
VO(OC) (5 V/div)
0
IO(OUT) (1 A/div)
VO(OC)
IO(OUT)
VI(IN) = 5 V
RL = 2.6 Ω
TA = 25°C
TPS2030−Q1, TPS2031−Q1, TPS2032−Q1, TPS2033−Q1, TPS2034−Q1
POWER-DISTRIBUTION SWITCHES
SGLS298B − SEPTEMBER 2005 − REVISED JUNE 2008
12 TI.COM
PARAMETER MEASUREMENT INFORMATION
Figure 18. 1.2-Ω Load Connected to an Enabled
TPS2032 Device
100 200 300 400 500 600 700 800 900 1000
t − Time − µs
VO(OC) (5 V/div)
0
IO(OUT) (1 A/div)
VO(OC)
IO(OUT)
VI(IN) = 5 V
RL = 1.2 Ω
TA = 25°C
Figure 19. 1.2-Ω Load Connected to an Enabled
TPS2033 Device
100 200 300 400 500 600 700 800 900 1000
t − Time − µs
VO(OC) (5 V/div)
0
IO(OUT) (2 A/div)
VO(OC)
IO(OUT)
VI(IN) = 5 V
RL = 1.2 Ω
TA = 25°C
Figure 20. 0.9-Ω Load Connected to an Enabled
TPS2033 Device
100 200 300 400 500 600 700 800 900 1000
t − Time − µs
VO(OC) (5 V/div)
0
IO(OUT) (2 A/div)
VO(OC)
IO(OUT)
VI(IN) = 5 V
RL = 0.9 Ω
TA = 25°C
Figure 21. 0.9-Ω Load Connected to an Enabled
TPS2034 Device
100 200 300 400 500 600 700 800 900 1000
t − Time − µs
VO(OC) (5 V/div)
0
IO(OUT) (5 A/div)
VO(OC)
IO(OUT)
VI(IN) = 5 V
RL = 0.9 Ω
TA = 25°C
TPS2030−Q1, TPS2031−Q1, TPS2032−Q1, TPS2033−Q1, TPS2034−Q1
POWER-DISTRIBUTION SWITCHES
SGLS298B − SEPTEMBER 2005 − REVISED JUNE 2008
13
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PARAMETER MEASUREMENT INFORMATION
Figure 22. 0.5-Ω Load Connected to an Enabled
TPS2034 Device
50 100 150 200 250 300 350 400 450 500
t − Time − µs
VO(OC) (5 V/div)
0
IO(OUT) (5 A/div)
VO(OC)
IO(OUT)
VI(IN) = 5 V
RL = 0.5 Ω
TA = 25°C
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
td(on) Turnon delay time vs Output voltage 23
td(off) Turnoff delay time vs Input voltage 24
trRise time vs Load current 25
tfFall time vs Load current 26
Supply current (enabled) vs Junction temperature 27
Supply current (disabled) vs Junction temperature 28
Supply current (enabled) vs Input voltage 29
Supply current (disabled) vs Input voltage 30
Short circuit current limit
vs Input voltage 31
IOS Short-circuit current limit vs Junction temperature 32
vs Input voltage 33
Static drain source on state resistance
vs Junction temperature 34
rDS(on) Static drain-source on-state resistance vs Input voltage 35
vs Junction temperature 36
VIInput voltage Undervoltage lockout 37
TPS2030−Q1, TPS2031−Q1, TPS2032−Q1, TPS2033−Q1, TPS2034−Q1
POWER-DISTRIBUTION SWITCHES
SGLS298B − SEPTEMBER 2005 − REVISED JUNE 2008
14 TI.COM
TYPICAL CHARACTERISTICS
Figure 23
4.5
4
3.5
2.5 3 3.5 4 4.5
− Turn-on Delay Time − ms
5
5.5
TURNON DELAY TIME
vs
OUTPUT VOLTAGE
7.5
5 5.5 6
VI − Input Voltage − V
td(on)
6
6.5
7
TA = 25°C
CL = 1 µF
Figure 24
17
16.5
16
2.5 3 3.5 4 4.5
17.5
TURNOFF DELAY TIME
vs
INPUT VOLTAGE
18
5 5.5 6
VI − Input Voltage − V
− Turn-off Delay Time − ms
td(off)
TA = 25°C
CL = 1 µF
Figure 25
5.5
5
0 0.5 1
− Rise Time − ms
6
RISE TIME
vs
LOAD CURRENT
6.5
1.5 2
IL − Load Current − A
tr
TA = 25°C
CL = 1 µF
Figure 26
3.25
2.75
2.5
0 0.5
− Fall Time − ms
3.5
FALL TIME
vs
LOAD CURRENT
1 1.5 2
3
IL − Load Current − A
tf
TA = 25°C
CL = 1 µF
TPS2030−Q1, TPS2031−Q1, TPS2032−Q1, TPS2033−Q1, TPS2034−Q1
POWER-DISTRIBUTION SWITCHES
SGLS298B − SEPTEMBER 2005 − REVISED JUNE 2008
15
TI.COM
TYPICAL CHARACTERISTICS
Figure 27
55
45
35
−50 −25 0 25 50
65
SUPPLY CURRENT (ENABLED)
vs
JUNCTION TEMPERATURE
75
75 100 150
TJ − Junction Temperature − °C
Supply Current (Enabled) − Aµ
125
VI(IN) = 3.3 V
VI(IN) = 4 V
VI(IN) = 5 V
VI(IN) = 5.5 V
VI(IN) = 2.7 V
Figure 28
1
0
−1
−50 −25 0 25 50
4
SUPPLY CURRENT (DISABLED)
vs
JUNCTION TEMPERATURE
5
75 100 150
TJ − Junction Temperature − °C
Supply Current (Disabled) − Aµ
125
3
2
VI(IN) = 4 V
VI(IN) = 2.7 V
VI(IN) = 5 V
VI(IN) = 5.5 V
VI(IN) = 3.3 V
Figure 29
55
45
35
2.5 3 3.5 4 4.5
65
SUPPLY CURRENT (ENABLED)
vs
INPUT VOLTAGE
75
5 5.5 6
VI − Input Voltage − V
Supply Current (Enabled) − Aµ
TJ = 125°C
TJ = 85°C
TJ = 25°C
TJ = 0°C
TJ = −40°C
Figure 30
1
0
−1
2.5 3 3.5 4 4.5
4
SUPPLY CURRENT (DISABLED)
vs
INPUT VOLTAGE
5
5 5.5 6
VI − Input Voltage − V
Supply Current (Disabled) − Aµ
3
2TJ = 85°C
TJ = 0°C
TJ = −40°C
TJ = 125°C
TJ = 25°C
TPS2030−Q1, TPS2031−Q1, TPS2032−Q1, TPS2033−Q1, TPS2034−Q1
POWER-DISTRIBUTION SWITCHES
SGLS298B − SEPTEMBER 2005 − REVISED JUNE 2008
16 TI.COM
SHORT-CIRCUIT CURRENT LIMIT
vs
INPUT VOLTAGE
Figure 31
1.5
0.5
0
23 4
2.5
3.5
56
VI − Input Voltage − V
− Short-Circuit Current Limit − A
IOS
1
2
3
TPS2033
TPS2032
TPS2031
TPS2030
TPS2034
TA = 25°C
Figure 32
SHORT-CIRCUIT CURRENT LIMIT
vs
JUNCTION TEMPERATURE
1.5
0.5
0
−50 −25 0
2.5
3.5
25 100
TJ − Junction Temperature − °C
− Short-Circuit Current Limit − A
IOS
1
2
3
TPS2033
TPS2032
TPS2031
TPS2030
TPS2034
50 75
Figure 33
STATIC DRAIN-SOURCE ON-STATE RESISTANCE
vs
INPUT VOLTAGE
20
2.5 3 3.5
40
60
46
VI − Input Voltage − V
30
50
4.5 5
Ω
rDS(on) − Static Drain-Source On-State Resistance − m
5.5
TJ = 25°C
TJ = 125°C
TJ = −40°C
IO = 0.18 A
Figure 34
STATIC DRAIN-SOURCE ON-STATE RESISTANCE
vs
JUNCTION TEMPERATURE
20
−50 −25 0
40
60
25 150
TJ − Junction Temperature − °C
30
50
VI = 2.7 V
50 75 100 125
VI = 3.3 V
VI = 5.5 V
IO = 0.18 A
Ω
rDS(on) − Static Drain-Source On-State Resistance − m
TPS2030−Q1, TPS2031−Q1, TPS2032−Q1, TPS2033−Q1, TPS2034−Q1
POWER-DISTRIBUTION SWITCHES
SGLS298B − SEPTEMBER 2005 − REVISED JUNE 2008
17
TI.COM
TYPICAL CHARACTERISTICS
STATIC DRAIN-SOURCE ON-STATE RESISTANCE
vs
INPUT VOLTAGE
20
3 3.5
40
60
46
VI − Input Voltage − V
30
50
4.5 5 5.5
TJ = 25°C
TJ = 125°C
Figure 35
IO = 1.8 A
TJ = −40°C
Ω
rDS(on) − Static Drain-Source On-State Resistance − m
Figure 36
STATIC DRAIN-SOURCE ON-STATE RESISTANCE
vs
JUNCTION TEMPERATURE
20
−50 −25 0
40
60
25 150
TJ − Junction Temperature − °C
30
50
50 75 100 125
VI = 4 V
VI = 5.5 V
IO = 1.8 A
Ω
rDS(on) − Static Drain-Source On-State Resistance − m
VI = 3.3 V
Figure 37
2
−50 0 50 100
2.4
UNDERVOLTAGE LOCKOUT
2.5
150
TJ − Temperature − °C
2.3
2.2
Start Threshold
Stop Threshold
2.1
VI− Input Voltage − V
TPS2030−Q1, TPS2031−Q1, TPS2032−Q1, TPS2033−Q1, TPS2034−Q1
POWER-DISTRIBUTION SWITCHES
SGLS298B − SEPTEMBER 2005 − REVISED JUNE 2008
18 TI.COM
APPLICATION INFORMATION
IN
OC
EN
GND
0.1 µF
2,3
5
4
6,7,8
0.1 µF22 µF
Load
1
OUT
TPS2034
Power Supply
2.7 V to 5.5 V
10 kΩ
Figure 38. Typical Application
power supply considerations
A 0.01-µF to 0.1-µF ceramic bypass capacitor between IN and GND, close to the device, is recommended.
Placing a high-value electrolytic capacitor on the output and input pins is recommended when the output load
is heavy. This precaution reduces power supply transients that may cause ringing on the input. Additionally,
bypassing the output with a 0.01-µF to 0.1-µF ceramic capacitor improves the immunity of the device to
short-circuit transients.
overcurrent
A sense FET checks for overcurrent conditions. Unlike current-sense resistors, sense FETs do not increase the
series resistance of the current path. When an overcurrent condition is detected, the device maintains a
constant output current and reduces the output voltage accordingly. Complete shutdown occurs only if the fault
is present long enough to activate thermal limiting.
Three possible overload conditions can occur. In the first condition, the output has been shorted before the
device is enabled or before VI(IN) has been applied (see Figure 6). The TPS203x senses the short and
immediately switches into a constant-current output.
In the second condition, the excessive load occurs while the device is enabled. At the instant the excessive load
occurs, high currents may flow for a short time before the current-limit circuit can react (see Figure 13 through
Figure 22). After the current-limit circuit has tripped (reached the overcurrent trip threshhold) the device
switches into constant-current mode.
In the third condition, the load has been gradually increased beyond the recommended operating current. The
current is permitted to rise until the current-limit threshold is reached or until the thermal limit of the device is
exceeded (see Figure 7 through Figure 11). The TPS203x is capable of delivering current up to the current-limit
threshold without damaging the device. Once the threshold has been reached, the device switches into its
constant-current mode.
OC response
The OC open-drain output is asserted (active low) when an overcurrent or overtemperature condition is
encountered. The output remains asserted until the overcurrent or overtemperature condition is removed.
Connecting a heavy capacitive load to an enabled device can cause momentary false overcurrent reporting from
the inrush current flowing through the device, charging the downstream capacitor. An RC filter can be connected
to the OC pin to reduce false overcurrent reporting. Using low-ESR electrolytic capacitors on the output lowers
the inrush current flow through the device during hot-plug events by providing a low impedance energy source,
thereby reducing erroneous overcurrent reporting.
TPS2030−Q1, TPS2031−Q1, TPS2032−Q1, TPS2033−Q1, TPS2034−Q1
POWER-DISTRIBUTION SWITCHES
SGLS298B − SEPTEMBER 2005 − REVISED JUNE 2008
19
TI.COM
APPLICATION INFORMATION
GND
IN
IN
EN
OUT
OC
OUT
OUT
TPS203x
GND
IN
IN
EN
OUT
OC
OUT
OUT
TPS203x
Rpullup
V+
Rfilter
Rpullup
Cfilter
V+
Figure 39. Typical Circuit for OC Pin and RC Filter for Damping Inrush OC Responses
power dissipation and junction temperature
The low on-resistance on the n-channel MOSFET allows small surface-mount packages, such as SOIC, to pass
large currents. The thermal resistances of these packages are high compared to those of power packages; it
is good design practice to check power dissipation and junction temperature. The first step is to find rDS(on) at
the input voltage and operating temperature. As an initial estimate, use the highest operating ambient
temperature of interest and read rDS(on) from Figure 33 through Figure 36. Next, calculate the power dissipation
using:
PD+rDS(on) I2
Finally, calculate the junction temperature:
TJ+PD RqJA )TA
Where:
TA = Ambient Temperature °C
RθJA = Thermal resistance SOIC = 172°C/W, PDIP = 106°C/W
Compare the calculated junction temperature with the initial estimate. If they do not agree within a few degrees,
repeat the calculation, using the calculated value as the new estimate. Two or three iterations are generally
sufficient to get an acceptable answer.
thermal protection
Thermal protection prevents damage to the IC when heavy-overload or short-circuit faults are present for
extended periods of time. The faults force the TPS203x into constant current mode, which causes the voltage
across the high-side switch to increase; under short-circuit conditions, the voltage across the switch is equal
to the input voltage. The increased dissipation causes the junction temperature to rise to high levels. The
protection circuit senses the junction temperature of the switch and shuts it off. Hysteresis is built into the thermal
sense circuit, and after the device has cooled approximately 20 degrees, the switch turns back on. The switch
continues to cycle in this manner until the load fault or input power is removed.
undervoltage lockout (UVLO)
An undervoltage lockout ensures that the power switch is in the off state at powerup. Whenever the input voltage
falls below approximately 2 V, the power switch will be quickly turned off. This facilitates the design of
hot-insertion systems where it is not possible to turn off the power switch before input power is removed. The
UVLO also keeps the switch from being turned on until the power supply has reached at least 2 V, even if the
switch is enabled. Upon reinsertion, the power switch will be turned on, with a controlled rise time to reduce EMI
and voltage overshoots.
TPS2030−Q1, TPS2031−Q1, TPS2032−Q1, TPS2033−Q1, TPS2034−Q1
POWER-DISTRIBUTION SWITCHES
SGLS298B − SEPTEMBER 2005 − REVISED JUNE 2008
20 TI.COM
APPLICATION INFORMATION
generic hot-plug applications (see Figure 40)
In many applications it may be necessary to remove modules or pc boards while the main unit is still operating.
These are considered hot-plug applications. Such implementations require the control of current surges seen
by the main power supply and the card being inserted. The most effective way to control these surges is to limit
and slowly ramp the current and voltage being applied to the card, similar to the way in which a power supply
normally turns on. Because of the controlled rise times and fall times of the TPS203x series, these devices can
be used to provide a softer start-up to devices being hot-plugged into a powered system. The UVLO feature
of the TPS203x also ensures the switch will be off after the card has been removed, and the switch will be off
during the next insertion. The UVLO feature assures a soft start with a controlled rise time for every insertion
of the card or module.
Power
Supply
Block of
Circuitry
TPS2034
GND
IN
IN
EN
OUT
OUT
OUT
OC
0.1 µF
1000 µF
Optimum
2.7 V to 5.5 V
PC Board
Overcurrent Response
Figure 40. Typical Hot-Plug Implementation
By placing the TPS203x between the VCC input and the rest of the circuitry, the input power reaches this device
first after insertion. The typical rise time of the switch is approximately 9 ms, providing a slow voltage ramp at
the output of the device. This implementation controls system surge currents and provides a hot-plugging
mechanism for any device.
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
TPS2030IDRG4Q1 ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2030IDRQ1 ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TPS2030-Q1 :
•Catalog: TPS2030
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product
PACKAGE OPTION ADDENDUM
www.ti.com 26-Mar-2010
Addendum-Page 1
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