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• Organization: 1M×8/512K×16
• Sector architecture
- One 16K; two 8K; one 32K; and fifteen 64K byte sectors
- One 8K; two 4K; one 16K; and fifteen 32K word sectors
- Boot code sector architecture—T (top) or B (bottom)
- Erase any combination of sectors or full chip
• Single 2.7-3.6V power supply for read/write operations
• Sector protection
• High speed 70/80/90/120 ns address access time
• Automated on-chip programming algorithm
- Automatically programs/verifies data at specified address
• Automated on-chip erase algorithm
- Aut omatically preprog rams/erases chip or sp ecified sector s
• Hardware RESET pin
- Resets int ern al state machine t o re ad m o d e
• Low power consumption
- 200 nA typical automatic sleep mode current
- 200 n A ty pical stand by cu rren t
- 10 mA typica l read cu rren t
• JEDEC standard software, packages and pinouts
- 48-pin TSOP
- 44- p in S O ( av a ilab ility T B D )
• Detection of program/erase cycle completion
-DQ7 DATA
pollin g
- DQ6 toggle bit
- DQ2 toggle bit
-RY/BY
output
• Erase suspend/resume
- Supports reading data from or programming data to
a sector not being erased
• Low VCC write lock-out below 1.5V
• 1 0 year data retention at 150C
• 100,000 write/eras e cycle endurance
/RJLFEORFNGLDJUDP
X decoder
VCC
VSS
Cell m a trix
Y decoder Y gating
Data latch
Chip enable
Address latch
Input/output
buffers
Sector protect/
Command
register
Program/erase
control
VCC detector
Erase voltage
generator
Prog ram v o ltag e
generator
Timer
A0–A18
CE
OE
STB
STB
Output enable
Logic
RY/BY
WE
RESET
DQ0–DQ15
switches
erase volta ge
BYTE
A-1
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29LV800-70R1
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29LV800-80 29LV800-90 29LV800-120 Unit
Max imum ac cess time tAA 70 80 90 120 ns
Max imum c hip enable access time tCE 70 80 90 120 ns
Max imum output enable ac cess time tOE 30 30 35 50 ns
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48-pin TSOP
44-pin SO (availability TBD)
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
A14
A15
A16
BYTE
VSS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
A6
A5
A4
A3
A2
A1
A0
CE
VSS
OE
DQ0
DQ8
DQ1
DQ9
DQ2
DQ10 21
22
DQ3
DQ11
A10
A11
A12
A13
2A18 3A17 4A7
1RY/BY
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
43
42
41
44 WE
A8
A9
RESET
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A8
A9
A10
A11
A12
A13
A14
A15 A16
BYTE
VSS
DQ7
DQ14
NC
NC
WE
RESET
NC
NC
A18 DQ2
DQ10
DQ3
DQ11
VCC
DQ4
DQ12
DQ5
DQ6
DQ13
1
2
3
4
5
6
7
8
9
10
11
12
13
14
48
47
46
45
44
43
42
41
40
39
38
37
36
35
15
16 34
33
A17
A7
A6
A5
A4
A3
A2
A1
A0
CE
VSS
OE
DQ0
DQ8
DQ1
DQ9
17
18
19
20
21
22
32
31
30
29
28
27
23
24 26
25
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The AS29LV800 is an 8 megabit, 3.0 volt Flash memory organized as 1 Megabyte of 8 bits/512Kbytes of 16 bits each. For
flex ible e rase and program capabili ty, the 8 megabit s of data is divided int o ninetee n sectors : one 16K , two 8K, one 3 2K, and
fifteen 64k byte sectors; or one 8K, two 4K, one 16K, and fifteen 32K w ord sectors. The ×8 data appears on DQ0–DQ7; the ×16
data appears on DQ0–DQ15. The AS29LV800 is offered in JEDEC standard 48-pin TSOP and 44-pin SO (availability TBD)
packages. This device is desi g ned to be progr ammed a nd erased in -system with a single 3. 0V VCC supply. The device can also be
reprogrammed in standard EPROM programmers.
The AS29LV800 offers access times of 70/80/90/120 ns, allowing 0-wait state operation of high speed microprocessors. To
eliminate bus contention the device has separate chip enable (CE), wr ite enable (WE) , and output en able (OE ) controls. Word
mode (×16 output) is selected by BYTE = high. Byte mode (×8 output) is selected by BYTE = l ow.
The AS29LV800 is fully compatible with the JEDEC single power supply Flash standard. Write commands are sent to the
command register using standard microprocessor write timings. An internal state-machine uses register contents to control the
erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase
ope rations. Rea d data from the device occu rs in the sa me man ner as oth er Fla sh or EPROM device s. Use the progr am com mand
sequence to invoke the automated on-chip programming algorithm that automatically times the program pulse widths and
verif ies pro per cell margin. Use the era se comman d sequ ence to invok e th e auto mat ed on -chip erase algorith m tha t pr epr og rams
the sector (if it is not already programmed before executing the erase operation), times the erase pulse widths, and verifies
proper cell margin.
Boot sector architecture enables the system to boot from either the top (AS29LV800T) or the bottom (AS29LV800B) sector.
Sector erase architecture allows specified sectors of memory to be erased and reprogrammed without altering data in other
sectors. A sector typically erases and verifies within 1.0 seconds. Hardware sector protection disables both program and erase
operations in all, or any combination of, the nineteen sectors. The device provides true background erase with Erase Suspend,
which puts erase op era ti ons on h old t o ei ther r ead da ta f ro m, or p ro gram dat a to , a se ctor th at is not bein g eras ed . The chip e rase
command will auto maticall y erase all unprot ected sectors.
A factory shi pp ed A S2 9LV800 is ful ly erased (a ll bits = 1) . The pro g ram min g op er ation set s bits to 0 . Data i s prog ra mme d in to
the array one byte at a time in any sequence and across sector boundar ies. A sector must be erased to change bits from 0 to 1.
Erase returns all bytes in a sector to the erased state (all bits = 1). Each sector is erased individually with no effect on other
sectors.
The device fe atures sing le 3.0V power supp ly operation for Read, Write, and Erase functions. Internally gener ated and regulated
voltages are provided for the Program and Erase operations. A low VCC detector automatically inhibits write operations during
power t ranstit ions. The RY/B Y pin, DATA po lling of DQ7, or toggle bit (D Q6) may be us ed to de tect end of progra m or e rase
operations. The device automatically resets to the read mode after program/erase operations are completed. DQ2 indicates
which sectors ar e being erased.
The AS29LV800 resists accidental erasure or spurious programming signals resulting from power transitions. Control register
architecture permits alteration of memory contents only after successful completion of specific command sequences. During
power up, the device is set to read mode with all program/erase commands disabled when VCC is less than VLKO (lockout
vol ta ge ). Th e com mand r egi sters are not affected b y noise pul ses o f les s th an 5 ns on OE, CE, or WE. To initia te write command s,
CE and WE must be logical zero and OE a logical 1.
When the device’s hardware RESET pin is driven low, any program/erase operation in progress is terminated and the internal
state machine is reset to read mode. If the RESET pin is tied to the system reset circuitry and a system reset occurs during an
automated on-chip program/erase algorithm, data in address locations being operated on may become corr upted and requires
rewriting. Resetting the device enables the system’s microprocessor to read boot-up firmware from the Flash memory.
The AS29LV800 uses Fowler-Nordheim tunnelling to electrically erase all bits within a sector simultaneously. Bytes are
programmed one at a time using EPROM programming mechanism of hot electron injection.
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L = Low (<V IL) = lo g i c 0; H = Hig h (>V IH) = logic 1; VID = 10.0 ± 1.0V; X = don’t care.
In ×16 mode, BYTE = VIH. In ×8 mode, BYTE = VIL with DQ8-DQ14 in high Z and DQ15 = A-1.
†Verification of sector protect/unprotect during A9 = VID.
0RGHGHILQLWLRQV
Mode CE OE WE A0 A1 A6 A9 RESET DQ
ID read MFR codeLLHLLLV
ID HCode
ID read device code L L H H L L VID HCode
Read L L H A0A1A6A9H D
OUT
Standby HXXXXXXHHigh Z
Output disable L HHXXXXHHigh Z
Write L H L A0 A1 A6 A9 H DIN
Enable sector protect L VID Pulse/L L H L VID HX
Sector unprotect L VID Pulse/L L H H VID HX
Temporary sector
unprotect XXXXXXXV
ID X
Verify sector protect†LLHLHLV
ID HCode
Verify sector unprotect†LLHLHHV
ID HCode
Hardware Reset XXXXXXXLHigh Z
Item Description
ID MFR cod e,
device code
Selected by A9 = VID(9.5V–10.5V), CE = OE = A1 = A6 = L, en abli ng outputs.
When A0 is low (VIL) the output data = 52h, a uniq ue Mfr. code fo r Allian ce Sem iconduc tor Fl ash pr odu cts .
When A0 is high (VIH), DOUT represents the device code for the AS29LV800.
Read mode Selecte d wit h CE = OE = L, WE = H. Data is valid in tACC time after addresses are stable, tCE after CE is low
and tOE after OE is low.
Standby Selected w ith CE = H. P art is po were d down, and I CC reduced to <1.0 µA when CE = VCC ± 0.3V = RESET. If
activated during an automated on-chip algorithm, the device completes the operation before entering
standby.
Outpu t disable Part remai n s powered up; but ou tputs di sabled with OE pulled high.
Write
Selected with CE = WE = L, O E = H. Acco mp lish all Flash erasur e and pr ogramming thr ou gh th e command
register. Contents of command register serve as inputs to the internal state machine. Address latching occurs
on the falling edge of WE or CE, whichever occurs later. Data latc hing occurs on the rising edge WE or CE,
whichever occurs first. Filters on WE preven t spurious noise events from appea rin g as write commands.
Enable
sector protect
Hardware pr ot ection circu it ry imp l em ented with ext ernal programmin g equipment ca uses the device to
disable prog ra m and erase op eration s for speci fie d sectors. For in-syst em sector prote ction, refer to Sector
protect algorithm on page 14.
Sector
unprotect
Disables sec tor prote ction for all sectors using exte rna l programming equipm ent. All secto rs must be
protected prior to se ctor unpr otection. For in-system sector unprotection, refer to Sector unprotect
algorithm on page 14.
Verify sector
protect/
unprotect
Verifies write protection for sector. Sectors are protected from program/erase operations on commercial
prog ramm ing eq uipme nt. Dete rmine if secto r pr ot ecti on exis ts in a sys tem b y writing t he ID r ead com mand
sequence and reading location XXX02h, where address bits A12–18 select the defined sector addresses. A
logical 1 on DQ0 indicates a protected sector; a logical 0 indicates an unprotected sector.
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In word mode, there are one 8K word, two 4K word, one 16K word, and fifteen 32K word sectors. Address range is A18–A-1 if BYTE = VIL; address range is
A18–A0 if BYTE = VIH.
Temporary
sector
unprotect
Temporarily disab les sector protection for in-system data changes to protected sectors. Apply +10V to RESET
to activate temporary sector unprotect mode. During temporary sector unprotect mode, program protected
sectors by selecting the appropriate sector address. All protected sectors revert to protected state on removal
of +10V from RESET.
RESET Resets the interal state machine to read mode. If device is programming or erasing when RESET = L, data
may be corrupted.
Deep
power down Hold RESET low to enter deep power down mode (<1 µA). Recovery time to start of first read cycle is 50ns.
Automatic
sleep mode
Enabled automatically when addresses remain stable for 300ns. Typical current draw is 1 µA. Existing data is
availa b le to the sys tem d uring thi s mod e . If an addr e ss is changed, automa ti c slee p mode i s disa bled and ne w
data is returned within standard access times.
Sector
Bottom boot sector architecture (AS29LV800B) Top boot sector architecture (AS29LV800T)
×8 ×16 Size
(Kbytes) ×8 ×16 Size
(Kbytes)
0 00000h–03FFFh 00000h–01FFFh 16 00000h–0FFFFh 00000h–07FFFh 64
1 04000h–05FFFh 02000h–02FFFh 8 10000h–1FFFFh 08000h–0FFFFh 64
2 06000h–07FFFh 03000h–03FFFh 8 20000h–2FFFFh 10000h–17FFFh 64
3 08000h–0FFFFh 04000h–07FFFh 32 30000h–3FFFFh 18000h–1FFFFh 64
4 10000h–1FFFFh 08000h–0FFFFh 64 40000h–4FFFFh 20000h–27FFFh 64
5 20000h–2FFFFh 10000h–17FFFh 64 50000h–5FFFFh 28000h–2FFFFh 64
6 30000h–3FFFFh 18000h–1FFFFh 64 60000h–6FFFFh 30000h–37FFFh 64
7 40000h–4FFFFh 20000h–27FFFh 64 70000h–7FFFFh 38000h–3FFFFh 64
8 50000h–5FFFFh 28000h–2FFFFh 64 80000h–8FFFFh 40000h–47FFFh 64
9 60000h–6FFFFh 30000h–37FFFh 64 90000h–9FFFFh 48000h–4FFFFh 64
10 70000h–7FFFFh 38000h–3FFFFh 64 A0000h–AFFFFh 50000h–57FFFh 64
11 80000h–8FFFFh 40000h–47FFFh 64 B0000h–BFFFFh 58000h–5FFFFh 64
12 90000h–9FFFFh 48000h–4FFFFh 64 C0000h–CFFFFh 60000h–67FFFh 64
13 A0000h–AFFFFh 50000h–57FFFh 64 D0000h–DFFFFh 68000h–6FFFFh 64
14 B0000h–BFFFFh 58000h–5FFFFh 64 E0000h–EFFFFh 70000h–77FFFh 64
15 C0000h–CFFFFh 60000h–67FFFh 64 F0000h–F7FFFh 78000h–7BFFFh 32
16 D0000h–DFFFFh 68000h–6FFFFh 64 F8000h–F9FFFh 7C000h–7CFFFh 8
17 E0000h–EFFFFh 70000h–77FFFh 64 FA000h–FBFFFh 7D000h–7DFFFh 8
18 F0000h–FFFFFh 78000h–7FFFFh 64 FC000h–FFFFFh 7E000h–7FFFFh 16
Item Description
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Key: L =Low (<VIL); H = High (>V IH); X =Don’t care
Sector
Bot tom boot sector add ress
(AS29LV800B) Top boot sector address
(AS29LV800T)
A18 A17 A16 A15 A14 A13 A12 A18 A17 A16 A15 A14 A13 A12
0 000000X 0000XXX
1 0000010 0001XXX
2 0000011 0010XXX
3 00001XX 0011XXX
4 0001XXX 0100XXX
5 0010XXX 0101XXX
6 0011XXX 0110XXX
7 0100XXX 0111XXX
8 0101XXX 1000XXX
9 0110XXX 1001XXX
10 0111XXX 1010XXX
11 1000XXX 1011XXX
12 1001XXX 1100XXX
13 1010XXX 1101XXX
14 1011XXX 1110XXX
15 1100XXX 11110XX
16 1101XXX 1111100
17 1110XXX 1111101
18 1111XXX 111111X
Mode A18–A12 A6 A1 A0 Code
MFR code (Alliance Semiconductor) X L L L 52h
Device code
×8 T boot X L L H DAh
×8 B bo ot X L L H 5Bh
×16 T boot X L L H 22DAh
×16 B boot X L L H 225B h
Sector protection Sector address L H L 01h prote cted
00h un protected
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1 Bus operations defined in "Mode defin itions," on page 3.
2 Reading from and programming to non-erasing se ctors allowe d in Erase Suspend mode.
3 Address bits A11-A18 = X = Don’t Care for all address commands except where Program Addr e ss and Sector Address are r equ ire d.
4 Data bits DQ15-DQ8 are don’t care for unlock and command cycles.
5 The Unlock Bypass command must be initiated before the Unlock Bypass Program command.
6 The Unlock Bypass Reset command returns the device to reading array data when it is in the unlock bypass mode.
Command sequence Required bus
write cycles 1st bus cycle 2nd bus cycle 3rd bus cycle 4th bus cycle 5th bus cycle 6th bus cycle
Address Data Address Data Address Data Address Data Address Data Address Data
Reset/Read 1 XXXh F0h Read
Address Read Data
Reset/Read ×16 3555h AAh 2AAh 55h 555h F0h Read Address Read
Data
×8 AAAh 555h AAAh
Autoselect
ID Read
×16
3
555h AAh 2AAh 55h 555h 90h
01h
Device code 22DAh (T)
225Bh (B)
×8 AAAh 555h AAAh 02h
Device code DAh (T) 5B h
(B)
×16 555h AAh 2AAh 55h 555h 90h 00h
MFR c o de 0052h
×8 AAAh 555h AAAh 52h
×16 555h AAh 2AAh 55h 555h 90h
XXX02h
Sector protection 0001h = prot ected
0000h = unprote ct ed
×8 AAAh 555h AAAh XXX04h
Sector protection 0001h=protected
0000h=unprotected
Program ×16 4555h AAh 2AAh 55h 555h A0h Progr am Addres s Program Data
×8 AAAh 555h AAAh
Unlock bypa ss ×16 3555 AAh 2AA 55h 555 20h
×8 AAA 555 AAA
Unloc k bypass program 2 XXX A0h Program
address Program
data
Unlock bypass reset 2 XXX 90h XXX 00h
Chip Erase ×16 6555h AAh 2AAh 55h 555h 80h 555h AAh 2AAh 55h 555h 10h
×8 AAAh 555h AAAh AAAh 555h AAAh
Sect or Erase ×16 6555h AAh 2AAh 55h 555h 80h 555h AAh 2AAh 55h Sector
Address 30h
×8 AAAh 555h AAAh AAAh 555h
Sector Erase Suspen d 1 XXXh B0h
Sector Erase Resume 1 XXXh 30h
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Item Description
Reset/Read
Initiate read or reset operations by writing the Read/Reset command sequence into the command
register. This allows the microprocessor to retrieve data from the memory. Device remains in read
mode until command register contents are altered.
Device automatically powers u p in read/reset state. This feature allows only read s, therefore
ensu ring no spu rio us memory co ntent alterations during power up.
ID Read
AS29LV800 provides manufacturer and device codes in two ways. Externa l PROM prog rammer s
typically access the device codes by driving +10V on A9. AS29LV800 also contains an ID Read
command to read the dev ice code with only +3V, since multiplexing +10V on address lines is
generally und esirable.
Initiate device ID read by wr iting the ID Read command sequence into the command register.
F oll ow with a read sequenc e fr om addr ess XX X00h to return MFR code . Follow I D Read comman d
seque nce wit h a re ad sequence fr om add ress XXX0 1h to r eturn device code.
To v eri fy write protect status o n sectors, r ead address XXX02 h . Sector addr esses A18 –A 12 produce
a 1 on DQ0 for protected sector and a 0 for unprotected sector.
Exit from ID read mode with Read /Reset command seque nc e.
Hardware Reset
Holding RESET low for 500 ns rese ts the device, ter mi n ating any operation in progress; data
handled in the operation is corrupted. The internal state machine resets 20 µs after RESET is driv e n
lo w. RY/BY remains low until internal state machine r e sets. Af te r RESET is set high, there is a delay
of 50 ns for the device to per mit read operati ons.
Byte/word
Programming
Programming th e AS29LV800 is a four bus cyc le operation perfor med on a byte-by-byte or word-
by-word basis. Two unlock wri te cycles precede the Program Setup c o mmand and progr am data
write cycle. Upon execution of the program command, no additional CPU controls or timings are
necessary. Addresses are latched on the falling edge of CE or WE, whichever is last; data is latched
on the ris ing edge of CE or WE, whichever is first. The AS 29LV800’s automated on-chip progra m
algo ri thm provides ad equate internally-generat ed progr am ming p ulses and verifies the
progra mmed cel l margin.
Check progr amming status by sampling data on the RY/BY pin, or either the DATA polling (DQ7)
or toggl e bit ( DQ 6) at the pro gram address locatio n. Th e programming operation is complete if
DQ7 ret urns equivalent d ata, if DQ6 = no toggle, or if RY/BY pin = high.
The AS29LV800 ig nores commands writ ten during progra mming. A har dware rese t occurring
during programming ma y corrupt the data at the programmed location.
AS29LV800 allows pr ogrammi ng in any sequence, acros s any sector bou ndary. Changi ng da t a f rom
0 to 1 requ ires an erase operation . Attempting to program data 0 to 1 results in either DQ5 = 1
(exceeded programming time limits); reading this data after a read/reset operation returns a 0.
When pr o gramming time limit is exceeded, DQ5 reads high, and DQ6 continu es to toggle. In this
state, a Reset command returns the device to read mode.
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Unlock Bypass
Command Sequence
The unl ock by pass fe ature increases th e sp eed at which the sys te m programs bytes or words to the
de vic e be cause i t b ypass es t he f irs t two unlock cycles of the st andar d pr og ram command s eque nce .
To initiate the unlock bypass command sequence, two unlock cycles must be written, then
followed by a third cycle which has the unlock bypass command, 20h.
The device then begins the unlock bypass mode. In order to program in this mode, a two cycle
unlock bypass program sequence is required. The first cycle has the unlock bypass program
command, A0h. It is followed by a second cycle which has the program address and data. To
progra m additional d ata, the same sequ ence must be followed.
The un l ock bypass mode has two valid com mands, the Unlo ck Bypass Prog ram com m and and the
Unlock Bypass Reset command. The only way the system can exit the unlock bypass mode is by
issuing the unlock bypass reset command sequence. This sequence involves two cycles. The first
cycle contains the data, 90h. The sec on d cycle co nt ain s th e data 00h. Addr e sses are don’t care f o r
both cycles. The device then returns to reading array data.
Chip Erase
Chip erase requires six bus cycles: two unlock write cycles; a setup command, two additional
unlock write cycles; and finally the Chip Erase command.
Chip erase does not require logical 0 s to be written prior to er asure . W hen the aut omated on-chip
eras e a lgorithm is invoked with the Chip Erase co mmand sequen ce, AS29LV800 autom atically
programs and ver ifies the entire memory array for an all-zero pattern prior to erase. The 29LV800
returns to read mode upon completion of chip erase unless DQ5 is set high as a result of exceeding
time lim i t .
Sector Erase
Sector erase requires six bus cycles: two unlock write cycles, a setup command, two additional
unlock write cycles, and finally the Sector Erase command. Identify the sector to be erased by
addressing any location in the sector. The address is latc hed on the falling edge of WE; th e
command, 30h is latched on the rising edge of WE. The sector era se opera tion begin s after a sect or
erase time-out.
To erase multiple sectors, write the Sector Era se command to each of the addre sses of sectors to
erase afte r fo llo wing th e six b us cycle op erati on a bo ve. Timing between writes of a dditional sectors
must be l ess than the erase time-out period, or the AS29 LV800 igno res the command and erasure
begi ns. During the time-out period a ny falli ng edge of WE resets the time-out. Any comman d
(other than Sector Erase or Erase Suspend) dur ing time-out period resets the AS29LV800 to read
mode, and the device ignores the sector erase command string. Erase such ignored sectors by
restarting the Sector Erase command on the ignored sectors.
The en tire array need not be wri tten wi th 0s prior to erasu re. AS29LV 800 writes 0s to the entire
sector prior to electrical erase; writing of 0s affects only selected sectors, leaving non-selected
sectors unaffected. AS29LV800 requires no CPU control or timing signals during sector erase
operations.
Automatic sector erase begins after sector erase time-out from the last rising edge of WE from the
sector erase command stream and ends when the DATA polling (DQ7) is logical 1. DATA polling
address must be performed on addresses that fall within the sectors being erased. AS29LV800
retu rns to r ead mode after secto r erase unless DQ5 is set hig h by exceeding the time limit.
Item Description
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9/26/01; V.1.5 $OOLDQFH6HPLFRQGXFWRU P. 10 of 25
Erase Suspend
Erase Suspend allows interruption of sector erase operations to read data from or program data to a
sector not being erased. Erase suspend applies only during sector erase operations, including the
time-out period. Writing an Erase Suspend command during sector erase time-out results in
immediate term inatio n of the tim e-out period an d suspensio n of erase operati on.
AS29LV800 ignores any commands d uring erase su spen d other than Read/ Res et, Pr ogra m or Erase
Resume co mmands. Writing th e Erase Resume C ommand contin ues erase operati ons. Ad dresses are
Don’t Care when writing Erase Suspend or Erase Resume commands.
AS29LV800 takes 0.2–15 µs to suspend erase operations after receiving Erase Suspend command.
To deter mine completion of erase suspend, either check DQ6 after selecting an address of a sector
not bein g erased, or poll RY/BY. Chec k DQ2 in conjunction with DQ6 to determine if a sector is
being erased. AS29LV800 ignores redundant writes of Erase Suspend.
While in erase -suspen d mode , A S29LV800 allo ws rea ding da ta (e rase-su spend-r ead mode) f rom o r
programming data (erase-suspend-program mode) to any sector not undergoing sector erase;
the se op erations are treated as standard read or standard programmi ng mode. AS29LV800 defaults
to erase-suspend-read mode while an erase operation has been suspended.
Write th e R esume co mmand 30h to continue operatio n of sector erase. AS29LV800 ignores
redu ndant writes of the Resume com mand. AS29LV 80 0 pe rmits m ult iple suspend/ resume
ope rations during sec tor er ase.
Sector Protect
When attempting to write to a protected sector, DATA polling and Toggle Bit 1 (DQ6) are activ a ted
for about <1 µ s. When attem pting to erase a protected sect or, DATA polling and
Toggle Bi t 1 (D Q 6) a r e activa ted for about <5 µs. In both cas es, the device re tu rns to read mode
with out altering the specifie d secto rs.
Ready/Busy
RY/BY indi cates wh ether an a u tomated on-chip a lg or ithm is in progress (RY/BY = low) or
complete d (RY/BY = high). The device does not accept Program/Erase commands when
RY/BY = low. RY/BY= high when device is in erase suspend mode. RY/BY = high when device
exceeds ti me limit , indi ca ting tha t a prog ram or eras e operation has f a iled. RY/BY is an ope n drain
output, enabling multiple RY /BY pins to be tied in parallel with a pull up resistor to VCC.
Item Description
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DQ2 toggles when an erase-suspen ded sector is read r epe atedly.
DQ6 toggles when any addr ess is read r epeat edly.
DQ2 = 1 if byte address being pr ogrammed is read during erase-suspend program mode.
†DQ2 toggles when the read address applied points to a sector which is undergoing erase, suspended erase, or a failure to erase.
DATA polling (DQ7)
Only active dur ing automated on-chip algorithms or sector erase time outs. DQ7 reflects
compleme nt of data las t written w h en read duri ng the au tomated on-chip prog ram algor ithm (0
during erase a lg orithm); reflects true data wh en read after completion of an automated on- chip
program algorithm (1 after completion of erase agorithm).
Toggle bit 1 (DQ6)
Active during automated on-chip algorithms or sector erase time outs. DQ6 toggles when CE or OE
toggles, or an Erase Resume command is invoked. DQ6 is valid after the rising edge of the fourth
pulse of WE during programming; after th e rising ed ge of the sixt h WE pulse during chip erase;
after th e last rising edge of the se cto r erase WE pulse for sector erase. For protecte d sectors,
DQ6 toggle s f or <1 µ s during pro gra m mode writes, an d <5 µs during eras e (i f all se lected s ector s
are protected).
Exceeding time limit
(DQ5)
Indi cates unsuccessful completion of program/er a se oper ation (DQ 5 = 1). DATA polling remains
activ e . If DQ5 = 1 during chip e rase , all or some se ctors ar e d efect iv e; during b yte prog ramming o r
sector erase, the sector is defective (in this case, reset the device and execute a program or erase
comm a nd sequ ence to continue working with functional sectors). Attemp ting to prog ram 0 to 1
will set DQ5 = 1.
Sector erase timer
(DQ3)
Checks whether sector erase timer window is open. If DQ3 = 1, erase is in progress; no commands
will be accep ted. If DQ3 = 0, the d ev ice will accep t sector erase commands . Check DQ3 befor e and
after each Sector Erase command to verify that the command was accepted.
Toggle bit 2 (DQ2)
During sector erase, DQ2 toggles with OE or CE only during an attempt to read a sector being
erased. Dur ing c hip erase, DQ2 toggles with OE or CE for all addresses. If DQ5 = 1, DQ2 toggles
only at sector addresses where failure occurred, and will not toggle at other sector addresses. Use
DQ2 in conjunction with DQ6 to determine whether device is in auto erase or erase suspend
mode.
Status DQ7 DQ6 DQ5 DQ3 DQ2 RY/BY
Stan dard mode Auto programming DQ7 Toggle 0 N/A No toggle 0
Program/erase in auto erase 0 Toggle 0 1 Toggle†0
Era se susp end mode Read erasing sector 1 No toggle 0 N/A Toggle 1
Read non-erasing sector Data Data Data Data Data 1
Progr am in er ase su spend DQ7 Toggle 0 N/A Toggle†0
Exceeded time limit s
Auto programming (b y te ) DQ7 Toggle 1 N/A No toggle 1
Program/erase in auto erase 0 Toggle 1 N/A Toggle†1
Progr a m in era se sus pend
(non-erase suspended sector) DQ7 Toggle 1 N/A No toggle 1
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†The system software should check the status of DQ3 prior to and following each
subsequent sector erase command to ensure command completion. The device may
not have accepted the command if DQ3 is high on second status check.
START
555h/AAh
2AAh/55h
555h/A0h
Program address/program data
Program command sequence
×16 mode (address/ data):
Write program command sequence
(see below)
DATA polling or toggle bit
successfully completed
Last
address?
Programming completed
YES
Increment
address
NO 555h/AAh
2AAh/55h
555h/80h
erase command sequence
555h/AAh
2AAh/55h
Sector address/30h
Erase complete
×16 mode (a ddress/data ) :
DATA pol lin g or to ggle bit
successfully completed
Write erase comma nd seq uence
(see below)
555h/AAh
2AAh/55h
555h/80h
Chip erase command seque nce
555h/AAh
2AAh/55h
555h/10h
×16 mode (address/data):
In di vidu al s e ctor/multiple s e ctor
Sector address/30h
Sector address/30h
optional sector erase commands
START
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START
Write unlock
bypa ss comma nd
(3 cycles)
Write unlo ck
by pa ss progr am co m man d
(2 cycles)
DATA polling or
Last
address?
YES
Increment
address
NO
Write unlock
bypass reset command
(2 cycles)
Programming completed
toggle bit
successfully completed
555h/AAh
2AAh/55h
555h/20h
Unlock bypass command sequence
x16 mode (address/data)
xxxh/A0h
Unlock by p as s pr ogram
x16 mode (address/data)
command sequence
progr am ad dr e s s/
pro gram data
xxxh/90h
Unlock b ypass re se t
x16 mode (address/data)
command sequence
xxxh/00h
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START
PLS CNT = 1
RESET# = V
ID
Wait 1 µs
First Write
Cycle=60h?
Temporar y sector
unprotect mode No
Set up sec t or
Sector protect:
address
write 60h to sector
address with
A6=0, A1=1,
A0=0
Wait 150 µs
Verify sector
protect; write 40h
to sector address
with A6=0,
A1=1, A0=0
Read fr o m s ect or
address with A6=0,
A1=1, A0=0
Data=01h?
Protect
sector?
PLSCNT=25?
No
Increment
PLSCNT
No
Device failed
Yes
Yes
Yes
No
START
PLSCNT = 1
RESET# = V
ID
Wait 1 µs
First Write
Cycle=60h?
Temporary sector
unprotect mode
No
Yes
All sectors
protected?
Set up first
Sector unprotect:
sector address
write 60h to sector
address with
A6=1, A1=1,
A0=0
Wait 15 ms
Verify sector
unprotect; write 40h
to sector address
with A6=1,
A1=1, A0=0
Read from sector
address with A6=1,
A1=1, A0=0
Data=00h?
Last sector
verified?
No
Yes
Yes
Remove V
ID
from R ESET#
Write reset
command
Sector unprotect
complete
Remove V
ID
from RESET#
Write reset
command
Sector protect
complete
PLSCNT
Increment
PLSCNT
No
Device fa iled
Yes
=1000?
Set up next
sector address
No
Protect all sectors:
The shaded po rtion of
the sec tor protct
initiated for all
unprotected sectors
before calling the
sector unprotect No
Yes
Yes algorithm must be
another
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†VA = Byte address for programming. VA = any of the sector
addresses within the sector being erased during Sector Erase. VA
= valid address equals any non-protected sector group address
during Chip Erase.
‡DQ7 rechec ked even if DQ5 = 1 b ecause DQ5 an d DQ7 may not
change simultaneously.
7RJJOHELWDOJRULWKP
†DQ6 rechec ked even if DQ5 = 1 because DQ6 may stop toggling
when DQ5 changes to 1.
Read byte (DQ0–DQ7)
Address = VA†
Read byte (DQ0–DQ7)
Address = VA
NO
DONE
NO
NO†
YES
FAIL
YES†
YES
DONE
DQ7
=
data
?
DQ5
=
1
?
DQ7
=
data
‡
?
Read byte (DQ0–DQ7)
Address = don’t care
Read byte (DQ0–DQ7)
Address = don’t care
NO
DONE
YES
YES
YES
FAIL
NO
NO
DONE
DQ6
=
toggle
?
DQ6
=
toggle
†
?
DQ5
=
1
?
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Parameter Symb ol Test condit ions Min Max Unit
Input load current ILI VIN = VSS to VCC, VCC = VCC MAX -±1
µA
A9 Input load current ILIT VCC = VCC MAX, A9 = 10V 35 µA
Output leakage current ILO VOUT = VSS to VCC, VCC = VCC MAX -±1
µA
Active cur rent, read @ 5MHz I CC1 CE = VIL, OE = VIH -20mA
Active current, prog ram/ erase I CC2 CE = VIL, OE = VIH - 100 mA
Automatic sleep mode1
1 A utom atic sleep mode enables the deep power down mode when addresses are sta ble for 150 ns. Typical sleep m ode curr ent is 200 nA.
ICC3 CE = VIL, OE = VIH;
VIL= 0.3 V, VIH = VCC - 0.3V -5µA
Standby current ISB CE = VCC - 0.3V, RESET = VCC - .3V - 5 µA
Deep power down current3IPD RESET = 0.3V - 5 µA
Input low voltage VIL -0.5 0.8 V
Input high voltage VIH 0.7×VCC VCC + 0.3 V
Output lo w voltage VOL IOL = 4.0mA, VCC = VCC MIN -0.45V
Output high voltage VOH IOH = -2.0 mA, VCC = VCC MIN 0.85×VCC -V
Low VCC lock out voltage VLKO 1.5 - V
Input HV select voltage VID 911V
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JEDEC
Symbol Std
Symbol Parameter -70R -80 -90 -120 UnitMin Max Min Max Min Max Min Max
tAVAV tRC Read cycle time 70 - 80 - 90 - 120 - ns
tAVQV tACC Address to output delay - 70 - 80 - 90 - 120 ns
tELQV tCE Chi p enable to output - 70 - 80 - 90 - 120 ns
tGLQV tOE Output enable to outp ut - 30 - 30 - 35 - 50 ns
tOES Out put ena ble setup time 0 - 0 - 0 - 0 - ns
tEHQZ tDF Chip enable to output High Z - 20 - 20 - 30 - 30 ns
tGHQZ tDF Output enable to outp ut High Z - 20 - 20 - 30 - 30 ns
tAXQX tOH Output hold time from addresses,
first occurrence of CE or OE 0-0-0-0-ns
tOEH
Output enable hold time: Read 10 - 10 - 10 - 10 - ns
Output enable hold time:
To ggle and data po lling 10 - 10 - 10 - 10 - ns
tPHQV tRH RESET high to output delay - 50 - 50 - 50 - 50 ns
tREADY RESET pin low to rea d mode - 10 - 10 - 10 - 1 0 µs
tRP RESET pulse 500 - 500 - 500 - 500 - n s
Addresses sta ble
Addresses
tRC
tACC
tOE
tOEH
tCE tOH
tDF
CE
OE
WE
Outputs High Z High Z
Output valid
tRH
RESET
tOES
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JEDEC
Symbol Std
Symbol Parameter
-70R -80 -90 -120
UnitMin Max Min Max Min Max Min Max
tAVAV tWC Write cyc l e time 70 - 80 - 90 - 120 - ns
tAVWL tAS Address setup time 0 - 0 - 0 - 0 - ns
tWLAX tAH Address hold time 45 - 45 - 45 - 50 - ns
tDVWH tDS Data setup time 35 - 35 - 45 - 50 - ns
tWHDX tDH Data hold time 0 - 0 - 0 - 0 - ns
tGHWL tGHWL Read reco ver time before write 0 - 0 - 0 - 0 - ns
tELWL tCS CE setup time 0-0-0-0-ns
tWHEH tCH CE hold time 0-0-0-0-ns
tWLWH tWP Write pulse width 35 - 35 - 35 - 50 - ns
tWHWL tWPH Write pulse width high 30 - 30 - 30 - 30 - ns
Addresses
CE
OE
WE
DATA
tWC tAS
tAH
tGHWL; tOES
tWP
tCS tWPH
tDH
tWHWH1 or 2
tDS
DQ7D
OUT
Program
555h Program ad dre ss Program addres s
3rd bus cycle
tCH
DATA polling
A0h data
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JEDEC
Symbol Std
Symbol Parameter
-70R -80 -90 -120
UnitMin Max Min Max Min Max Min Max
tAVAV tWC Write cycle time 70 - 80 - 90 - 120 - ns
tAVEL tAS Address setup time 0 - 0 - 0 - 0 - ns
tELAX tAH Address hold time 45 - 45 - 45 - 50 - ns
tDVEH tDS Data setup time 35 - 35 - 45 - 50 - ns
tEHDX tDH Data hold time 0 - 0 - 0 - 0 - ns
tGHEL tGHEL Read recover time before write 0 - 0 - 0 - 0 - ns
tWLEL tWS WE setup time 0 - 0 - 0 - 0 - ns
tEHWH tWH WE hold time 0 - 0 - 0 - 0 - ns
tELEH tCP CE pul se width 35 - 35 - 35 - 50 - ns
tEHEL tCPH CE pulse width high 30 - 30 - 30 - 30 - ns
Addresses
WE
OE
CE
DATA
Program address555h Program address
A0h Program DQ7D
OUT
tWC tAS tAH
tCP
tCPH tDH
tDS
tWHWH1 or 2
DATA polling
data
tGHEL, tOES
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JEDEC
Symbol Std Symbol Parameter
-70R/80/90/120
UnitMin Max
tVIDR VID rise and fall time 500 - ns
tRSP RESET setup time for temporary sector
unprotect 4-µs
JEDEC
Symbol Std Symbol Parameter
-70R/80/90/120
UnitMin Max
tRP RESET pulse 500 - ns
tRH RESET High time before Read -50ns
tREADY RESET Low to Read mode -10µs
RESET
CE
WE
RY/BY
0 or 3 V tVIDR tVIDR 0 or 3V
tRSP
Program/erase command sequence
10V
RESET
RY/BY
DQ
tRP
tREADY
tRP
tRH valid datavalid datastatusstatus
Addresses
CE
OE
WE
Data
555h 2AAh 555h 555h 2AAh Sector address
tWC tAS
tAH
tGHWL
AAh 55h 80h AAh 55h 30h
10h f or Chip Erase
tWP
tCS tWPH tDH
tDS
tWC
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JEDEC
Symbol Std Symbol Parameter
-70R/80/90/120
UnitMin Max
-t
VCS VCC setup time 50 - µs
-t
RB Recovery time from RY/BY 0- ns
-t
BUSY Progr am/er a se valid t o RY/B Y delay 90 - ns
CE
WE
RY/BY
Rising edge of last WE signal
Program/erase
operation
tri-stated open-drain
VCC tVCS
tRB
tBUSY
CE
OE
WE
DQ7
tCH
tOH
tWHWH1 or 2
tOE
tOEH
tCE
tDF
High Z
Input DQ7 Output DQ7Output
CE
WE
OE
DQ6
tOEH
tDH
tOE toggletoggle no toggle
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Includes all pins except VCC. Test conditions: VCC = 3.0V, one pin at a time.
Test Condition -70R,-80 -90, -120 Unit
Output Load 1 TTL gate
Output Load Capacitance CL (including jig capacitance) 30 100 pF
Input Rise and Fall Times 5ns
Input Pulse Levels 0.0-3.0 V
Input timing measurement reference le vels 1.5 V
Output timing measurement reference levels 1.5 V
Parameter Limits UnitMin Typical Max
Sector era se and ver ify-1 ti me (excludes 00h programm ing
prior to erase) -1.0 15 sec
Programming time Byte - 10 300 µs
Word - 15 360 µs
Chip programmi ng ti me - 7.2 27 sec
Erase/program cycles1
1 Erase/program cycle test is not verified on each shipped unit.
- 100,000 - cycles
Parameter Min Max Unit
Input voltage with respect to VSS on A9, OE, an d RESET pin -1.0 +12.0 V
Input voltage with respect to VSS on all DQ , address, and control pins -0.5 VCC+0.5 V
Current -100 +100 mA
.Ω
&/
.Ω
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966 966
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1
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Stresses gr eater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions outside those indicated in the operational sections of this specif ication is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect relia bility.
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Parameter Comments Symbol Min Max Unit
Supp ly voltage
)RUIXOOYROWDJHUDQJH Vcc +2.7 +3.6 V
)RUUHJXODWHGYROWDJHUDQJH Vcc +3.0 +3.6 V
VSS 00V
Input voltage VIH 1.9 VCC + 0.3 V
VIL –0.5 0.8 V
Parameter Symbol Min Max Unit
Input voltage (Input or DQ pi n) VIN –0.5 VCC+ 0.5 V
Input vol tage (A9 pi n, OE, RESE T)V
IN –0.5 +12.5 V
P ower supply voltage VCC -0.5 +4.0 V
Operating temperature T OPR –55 +125 °C
Stor age tem perature (plastic) TSTG –65 +150 °C
Short circ uit outp ut current IOUT -150mA
Symbol Paramet er Test setu p Typ Max Unit
CIN Input capacitance VIN = 0 6 7.5 pF
COUT Output capacitance VOUT = 0 8.5 12 p F
CIN2 Control pin capacitanc e VIN = 0 8 10 pF
Symbol Paramete r Test setu p Typ Max U nit
CIN Input capacitance VIN = 0 6 7.5 pF
COUT Output capacitance VOUT = 0 8.5 12 pF
CIN2 Control pin capacitance VIN = 0 8 10 pF
Parameter Temp.(°C) Min Unit
Minimum pattern data retention time 150° 10 years
125° 20 years
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e
b
E
HdD
48-pin
12×20
Min Max
A – 1.20
A1 0.05 0.15
A2 0.95 1.05
b0.170.27
c 0.15 nominal
D 18.20 18.60
e 0.50 n ominal
E 11.90 12.10
Hd 19.80 20.20
L0.500.70
α0° 5°
c
LA1AA2
48-pin
pin 1 pin 48
pin 24 pin 25
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JEDEC MO - 175 AA
44-pin SO
Min (mm) Max (mm)
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b 0.25 0.45
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e 12.4 12.8
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© Copyright Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names may be the trade-
marks of their respective companies. Alliance r eserves the right to make changes to this document and its products at any time without notice. Alliance assumes no responsibility f or any errors that may appear in this document.
The data contained herein represents Alliance’s best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any time, without notice. If the product described herein is under
development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate
as, or provide, any guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or
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tems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use.
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Package \ Access Time 70 ns
(commercial/industrial) 80 ns
(commercial/industrial) 90 ns
(commercial/industrial) 120 ns
(commercial/industrial)
TSOP, 12×20 mm, 48-pin
Top boot configur ation AS29LV800T-70R1TC
AS29LV800T-70RTI
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AS29LV800T-80TC
AS29LV800T-80TI AS29LV800T-90TC
AS29LV800T-90TI AS29LV800T-120TC
AS29LV800T-120TI
TSOP, 12×20 mm, 48-pin
Bottom boot configuration AS29LV800B-70RTC
AS29LV800B-70RTI AS29LV800B-80TC
AS29LV800B-80TI AS29LV800B-90TC
AS29LV800B-90TI AS29LV800B-120TC
AS29LV800B-120TI
SO2, 13.3 mm, 44-pinTop boot
configuration
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AS29LV800T-70RSC
AS29LV800T-70RSI AS29LV800T-80SC
AS29LV800T-80SI AS29LV800T-90SC
AS29LV800T-90SI AS29LV800T-120SC
AS29LV800T-120SI
SO, 13.3 mm, 44-pin
Bottom boot configuration AS29LV800B-70RSC
AS29LV800B-70RSI AS29LV800B-80SC
AS29LV800B-80SI AS29LV800B-90SC
AS29LV800B-90SI AS29LV800B-120SC
AS29LV800B-120SI
AS29LV 800 X –XXX X X X
3V Flash
EEPROM
prefix
Device
number T= Top boot configuration
B= Bottom boot configuration Address
acce ss time
Package:
S= SO
T= TSOP
Temperature range:
C = Commercial: 0°C to 70°C
I = Industrial: -40°C to 85°C
Options:
B = Burn-in
H= High ISB (<1mA)
Blan k= Standard