PE45361
Document Category: Product Specification
UltraCMOS® Power Limiter, 10 MHz–6 GHz
©2016-2017, Peregrine Semiconductor Corporation. All rights reserved. • Headquarters: 9380 Carroll Park Drive, San Diego, CA, 92121
Product Specification DOC-75388-4 – (04/2017)
www.psemi.com
Features
• Monolithic drop-in solution with no external bias
components
• Adjustable low power limiting threshold from
+7 dBm to +13 dBm
• High maximum power handling of 50 dBm,
100W pulsed
• Positive threshold control from +0V to +0.3V
• Fast response time of less than 1 ns
• Packaging – 12-lead 3 × 3 × 0.5 mm QFN
Applications
• Wireless infrastructure transceivers and antennas
• Test and measurement (T&M)
Product Description
The PE45361 is a HaRP™ technology-enhanced power limiter designed for use in high performance power
limiting applications in test and measurement equipment and wireless infrastructure transceivers and antennas.
Unlike traditional PIN diode solutions, the PE45361 achieves an adjustable input 1dB compression point or
limiting threshold via a low current control voltage (VCTRL), eliminating the need for external bias components
such as DC blocking capacitors, RF choke inductors and bias resistors.
It delivers low insertion loss and high linearity under non-limiting power levels and extremely fast response time
in a limiting event, ensuring protection of sensitive circuitry. It also offers excellent ESD rating and ESD
protection.
The PE45361 is manufactured on Peregrine’s UltraCMOS® process, a patented advanced form of silicon-on-
insulator (SOI) technology, offering the performance of GaAs with the economy and integration of conventional
CMOS.
Figure 1 • PE45361 Functional Diagram
Voltage Control and ESD
RF1
VCTRL
RF2
P
OUT
P1dB
P
IN
PE45361
Power Limiter
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Absolute Maximum Ratings
Exceeding absolute maximum ratings listed in Table 1 may cause permanent damage. Operation should be
restricted to the limits in Table 2. Operation between operating range maximum and absolute maximum for
extended periods may reduce reliability.
ESD Precautions
When handling this UltraCMOS device, observe the same precautions as with any other ESD-sensitive devices.
Although this device contains circuitry to protect it from damage due to ESD, precautions should be taken to
avoid exceeding the rating specified in Table 1.
Latch-up Immunity
Unlike conventional CMOS devices, UltraCMOS devices are immune to latch-up.
Table 1 • Absolute Maximum Ratings for PE45361
Parameter/Condition Min Max Unit
Control vo lt age, VCTRL
Power limiting mode 03.6V
RF input power, Pulsed(1) 50 dBm
Storage temperature range –65 +150 °C
ESD voltage HBM, all pins(2) 7000 V
ESD voltage CDM, all pins(3) 2000 V
Notes:
1) Pulsed, 1.0% duty cycle of 10 µs pulse width in 1 ms period, 50Ω at +25 °C.
2) Human bod y mo de l ( MIL -S TD 8 83 Me th od 30 15).
3) Charged device mo del ( JEDE C JESD 22-C 10 1).
DOC-75388-4 – (04/2017) Page 3
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PE45361
Power Limiter
Recommended Operating Conditions
Table 2 lists the recommended operating conditions for the PE45361. Devices should not be operated outside
the operating conditions listed below.
Table 2 • Recommended Operating Conditions for PE45361
Parameter Min Typ Max Unit
Control voltage, VCTRL
Power limiting mode
Power reflecting mode 0
0+0.3
+3.0 V
V
RF input power, CW(*) Fig. 2 dBm
Operating temperature range –55 +25 +105 °C
Operating max junction temperature +150 °C
Note: * See Fig. 2.
PE45361
Power Limiter
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Electrical Specifications
Table 3 provides the PE45361 key electrical specifications at +25 °C (ZS = ZL = 50Ω), unless otherwise
specified.
Table 3 • PE45361 Electrical Specifications
Parameter Condition Min Typ Max Unit
Operation frequency 10 MHz 6 GHz As
shown
Power limiting mode
Insertion loss 10 MHz–3 GHz
3–6 GHz 0.40
0.95 0.50
1.20 dB
dB
Return loss 10 MHz–3 GHz
3–6 GHz 22
12 dB
dB
P1dB/limiting threshold
VCTRL = 0V @ 915 MHz
VCTRL = +0.15V @ 915 MHz
VCTRL = +0.3V @ 915 MHz
13
10
7
dBm
dBm
dBm
Leakage power(1)
VCTRL = 0V @ 915 MHz
VCTRL = +0.15V @ 915 MHz
VCTRL = +0.3V @ 915 MHz
15.8
14.8
13.3
16.8
15.9
14.7
dBm
dBm
dBm
Input IP2 VCTRL = 0V @ 915 MHz
VCTRL = 0V @ 6 GHz 88
70 dBm
dBm
Input IP3 VCTRL = 0V @ 915 MHz
VCTRL = 0V @ 6 GHz 37
31 dBm
dBm
Response time 1 GHz 0.6 ns
Recovery time(4) 1 GHz, PIN, Pulse = 30 dBm 1.0 ns
Power reflecting mode(2)
Leakage power(1) VCTRL = +3.0V @ 915 MHz –41 –39 dBm
Switching time(3) State change to 10% RF 2.7 µs
Notes:
1) Measured with +3 0 dB m CW ap plied a t in pu t.
2) This mode requires the co ntr ol volt age t o t oggle be tw een +3 .0 V a nd 0V. At +3.0V, the lim iter e qui valen t cir cu it is a lo w impedance to ground,
reflecting most of the incide nt powe r back to the source.
3) State change is VCTRL toggle from 0V to +3.0V.
4) Pulsed, 1% duty cycle of 10 µs pulse width in 1 ms period, 50 Ω @ +25 °C.
DOC-75388-4 – (04/2017) Page 5
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PE45361
Power Limiter
Thermal Data
Psi-JT (ΨJT), junction top-of-package, is a thermal
metric to estimate junction temperature of a device on
the customer application PCB (JEDEC JESD51-2).
ΨJT = (TJ – TT)/P
where
ΨJT = junction-to-top of package characterization
parameter, °C/W
TJ = die junction temperature, °C
TT = package temperature (top surface, in the
center), °C
P = power dissipated by device, Watts
Power De-rating Curve
Figure 2 shows the power de-rating curve indicating maximum allowable operating RF input power (CW) up to
the part’s maximum operating ambient temperature of +105 °C. This RF input power maintains the maximum
operating junction temperature requirement of +150 °C.
Table 4 • Thermal Data for PE45361
Parameter Typ Unit
ΨJT 35 °C/W
ΘJA, junction-to-ambient thermal resistance 73 °C/W
Figure 2 • Power De-rating Curve, 10 MHz–6 GHz, +25 °C to +105 °C Ambient, CW, 50Ω(*)
Note: * High frequency CW power handling can be improved with 0.30pF capacitive matching on input and output RF ports.
27
28
29
30
31
32
33
34
35
36
37
1.00E+05 1.00E+06 1.00E+07 1.00E+08 1.00E+09 6.00E+09
Suggested Power (dBm)
Frequency (Hz)
25 C 85 C 105 C
PE45361
Power Limiter
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Dual Mode Operation
Power Limiting Mode
The PE45361 performs as a linear power limiter with
adjustable P1dB/limiting threshold. The P1dB/limiting
threshold can be adjusted by changing the control
voltage between 0V and +0.3V. If unbiased, or if
VCTRL = 0V, the PE45361 still offers power limiting
protection.
Power Reflecting Mode
Power reflecting mode requires a power detector to
sample the RF input power and a microcontroller to
toggle the limiter control voltage between +3.0V and
0V based on the system protection requirements. At
+3.0V, the limiter impedance to ground is less than 1Ω
and most of the incident power will be reflected back
to the source. At 0V, the device operates as in power
limiting mode.
DOC-75388-4 – (04/2017) Page 7
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PE45361
Power Limiter
Typical Performance Data
Fig. 3–Figure 16 show the typical performance data at +25 °C (ZS = ZL = 50Ω), unless otherwise specified.
Figure 3 • Insertion Loss vs Temp
Figure 4 • Input Return Loss vs Temp
-5
-4.5
-4
-3.5
-3
-2.5
-2
-1.5
-1
-0.5
0
0123456
Insertion Loss (dB)
Frequency (GHz)
-55 °C +25 °C +85 °C +1 05 °C
-45
-40
-35
-30
-25
-20
-15
-10
-5
0
0123456
Return Loss (dB)
Frequency (GHz)
-55 °C +25 °C +85 °C +105 °C
Figure 5 • Output Return Loss vs Temp
-45
-40
-35
-30
-25
-20
-15
-10
-5
0
0123456
Return Loss (dB)
Frequency (GHz)
-55 °C +25 °C +85 °C +105 °C
PE45361
Power Limiter
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Figure 6 • POUT vs PIN Over VCTRL (Limiting Mode @
915 MHz)
Figure 7 • POUT vs PIN Over VCTRL (Limiting Mode @
6 GHz)
Figure 8 • P1dB vs VCTRL Over Temp @ 915 MHz
-2
0
2
4
6
8
10
12
14
16
18
20
0 5 10 15 20 25 30 35 40
Pout (dBm)
Pin (dBm)
0 V 0.15 V 0.3 V
-2
0
2
4
6
8
10
12
14
16
18
20
0 5 10 15 20 25 30 35
Pout (dBm)
Pin (dBm)
0 V 0.15 V 0.3 V
0
2
4
6
8
10
12
14
0 0.05 0.1 0.15 0.2 0.25 0.3
P1dB (dBm)
VCTRL (V)
-55 °C +25 °C +85 °C +105 °C
Figure 9 • POUT vs PIN Over VCTRL (Reflecting Mode @
915 MHz)
Figure 10 • POUT vs PIN Over VCTRL (Reflecting Mode @
6 GHz)
Figure 11 • P1dB vs VCTRL Over Temp @ 6 GHz
-80
-70
-60
-50
-40
-30
-20
-10
0
0 5 10 15 20 25 30 35 40
Pout (dBm)
Pin (dBm)
1 V 2 V 3 V
-60
-50
-40
-30
-20
-10
0
0 5 10 15 20 25 30 35
Pout (dBm)
Pin (dBm)
1 V 2 V 3 V
0
2
4
6
8
10
12
14
0 0.05 0.1 0.15 0.2 0.25 0.3
P1dB (dB)
V
CTRL
(V)
-55 °C +25 °C +85 °C +105 °C
DOC-75388-4 – (04/2017) Page 9
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PE45361
Power Limiter
Figure 12 • Leakage Power @ PMAX vs VCTRL Over Temp
@ 915 MHz
Figure 13 • IIP2/IIP3 vs PIN Over VCTRL @ 915 MHz
Figure 14 • IIP2/IIP3 vs VCTRL Over PIN @ 915 MHz
0
2
4
6
8
10
12
14
16
18
0 0.05 0.1 0.15 0.2 0.25 0.3
Leakage Power (dBm)
VCTRL
(V)
-55 °C +25 °C +85 °C +105 °C
0
20
40
60
80
100
-10 0 10 20
IIP2/IIP3 (dBm)
PIN (dBm)
IIP2 @ VCTRL = 0V
IIP2 @ VCTRL = 0.15V
IIP2 @ VCTRL = 0.3V
IIP3 @ VCTRL = 0V
IIP3 @ VCTRL = 0.15V
IIP3 @ VCTRL = 0.3V
0
20
40
60
80
100
0 0.1 0.2 0.3
IIP2/IIP3 (dBm)
VCTRL
IIP2 @ Pin = -5dBm
IIP2 @ Pin = 0dBm
IIP2 @ Pin = 5dBm
IIP3 @ Pin = -5dBm
IIP3 @ Pin = 0dBm
IIP3 @ Pin = 5dBm
Figure 15 • Leakage Power @ PMAX vs VCTRL Over Temp
@ 6 GHz
Figure 16 • IIP2/IIP3 vs PIN Over VCTRL @ 6 GHz
Figure 17 • IIP2/IIP3 vs VCTRL Over PIN @ 6 GHz
0
2
4
6
8
10
12
14
0 0.05 0.1 0.15 0.2 0.25 0.3
Leakage Power (dBm)
V
CTRL
(V)
-55 °C +25 °C +85 °C +105 °C
16
18
0
20
40
60
80
-10-5 0 5 10152025
IIP2/IIP3 (dBm)
P
IN
IIP2 @ VCTRL = 0V IIP3 @ VCTRL = 0V
IIP2 @ VCTRL = 0.3V IIP3 @ VCTRL = 0.3V
IIP2 @ VCTRL = 0.15V IIP3 @ VCTRL = 0.15V
(dBm)
0
20
40
60
80
00.10.20.3
IIP2/IIP3 (dBm)
V
CTRL
IIP2 @ Pin = -5dBm IIP3 @ Pin = -5dBm
IIP2 @ Pin = 0dBm IIP3 @ Pin = 0dBm
IIP2 @ Pin = 5dBm IIP3 @ Pin = 5dBm
PE45361
Power Limiter
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Evaluation Kit
The power limiter evaluation kit board (EVB) was designed to ease customer evaluation of Peregrine’s
PE45361. The uni-directional RF input and output are connected to the RF1 and RF2 port through a 50Ω trans-
mission line via SMA connectors J2 and J3. A through 50Ω transmission line is available via SMA connectors J5
and J6. This transmission line can be used to estimate the loss of the PCB over the environmental conditions
being evaluated. The 2-pin connector J4 is connected to the external bias VCTRL.
The board is constructed of a four metal layer material with a total thickness of 62 mils. The top RF layer is
Rogers RO4350B material with a 6.6 mil RF core and ƐR = 3.66. The middle layers provide ground for the trans-
mission lines. The transmissio n lines were de signed using a coplanar wave quide with ground plane model using
a trace width of 13.5 mils, trace gaps of 10 mils, and metal thickness of 2.1 mils.
Figure 18 • Evaluation Kit Layout for PE45361
DOC-75388-4 – (04/2017) Page 11
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PE45361
Power Limiter
Pin Information
This section provides pinout information for the
PE45361. Figure 19 shows the pin map of this device
for the available package. Table 5 provides a
description fo r each pin.
Figure 19 • Pin Configuration (Top View)
Table 5 • Pin Descriptions for PE45361
Pin No. Pin
Name Description
1, 3, 4, 6, 7 ,
9GND Ground
2RF1(1)(3) RF port 1
5VCTRL Control voltage
8RF2(1)(3) RF port 2
10–12 N/C(2) No connect
Pad GND Exposed pad: ground for proper oper-
ation
Notes:
1) RF pins 2 and 8 must be at 0 VDC. The RF pins do not require DC
blocking capacitors for proper operat ion if the 0 VDC requirement
is met.
2) Pins 10–12 can b e grou nd ed if d eeme d n ecessar y by th e cu s-
tomer.
3) The limiter is not bi-directional. RF1 is the RF input and RF2 is the
RF output.
PE45361
Power Limiter
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Packaging Information
This section provides packaging data including the moisture sensitivity level, package drawing, package
marking and tape-and-reel information.
Moisture Sensitivity Level
The moisture sensitivity level rating for the PE45361 in the 12-lead 3 × 3 × 0.5 mm QFN package is MSL1.
Package Drawing
Top-Marking Specification
Figure 20 • Package Mechanical Drawing for 12-lead 3 × 3 × 0.5 mm QFN
Figure 21 • Package Marking Specifications for PE45361
TOP VIEW BOTTOM VIEW
SIDE VIEW
RECOMMENDED LAND PATTERN
A0.10 C
(2X)
C
0.10 C
0.05 C
SEATING PLANE
B
0.10 C
(2X)
0.10 C A B
0.05 C
ALL FEATURES
PIN #1 CORNER
3.00
3.00
0.50±0.05
0.02
0.152
Ref.
1.80±0.10
1.80±0.10
1.00
Ref.
0.50
0.25±0.05
(x12)
0.30±0.05
(x12)
(x8)
0.30
(x12)
0.70
(x12)
1.90
3.80
3.10
1.90
0.50
(x8)
=
YY =
WW =
ZZZZZZ =
Pin 1 indicator
Last two digits of assembly year
Assembly work week
Assembly lot code (maximum six characters)
45361
YYWW
ZZZZZZ
DOC-75388-4 – (04/2017) Page 13
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PE45361
Power Limiter
Tape and Reel Specification
Figure 22 • Tape and Reel Specifications for 12-lead 3 × 3 × 0.5 mm QFN
.
T
K0 A0
B0
P0 P1 D1 A
Section A-A
A
Direction of Feed
D0
E
W0
P2
see note 3
see
note 1
F
see note 3
A0
B0
K0
D0
D1
E
F
P0
P1
P2
T
W0
3.3
3.3
1.10
1.50 + 0.10/ -0.00
1.50 min
1.75 ± 0.10
5.50 ± 0.05
4.00
8.00
2.00 ± 0.05
0.30 ± 0.05
12.00 ± 0.30 Device Orientation in Tape
Pin 1
Notes:
1. 10 Sprocket hole pitch cumulative tolerance ±0.2
2. Camber in compliance with EIA 481
3. Pocket position relative to sprocket hole measured
as true position of pocket, not pocket hole
Dimensions are in milimeters unless otherwise specified
PE45361 Power Limiter
Product Specification www.psemi.com DOC-75388-4 – (04/2017)
Document Categories
Advance Information
The product is in a formative or design stage. The datasheet contains design target specifications for product development. Specifications and
features may change in any manner without notice.
Preliminary Specification
The datasheet contains preliminary data. Additional data may be added at a later date. Peregrine reserves the right to change specifications at any
time without notice in order to supply the best possible product.
Product Specification
The datasheet contains final data. In the event Peregrine decides to change the specifications, Peregrine will notify customers of the intended
changes by issuing a CNF (Customer Notification Form).
Sales Contact
For additional information, contact Sales at sales@psemi.com.
Disclaimers
The information in this document is believed to be reliable. However, Peregrine assumes no liability for the use of this information. Use shall be
entirely at the user’s own risk. No patent rights or licenses to any circuits described in this document are implied or granted to any third party.
Peregrine’s products are not designed or intended for use in devices or systems intended for surgical implant, or in other applications intended to
support or sustain life, or in any application in which the failure of the Peregrine product could create a situation in which personal injury or death
might occur. Peregrine assumes no liability for damages, including consequential or incidental damages, arising out of the use of its products in
such applications.
Patent Statement
Peregrine products are protected under one or more of the following U.S. patents: patents.psemi.com
Copyright and Trademark
©2016-2017, Peregrine Semiconductor Corporation. All rights reserved. The Peregrine name, logo, UTSi and UltraCMOS are registered trade-
marks and HaRP, MultiSwitch and DuNE are trademarks of Peregrine Semiconductor Corp.
Ordering Information
Table 6 lists the available ordering codes for the PE45361 as well as available shipping methods.
Table 6 • Order Codes for PE45361
Order Codes Description Packaging Shipping Method
PE45361A–X PE45361 Power limiter 12-lead 3 × 3 × 0.5 mm QFN 500 units/T&R
EK45361–01 PE45361 Evaluation kit Evaluation kit 1/box