Triple Differential Driver
for Wideband Video
AD8146/AD8147/AD8148
Rev. A
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FEATURES
Triple high speed fully differential driver
700 MHz, −3 dB, 2 V p-p bandwidth (AD8146/AD8148)
600 MHz, −3 dB, 2 V p-p bandwidth (AD8147)
200 MHz, 0.1 dB, 2 V p-p bandwidth
3000 V/μs slew rate
Fixed gain (AD8146/AD8147: G = 2, AD8148: G = 4)
Differential or single-ended input to differential output
Can be used as differential-to-differential receiver
Drives one or two 100 Ω UTP cables
Adjustable output common-mode voltage (AD8146)
Internal common-mode feedback network
Output balance error −50 dB @ 50 MHz
On-chip, sync-on common-mode encoding (AD8147/AD8148)
Output pull-down feature for line isolation
Low power: 57 mA @ 5 V for 3 drivers (AD8146)
Wide supply voltage range: +5 V to ±5 V
Available in a small 4 mm × 4 mm LFCSP
APPLICATIONS
QXGA or 1080p video transmission
KVM networking
Video over unshielded twisted pair (UTP)
Differential signal multiplexing
FUNCTIONAL BLOCK DIAGRAMS
AD8146
OPD
1
V
S– 2
–IN A
3
+IN A
4
V
S– 5
V
OCM
C
V
S+
–IN C
+IN C
V
S–
18
17
16
15
14
–OUT A
6
–OUT C
13
V
S+
–IN B
+IN B
V
S–
V
OCM
A
24 23 22 21 20
V
OCM
B
19
+OUT A
V
S+
+OUT B
–OUT B
V
S+
78910 11
+OUT
C
12
ABC
09327-001
Figure 1.
AD8147/
AD8148
OPD
1
V
S– 2
–IN R
3
+IN R
4
V
S– 5
SYNC LEVEL
V
S+
(SYNC)
–IN B
+IN B
V
S–
18
17
16
15
14
–
OUT
R
6
–OUT B
13
V
S+
–IN G
+IN G
V
S–
(SYNC)
V
SYNC
24 23 22 21 20
H
SYNC
19
+OUT
R
V
S+
+OUT G
–OUT G
V
S+
78910 11
+OUT B
12
ABC
×2
09327-002
Figure 2.
GENERAL DESCRIPTION
The AD8146/AD8147/AD8148 are high speed triple, differential or
single-ended input to differential output drivers. The AD8146
and AD8147 have a fixed gain of 2, and the AD8148 has a fixed
gain of 4. They are all specifically designed for the highest
resolution component video signals but can be used for any
type of analog signals or high speed data transmission over
either Category 5 UTP cable or differential printed circuit
board (PCB) transmission lines.
These drivers can be used with the AD8145 triple differential-
to-singled-ended receiver, and the AD8117 crosspoint switch to
produce a video distribution system capable of supporting
UXGA or 1080p signals.
Manufactured on the Analog Devices, Inc. second generation
XFCB bipolar process, the drivers have large signal bandwidths
of 700 MHz and fast slew rates. They have an internal common-
mode feedback feature that provides output amplitude and
phase matching that is balanced to −60 dB at 50 MHz, suppressing
even-order harmonics and minimizing radiated
electromagnetic interference (EMI).
The common-mode voltage of each AD8146 output can be set
to any level, allowing transmission of signals over the common-
mode voltages. The AD8147 and AD8148 encode the vertical
and horizontal sync signals on the common-mode voltages of
the outputs. All outputs can be independently set to low voltage
states to be used with series diodes for line isolation, allowing
easy differential multiplexing over the same twisted pair cable.
The AD8146/AD8147/AD8148 are available in a 24-lead LFCSP
and operate over a temperature range of −40°C to +85°C.
AD8146/AD8147/AD8148
Rev. A | Page 2 of 24
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagrams ............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Absolute Maximum Ratings ............................................................ 7
Thermal Resistance ...................................................................... 7
ESD Caution .................................................................................. 7
Pin Configurations and Function Descriptions ........................... 8
Typical Performance Characteristics ........................................... 10
Theory of Operation ...................................................................... 14
Definition of Terms .................................................................... 14
Analyzing an Application Circuit ............................................. 14
Closed-Loop Gain ...................................................................... 14
Calculating the Input Impedance ............................................. 15
Input Common-Mo de Voltage Range in Single-Supply
Applications ................................................................................ 15
Output Common-Mode Control ............................................. 15
Sync-On Common-Mode ......................................................... 15
Applications ..................................................................................... 16
Driving RGB Video Signals Over Category-5 UTP Cable.... 16
Video Sync-On Common-Mode .............................................. 16
Driving Two UTP Cables With One Driver ........................... 18
Using the AD8146 as a Receiver ............................................... 18
Output Pull-Down (OPD) ........................................................ 19
Layout and Power Supply Decoupling Considerations ......... 19
Driving a Capacitive Load ......................................................... 19
Adding Pre-Emphasis to the AD8148 ..................................... 20
Exposed Paddle (EP).................................................................. 21
Outline Dimensions ....................................................................... 22
Ordering Guide .......................................................................... 22
REVISION HISTORY
8/10—Rev. 0 to Rev. A
Changes to Table 1 ............................................................................ 3
Changes to Table 2 ............................................................................ 5
Changes to Pin Configurations and Function Descriptions
Section ................................................................................................ 8
Changes to Adding Pre-Emphasis to the AD8148 Section ....... 20
Updated Outline Dimensions ....................................................... 22
5/07—Revision 0: Initial Version
AD8146/AD8147/AD8148
Rev. A | Page 3 of 24
SPECIFICATIONS
VS = ±5V, VOCM = 0 V (AD8146); SYNC LEVEL = 0 V (AD8147/AD8148); T = 25°C; RL, dm = 200 Ω, unless otherwise noted.
TMIN to TMAX = −40°C to +85°C.
Table 1.
Parameter Conditions Min Typ Max Unit
DIFFERENTIAL INPUT AC
Dynamic Performance
−3 dB Small Signal Bandwidth VO = 0.2 V p-p,
AD8146/AD8148 900 MHz
AD8147 780 MHz
−3 dB Large Signal Bandwidth VO = 2 V p-p,
AD8146/AD8148 700 MHz
AD8147 600 MHz
Bandwidth for 0.1 dB Flatness VO = 2 V p-p,
AD8146/AD8147 200 MHz
AD8148 235 MHz
Slew Rate VO = 2 V p-p, 25% to 75% 3000 V/µs
Isolation Between Amplifiers f = 10 MHz
AD8146/AD8147 −86 dB
AD8148 −80 dB
DIFFERENTIAL INPUT DC
Input Common-Mode Voltage Range −5 to +5 V
Input Resistance Differential 1.0 kΩ
Single-ended input
AD8146/AD8147 750 Ω
AD8148 833 Ω
Input Capacitance Differential 2 pF
DC CMRR ΔVOUT, dm/ΔVIN, cm, ΔVIN, cm = ±1 V
AD8146/AD8147/AD8148 −53/−49/−55 dB
DIFFERENTIAL OUTPUT
Differential Signal Gain ΔVOUT, dm/ΔVIN, dm; ΔVIN, dm = ±1 V
AD8146/AD8147 1.94 2.00 V/V
ΔVOUT, dm/ΔVIN, dm; ΔVIN, dm = ±1 V
AD8148 3.8 4.0 V/V
Output Voltage Swing Each single-ended output
AD8146/AD8147/AD8148 −3/−2.25/−3.42 +3.4/+3.4/+3.5 V
Output Offset Voltage −19 +19 mV
Output Offset Drift TMIN to TMAX ±8 µV/°C
Output Balance Error ΔVOUT, cm/ΔVIN, dm, ΔVOUT, dm = 2 V p-p
f = 50 MHz
AD8146/AD8147 −52 dB
AD8148 −49 dB
DC
AD8146/AD8148 −41 dB
AD8147 −44 dB
Output Voltage Noise (RTO) f = 1 MHz
AD8146/AD8147 25 nV/√Hz
AD8148 42 nV/√Hz
Output Short-Circuit Current Short to GND, source/sink +87/−67 mA
AD8146/AD8147/AD8148
Rev. A | Page 4 of 24
Parameter Conditions Min Typ Max Unit
VOCM DYNAMIC PERFORMANCE (AD8146 ONLY)
−3 dB Bandwidth ΔVOCM = 100 mV p-p 340 MHz
Slew Rate VOCM = −1 V to +1 V, 25% to 75% 800 V/μs
DC Gain ΔVOCM = ±1 V 0.98 1.00 V/V
VOCM INPUT CHARACTERISTICS (AD8146 ONLY)
Input Voltage Range ±3 V
Input Resistance 12.5 kΩ
Input Offset Voltage −36 +36 mV
DC CMRR ΔVOUT, dm/ΔVOCM, ΔVOCM = ±1 V −48 dB
SYNC DYNAMIC PERFORMANCE (AD8147/
AD8148 ONLY)
Slew Rate VOUT, cm = −1 V to +1 V; 25% to 75% 1000 V/μs
HSYNC AND VSYNC INPUTS (AD8147/AD8148
ONLY)
Low-to-High Threshold 1.5 to1.7 V
High-to-Low Threshold 1.5 to1.7 V
SYNC LEVEL INPUT (AD8147/AD8148 ONLY)
Setting to 0.5 V Pulse Levels 0.5 V
Gain to Red Common-Mode Output ΔVO, cm/ΔVSYNC LEVEL, AD8147/AD8148 0.93/0.96 1.10/1.05 V/V
Gain to Green Common-Mode Output ΔVO, cm/ΔVSYNC LEVEL, AD8147/AD8148 1.91/1.93 2.15/2.08 V/V
Gain to Blue Common-Mode Output ΔVO, cm/ΔVSYNC LEVEL, AD8147/AD8148 −1.10/−1.05 −0.93/−0.96 V/V
POWER SUPPLY
Operating Range +4.5 ±5.5 V
Quiescent Current, Positive Supply AD8146/AD8147/AD8148 58/61.5/62.5 mA
Disabled
AD8146 6 mA
AD8147/AD8148 21.5 mA
Quiescent Current, Negative Supply AD8146/AD8147/AD8148 −58/−60.5/−62 mA
Disabled −37 mA
PSRR ΔVOUT, dm/ΔVS; ΔVS = ±1 V
AD8146/AD8147/AD8148 −66/−52/−55 dB
OUTPUT PULL-DOWN
OPD Input Low Voltage 1.1 V
OPD Input High Voltage 2.1 V
OPD Input Bias Current 520 μA
OPD Assert Time 1 μs
OPD Deassert Time 10 ns
Output Voltage When OPD Asserted Each output, OPD input @ VS+ −3.8 V
AD8146/AD8147/AD8148
Rev. A | Page 5 of 24
VS = +5 V or ±2.5 V; VOCM = midsupply (AD8146); SYNC LEVEL = 0 V (AD8147/AD8148); T = 25°C; RL, dm = 200 Ω, unless otherwise noted.
TMIN to TMAX = −40°C to +85°C.
Table 2.
Parameter Conditions Min Typ Max Unit
DIFFERENTIAL INPUT AC
Dynamic Performance
−3 dB Small Signal Bandwidth VO = 0.2 V p-p,
AD8146 870 MHz
AD8147/AD8148 680 MHz
−3 dB Large Signal Bandwidth VO = 2 V p-p,
AD8147 590 MHz
AD8146/AD8148 620 MHz
Bandwidth for 0.1 dB Flatness VO = 2 V p-p,
AD8146/AD8147 165 MHz
AD8148 200 MHz
DIFFERENTIAL INPUT DC
Input Common-Mode Voltage Range 0 to 5 V
Input Resistance Differential 1.0 kΩ
Single-ended input
AD8146/AD8147 750 Ω
AD8148 833 Ω
Input Capacitance Differential 2 pF
DC CMRR ΔVOUT, dm/ΔVIN, cm; ΔVIN, cm = ±1 V,
AD8146/AD8147/AD8148 −49/−45/−49 dB
DIFFERENTIAL OUTPUT
Differential Signal Gain ΔVOUT, dm/ΔVIN, dm; ΔVIN, dm = ±1 V,
AD8146/AD8147 1.94 2.00 V/V
ΔVOUT, dm/ΔVIN, dm; ΔVIN, dm = ±1 V
AD8148 3.80 4.00 V/V
Output Voltage Swing Each single-ended output, VS = ±2.5 V −1.17 +1.24 V
Output Offset Voltage −17 +17 mV
Output Offset Drift TMIN to TMAX ±8 μV/°C
Output Balance Error ΔVOUT, cm/ΔVIN, dm, ΔVOUT, dm = 2 V p-p,
f = 50 MHz −53 dB
AD8146/AD8147 −49 dB
AD8148
DC
AD8146/AD8148 −41 dB
AD8147 −44 dB
Output Voltage Noise (RTO) f = 1 MHz
AD8146/AD8147 25 nV/√Hz
AD8148 42 nV/√Hz
Output Short-Circuit Current Short to GND, source/sink +63/−48 mA
VOCM DYNAMIC PERFORMANCE (AD8146
ONLY)
−3 dB Bandwidth ΔVOCM = 100 mV p-p 310 MHz
Slew Rate VOCM = −1 V to +1 V, 25% to 75% 800 V/μs
DC Gain ΔVOCM = ±1 V 0.98 1.00 V/V
AD8146/AD8147/AD8148
Rev. A | Page 6 of 24
Parameter Conditions Min Typ Max Unit
VOCM INPUT CHARACTERISTICS (AD8146
ONLY)
Input Voltage Range ±1.2 V
Input Resistance 12.5 kΩ
Input Offset Voltage −36 +36 mV
DC CMRR ΔVO, dm/ΔVOCM; ΔVOCM = ±1 V −42 dB
SYNC DYNAMIC PERFORMANCE (AD8147/
AD8148 ONLY)
Slew Rate VOUT, cm = −1 V to +1 V; 25% to 75% 800 V/μs
HSYNC AND VSYNC INPUTS (AD8147/AD8148
ONLY)
Low-to-High Threshold 1.3 to 1.5 V
High-to-Low Threshold 1.3 to 1.5 V
SYNC LEVEL INPUT (AD8147/AD8148 ONLY)
Setting to 0.5 V Pulse Levels 0.5 V
Gain to Red Common-Mode Output ΔVO, cm/ΔVSYNC LEVEL, AD8147/AD8148 0.88/0.92 1.07/1.04 V/V
Gain to Green Common-Mode Output ΔVO, cm/ΔVSYNC LEVEL, AD8147/AD8148 1.83/1.85 2.08/2.00 V/V
Gain to Blue Common-Mode Output ΔVO, cm/ΔVSYNC LEVEL, AD8147/AD8148 −1.07/−1.04 −0.88/−0.92 V/V
POWER SUPPLY
Operating Range +4.5 ±5.5 V
Quiescent Current Positive Supply AD8146/AD8147/AD8148 50/55.5/ 54 mA
Disable
AD8146 4 mA
AD8147/AD8148 12 mA
Quiescent Current Negative Supply AD8146/AD8147/AD8148 −50/−55/−53 mA
Disabled
AD8146/AD8147/ AD8148 −14/−18.2/−15 mA
PSRR ΔVOUT, dm/ΔVS; ΔVS = ±1 V,
AD8146/AD8147/AD8148 −70/−52/-60 dB
OUTPUT PULL-DOWN
OPD Input Low Voltage 1.0 V
OPD Input High Voltage 2.0 V
OPD Input Bias Current 160 μA
OPD Assert Time 600 ns
OPD Deassert Time 10 ns
Output Voltage When OPD Asserted Each output, OPD input @ VS+ −1.6 V
AD8146/AD8147/AD8148
Rev. A | Page 7 of 24
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Rating
Supply Voltage 11 V
All VOCM ±VS
Power Dissipation See Figure 3
Input Common-Mode Voltage ±VS
Storage Temperature Range −65°C to +125°C
Operating Temperature Range −40°C to +85°C
Lead Temperature (Soldering, 10 sec) 300°C
Junction Temperature 150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, θJA is
specified for the device soldered in a circuit board in still air.
Table 4. Thermal Resistance with the Underside Pad
Connected to the Plane
Package Type/PCB Type θJA Unit
24-Lead LFCSP/4-Layer 57 °C/W
Maximum Power Dissipation
The maximum safe power dissipation in the AD8146/
AD8147/AD8148 package is limited by the associated rise in
junction temperature (TJ) on the die. At approximately 150°C,
which is the glass transition temperature, the plastic changes its
properties. Even temporarily exceeding this temperature limit
can change the stresses that the package exerts on the die,
permanently shifting the parametric performance of the
AD8146/AD8147/AD8148. Exceeding a junction temperature
of 175°C for an extended time can result in changes in the
silicon devices, potentially causing failure.
The power dissipated in the package (PD) is the sum of the
quiescent power dissipation and the power dissipated in the
package due to the load drive for all outputs. The quiescent
power is the voltage between the supply pins (VS) times the
quiescent current (IS). The load current consists of differential
and common-mode currents flowing to the loads, as well as
currents flowing through the internal differential and common-
mode feedback loops. The internal resistor tap used in the
common-mode feedback loop places a 4 kΩ differential load on
the output. Differential feedback, network resistor values are
given in the Theory of Operation section and Applications
section. RMS output voltages should be considered when
dealing with ac signals.
Airflow reduces θJA. In addition, more metal directly in contact
with the package leads from metal traces, through holes,
ground, and power planes reduces the θJA. The exposed paddle
on the underside of the package must be soldered to a pad on
the PCB surface that is thermally connected to a ground plane
to achieve the specified θJA.
Figure 3 shows the maximum safe power dissipation in the
package vs. the ambient temperature for the 24-lead LFCSP
(57°C/W) package on a JEDEC standard 4-layer board with the
underside paddle soldered to a pad that is thermally connected
to a ground plane. θJA values are approximations.
3.5
0
–40 –20 020 40 60 80
AMBI E NT TE M P E RATURE ( °C)
MAXIMUM POWER DISSIPATIO N (W)
3.0
2.5
2.0
1.5
1.0
0.5
09327-021
Figure 3. Maximum Power Dissipation vs. Temperature for a 4-Layer Board
ESD CAUTION
AD8146/AD8147/AD8148
Rev. A | Page 8 of 24
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
1OPD 2V
S–
3–IN A 4+IN A 5V
S–
6–OUT A
NOTES
1. THE EX P OSE D P ADDLE O N THE UNDE RS IDE O F T HE
CHIP M US T BE CO NNE CTED TO A GRO UND P LANE.
15 +IN C
16 –IN C
17 V
S+
18 V
OCM
C
14 V
S–
13 –OUT C
7+OUT A 8V
S+
9+OUT B
11V
S+
12+OUT C
10–OUT B 21 V
S–
22 +IN B
23 –IN B
24 V
S+
20 V
OCM
A
19 V
OCM
B
AD8146
TOP VI EW
(No t t o Scal e)
09327-004
Figure 4. AD8146 Pin Configuration
Table 5. AD8146 Pin Function Descriptions
Pin No. Mnemonic Description
1 OPD Output Pull-Down.
2, 5, 14, 21 VS− Negative Power Supply Voltage.
3 −IN A Inverting Input, Amplifier A.
4 +IN A Noninverting Input, Amplifier A.
6 −OUT A Negative Output, Amplifier A.
7 +OUT A Positive Output, Amplifier A.
8, 11, 17, 24 VS+ Positive Power Supply Voltage.
9 +OUT B Positive Output, Amplifier B.
10 −OUT B Negative Output, Amplifier B.
12 +OUT C Positive Output, Amplifier C.
13 −OUT C Negative Output, Amplifier C.
15 +IN C Noninverting Input, Amplifier C.
16 −IN C Inverting Input, Amplifier C.
18 VOCMC The voltage applied to this pin controls output common-mode voltage, Amplifier C.
19 VOCMB The voltage applied to this pin controls output common-mode voltage, Amplifier B.
20 V
OCM
A The voltage applied to this pin controls output common-mode voltage, Amplifier A.
22 +IN B Noninverting Input, Amplifier B.
23 −IN B Inverting Input, Amplifier B.
Exposed Paddle GND Signal Ground Reference.
AD8146/AD8147/AD8148
Rev. A | Page 9 of 24
PIN 1
INDICATOR
1OPD 2VS– 3–IN R 4+IN R 5VS– 6–OUT R
15 +IN B
16 –IN B
17 VS+ (SYNC)
18 SYNC LEVEL
14 VS–
13 –OUT B
7+OUT R 8VS+ 9+OUT G
11VS+ 12+OUT B
10–OUT G 21 VS– (SYNC)
22 +IN G
23 –IN G
24 VS+
20 VSYNC
19 HSYNC
AD8147/
AD8148
TOP VI EW
(No t t o Scal e)
09327-005
NOTES
1. THE EX P OSE D P ADDLE O N THE UNDE RS IDE O F T HE
CHIP M US T BE CO NNE CTED TO A GRO UND P LANE.
Figure 5. AD8147/AD8148 Pin Configuration
Table 6. AD8147/AD8148 Pin Function Descriptions
Pin No. Mnemonic Description
1 OPD Output Pull-Down.
2, 5, 14 V
S−
Negative Power Supply Voltage.
3 −IN R Inverting Input, Red Amplifier.
4 +IN R Noninverting Input, Red Amplifier.
6 −OUT R Negative Output, Red Amplifier.
7 +OUT R Positive Output, Red Amplifier.
8, 11, 24 V
S+
Positive Power Supply Voltage.
9 +OUT G Positive Output, Green Amplifier.
10 −OUT G Negative Output, Green Amplifier.
12 +OUT B Positive Output, Blue Amplifier.
13 −OUT B Negative Output, Blue Amplifier.
15 +IN B Noninverting Input, Blue Amplifier.
16 −IN B Inverting Input, Blue Amplifier.
17 VS+ (SYNC) Positive Power Supply Voltage for Sync.
18 SYNC LEVEL The voltage applied to this pin controls the amplitude of the sync pulses that are applied to
the common-mode voltages.
19 HSYNC Horizontal Sync Pulse Input.
20 V
SYNC
Vertical Sync Pulse Input.
21 VS− (SYNC) Negative Power Supply Voltage for Sync.
22 +IN G Noninverting Input, Green Amplifier.
23 −IN G Inverting Input, Green Amplifier.
Exposed Paddle GND Signal Ground Reference.
AD8146/AD8147/AD8148
Rev. A | Page 10 of 24
TYPICAL PERFORMANCE CHARACTERISTICS
VS = ±5V; VOCM = 0 V (AD8146); SYNC LEVEL = 0 V (AD8147/AD8148); T = 25°C; RL, dm = 200 Ω; CL, dm = 0 pF, unless otherwise noted.
TMIN to TMAX = −40°C to +85°C.
9
–110 1000
FREQUENCY (MHz)
GAIN (d B)
100
8
7
6
5
4
3
2
1
0
V
OUT, dm
= 2V p-p
AD8146 (±2. 5V )
AD8146 (±5. 0V )
AD8147 (±2. 5V )
AD8147 (±5. 0V )
09327-010
Figure 6. AD8146/AD8147 Large Signal Frequency Response for Various Supplies
Figure 7. AD8146/AD8147 Small Signal Frequency Response for Various Supplies
6.5
5.5 11000
FREQUENCY (MHz)
GAIN (d B)
VOUT, dm = 2V p-p
AD8146 (±2. 5V )
AD8146 (±5. 0V )
AD8147 (±2. 5V )
AD8147 (±5. 0V )
10 100
6.4
6.3
6.2
6.1
6.0
5.9
5.8
5.7
5.6
09327-012
Figure 8. AD8146/AD8147 Large Signal 0.1 dB Flatness for Various Supplies
15
510 1000
FREQUENCY (MHz)
GAIN (d B)
100
14
13
12
11
10
9
8
7
6
VOUT, dm = 2V p-p
±5.0V
±2.5V
09327-013
Figure 9. AD8148 Large Signal Frequency Response for Various Supplies
15
510 1000
FREQUENCY (MHz)
GAIN (d B)
100
14
13
12
11
10
9
8
7
6
VOUT, dm = 0.2V p - p
±2.5V
±5.0V
09327-014
Figure 10. AD8148 Small Signal Frequency Response for Various Supplies
12.5
11.5 11000
FREQUENCY (MHz)
GAIN (d B)
10 100
12.4
12.3
12.2
12.1
12.0
11.9
11.8
11.7
11.6
±5.0V
±2.5V
V
OUT, dm
= 2V p-p
09327-015
Figure 11. AD8148 Large Signal 0.1 dB Flatness for Various Supplies
AD8146/AD8147/AD8148
Rev. A | Page 11 of 24
1.5
–1.5 020
TIME (n s)
VOLT AGE (V)
1.0
0.5
0
–0.5
–1.0
246810 12 14 16 18
VS = ±2. 5V
VS = ±5. 0V
VOUT, dm = 2V p-p
09327-016
Figure 12. AD8146/AD8147 Large Signal Transient Response for Various Supplies
150
–150 020
TIME (n s)
VOLT AGE (mV)
100
50
0
–50
–100
246810 12 14 16 18
VOUT, dm = 0.2V p - p
VS = ±2. 5V
VS = ±5. 0V
09327-017
Figure 13. AD8146/AD8147 Small Signal Transient Response for Various Supplies
–20
–70 11000
FREQUENCY (MHz)
OUTPUT BALANCE E RROR (d B)
10 100
–25
–30
–35
–40
–45
–50
–55
–60
–65
ΔVOUT, cm/ΔVOUT, dm
ΔVO UT, dm = 2V p-p
AD8147
AD8148
AD8146
09327-024
Figure 14. Output Balance vs. Frequency
1.5
–1.5 020
TIME (n s)
VOLT AGE (V)
1.0
0.5
0
–0.5
–1.0
246810 12 14 16
18
VOUT, dm = 2V p-p
VS = ±2. 5V
VS = ±5. 0V
09327-019
Figure 15. AD8148 Large Signal Transient Response for Various Supplies
150
–150 020
TIME (n s)
VOLT AGE (mV)
100
50
0
–50
–100
246810 12 14 16 18
VOUT, dm = 0.2V p - p
VS = ±2. 5V
V
S
= ±5. 0V
09327-020
Figure 16. AD8148 Small Signal Transient Response for Various Supplies
–20
–80 11000
FREQUENCY (MHz)
COM M ON-MODE RE JE CTION (dB)
10 100
–30
–40
–50
–60
–70
ΔVO UT, dm/ΔVIN, cm
ΔVIN, cm = 2V p-p
AD8146
AD8148
AD8147
09327-027
Figure 17. CMRR vs. Frequency
AD8146/AD8147/AD8148
Rev. A | Page 12 of 24
–20
–100
0.1 1000
FREQUENCY (MHz)
POWER SUPPLY REJECTION (dB)
110 100
–30
–40
–50
–60
–70
–80
–90
AD8146
AD8148
AD8147
ΔVO UT, dm/ΔVS+
ΔVS = 2V p-p
09327-028
Figure 18. Positive Power Supply Rejection vs. Frequency
1000
10
0.01 100000
FRE QUENCY ( kHz)
NOISE (nV/ Hz)
0.1 110 100 1000 10000
100
AD8148
AD8146
AD8147
V
S
= ±5V
09327-029
Figure 19. Output-Referred Voltage Noise vs. Frequency
10
–10 01000
TIME (n s)
VOLT AGE (V)
8
6
4
2
0
–2
–4
–6
–8
100 200 300 400 500 600 700 800 900
INP UT × 2 (VS = ± 5.0V)
OUTPUT (VS = ±5. 0V )
INP UT × 2 (VS = ± 2.5V)
OUTPUT (VS = ±2. 5V )
09327-030
Figure 20. AD8146/AD8147 Output Overdrive Recovery
–20
–110
0.1 1000
FREQUENCY (MHz)
POWER SUPPLY REJECTION (dB)
110 100
–30
–40
–50
–60
–70
–80
–90
–100
ΔV
OUT, dm
/ΔV
S–
ΔV
S
= 2V p-p
AD8146
AD8148
AD8147
09327-051
Figure 21. Negative Power Supply Rejection vs. Frequency
–20
–120
0.1 1000
FREQUENCY (MHz)
ISOLATION (dB)
110 100
–30
–40
–50
–60
–70
–80
–90
–100
–110
AD8148
AD8146
AD8147
ΔV
OUT, dm
B/ΔV
IN, dm
A
ΔV
IN, dm
A = 1V p - p
09327-052
Figure 22. Amplifier-to-Amplifier Isolation vs. Frequency
10
–10 01000
TIME (n s)
VOLT AGE (V)
8
6
4
2
0
–2
–4
–6
–8
100 200 300 400 500 600 700 800 900
INP UT × 4 (VS = ± 5.0V)
INP UT × 4 (VS = ± 2.5V)
OUTPUT (VS = ±2. 5V )
OUTPUT (V
S
= ±5. 0V )
09327-033
Figure 23. AD8148 Output Overdrive Recovery
AD8146/AD8147/AD8148
Rev. A | Page 13 of 24
59
45
–60 120
TEMPERATURE (°C)
SUPP LY CURRENT (mA)
57
55
53
51
49
47
–40 –20 020 40 60 80 100
I
S
+ (±2.5V)
I
S
+ (±5.0V)
R
L, dm
= OP E N CIRCUI T
09327-054
Figure 24. AD8146 Supply Current vs. Temperature
–35
–6511000
FREQUENCY (MHz)
V
OCM
CMRR (dB)
10 100
–40
–45
–50
–55
–60
AD8146
ΔV
OUT, dm
/ΔV
OCM
ΔV
OCM
= 2V p-p
09327-061
Figure 25. VOCM Common-Mode Rejection Ratio
62
48
–60 120
TEMPERATURE (°C)
SUPP LY CURRENT (mA)
60
58
56
54
52
50
–40 –20 020 40 60 80 100
R
L, dm
= OP E N CIRCUI T
I
S
+ (±5.0V)
I
S
+ (±2.5V)
09327-056
Figure 26. AD8147/AD8148 Supply Current vs. Temperature
1.5
–1.5 040
TIME (n s)
VOLT AGE (V)
1.0
0.5
0
–0.5
–1.0
510 15 20 25 30 35
±VS = 2. 5V
±VS = 5. 0V
VOUT, cm = 2V p-p
09327-037
Figure 27. AD8146 Large Signal VOCM Transient Response for Various Supplies
AD8146/AD8147/AD8148
Rev. A | Page 14 of 24
THEORY OF OPERATION
Each differential driver differs from a conventional op amp in
that it has two outputs whose voltages move in opposite directions.
Like an op amp, it relies on high open-loop gain and negative
feedback to force these outputs to the desired voltages. The
drivers make it easy to perform single-ended-to-differential
conversion, common-mode level shifting, and amplification of
differential signals.
Previous differential drivers, both discrete and integrated
designs, were based on using two independent amplifiers and
two independent feedback loops, one to control each of the
outputs. When these circuits are driven from a single-ended
source, the resulting outputs are typically not well balanced.
Achieving a balanced output has typically required exceptional
matching of the amplifiers and feedback networks.
DC common-mode level shifting has also been difficult with
previous differential drivers. Level shifting has required the use
of a third amplifier and feedback loop to control the output
common-mode level. Sometimes, the third amplifier was also
used to attempt to correct an inherently unbalanced circuit.
Excellent performance over a wide frequency range has proven
difficult with this approach.
Each of the drivers uses two feedback loops to separately
control the differential and common-mode output voltages.
The differential feedback, set by the internal resistors, controls
only the differential output voltage. The internal common-
mode feedback loop controls only the common-mode output
voltage. This architecture makes it easy to transmit signals over
the common-mode voltage channels by simply applying the
signal voltages to the VOCM inputs. The output common-mode
voltage is forced, by internal common-mode feedback, to equal
the voltage applied to the VOCM input, without affecting the
differential output voltage.
The driver architecture results in outputs that are highly
balanced over a wide frequency range without requiring
external components or adjustments. The common-mode
feedback loop forces the signal component of the output
common-mode voltage to be zeroed. The result is nearly
perfectly balanced differential outputs of identical
amplitude that are exactly 180° apart in phase.
DEFINITION OF TERMS
Differential Voltage
Differential voltage refers to the difference between two node
voltages that are balanced with respect to each other. For
example, in Figure 28 the output differential voltage (or
equivalently output differential mode voltage) is defined as
VOUT, dm = (VOP − VON)
Common-Mode Voltage
Common-mode voltage refers to the average of two node
voltages with respect to a common reference. The output
common-mode voltage is defined as
VOUT, cm = (VOP + VON)/2
Output Balance
Output balance is a measure of how well the differential output
signals are matched in amplitude and how close they are to
exactly 180° apart in phase. Balance is most easily determined
by placing a well-matched resistor divider between the differential
output voltage nodes and comparing the magnitude of the signal at
the divider’s midpoint with the magnitude of the differential
signal. By this definition, output balance error is the magnitude
of the change in output common-mode voltage divided by the
magnitude of the change in output differential mode voltage in
response to a differential input signal.
dmOUT
cmOUT
V
V
ErrorBalanceOutput
,
,
∆
∆
=
ANALYZING AN APPLICATION CIRCUIT
The drivers use high open-loop gain and negative feedback to
force their differential and common-mode output voltages to
minimize the differential and common-mode input error
voltages. The differential input error voltage is defined as the
voltage between the differential inputs labeled VAP and VAN in
Figure 28. For most purposes, this voltage can be assumed to be
zero. Similarly, the difference between the actual output common-
mode voltage and the voltage applied to VOCM can also be
assumed to be zero. Starting from these two assumptions,
any application circuit can be analyzed.
CLOSED-LOOP GAIN
The differential mode gain of the circuit in Figure 28 can be
described by
G
F
dmIN,
dmOUT,
R
R
V
V=
where:
RF is 1.0 kΩ and RG is 500 Ω nominally for the AD8146 and
AD8147.
RF is 2.0 kΩ and RG is 500 Ω nominally for the AD8148.
R
G
V
AP
V
AN
V
IP
V
IN
+
V
IN, dm
–V
OCM
V
ON
V
OP
V
OUT, dm
R
G
R
F
R
F
R
L, dm
09327-006
Figure 28. Internal Architecture and Signal Name Definitions
AD8146/AD8147/AD8148
Rev. A | Page 15 of 24
CALCULATING THE INPUT IMPEDANCE
The effective input impedance of a circuit such as that in
Figure 28 at VIP and VIN depends on whether the amplifier is
being driven by a single-ended or differential signal source. For
balanced differential input signals, the differential input impedance,
RIN, dm, between the inputs VIP and VIN for all devices is
RIN, dm = 2 × RG
In the case of a single-ended input signal (for example, if VIN is
grounded and the input signal is applied to VIP), the input
impedance becomes
( )
+×
−
=
F
G
F
G
dmIN,
RR
R
R
R
2
1
The single-ended input impedance of the AD8146 and the
AD8147 is therefore 750 Ω, and the single-ended input
impedance of the AD8148 is 833 Ω.
The input impedance of the circuit is effectively higher than it
would be for a conventional op amp connected as an inverter
because a fraction of the differential output voltage appears at
the inputs as a common-mode signal, partially bootstrapping
the voltage across the input resistor RG.
INPUT COMMON-MODE VOLTAGE RANGE IN
SINGLE-SUPPLY APPLICATIONS
The driver inputs are designed to facilitate level-shifting of
ground-referenced input signals on a single power supply. For a
single-ended input, this implies, for example, that the voltage at
VIN in Figure 28 would be 0 V when the negative power supply
voltage of the amplifier is also set to 0 V.
It is important to ensure that the common-mode voltage at the
amplifier inputs, VAP and VAN, stays within its specified range.
Because voltages VAP and VAN are driven to be essentially equal
by negative feedback, the input common-mode voltage of the
amplifier can be expressed as a single term, VACM. VACM can be
calculated as
3
2ICMOCM
ACM
VV
V+
=
where VICM is the common-mode voltage of the input signal,
that is, VICM = (VIP + VIN)/2.
OUTPUT COMMON-MODE CONTROL
The AD8146 allows the user to control each of the three
common-mode output levels independently through the three
VOCM input pins. The VOCM pins pass a signal to the common-
mode output level of each of their respective amplifiers with
330 MHz of small signal bandwidth and an internally fixed gain
of 1. In this way, additional control and communication signals
can be embedded on the common-mode levels as users see fit.
With no external circuitry, the level at the VOCM input of each
amplifier defaults to approximately midsupply. An internal
resistive divider with an impedance of approximately 12.5 kΩ
sets this level. To limit common-mode noise in dc common-
mode applications, external bypass capacitors should be
connected from each of the VOCM input pins to ground.
SYNC-ON COMMON-MODE
The AD8147 and AD8148 are specifically targeted at driving
RGB video signals over UTP cable using a sync-on common-
mode technique. The common-mode outputs of each of the R,
G, and B differential outputs are set using circuitry contained
within the device. This circuitry embeds the horizontal and
vertical sync pulses on the three common-mode outputs in a
way that also results in low radiated energy. For a more detailed
description of the sync scheme, see the Applications section.
The sync-on common-mode circuit generates a current based
on the SYNC LEVEL input pin (Pin 18). With the SYNC LEVEL
input tied to GND, the common-mode output of all drivers is
set at (VS+ + VS−)/2. Using a resistor divider, a voltage can be
applied between GND and SYNC LEVEL that determines the
maximum deviation of the common-mode outputs from their
midsupply level. If, for instance, SYNC LEVEL = 0.5 V and the
supply voltage is 5 V, the common-mode outputs fall within an
envelope of 2.5 V ± 0.5 V. The state of each VOU T, cm output based
on the HSYNC and VSYNC inputs is determined by the equations
defined in the Applications section.
In most cases, the sync-on common-mode circuit can be used
by directly applying the HSYNC and VSYNC signals to their respective
AD8147 or AD8148 inputs. The logic thresholds of the HSYNC
and VSYNC inputs are set to nominally 1.4 V with respect to
GND, and the exposed paddles of the AD8147 and AD8148
are used as the GND references for the incoming sync pulses.
When ±2.5 V supplies are used, however, external protection is
required to limit the positive excursion to less than 2.5 V. For
more details, see the Applications section.
The input paths from the HSYNC and VSYNC inputs to the switches
in the current mode level-shifting circuit are well matched to
eliminate false switching transients, maximizing common-
mode balance and minimizing radiated energy.
AD8146/AD8147/AD8148
Rev. A | Page 16 of 24
APPLICATIONS
DRIVING RGB VIDEO SIGNALS OVER CATEGORY-5
UTP CABLE
The foremost application of the drivers is the transmission of
RGB video signals over UTP cable in KVM networks. The
excellent balance of the differential outputs ensures low radiated
energy from each of the twisted pairs. Single-ended video signals
are easily converted to differential signals for transmission over
the cable, and the internally fixed gain of 2 or 4 automatically
compensates for the losses incurred by the source and load
terminations. The common topologies used in KVM networks,
such as daisy-chained, star, and point-to-point, are supported
by the drivers. Figure 29 shows the AD8146 in a triple single-
ended-to-differential application when driven from a 75 Ω
source, which is typical of how RGB video is driven over an
UTP cable.
V
OCM
+2.5V
–
OUT A
+
A
1kΩ
VIDEO
SO URCE A
1kΩ
AD8146
500Ω
82.5Ω
39.2Ω
39.2Ω
39.2Ω
500Ω
49.9Ω
49.9Ω
75Ω
V
OCM
+2.5V
–
OUT B
+
B
1kΩ
VIDEO
SO URCE B
1kΩ
500Ω
82.5Ω
OUTPUT
PULLDOWN
500Ω
49.9Ω
49.9Ω
75Ω
V
OCM
+2.5V
–
OUT C
+
C
1kΩ
VIDEO
SO URCE C
1kΩ
500Ω
82.5Ω500Ω
OPD
49.9Ω
49.9Ω
75Ω
+5V
V
S+
0.1µF ON ALL V
S+
PI NS
V
S–
09327-007
Figure 29. AD8146 in Single-Ended-to-Differential Application
VIDEO SYNC-ON COMMON-MODE
In computer video applications, the horizontal and vertical sync
signals are often separate from the video information signals.
For example, in typical computer monitor applications, the red,
green, and blue (RGB) color signals are transmitted over separate
cables, as are the vertical and horizontal sync signals. When
transmitting these types of video signals over long distances on
UTP cable, it is desirable to reduce the required number of
physical channels. One way to do this is to encode the vertical
and horizontal sync signals as weighted sums and differences of
the output common-mode signals. The RGB color signals are
each transmitted differentially over separate physical channels.
The fact that the differential and common-mode signals are
orthogonal allows the RGB color and sync signals to be
separated at the channel’s receiver.
Cat-5 cable contains four balanced twisted-pair physical
channels that can support both differential and common-mode
signals. Transmitting typical computer monitor video over this
cable can be accomplished by using three of the twisted pairs for
the RGB and sync signals and one wire of the fourth pair as a
return path for the Schottky diode bias currents. Each color is
transmitted differentially, one on each of the three pairs, and the
encoded sync signals are transmitted among the common-mode
signals of each of the three pairs. To minimize EMI from the
sync signals, the common-mode signals on each of the three
pairs produced by the sync encoding scheme induce electric
and magnetic fields that for the most part cancel each other. A
conceptual block diagram of the sync encoding scheme is
presented in Figure 30. Because the AD8147/AD8148 have the
sync encoding scheme implemented internally, the user simply
applies the horizontal and vertical sync signals to the appropriate
inputs. (See the Specifications tables for the high and low levels
of the horizontal and vertical sync pulse voltages).
AD8146/AD8147/AD8148
Rev. A | Page 17 of 24
–OUT R
+OUT R
–OUT G
+OUT G
–OUT B
+OUT B
V
OCM
WEIGHTING EQUATIONS:
RED V
OCM
= K(V
SYNC
– H
SYNC
) + V
MIDSUPPLY
GRE E N V
OCM
= K(–2V
SYNC
) + V
MIDSUPPLY
BLUE V
OCM
= K(V
SYNC
+ H
SYNC
) + V
MIDSUPPLY
+IN R
–IN R
V
SYNC
H
SYNC
SYNC LEVEL
+IN G
–IN G
+IN B
–IN B
R
1kΩ
1kΩ
AD8147/AD8148
500Ω
500Ω
G
1kΩ
1kΩ
500Ω
500Ω
V
OCM
V
OCM
V
OCM
B
1kΩ
1kΩ
500Ω
500Ω
OPD
×2
2
2
2
09327-008
Figure 30. AD8147/AD8148 Sync-On Common-Mode Encoding Scheme
0
0.5
1.0
1.5
2.0
4.0
3.5
4.5
2.5
3.0
5.0
0.98 0.99 1.00 1.01 1.03 1.04 1.051.02 1.06 1.07
TIME (µs)
H
SYNC
V
SYNC
2.0
2.1
2.2
2.3
2.4
2.9
2.8
3.0
2.5
2.6
2.7
3.1
R
G
B
VOLTSVOLTS
09327-009
Figure 31. AD8147 Sync-On Common-Mode Signals in Single 5 V Application
The transmitted common-mode sync signal magnitudes are
scaled by applying a dc voltage to the SYNC LEVEL input,
referenced to GND. The difference between the voltage applied
to the SYNC LEVEL input and GND sets the peak deviation of
the encoded sync signals about the midsupply, common-mode
voltage. For example, with the SYNC LEVEL input set at 500 m V,
the deviation of the encoded sync pulses about the nominal
midsupply, common-mode voltage is typically ±500 mV. T h e
equations in Figure 30 describe how the VSYNC and HSYNC signals
are encoded on each color’s midsupply common-mode signal.
In these equations, the weights of the VSYNC and HSYNC signals
are ±1 (+1 for high and −1 for low), and the constant K is equal
to the peak deviation of the encoded sync signals.
Figure 31 shows how the sync signals appear on each common-
mode voltage in a single 5 V supply application when the voltage
applied to the SYNC LEVEL input is 500 mV, which is the
typical setting for most applications.
AD8146/AD8147/AD8148
Rev. A | Page 18 of 24
Sync pulse amplitudes applied to the AD8147 and AD8148
must be less than or equal to the positive supply voltage. In low
positive supply applications, such as those that use ±2.5 V supplies,
external limiting may be required because many logic families
produce amplitudes up to 5 V. Figure 32 illustrates how to use a
monolithic triple diode to limit a sync pulse with 5 V amplitude
to an amplitude of approximately 2 V.
301Ω
1
6
2
5
3
4
HN2D02FUTW1T1
0V
+5V
INCOMING
SYNC PULSE
0V
+2V
LIMITED
SYNC PULSE
06655-036
Figure 32. Limiting Sync Pulse Amplitude in Low Positive Supply Applications
DRIVING TWO UTP CABLES WITH ONE DRIVER
Some applications require driving two UTP cables with a single
driver. Each individual driver of the AD8146/AD8147/AD8148
is capable of driving two doubly terminated cables, which places
a differential load of 100 Ω across the outputs of the driver.
Figure 33 illustrates how to drive two cables.
AD8146/AD8147/AD8148
49.9Ω
49.9Ω
100Ω
100Ω
100Ω
UTP
49.9Ω
49.9Ω
100Ω
UTP
V
OCM
09327-034
Figure 33. Driving Two UTP Cables With One Driver
Driver bandwidth is affected to a small degree when driving the
100 Ω load presented by the two cables, as compared with
driving a typical 200 Ω load. Figure 34 illustrates the AD8146/
AD8147/AD8148 bandwidths when driving a 100 Ω load.
15
–3
FREQUENCY (MHz)
GAIN (d B)
12
9
6
3
0
1000100101
AD8148
AD8147
AD8146
RL, dm = 100Ω
VOUT = 2V p-p
09327-044
Figure 34. Large Signal Frequency Response Driving 100 Ω Loads
USING THE AD8146 AS A RECEIVER
While the AD8146 excels as a differential driver, it can also be
used as a differential-to-differential receiver applied as an
input buffer that protects a more sophisticated device, such as a
differential crosspoint switch. See Figure 35 for an illustration of
this type of application.
Because the AD8146 VOCM input pins are uncommitted, any
incoming common-mode signal, such as encoded sync pulses,
can be reproduced at the AD8146 outputs by stripping it from
the received signal and applying it directly to the VOCM pin.
The two series 54.9 Ω resistors form a differential termination
resistor of 109.8 Ω, which when loaded with the 1 kΩ differential
input resistance of the AD8146, provides an overall termination
of approximately 100 Ω. The received common-mode voltages
are available at the center taps between the two resistors.
AD8146/AD8147/AD8148
Rev. A | Page 19 of 24
AD8146
CROSSPOINT SWITCH
54.9Ω
54.9Ω
1kΩ
1kΩ
500Ω
500Ω
INPUT I, NEGATIVE PHASE
INPUT I, POSITIVE PHASE
INP UT J, NE GAT IVE P HAS E
INPUT J, POSIT I VE PHASE
INP UT K, NE GAT IVE P HAS E
INPUT K, POSIT I VE PHASE
10Ω
10Ω
V
OCM
RED
CHANNEL 100Ω
UTP
54.9Ω
54.9Ω
1kΩ
1kΩ
500Ω
500Ω
10Ω
10Ω
VOCM
GREEN
CHANNEL 100Ω
UTP
54.9Ω
54.9Ω
1kΩ
1kΩ
500Ω
500Ω
10Ω
10Ω
VOCM
BLUE
CHANNEL 100Ω
UTP
VS+ = + 2.5V VPOS = +2.5V
VNEG = –2. 5V
VS– = –2.5V
09327-035
Figure 35. Using the AD8146 as a Differential Receiver
Terminations are not required between the AD8146 and the
switch if the interconnection lengths are kept short (less than
two inches). The 10 Ω series resistors buffer the input
capacitance of the switch (typically 2 pF) and produce a low-
pass rolloff that is down by only 0.025 dB at 600 MHz.
OUTPUT PULL-DOWN (OPD)
The output pull-down feature, when used in conjunction with
series Schottky diodes, offers a convenient means to multiplex a
number of driver outputs together to form a video network. The
OPD pin is a binary input that controls the state of the outputs.
Its binary input level is referenced to GND (see the Specifications
section for the logic levels). When the OPD input is driven to its
low state, the output is enabled and operates in normal fashion.
In this state, the VOCM input can be used to provide a positive
bias on the series diodes, allowing the drivers to transmit
signals over the network. When the OPD input is driven to its
high state, the outputs of the drivers are forced to a low voltage,
irrespective of the level on the VOCM input, reverse-biasing the
series diodes and thus presenting high impedance to the
network. This feature allows a three-state output to be realized
that maintains its high impedance state even when the drivers
are not powered.
It is recommended that the output pull-down feature only be
used in conjunction with series diodes in such a way as to
ensure that the diodes are reverse-biased when the output pull-
down feature is asserted, because some loading conditions can
prevent the output voltage from being pulled all the way down.
LAYOUT AND POWER SUPPLY DECOUPLING
CONSIDERATIONS
Standard high speed PCB layout practices should be adhered
to when designing with the drivers. A solid ground plane is
required and good wideband power supply decoupling
networks should be placed as close as possible to the supply
pins. Small surface-mount ceramic capacitors are recommended
for these networks, and tantalum capacitors are recommended
for bulk supply decoupling.
Source termination resistors on the differential outputs must be
placed as close as possible to the output pins to minimize load
capacitance due to the PCB traces.
DRIVING A CAPACITIVE LOAD
A purely capacitive load can react with the output impedance
of any amplifier to produce an undesirable phase shift, which
reduces phase margin and results in high frequency ringing in
the pulse response. The best way to minimize this effect is to
place a small resistor in series with each of the outputs of the
amplifier to buffer the load capacitance. Most applications
include 49.9 Ω source termination resistors, which effectively
buffer any stray load capacitance.
AD8146/AD8147/AD8148
Rev. A | Page 20 of 24
Under no circumstances should capacitance be intentionally
added to an output to introduce frequency domain peaking.
Figure 36 and Figure 37 illustrate how adding just 5 pF of
excessive load capacitance influences time and frequency
domain responses.
2.0
–2.0 020
TIME (n s)
VOLT AGE (V)
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
2468
10 12 14 16 18
VS = ±5V
RL, dm = 200Ω
VOUT, dm = 2V p-p
CL = 5pF
CL = 0pF
09327-031
Figure 36. Large Signal Transient Responses at Various Capacitive Loads
12
210 1000
FREQUENCY (MHz)
GAIN (d B)
100
11
10
9
8
7
6
5
4
3
VS = ±5V
RL, dm = 200Ω
VOUT, dm = 2V p-p CL = 5pF
CL = 0pF
09327-032
Figure 37. Large Signal Frequency Responses at Various Capacitive Loads
While high frequency peaking is desirable in some cable
equalization applications, it should be implemented using
methods that do not compromise the stability of the driver and
that do not depend on amplifier parasitic elements. The parasitic
elements are affected by process variations and cannot be
depended upon for circuit designs. The amplifier may break
into oscillation when excess load capacitance is intentionally
added. For more information on this topic, see the Adding Pre-
Emphasis to the AD8148 section for a description on how to
introduce a controlled amount of pre-emphasis for 30 meters of
UTP using the AD8148.
ADDING PRE-EMPHASIS TO THE AD8148
UTP cables exhibit loss characteristics that are low pass in
nature and are exponential functions of the square root of the
frequency. Over wideband video bandwidths, the losses are
predominantly due to the skin effect, which causes the resistance of
the cable to increase with frequency. Even though the loss
characteristics are nonlinear, suitable linear networks can be
designed to approximately compensate for the losses.
Placing the compensation network at the transmitting end of
the cable is referred to as pre-emphasis, because the higher
frequencies are emphasized, or boosted, before they are sent, to
compensate for the low-pass response of the cable. Because the
higher frequencies experience more loss than the lower frequencies
as they pass through the cable, the high and low frequencies
arrive at approximately the same level and at the end of the cable
when a properly designed pre-emphasis network is used at the
transmitter. The ideal cascaded frequency response of the pre-
emphasis network and the cable is therefore nominally flat.
Because the AD8148 has an internally set, closed-loop gain of 4
(12 dB), it is possible to reduce the gain at low frequencies using
external frequency selective components, then use these
components to provide increasing gain with increasing
frequency, back to a value close to 12 dB. These components, along
with the AD8148, form the pre-emphasis network. When properly
designed, the combined frequency response of the pre-emphasis
network and cable is approximately flat with a gain of 2 (6 dB).
Figure 38 illustrates how to construct a pre-emphasis network
using the AD8148 that compensates for 30 meters of UTP cable.
The network in the lower leg is required to match the transfer
function of the two feedback loops.
At dc, the capacitors are open circuits, and the network has a
gain of approximately 6.5 dB. (The additional 0.5 dB is added to
compensate for the cable flat loss that occurs at frequencies
below where the skin effect begins to take effect.) Moving up in
frequency, the 30 pF capacitor begins to take effect and introduces
a zero into the frequency response, causing the gain to increase
with frequency. Continuing to move up in frequency, the 30 pF
capacitor becomes an effective short, and the 487 Ω resistor
goes in parallel with the 442 Ω resistor, forming a pole in the
response. Continuing to move up in frequency, the 18 pF
capacitor takes effect, introducing another zero, and causes
the gain to further increase with frequency until it becomes
an effective short, and the gain starts to flatten out until the
amplifier response begins to roll off. The gain does not reach
12 dB before the amplifier begins to roll off because the 12 dB
value is a high frequency asymptote. The pole and zero locations
cited in the previous discussion are qualitative, but the
discussion describes the basic principles involved with the
operation of the pre-emphasis network.
AD8146/AD8147/AD8148
Rev. A | Page 21 of 24
Figure 39 illustrates the frequency response of the pre-emphasis
network.
Figure 40 illustrates the frequency response of the pre-emphasis
circuit cascaded with the cable compared with that of the cable
alone. It can be seen that the overall response is flat to within
±0.4 dB. The ±0.4 dB ripple in the response is due to the fact
that the pre-emphasis network is linear, comprised of two real-
axis pole/zero pairs, and the cable response is nonlinear.
EXPOSED PADDLE (EP)
The 24-lead LFCSP has an exposed paddle on the underside of
its body. To achieve the specified thermal resistance, it must
have a good thermal connection to one of the PCB planes. The
exposed paddle must therefore be soldered to a pad on the top
of the board that is connected to an inner plane with several
thermal vias. The AD8147/AD8148 use the paddle as a ground
reference; therefore, for these parts, the PCB plane used must be
the ground plane.
2kΩ
2kΩ
500Ω
500Ω
49.9Ω
49.9Ω
442Ω
82.5Ω
487Ω
39.2Ω
442Ω
487Ω
75Ω
100 FE E T
100Ω
UTP
AD8148
+
–
VIDEO
SOURCE
18pF
30pF
18pF
30pF
09327-048
Figure 38. Pre-Emphasis Network Using the AD8148 for 30 Meters of UTP Cable
12
6
FREQUENCY (MHz)
GAIN (d B)
11
10
9
8
7
1001010.1
VS = ±5V
09327-049
Figure 39. AD8148 Pre-Emphasis Network Frequency Response
9
–9
0.1
FREQUENCY (MHz)
GAIN (d B)
6
3
0
–3
–6
110 100
PRE-EMPHASIS
NETWORK
WITH CABLE
CABLE ALONE
VS = ±5V
09327-050
Figure 40. AD8148 Pre-Emphasis Network Cascaded With
30 Meters of UTP Cable vs. UTP Cable Alone
AD8146/AD8147/AD8148
Rev. A | Page 22 of 24
OUTLINE DIMENSIONS
1
24
6
7
13
19
18
12
2.25
2.10 S Q
1.95
0.60 M AX
0.50
0.40
0.30
0.30
0.23
0.18
2.50 RE F
0.50
BSC
12° M AX 0.80 MAX
0.65TYP 0.05 MAX
0.02 NOM
1.00
0.85
0.80
SEATING
PLANE
PIN 1
INDICATOR
TOP
VIEW 3.75
BSC SQ
4.00
BSC SQ PI N 1
INDICATOR
0.60 M AX
COPLANARITY
0.08
0.20 RE F
0.25 M IN
EXPOSED
PAD
(BOTTO M VI EW)
COMPLIANT TO JEDE C S TANDARDS MO-220- V GGD- 2
072208-A
FOR PRO P E R CONNECTION O F
THE EXPOSED PAD, REFER TO
THE P IN CONFI GURATIO N AND
FUNCTION DES CRIPT IO NS
SECTION OF THIS DATA SHEET.
Figure 41. 24-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
4 mm × 4 mm
(CP-24-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model1Temperature Range Package Description Package Option
AD8146ACPZ-R2 −40°C to +85°C 24-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-24-1
AD8146ACPZ-R7 −40°C to +85°C 24-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-24-1
AD8146ACPZ-RL −40°C to +85°C 24-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-24-1
AD8147ACPZ-R2 −40°C to +85°C 24-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-24-1
AD8147ACPZ-R7 −40°C to +85°C 24-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-24-1
AD8147ACPZ-RL −40°C to +85°C 24-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-24-1
AD8148ACPZ-R2 −40°C to +85°C 24-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-24-1
AD8148ACPZ-R7 −40°C to +85°C 24-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-24-1
AD8148ACPZ-RL −40°C to +85°C 24-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-24-1
1 Z = RoHS Compliant Part.
AD8146/AD8147/AD8148
Rev. A | Page 23 of 24
NOTES
AD8146/AD8147/AD8148
Rev. A | Page 24 of 24
NOTES
©2007-2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09327-0-8/10(A)