14-Bit, 1 MSPS, Unipolar/Bipolar
Programmable Input PulSAR
®
ADC
Data Sheet
AD7951
FEATURES
Multiple pins/software programmable input ranges:
5 V, 10 V, ±5 V, ±10 V
Pins or serial SPI® compatible input ranges/mode selection
Throughput
1 MSPS (warp mode)
800 kSPS (normal mode)
670 kSPS (impulse mode)
14-bit resolution with no missing codes
INL: ±0.3 LSB typ, ±1 LSB max (±61 ppm of FSR)
SNR: 85 dB @ 2 kHz
iCMOS® process technology
5 V internal reference: typical drift 3 ppm/°C; TEMP output
No pipeline delay (SAR architecture)
Parallel (14- or 8-bit bus) and serial 5 V/3.3 V interface
SPI-/QSPI™-/MICROWIRE™-/DSP-compatible
Power dissipation:
10 mW @ 100 kSPS
235 mW @ 1 MSPS
48-lead LQFP and LFCSP (7 mm × 7 mm) packages
APPLICATIONS
Process control
Medical instruments
High speed data acquisition
Digital signal processing
Instrumentation
Spectrum analysis
ATE
GENERAL DESCRIPTION
The AD7951 is a 14-bit, charge redistribution, successive
approximation register (SAR) architecture analog-to-digital
converter (ADC) fabricated on Analog Devices, Inc.’s iCMOS
high voltage process. The device is configured through hardware or
via a dedicated write only serial configuration port for input
range and operating mode. The AD7951 contains a high speed
14-bit sampling ADC, an internal conversion clock, an internal
reference (and buffer), error correction circuits, and both serial
and parallel system interface ports. A falling edge on CNVST
samples the analog input on IN+ with respect to a ground
sense, IN−. The AD7951 features four different analog input
ranges and three different sampling modes: warp mode for the
fastest throughput, normal mode for the fastest asynchronous
throughput, and impulse mode where power is scaled with
throughput. Operation is specified from −40°C to +85°C.
FUNCTIONAL BLOCK DIAGRAM
06396-001
14
CONTROL LOGIC AND
CALI BRATI ON CI RCUITRY
CLOCK
AD7951
DGND
DVDD
AVDD
AGND
REF REFGND
IN+
PD
RESET
CNVST
PDBUF
REFBUFIN
PDREF REF
TEMP
D[13:0]
BUSY
RD
CS
OB/2C
OGND
OVDD
BYTESWAP
SER/PAR
REF
AMP SERIAL DATA
PORT
PARALLEL
INTERFACE
SWITCHED
CAP DAC
VCC VEE
WARP IMPULSE BIPOLAR TEN
SERIAL
CONFIGURATION
PORT
IN–
Figure 1.
Table 1. 48-Lead 14-/16-/18-Bit PulSAR Selection
Type
100 kSPS to
250 kSPS
500 kSPS to
570 kSPS
570 kSPS to
1000 kSPS
>1000
kSPS
Pseudo
Differential
AD7651
AD7660
AD7661
AD7650
AD7652
AD7664
AD7666
AD7653
AD7667
True Bipolar AD7610
AD7663
AD7665 AD7951
AD7612
AD7671
True
Differential
AD7675 AD7676 AD7677 AD7621
AD7622
AD7623
18-Bit, True
Differential
AD7678 AD7679 AD7674 AD7641
AD7643
Multichannel/
Simultaneous
AD7654
AD7655
Rev. B Document Feedback
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Technical Support www.analog.com
AD7951 Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Timing Specifications .................................................................. 5
Absolute Maximum Ratings ............................................................ 7
ESD Caution .................................................................................. 7
Pin Configuration and Function Descriptions ............................. 8
Typical Performance Characteristics ........................................... 12
Terminology .................................................................................... 16
Theory of Operation ...................................................................... 17
Overview ...................................................................................... 17
Converter Operation .................................................................. 17
Modes of Operation ................................................................... 18
Transfer Functions...................................................................... 18
Typical Connection Diagram.................................................... 19
Analog Inputs.............................................................................. 20
Voltage Reference Input/Output .............................................. 21
Power Supplies ............................................................................ 22
Conversion Control ................................................................... 23
Interfaces.......................................................................................... 24
Digital Interface .......................................................................... 24
Parallel Interface ......................................................................... 24
Serial Interface ............................................................................ 25
Master Serial Interface ............................................................... 25
Slave Serial Interface .................................................................. 27
Hardware Configuration ........................................................... 29
Software Configuration ............................................................. 29
Microprocessor Interfacing ....................................................... 30
Application Information ................................................................ 31
Layout Guidelines....................................................................... 31
Outline Dimensions ....................................................................... 32
Ordering Guide .......................................................................... 32
REVISION HISTORY
5/15—Rev. A to Rev. B
Change to Acquisition Time Parameter, Table 3 .......................... 5
Deleted Evaluating Performance Section .................................... 31
Changes to Ordering Guide .......................................................... 32
12/12—Rev. 0 to Rev. A
Added Exposed Pad Note ................................................................ 8
Changes to Power Sequencing Section ........................................ 23
Updated Outline Dimensions ....................................................... 32
Changes to Ordering Guide .......................................................... 32
10/06—Revision 0: Initial Version
Rev. B | Page 2 of 32
Data Sheet AD7951
SPECIFICATIONS
AVDD = DVDD = 5 V; OVDD = 2.7 V to 5.5 V; VCC = 15 V; VEE = −15 V; VREF = 5 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter Conditions/Comments Min Typ Max Unit
RESOLUTION 14 Bits
ANALOG INPUT
Voltage Range, VIN VIN+ − VIN− = 0 V to 5 V −0.1 +5.1 V
VIN+ − VIN− = 0 V to 10 V −0.1 +10.1 V
VIN+ − VIN− = ±5 V −5.1 +5.1 V
VIN+ − VIN− = ±10 V −10.1 +10.1 V
VIN− to AGND −0.1 +0.1 V
Analog Input CMRR fIN = 100 kHz 75 dB
Input Current VIN = ±5 V, ±10 V @ 1 MSPS 3001 µA
Input Impedance
See the Analog Inputs section
THROUGHPUT SPEED
Complete Cycle In warp mode 1 μs
Throughput Rate In warp mode 1 1 MSPS
Time Between Conversions In warp mode 1 ms
Complete Cycle In normal mode 1.25 μs
Throughput Rate In normal mode 0 800 kSPS
Complete Cycle In impulse mode 1.49 μs
Throughput Rate In impulse mode 0 670 kSPS
DC ACCURACY
Integral Linearity Error2 −1 ±0.3 +1 LSB3
No Missing Codes
2
14
Differential Linearity Error2 −1 +1 LSB
Transition Noise 0.55 LSB
Zero Error (Unipolar or Bipolar) −15 +15 LSB
Zero Error Temperature Drift ±1 ppm/°C
Full-Scale Error (Unipolar or Bipolar) −20 +20 LSB
Full-Scale Error Temperature Drift ±1 ppm/°C
Power Supply Sensitivity AVDD = 5 V ± 5% ±0.8 LSB
AC ACCURACY
Dynamic Range fIN = 2 kHz, −60 dB 84.5 85.5 dB4
Signal-to-Noise Ratio fIN = 2 kHz 84.5 85.5 dB
fIN = 20 kHz 85.5 dB
Signal-to-(Noise + Distortion) (SINAD) fIN = 2 kHz 83 85.4 dB
Total Harmonic Distortion fIN = 2 kHz −105 dB
Spurious-Free Dynamic Range
f
IN
= 2 kHz
102
–3 dB Input Bandwidth VIN = 0 V to 5 V 45 MHz
Aperture Delay 2 ns
Aperture Jitter 5 ps rms
Transient Response Full-scale step 500 ns
INTERNAL REFERENCE PDREF = PDBUF = low
Output Voltage REF @ 25°C 4.965 5.000 5.035 V
Temperature Drift –40°C to +85°C ±3 ppm/°C
Line Regulation AVDD = 5 V ± 5% ±15 ppm/V
Long-Term Drift 1000 hours 50 ppm
Turn-On Settling Time CREF = 22 µF 10 ms
Rev. B | Page 3 of 32
AD7951 Data Sheet
Parameter Conditions/Comments Min Typ Max Unit
REFERENCE BUFFER PDREF = high
REFBUFIN Input Voltage Range 2.4 2.5 2.6 V
EXTERNAL REFERENCE PDREF = PDBUF = high
Voltage Range REF 4.75 5 AVDD + 0.1 V
Current Drain 1 MSPS throughput 200 µA
TEMPERATURE PIN
Voltage Output @ 25°C 311 mV
Temperature Sensitivity 1 mV/°C
Output Resistance 4.33 kΩ
DIGITAL INPUTS
Logic Levels
VIL −0.3 +0.6 V
VIH 2.1 OVDD + 0.3 V
IIL −1 +1 µA
IIH −1 +1 µA
DIGITAL OUTPUTS
Data Format Parallel or serial 14-bit
Pipeline Delay5
VOL ISINK = 500 µA 0.4 V
VOH ISOURCE = –500 µA OVDD − 0.6 V
POWER SUPPLIES
Specified Performance
AVDD 4.756 5 5.25 V
DVDD 4.75 5 5.25 V
OVDD 2.7 5.25 V
VCC 7 15 15.75 V
VEE −15.75 −15 0 V
Operating Current7, 8 @ 1 MSPS throughput
AVDD
With Internal Reference 20 mA
With Internal Reference Disabled 18.5 mA
DVDD 7 mA
OVDD 0.5 mA
VCC VCC = 15 V, with internal reference buffer 4 mA
VCC = 15 V 3 mA
VEE
VEE = −15 V
2
Power Dissipation @ 1 MSPS throughput
With Internal Reference PDREF = PDBUF = low 235 260 mW
With Internal Reference Disabled PDREF = PDBUF = high 215 240 mW
In Power-Down Mode9 PD = high 10 µW
TEMPERATURE RANGE10
Specified Performance TMIN to TMAX −40 +85 °C
1 With VIN = 0 V to 5 V or 0 V to 10 V ranges, the input current is typically 100 μA. In all input ranges, the input current scales with throughput. See the Analog Inputs section.
2 Linearity is tested using endpoints, not best fit. All linearity is tested with an external 5 V reference.
3 LSB means least significant bit. All specifications in LSB do not include the error contributed by the reference.
4 All specifications in dB are referred to a full-scale range input, FSR. Tested with an input signal at 0.5 dB below full-scale, unless otherwise specified.
5 Conversion results are available immediately after completed conversion.
6 4.75 V or VREF – 0.1 V, whichever is larger.
7 Tested in parallel reading mode.
8 With internal reference, PDREF = PDBUF = low; with internal reference disabled, PDREF = PDBUF = high. With internal reference buffer, PDBUF = low.
9 With all digital inputs forced to OVDD.
10 Consult sales for extended temperature range.
Rev. B | Page 4 of 32
Data Sheet AD7951
TIMING SPECIFICATIONS
AVDD = DVDD = 5 V; OVDD = 2.7 V to 5.5 V; VCC = 15 V; VEE = −15 V; VREF = 5 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter Symbol Min Typ Max Unit
CONVERSION AND RESET (See Figure 33 and Figure 34)
Convert Pulse Width t1 10 ns
Time Between Conversions t2
Warp Mode/Normal Mode/Impulse Mode1 1/1.25/1.49 μs
CNVST Low to BUSY High Delay t3 35 ns
BUSY High All Modes (Except Master Serial Read After Convert)
t
4
Warp Mode/Normal Mode/Impulse Mode 850/1100/1350 ns
Aperture Delay t5 2 ns
End of Conversion to BUSY Low Delay t6 10 ns
Conversion Time t7
Warp Mode/Normal Mode/Impulse Mode
850/1100/1350
ns
Acquisition Time t8
Warp Mode/Normal Mode/Impulse Mode 148 ns
RESET Pulse Width t9 10 ns
PARALLEL INTERFACE MODES (See Figure 35 and Figure 37)
CNVST Low to DATA Valid Delay t10
Warp Mode/Normal Mode/Impulse Mode 850/1100/1350 ns
DATA Valid to BUSY Low Delay t11 20 ns
Bus Access Request to DATA Valid
t
12
40
ns
Bus Relinquish Time t13 2 15 ns
MASTER SERIAL INTERFACE MODES2 (See Figure 39 and Figure 40)
CS Low to SYNC Valid Delay t14 10 ns
CS Low to Internal SDCLK Valid Delay2 t15 10 ns
CS Low to SDOUT Delay t16 10 ns
CNVST Low to SYNC Delay, Read During Convert t17
Warp Mode/Normal Mode/Impulse Mode 50/290/530 ns
SYNC Asserted to SDCLK First Edge Delay
t
18
3
ns
Internal SDCLK Period3 t19 30 45 ns
Internal SDCLK High3 t20 15 ns
Internal SDCLK Low3 t21 10 ns
SDOUT Valid Setup Time3 t22 4 ns
SDOUT Valid Hold Time3 t23 5 ns
SDCLK Last Edge to SYNC Delay3 t24 5 ns
CS High to SYNC High-Z t25 10 ns
CS High to Internal SDCLK High-Z t26 10 ns
CS High to SDOUT High-Z t27 10 ns
BUSY High in Master Serial Read After Convert3 t28 See Table 4
CNVST Low to SYNC Delay, Read After Convert t29
Warp Mode/Normal Mode/Impulse Mode
710/950/1190
ns
SYNC Deasserted to BUSY Low Delay t30 25 ns
Rev. B | Page 5 of 32
AD7951 Data Sheet
Parameter Symbol Min Typ Max Unit
SLAVE SERIAL/SERIAL CONFIGURATION INTERFACE MODES2
(See Figure 42, Figure 43, and Figure 45)
External SDCLK, SCCLK Setup Time t31 5 ns
External SDCLK Active Edge to SDOUT Delay t32 2 18 ns
SDIN/SCIN Setup Time t33 5 ns
SDIN/SCIN Hold Time t34 5 ns
External SDCLK/SCCLK Period t35 25 ns
External SDCLK/SCCLK High t36 10 ns
External SDCLK/SCCLK Low t37 10 ns
1 In warp mode only, the time between conversions is 1 ms; otherwise, there is no required maximum time.
2 In serial interface modes, the SDSYNC, SDSCLK, and SDOUT timings are defined with a maximum load CL of 10 pF; otherwise, the load is 60 pF maximum.
3 In serial master read during convert mode. See Table 4 for serial master read after convert mode.
Table 4. Serial Clock Timings in Master Read After Convert Mode
DIVSCLK[1] 0 0 1 1
DIVSCLK[0] Symbol 0 1 0 1 Unit
SYNC to SDCLK First Edge Delay Minimum t18 3 20 20 20 ns
Internal SDCLK Period Minimum t19 30 60 120 240 ns
Internal SDCLK Period Maximum t19 45 90 180 360 ns
Internal SDCLK High Minimum t20 12 30 60 120 ns
Internal SDCLK Low Minimum t21 10 25 55 115 ns
SDOUT Valid Setup Time Minimum t22 4 20 20 20 ns
SDOUT Valid Hold Time Minimum t23 5 8 35 90 ns
SDCLK Last Edge to SYNC Delay Minimum t24 5 7 35 90 ns
BUSY High Width Maximum t28
Warp Mode
1.60
2.35
3.75
6.75
µs
Normal Mode
1.85
2.60
4.00
7.00
µs
Impulse Mode 2.10 2.85 4.25 7.25 µs
NOTES
1. I N S E RIAL INT E RFACE M ODES, T HE S Y NC, SCLK, AND
SDOUT ARE DE FI NE D WI TH A MAXIMUM LO AD
CL OF 10pF; OTHERWISE, THE LOAD IS 60pF MAXIMUM.
1.6mA IOL
500µA IOH
1.4V
TO OUTPUT
PIN
C
L
60pF
06396-002
Figure 2. Load Circuit for Digital Interface Timing,
SDOUT, SYNC, and SCLK Outputs, CL = 10 pF
0.8V
2V
2V
0.8V
0.8V
2V
t
DELAY
t
DELAY
06396-003
Figure 3. Voltage Reference Levels for Timing
Rev. B | Page 6 of 32
Data Sheet AD7951
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter Rating
Analog Inputs/Outputs
IN+1, IN−1 to AGND VEE − 0.3 V to VCC + 0.3 V
REF, REFBUFIN, TEMP,
REFGND to AGND
AVDD + 0.3 V to
AGND − 0.3 V
Ground Voltage Differences
AGND, DGND, OGND ±0.3 V
Supply Voltages
AVDD, DVDD, OVDD −0.3 V to +7 V
AVDD to DVDD, AVDD to OVDD ±7 V
DVDD to OVDD ±7 V
VCC to AGND, DGND –0.3 V to +16.5 V
VEE to GND +0.3 V to −16.5 V
Digital Inputs −0.3 V to OVDD + 0.3 V
PDREF, PDBUF2 ±20 mA
Internal Power Dissipation3 700 mW
Internal Power Dissipation4 2.5 W
Junction Temperature 125°C
Storage Temperature Range
−65°C to +125°C
1 See the Analog Inputs section.
2 See the Voltage Reference Input section.
3 Specification is for the device in free air: 48-Lead LQFP; θJA = 91°C/W,
θJC = 30°C/W.
4 Specification is for the device in free air: 48-Lead LFCSP; θJA = 26°C/W.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
Rev. B | Page 7 of 32
AD7951 Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
06396-004
PDBUF
PDREF
REFBUFIN
TEMP
AVDD
IN+
AGND
VEE
VCC
IN–
REFGND
REF
D2/EXT/INT
D3/INVSYNC
D4/INVSCLK
D5/RDC/SDIN
OGND
OVDD
DVDD
DGND
D6/SDOUT
D7/SDCLK
D8/SYNC
D9/RDERROR
AGND
AVDD
AGND
BYTESWAP
OB/2C
SER/PAR
NC
NC
D0/DIVSCLK[0]
D1/DIVSCLK[1]
IMPULSE
WARP
BIPOLAR
CNVST
PD
RESET
CS
RD
TEN
BUSY
D13/SCCS
D12/SCCLK
D11/SCIN
D10/HW/SW
48 47 46 45 44 43 42 41 40 39 38 37
35
34
33
30
31
32
36
29
28
27
25
26
2
3
4
7
6
5
1
8
9
10
12
11
13 14 15 16 17 18 19 20 21 22 23 24
PIN 1
AD7951
TOP VIEW
(No t t o Scal e)
NOTES
1. NC = NO CONNECT.
2. FOR THE LEAD FRAME CHIP SCALE PACKAGE (LFCSP), T HE EXPOSED
PAD SHO ULD BE CONNECTED TO V E E . T HIS CONNECTION I S NOT
REQUIRED TO M E E T T HE E LECT RICAL P E RFO RM ANCE S .
Figure 4. Pin Configuration
Table 6. Pin Function Descriptions
Pin No. Mnemonic Type1 Description
1, 3, 42
AGND
P
Analog Power Ground Pins. Ground reference point for all analog I/O. All analog I/O should be
referenced to AGND and should be connected to the analog ground plane of the system. In addition,
the AGND, DGND, and OGND voltages should be at the same potential.
2, 44 AVDD P Analog Power Pins. Nominally 4.75 V to 5.25 V and decoupled with 10 μF and 100 nF capacitors.
4 BYTESWAP DI Parallel Mode Selection (8-Bit/14-Bit). When high, the LSB is output on D[15:8] and the MSB is output
on D[7:0]; when low, the LSB is output on D[7:0] and the MSB is output on D[15:8].
5 OB/2C DI2 Straight Binary/Binary Twos Complement Output. When high, the digital output is straight binary.
When low, the MSB is inverted resulting in a twos complement output from its internal shift register.
6 WARP DI2 Conversion Mode Selection. Used in conjunction with the IMPULSE input per the following:
Conversion Mode WARP IMPULSE
Normal Low Low
Impulse Low High
Warp High Low
Normal High High
See the Modes of Operation section for a more detailed description.
7 IMPULSE DI2 Conversion Mode Selection. See the WARP pin description in the previous row of this table. See the
Modes of Operation section for a more detailed description.
8 SER/PAR DI Serial/Parallel Selection Input.
When SER/PAR = low, the parallel mode is selected.
When SER/PAR = high, the serial modes are selected. Some bits of the data bus are used as a serial port
and the remaining data bits are high impedance outputs.
9, 10 NC DO No Connect. Do not connect.
Rev. B | Page 8 of 32
Data Sheet AD7951
Pin No. Mnemonic Type1 Description
11, 12 D[0:1] or DI/O In parallel mode, these outputs are used as Bit 0 and Bit 1 of the parallel port data output bus.
DIVSCLK[0:1] Serial Data Division Clock Selection. In serial master read after convert mode (SER/PAR = high,
EXT/INT = low, RDC/SDIN = low) these inputs can be used to slow down the internally generated serial
data clock that clocks the data output. In other serial modes, these pins are high impedance outputs.
13 D2 or DI/O In parallel mode, this output is used as Bit 2 of the parallel port data output bus.
EXT/INT Serial Data Clock Source Select. In serial mode, this input is used to select the internally generated
(master) or external (slave) serial data clock for the AD7951 output data.
When EXT/INT = low, master mode; the internal serial data clock is selected on SDCLK output.
When EXT/INT = high, slave mode; the output data is synchronized to an external clock signal (gated
by CS) connected to the SDCLK input.
14 D3 or DI/O In parallel mode, this output is used as Bit 3 of the parallel port data output bus.
INVSYNC Serial Data Invert Sync Select. In serial master mode (SER/PAR = high, EXT/INT = low). This input is used
to select the active state of the SYNC signal.
When INVSYNC = low, SYNC is active high.
When INVSYNC = high, SYNC is active low.
15 D4 or DI/O In parallel mode, this output is used as Bit 4 of the parallel port data output bus.
INVSCLK In all serial modes, invert SDCLK/SCCLK select. This input is used to invert both SDCLK and SCCLK.
When INVSCLK = low, the rising edge of SDCLK/SCCLK are used.
When INVSCLK = high, the falling edge of SDCLK/SCCLK are used.
16 D5 or DI/O In parallel mode, this output is used as Bit 5 of the parallel port data output bus.
RDC or Serial Data Read During Convert. In serial master mode (SER/PAR = high, EXT/INT = low) RDC is used to
select the read mode. Refer to the Master Serial Interface section.
When RDC = low, the current result is read after conversion. Note the maximum throughput is not
attainable in this mode.
When RDC = high, the previous conversion result is read during the current conversion.
SDIN Serial Data In. In serial slave mode (SER/PAR = high EXT/INT = high) SDIN can be used as a data input to
daisy-chain the conversion results from two or more ADCs onto a single SDOUT line. The digital data
level on SDIN is output on SDOUT with a delay of 16 SDCLK periods after the initiation of the read sequence.
17 OGND P Input/Output Interface Digital Power Ground. Ground reference point for digital outputs. Should be
connected to the system digital ground ideally at the same potential as AGND and DGND.
18 OVDD P Input/Output Interface Digital Power. Nominally at the same supply as the supply of the host interface
2.5 V, 3 V, or 5 V and decoupled with 10 μF and 100 nF capacitors.
19 DVDD P Digital Power. Nominally at 4.75 V to 5.25 V and decoupled with 10 μF and 100 nF capacitors. Can be
supplied from AVDD.
20 DGND P Digital Power Ground. Ground reference point for digital outputs. Should be connected to system
digital ground ideally at the same potential as AGND and OGND.
21 D6 or DO In parallel mode, this output is used as Bit 6 of the parallel port data output bus.
SDOUT Serial Data output. In all serial modes this pin is used as the serial data output synchronized to SDCLK.
Conversion results are stored in an on-chip register. The AD7951 provides the conversion result, MSB
first, from its internal shift register. The data format is determined by the logic level of OB/2C.
When EXT/INT = low (master mode), SDOUT is valid on both edges of SDCLK.
When EXT/INT = high (slave mode):
When INVSCLK = low, SDOUT is updated on SDCLK rising edge.
When INVSCLK = high, SDOUT is updated on SDCLK falling edge.
22 D7 or DI/O In parallel mode, this output is used as Bit 7 of the parallel port data output bus.
SDCLK
Serial Data Clock. In all serial modes, this pin is used as the serial data clock input or output, dependent
on the logic state of the EXT/INT pin. The active edge where the data SDOUT is updated depends on
the logic state of the INVSCLK pin.
Rev. B | Page 9 of 32
AD7951 Data Sheet
Pin No. Mnemonic Type1 Description
23 D8 or DO In parallel mode, this output is used as Bit 8 of the parallel port data output bus.
SYNC Serial Data Frame Synchronization. In serial master mode (SER/PAR = high, EXT/INT= low), this output
is used as a digital output frame synchronization for use with the internal data clock.
When a read sequence is initiated and INVSYNC = low, SYNC is driven high and remains high while the
SDOUT output is valid.
When a read sequence is initiated and INVSYNC = high, SYNC is driven low and remains low while the
SDOUT output is valid.
24 D9 or DO In parallel mode, this output is used as Bit 9 of the parallel port data output bus.
RDERROR Serial Data Read Error. In serial slave mode (SER/PAR = high, EXT/INT = high), this output is used as an
incomplete data read error flag. If a data read is started and not completed when the current
conversion is complete, the current data is lost and RDERROR is pulsed high.
25 D10 or DI/O In parallel mode, this output is used as Bit 10 of the parallel port data output bus.
HW/SW
Serial Configuration Hardware/Software Select. In serial mode, this input is used to configure
the AD7951 by hardware or software. See the Hardware Configuration section and Software
Configuration section.
When HW/SW = low, the AD7951 is configured through software using the serial configuration register.
When HW/SW = high, the AD7951 is configured through dedicated hardware input pins.
26 D11 or DI/O In parallel mode, this output is used as Bit 11 of the parallel port data output bus.
SCIN Serial Configuration Data Input. In serial software configuration mode (SER/PAR = high, HW/SW = low)
this input is used to serially write in, MSB first, the configuration data into the serial configuration
register. The data on this input is latched with SCCLK. See the Software Configuration section.
27 D12 or DI/O In parallel mode, this output is used as Bit 12 of the parallel port data output bus.
SCCLK Serial Configuration Clock. In serial software configuration mode (SER/PAR = high, HW/SW = low) this
input is used to clock in the data on SCIN. The active edge where the data SCIN is updated depends on
the logic state of the INVSCLK pin. See the Software Configuration section.
28 D13 or DI/O In parallel mode, this output is used as Bit 13 of the parallel port data output bus.
SCCS Serial Configuration Chip Select. In serial software configuration mode (SER/PAR = high, HW/SW = low)
this input enables the serial configuration port. See the Software Configuration section.
29 BUSY DO Busy Output. Transitions high when a conversion is started, and remains high until the conversion
is complete and the data is latched into the on-chip shift register. The falling edge of BUSY can be
used as a data ready clock signal. Note that in master read after convert mode (SER/PAR = high,
EXT/INT = low, RDC = low), the busy time changes according to Table 4.
30 TEN DI2 Input Range Select. Used in conjunction with BIPOLAR per the following:
Input Range BIPOLAR TEN
0 V to 5 V Low Low
0 V to 10 V Low High
±5 V High Low
±10 V
High
High
31 RD DI Read Data. When CS and RD are both low, the interface parallel or serial output bus is enabled.
32 CS DI Chip Select. When CS and RD are both low, the interface parallel or serial output bus is enabled. CS is
also used to gate the external clock in slave serial mode (not used for serial programmable port).
33 RESET DI Reset Input. When high, reset the AD7951. Current conversion, if any, is aborted. The falling edge of
RESET resets the data outputs to all zeros (with OB/2C = high) and clears the configuration register. See
the Digital Interface section. If not used, this pin can be tied to OGND.
34 PD DI2 Power-Down Input. When PD = high, powers down the ADC. Power consumption is reduced and
conversions are inhibited after the current one is completed. The digital interface remains active
during power-down.
35 CNVST DI Conversion Start. A falling edge on CNVST puts the internal sample-and-hold into the hold state and
initiates a conversion.
36 BIPOLAR DI2 Input Range Select. See description for Pin 30.
Rev. B | Page 10 of 32
Data Sheet AD7951
Pin No. Mnemonic Type1 Description
37 REF AI/O Reference Input/Output. When PDREF/PDBUF = low, the internal reference and buffer are enabled,
producing 5 V on this pin. When PDREF/PDBUF = high, the internal reference and buffer are disabled,
allowing an externally supplied voltage reference up to AVDD volts. Decoupling with at least a 22 μF is
required with or without the internal reference and buffer. See the Reference Decoupling section.
38
REFGND
AI
Reference Input Analog Ground. Connected to analog ground plane.
39 IN− AI Analog Input Ground Sense. Should be connected to the analog ground plane or to a remote sense ground.
40 VCC P High Voltage Positive Supply. Normally +7 V to +15 V.
41 VEE P High Voltage Negative Supply. Normally 0 V to −15 V (0 V in unipolar ranges).
43 IN+ AI Analog Input. Referenced to IN−.
45 TEMP AO Temperature Sensor Analog Output. Enabled when the internal reference is turned on
(PDREF = PDBUF = low). See the Temperature Sensor section.
46 REFBUFIN AI Reference Buffer Input. When using an external reference with the internal reference buffer
(PDBUF = low, PDREF = high), applying 2.5 V on this pin produces 5 V on the REF pin.
See the Voltage Reference Input section.
47 PDREF DI Internal Reference Power-Down Input.
When low, the internal reference is enabled.
When high, the internal reference is powered down, and an external reference must be used.
48 PDBUF DI Internal Reference Buffer Power-Down Input.
When low, the buffer is enabled (must be low when using internal reference).
When high, the buffer is powered-down.
49 EPAD3 NC Exposed Pad. The exposed pad is not connected internally. It is recommended that the pad be
soldered to VEE.
1 AI = analog input; AI/O = bidirectional analog; AO = analog output; DI = digital input; DI/O = bidirectional digital; DO = digital output; P = power.
2 In serial configuration mode (SER/PAR = high, HW/SW = low), this input is programmed with the serial configuration register and this pin is a don’t care. See the
Hardware Configuration section and Software Configuration section.
3 LFCSP_VQ package only.
Rev. B | Page 11 of 32
AD7951 Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
AVDD = DVDD = 5 V; OVDD = 5 V; VCC = 15 V; VEE = −15 V; VREF = 5 V; TA = 25°C.
–1.0
–0.5
0
0.5
1.0
04096 8192 12288 16384
CODE
INL (LSB)
POSITIVE INL = +0.15
NEGATI V E INL = –0.15
06396-005
Figure 5. Integral Nonlinearity vs. Code
0
50
100
150
200
250
–1.0 –0.8 –0.6 –0.4 –0.2 00.2 0.4 0.6 0.8 1.0
NEGATIVE INL
POSITIVE INL
INL DISTRIBUTION (LSB)
NUMBER O F UNI TS
06396-006
Figure 6. Integral Nonlinearity Distribution (239 Devices)
0
50000
100000
150000
200000
250000
300000
1FFF 2000 2001 2002 2003
CODE IN HEX
COUNTS
0 0
261120
00
06396-007
Figure 7. Histogram of 261,120 Conversions of a DC Input
at the Code Center
–1.0
–0.5
0
0.5
1.0
04096 8192 12288 16384
CODE
DNL ( LSB)
POSITIVE DNL = +0.27
NEGATI V E DNL = –0.27
06396-008
Figure 8. Differential Nonlinearity vs. Code
0
20
40
60
80
100
120
140
160
180
200
NUMBER O F UNI TS
–1.0 –0.8 –0.6 –0.4 –0.2 00.2 0.4 0.6 0.8 1.0
NEGATI V E DNL
POSITI VE DNL
DNL DI S TRI BUTI ON (LSB)
06396-009
Figure 9. Differential Nonlinearity Distribution (239 Devices)
0
20000
40000
60000
80000
100000
120000
140000
8192 8193 8194 8195 8196 8197
0 0
132052
0
129068
0
CODE IN HEX
COUNTS
06396-010
Figure 10. Histogram of 261,120 Conversions of a DC Input
at the Code Transition
Rev. B | Page 12 of 32
Data Sheet AD7951
–160
–140
–120
–100
–80
–60
–40
–20
0
0100 200 400
300 500
FREQUENCY ( kHz )
AMPLITUDE (dB OF FULL SCALE)
f
S = 1000kSPS
f
IN = 19.94kHz
SNR = 85. 4dB
THD = –107dB
SFDR = 116dB
SINAD = 85.4d B
06396-011
Figure 11. FFT 20 kHz
78
80
82
84
86
88
110 100
13.5
13.7
13.9
14.1
14.3
14.5
ENOB ( Bits)
SNR
SINAD
ENOB
FREQUENCY ( kHz )
SNR, S INAD (dB)
06396-012
Figure 12. SNR, SINAD, and ENOB vs. Frequency
84.0
84.5
85.0
85.5
86.0
–55 –35 –15 525 45 65 85 105 125
0V TO 5V
0V TO 10V
±5V
±10V
TEMPERATURE (°C)
SNR (dB)
06396-013
Figure 13. SNR vs. Temperature
85.0
85.5
86.0
86.5
–60 –50 –40 –30 –20 –10 0
06396-014
INPUT LEVEL (d B)
SNR, S INAD REFERRE D TO FULL SCALE ( dB)
SNR
SINAD
Figure 14. SNR and SINAD vs. Input Level (Referred to Full Scale)
–130
–120
–110
–100
–90
–80
–70
110 100
60
70
80
90
100
110
120
SFDR (dB)
SFDR
THD
SECOND
HARMONIC
THD, HARMONICS ( dB)
FREQUENCY ( kHz )
THIRD
HARMONIC
06396-015
Figure 15. THD, Harmonics, and SFDR vs. Frequency
84.0
84.5
85.0
85.5
86.0
TEMPERATURE (°C)
SINAD ( dB)
–55 –35 –15 525 45 65 85 105 125
0V TO 5V
0V TO 10V
±5V
±10V
06396-016
Figure 16. SINAD vs. Temperature
Rev. B | Page 13 of 32
AD7951 Data Sheet
–120
–116
–112
–108
–104
–100
–96
TEMPERATURE (°C)
THD ( dB)
–55 –35 –15 525 45 65 85 105 125
0V TO 5V
0V TO 10V
±5V
±10V
06396-017
Figure 17. THD vs. Temperature
1.5
–1.5
–55 125
ZERO ERROR, FUL L SCAL E E RROR (LSB)
TEMPERATURE (°C)
1.0
0
0.5
–0.5
–1.0
25 65 85 105–35 –15 545
ZERO ERROR
POSITI VE F S ERROR
NEGATI VE F S ERROR
06396-018
Figure 18. Zero Error, Positive and Negative Full Scale vs. Temperature
60
008
REFE RE NCE DRIF T (pp m/° C)
NUMBER O F UNI TS
50
40
30
20
10
1 2 3
4 5 6 7
06396-019
Figure 19. Reference Voltage Temperature Coefficient Distribution (247 Devices)
106
108
110
112
114
116
118
120
122
124
TEMPERATURE (°C)
SFDR (dB)
–55 –35 –15 525 45 65 85 105 125
0V TO 5V
0V TO 10V
±5V
±10V
06396-020
Figure 20. SFDR vs. Temperature (Excludes Harmonics)
5.008
4.996
–55 125
VREF (V)
TEMPERATURE (°C)
5.006
5.002
5.004
5.000
4.998
25 65 85 105–35 –15 545
06396-021
Figure 21. Typical Reference Voltage Output vs. Temperature (3 Devices)
100000
0.001 1000000
OPE RATI NG CURRENTS ( µ A)
SAMPLING RATE (SPS)
06396-022
100
10
10 100 1000 10000 100000
1000
1
0.1
0.01
10000
PDREF = P DBUF = HIG H
VCC +15V
VEE –15V
ALL MODES
AVDD, WARP/NO RM AL
OVDD, ALL MODES
DVDD, ALL M ODES
AVDD, IMP ULSE
Figure 22. Operating Currents vs. Sample Rate
Rev. B | Page 14 of 32
Data Sheet AD7951
0
100
200
300
400
500
600
700
06396-023
TEMPERATURE (°C)
POWER–DOW N OPE RATING CURRENTS ( nA)
–55 –35 –15 525 45 65 85 105
PD = PDBUF = P DRE F = HIG H
VEE = –15V
VCC = +15V
DVDD
OVDD
AVDD
Figure 23. Power-Down Operating Currents vs. Temperature
0
5
10
15
20
25
30
35
40
45
50
050 100 150 200
CL (pF)
t
12 DELAY (ns)
OVDD = 2.7V @ 25°C
OVDD = 2.7V @ 85°C
OVDD = 5V @ 85°C
OVDD = 5V @ 25°C
06396-024
Figure 24. Typical Delay vs. Load Capacitance CL
Rev. B | Page 15 of 32
AD7951 Data Sheet
TERMINOLOGY
Least Significant Bit (LSB)
The least significant bit, or LSB, is the smallest increment that
can be represented by a converter. For an analog-to-digital
converter with N bits of resolution, the LSB expressed in volts is
N
pINp
V
LSB 2
(max)
(V)
−
=
Integral Nonlinearity Error (INL)
Linearity error refers to the deviation of each individual code
from a line drawn from negative full-scale through positive full-
scale. The point used as negative full-scale occurs a ½ LSB
before the first code transition. Positive full-scale is defined as a
level 1½ LSBs beyond the last code transition. The deviation is
measured from the middle of each code to the true straight line.
Differential Nonlinearity Error (DNL)
In an ideal ADC, code transitions are 1 LSB apart. Differential
nonlinearity is the maximum deviation from this ideal value. It
is often specified in terms of resolution for which no missing
codes are guaranteed.
Bipolar Zero Error
The difference between the ideal midscale input voltage (0 V)
and the actual voltage producing the midscale output code.
Unipolar Offset Error
The first transition should occur at a level ½ LSB above analog
ground. The unipolar offset error is the deviation of the actual
transition from that point.
Full-Scale Error
The last transition (from 111…10 to 111…11) should occur for
an analog voltage 1½ LSB below the nominal full-scale. The
full-scale error is the deviation in LSB (or % of full-scale range)
of the actual level of the last transition from the ideal level and
includes the effect of the offset error. Closely related is the gain
error (also in LSB or % of full-scale range), which does not
include the effects of the offset error.
Dynamic Range
Dynamic range is the ratio of the rms value of the full-scale to
the rms noise measured for an input typically at −60 dB. The
value for dynamic range is expressed in decibels.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the rms value of the actual input signal to the
rms sum of all other spectral components below the Nyquist
frequency, excluding harmonics and dc. The value for SNR is
expressed in decibels.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first five harmonic
components to the rms value of a full-scale input signal and is
expressed in decibels.
Signal-to-(Noise + Distortion) Ratio (SINAD)
SINAD is the ratio of the rms value of the actual input signal to
the rms sum of all other spectral components below the Nyquist
frequency, including harmonics but excluding dc. The value for
SINAD is expressed in decibels.
Spurious-Free Dynamic Range (SFDR)
The difference, in decibels (dB), between the rms amplitude of
the input signal and the peak spurious signal.
Effective Number of Bits (ENOB)
ENOB is a measurement of the resolution with a sine wave
input. It is related to SINAD and is expressed in bits by
ENOB = [(SINADdB − 1.76)/6.02]
Aperture Delay
Aperture delay is a measure of the acquisition performance
measured from the falling edge of the CNVST input to when
the input signal is held for a conversion.
Transient Response
The time required for the AD7951 to achieve its rated accuracy
after a full-scale step function is applied to its input.
Reference Voltage Temperature Coefficient
Reference voltage temperature coefficient is derived from the
typical shift of output voltage at 25°C on a sample of parts at the
maximum and minimum reference output voltage (VREF)
measured at TMIN, T(25°C), and TMAX. It is expressed in ppm/°C as
6
10
)–()C25(
)
–)
)Cppm/(×
×°
=°
MIN
MAX
REF
REFREF
REF
TTV
Min(VMax(V
TCV
where:
VREF (Max) = maximum VREF at TMIN, T(25°C), or TMAX.
VREF (Min) = minimum VREF at TMIN, T(25°C), or TMAX.
VREF (25°C) = VREF at 25°C.
TMAX = +85°C.
TMIN = –40°C.
Rev. B | Page 16 of 32
Data Sheet AD7951
THEORY OF OPERATION
SW
A
SW
B
IN+
REF
REFGND
LSB
MSB
8,192C
IN–
4,096C 4C 2C CC
16,384C
CONTROL
LOGIC
SWITCHES
CONTROL
BUSY
OUTPUT
CODE
CNVST
COMP
06396-025
Figure 25. ADC Simplified Schematic
OVERVIEW
The AD7951 is a very fast, low power, precise, 14-bit analog-to-
digital converter (ADC) using successive approximation capacitive
digital-to-analog (CDAC) converter architecture.
The AD7951 can be configured at any time for one of four input
ranges and conversion mode with inputs in parallel and serial
hardware modes or by a dedicated write only, SPI-compatible
interface via a configuration register in serial software mode.
The AD7951 uses Analog Devices’ patented iCMOS high
voltage process to accommodate 0 to 5 V, 0 to 10 V, ±5 V, and
±10 V input ranges without the use of conventional thin films.
Only one acquisition cycle, t8, is required for the inputs to latch to
the correct configuration. Resetting or power cycling is not
required for reconfiguring the ADC.
The AD7951 features different modes to optimize performance
according to the applications. It is capable of converting
1,000,000 samples per second (1 MSPS) in warp mode, 800 kSPS
in normal mode, and 670 kSPS in impulse mode.
The AD7951 provides the user with an on-chip track-and-hold,
successive approximation ADC that does not exhibit any pipe-
line or latency, making it ideal for multiple, multiplexed channel
applications.
For unipolar input ranges, the AD7951 typically requires three
supplies; VCC, AVDD (which can supply DVDD), and OVDD
which can be interfaced to either 5 V, 3.3 V, or 2.5 V digital
logic. For bipolar input ranges, the AD7951 requires the use of
the additional VEE supply.
The device is housed in Pb-free, 48-lead LQFP or tiny LFCSP
7 mm × 7 mm packages that combine space savings with
flexibility. In addition, the AD7951 can be configured as either a
parallel or a serial SPI-compatible interface.
CONVERTER OPERATION
The AD7951 is a successive approximation ADC based on a
charge redistribution DAC. Figure 25 shows the simplified
schematic of the ADC. The CDAC consists of two identical
arrays of 16 binary weighted capacitors, which are connected to
the two comparator inputs.
During the acquisition phase, terminals of the array tied to the
comparator’s input are connected to AGND via SW+ and SW−.
All independent switches are connected to the analog inputs.
Thus, the capacitor arrays are used as sampling capacitors and
acquire the analog signal on IN+ and IN− inputs. A conversion
phase is initiated once the acquisition phase is complete and the
CNVST input goes low. When the conversion phase begins,
SW+ and SW− are opened first. The two capacitor arrays are
then disconnected from the inputs and connected to the REFGND
input. Therefore, the differential voltage between the inputs
(IN+ and IN−) captured at the end of the acquisition phase is
applied to the comparator inputs, causing the comparator to
become unbalanced. By switching each element of the capacitor
array between REFGND and REF, the comparator input varies
by binary weighted voltage steps (VREF/2, VREF/4 through VREF/
16,384). The control logic toggles these switches, starting with
the MSB first, in order to bring the comparator back into a
balanced condition.
After the completion of this process, the control logic generates
the ADC output code and brings the BUSY output low.
Rev. B | Page 17 of 32
AD7951 Data Sheet
Rev. B | Page 18 of 32
MODES OF OPERATION
The AD7951 features three modes of operation: warp, normal,
and impulse. Each of these modes is more suitable to specific
applications. The mode is configured with the input pins, WARP
and IMPULSE, or via the configuration register. See Table 6 for
the pin details and the Hardware Configuration section and
Software Configuration section for programming the mode
selection with either pins or configuration register. Note that
when using the configuration register, the WARP and IMPULSE
inputs are don’t cares and should be tied to either high or low.
Warp Mode
Setting WARP = high and IMPULSE = low allows the fastest
conversion rate up to 1 MSPS. However, in this mode, the full
specified accuracy is guaranteed only when the time between
conversions does not exceed 1 ms. If the time between two
consecutive conversions is longer than 1 ms (after power-up),
the first conversion result should be ignored since in warp mode,
the ADC performs a background calibration during the SAR
conversion process. This calibration can drift if the time between
conversions exceeds 1 ms thus causing the first conversion to
appear offset. This mode makes the AD7951 ideal for applications
where both high accuracy and fast sample rate are required.
Normal Mode
Setting WARP = IMPULSE = low or WARP = IMPULSE = high
allows the fastest mode (800 kSPS) without any limitation on
time between conversions. This mode makes the AD7951 ideal
for asynchronous applications such as data acquisition systems,
where both high accuracy and fast sample rate are required.
Impulse Mode
Setting WARP = low and IMPULSE = high uses the lowest power
dissipation mode and allows power saving between conversions.
The maximum throughput in this mode is 670 kSPS and in this
mode, the ADC powers down circuits after conversion making
the AD7951 ideal for battery-powered applications.
TRANSFER FUNCTIONS
Using the OB/2C digital input or via the configuration register,
the AD7951 offers two output codings: straight binary and twos
complement. See Figure 26 and Table 7 for the ideal transfer
characteristic and digital output codes for the different analog
input ranges, VIN. Note that when using the configuration
register, the OB/2C input is a don’t care and should be tied to
either high or low.
000...000
000...001
000...010
111...101
111...110
111...111
ADC CODE (S t raight Bin ary)
ANALOG INPUT
+FSR – 1.5 LSB
+FSR –1LSB–FSR + 1 LSB
–FSR
–FSR + 0.5 LSB
06396-026
Figure 26. ADC Ideal Transfer Function
Table 7. Output Codes and Ideal Input Voltages
VREF = 5 V Digital Output Code
Description VIN = 5 V VIN = 10 V VIN = ±5 V VIN = ±10 V Straight Binary Twos Complement
FSR − 1 LSB 4.999695 V 9.999389 V +4.999389 V +9.998779 V 0x3FFF1 0x1FFF1
FSR − 2 LSB 4.999390 V 9.998779 V +4.998779 V +9.997558 V 0x3FFE 0x1FFE
Midscale + 1 LSB 2.500305 V 5.000610 V +610.4 μV +1.221 mV 0x2001 0x0001
Midscale 2.5 V 5.000000 V 0 V 0 V 0x2000 0x0000
Midscale − 1 LSB 2.499695 V 4.999389 V −610.4 μV −1.221 mV 0x1FFF 0x3FFF
−FSR + 1 LSB 305.2 μV 610.4 μV −4.999389 V −9.998779 V 0x0001 0x2001
−FSR 0 V 0 V −5 V −10 V 0x00002 0x20002
1 This is also the code for overrange analog input (VIN+ − VIN− above VREF − VREFGND).
2 This is also the code for overrange analog input (VIN+ − VIN− below VREF − VREFGND).
Data Sheet AD7951
Rev. B | Page 19 of 32
TYPICAL CONNECTION DIAGRAM
Figure 27 shows a typical connection diagram for the AD7951 using the internal reference, serial data and serial configuration interfaces.
Different circuitry from that shown in Figure 27 is optional and is discussed in the following sections.
RD CS
100nF 100nF
AVDD
10µF 100nF
AGND DGND DVDD OVDD OGND
CNVST
BUSY
SDOUT
SDCLK
RESETPD
REFBUFIN
D
CLOCK
AD7951
MICROCONVERTER/
MICROPROCESSOR/
DSP
DIGITAL
INTERFACE
SUPPLY
(2.5V, 3.3V, OR 5V)
ANALOG
SUPPLY (5V)
OVDD
DIGITAL
SUPPLY (5V)
IN+
IN–
NOTE 5
ANALOG
INPUT+
C
C
2.7nF
U1
NOTE 1
SER/PAR
OB/2C
REFGND
REF
PDBUF
PDREF
100nF
NOTE 3
NOTE 4
NOTE 3
NOTE 7
10µF
10µF
C
REF
22µF
NOTES
1. SEE ANALOG INPUT SECTION. ANALOG INPUT(–) IS REFERENCED TO AGND ±0.1V.
2. THE AD8021 IS RECOMMENDED. SEE DRIVER AMPLIFIER CHOICE SECTION.
3. THE CONFIGURATION SHOWN IS USING THE INTERNAL REFERENCE. SEE VOLTAGE REFERENCE INPUT SECTION.
4. A 22µF CERAMIC CAPACITOR (X5R, 1206 SIZE) IS RECOMMENDED (FOR EXAMPLE, PANASONIC ECJ4YB1A226M).
SEE VOLTAGE REFERENCE INPUT SECTION.
5. OPTION, SEE POWER SUPPLY SECTION.
6. THE VCC AND VEE SUPPLIES SHOULD BE VCC = [VIN(MAX) +2V] AND VEE = [VIN(MIN) –2V] FOR BIPOLAR INPUT RANGES.
FOR UNIPOLAR INPUT RANGES, VEE CAN BE 0V. SEE POWER SUPPLY SECTION.
7. OPTIONAL LOW JITTER CNVST, SEE CONVERSION CONTROL SECTION.
ANALOG
INPUT–
NOTE 2
VCC
VEE
10µF 100nF
+7V TO +15.75V
SUPPLY
10µF 100nF
–7V TO –15.75V
SUPPLY
NOTE 6
HW/SW
SCCS
SCCLK
SCIN
BIPOLAR
TEN
SERIAL
PORT 1
SERIAL
PORT 2
WARP
IMPULSE
06396-027
50Ω
15Ω
10Ω
Figure 27. Typical Connection Diagram Shown with Serial Interface and Serial Programmable Port
AD7951 Data Sheet
Rev. B | Page 20 of 32
ANALOG INPUTS
Input Range Selection
In parallel mode and serial hardware mode, the input range is
selected by using the BIPOLAR (bipolar) and TEN (10 Volt
range) inputs. See Table 6 for pin details and the Hardware
Configuration section and Software Configuration section for
programming the mode selection with either pins or configuration
register. Note that when using the configuration register, the
BIPOLAR and TEN inputs are don’t cares and should be tied to
either high or low.
Input Structure
Figure 28 shows an equivalent circuit for the input structure of
the AD7951.
D1 R
IN
C
IN
D2
IN+ OR IN–
VEE
VCC
C
PIN
AGND
D3
D4
AVDD
0
V
TO 5V
RANGE ONLY
0
6396-028
Figure 28. AD7951 Simplified Analog Input
The four diodes, D1 to D4, provide ESD protection for the analog
inputs, IN+ and IN−. Care must be taken to ensure that the analog
input signal never exceeds the supply rails by more than 0.3 V,
because this causes the diodes to become forward-biased and to
start conducting current. These diodes can handle a forward-
biased current of 120 mA maximum. For instance, these conditions
could eventually occur when the input buffer’s U1 supplies are
different from AVDD, VCC, and VEE. In such a case, an input
buffer with a short-circuit current limitation can be used to protect
the part although most op amps’ short circuit current is <100 mA.
Note that D3 and D4 are only used in the 0 V to 5 V range to
allow for additional protection in applications that are switching
from the higher voltage ranges.
This analog input structure allows the sampling of the differential
signal between IN+ and IN−. By using this differential input,
small signals common to both inputs are rejected as shown in
Figure 29, which represents the typical CMRR over frequency.
For instance, by using IN− to sense a remote signal ground,
ground potential differences between the sensor and the local
ADC ground are eliminated.
100
01 10000
FREQUENCY ( kHz)
CMRR (dB)
90
80
70
60
50
40
30
20
10
10 100 1000
06396-029
Figure 29. Analog Input CMRR vs. Frequency
During the acquisition phase for ac signals, the impedance of
the analog inputs, IN+ and IN−, can be modeled as a parallel
combination of Capacitor CPIN and the network formed by the
series connection of RIN and CIN. CPIN is primarily the pin
capacitance. RIN is typically 70 Ω and is a lumped component
comprised of serial resistors and the on resistance of the switches.
CIN is primarily the ADC sampling capacitor and depending on the
input range selected is typically 48 pF in the 0 V to 5 V range,
typically 24 pF in the 0 V to 10 V and ±5 V ranges and typically
12 pF in the ±10 V range. During the conversion phase, when the
switches are opened, the input impedance is limited to CPIN.
Since the input impedance of the AD7951 is very high, it can be
directly driven by a low impedance source without gain error.
To further improve the noise filtering achieved by the AD7951
analog input circuit, an external, one-pole RC filter between the
amplifier’s outputs and the ADC analog inputs can be used, as
shown in Figure 27. However, large source impedances signifi-
cantly affect the ac performance, especially total harmonic
distortion (THD). The maximum source impedance depends on
the amount of THD that can be tolerated. The THD degrades as
a function of the source impedance and the maximum input
frequency.
Data Sheet AD7951
Rev. B | Page 21 of 32
DRIVER AMPLIFIER CHOICE
Although the AD7951 is easy to drive, the driver amplifier must
meet the following requirements:
For multichannel, multiplexed applications, the driver
amplifier and the AD7951 analog input circuit must be
able to settle for a full-scale step of the capacitor array at a
14-bit level (0.006%). For the amplifier, settling at 0.1% to
0.01% is more commonly specified. This differs significantly
from the settling time at a 14-bit level and should be
verified prior to driver selection. The AD8021 op amp com-
bines ultralow noise and high gain bandwidth and meets
this settling time requirement even when used with gains
of up to 13.
The noise generated by the driver amplifier needs to be
kept as low as possible to preserve the SNR and transition
noise performance of the AD7951. The noise coming from
the driver is filtered by the external one-pole low-pass filter
as shown in Figure 27. The SNR degradation due to the
amplifier is

2
3
2
2
log20
N
dB
NADC
NADC
LOSS
NefV
V
SNR
where:
VNADC is the noise of the ADC, which is:
20
10
22
SNR
INp-p
NADC
V
V
f–3dB is the cutoff frequency of the input filter (3.9 MHz).
N is the noise factor of the amplifier (+1 in buffer
configuration).
eN is the equivalent input voltage noise density of the op
amp, in nV/√Hz.
The driver needs to have a THD performance suitable to
that of the AD7951. Figure 15 shows the THD vs. frequency
that the driver should exceed.
The AD8021 meets these requirements and is appropriate for
almost all applications. The AD8021 needs a 10 pF external
compensation capacitor that should have good linearity as an
NPO ceramic or mica type. Moreover, the use of a noninverting
+1 gain arrangement is recommended and helps to obtain the
best signal-to-noise ratio.
The AD8022 can also be used when a dual version is needed
and a gain of 1 is present. The AD829 is an alternative in applica-
tions where high frequency (above 100 kHz) performance is not
required. In applications with a gain of 1, an 82 pF compensation
capacitor is required. The AD8610 is an option when low bias
current is needed in low frequency applications.
Since the AD7951 uses a large geometry, high voltage input
switch, the best linearity performance is obtained when using
the amplifier at its maximum full power bandwidth. Gaining
the amplifier to make use of the more dynamic range of the
ADC results in increased linearity errors. For applications
requiring more resolution, the use of an additional amplifier
with gain should precede a unity follower driving the AD7951.
See Table 8 for a list of recommended op amps.
Table 8. Recommended Driver Amplifiers
Amplifier Typical Application
ADA4841-1/
ADA4841-2
12 V supply, very low noise, low distortion,
low power, low frequency
AD829 ±15 V supplies, very low noise, low frequency
AD8021 ±12 V supplies, very low noise, high frequency
AD8022 ±12 V supplies, very low noise, high
frequency, dual
AD8610/
AD8620
±13 V supplies, low bias current, low
frequency, single/dual
VOLTAGE REFERENCE INPUT/OUTPUT
The AD7951 allows the choice of either a very low temperature
drift internal voltage reference, an external reference, or an
external buffered reference.
The internal reference of the AD7951 provides excellent perform-
ance and can be used in almost all applications. However, the
linearity performance is guaranteed only with an external reference.
AD7951 Data Sheet
Rev. B | Page 22 of 32
Internal Reference (REF = 5 V)
(PDREF = Low, PDBUF = Low)
To use the internal reference, the PDREF and PDBUF inputs
must be low. This enables the on-chip band gap reference, buffer,
and TEMP sensor resulting in a 5.00 V reference on the REF pin.
The internal reference is temperature-compensated to 5.000 V
±35 mV. The reference is trimmed to provide a typical drift of
3 ppm/°C. This typical drift characteristic is shown in Figure 19.
External 2.5 V Reference and Internal Buffer (REF = 5 V)
(PDREF = High, PDBUF = Low)
To use an external reference with the internal buffer, PDREF
should be high and PDBUF should be low. This powers down
the internal reference and allows the 2.5 V reference to be applied
to REFBUFIN producing 5 V on the REF pin. The internal
reference buffer is useful in multiconverter applications because
a buffer is typically required in these applications.
External 5 V Reference (PDREF = High, PDBUF = High)
To use an external reference directly on the REF pin, PDREF
and PDBUF should both be high. PDREF and PDBUF power
down the internal reference and the internal reference buffer,
respectively. For improved drift performance, an external
reference such as the ADR445 or ADR435 is recommended.
Reference Decoupling
Whether using an internal or external reference, the AD7951
voltage reference input (REF) has a dynamic input impedance;
therefore, it should be driven by a low impedance source with
efficient decoupling between the REF and REFGND inputs. This
decoupling depends on the choice of the voltage reference, but
usually consists of a low ESR capacitor connected to REF and
REFGND with minimum parasitic inductance. A 22 µF (X5R,
1206 size) ceramic chip capacitor (or 47 µF tantalum capacitor)
is appropriate when using either the internal reference or the
ADR445/ADR435 external reference.
The placement of the reference decoupling is also important to
the performance of the AD7951. The decoupling capacitor should
be mounted on the same side as the ADC, right at the REF pin
with a thick PCB trace. The REFGND should also connect to
the reference decoupling capacitor with the shortest distance
and to the analog ground plane with several vias.
For applications that use multiple AD7951 or other PulSAR
devices, it is more effective to use the internal reference buffer
to buffer the external 2.5 V reference voltage.
The voltage reference temperature coefficient (TC) directly impacts
full scale; therefore, in applications where full-scale accuracy
matters, care must be taken with the TC. For instance, a
±15 ppm/°C TC of the reference changes full-scale by ±1 LSB/°C.
Temperature Sensor
When the internal reference is enabled (PDREF = PDBUF =
low), the on-chip temperature sensor output (TEMP) is enabled
and can be use to measure the temperature of the AD7951. To
improve the calibration accuracy over the temperature range, the
output of the TEMP pin is applied to one of the inputs of the
analog switch (such as ADG779), and the ADC itself is used to
measure its own temperature. This configuration is shown
in Figure 30.
ADG779
C
C
ANALO G INP UT
AD7951
IN+ TEMPERATURE
SENSOR
TEMP
06396-030
Figure 30. Use of the Temperature Sensor
POWER SUPPLIES
The AD7951 uses five sets of power supply pins:
AVDD: analog 5 V core supply
VCC: analog high voltage positive supply
VEE: high voltage negative supply
DVDD: digital 5 V core supply
OVDD: digital input/output interface supply
Core Supplies
The AVDD and DVDD supply the AD7951 analog and digital
cores respectively. Sufficient decoupling of these supplies is
required consisting of at least a 10 F capacitor and 100 nF on
each supply. The 100 nF capacitors should be placed as close as
possible to the AD7951. To reduce the number of supplies needed,
the DVDD can be supplied through a simple RC filter from the
analog supply, as shown in Figure 27.
High Voltage Supplies
The high voltage bipolar supplies, VCC and VEE are required
and must be at least 2 V larger than the maximum input, VIN.
For example, if using the bipolar 10 V range, the supplies should
be ±12 V minimum. Sufficient decoupling of these supplies is
also required consisting of at least a 10 F capacitor and 100 nF
on each supply. For unipolar operation, the VEE supply can be
grounded with some slight THD performance degradation.
Digital Output Supply
The OVDD supplies the digital outputs and allows direct interface
with any logic working between 2.3 V and 5.25 V. OVDD should
be set to the same level as the system interface. Sufficient
decoupling is required, consisting of at least a 10 F capacitor and
100 nF with the 100 nF placed as close as possible to the AD7951.
Data Sheet AD7951
Rev. B | Page 23 of 32
Power Sequencing
The AD7951 requires sequencing of the AVDD and DVDD
supplies. AVDD should come up prior to or simultaneously
with DVDD. This can be achieved using the configuration in
Figure 27 or sequencing the supplies in that manner. The
other supplies can be sequenced as desired as long as absolute
maximum ratings are observed. The AD7951 is very insensitive
to power supply variations on AVDD over a wide frequency
range, as shown in Figure 31.
80
75
1 10000
FRE QUENCY (kHz )
PSRR (dB)
10 100 1000
70
65
60
55
50
45
40
35
30
EXT REF
INT REF
0
6396-031
Figure 31. AVDD PSRR vs. Frequency
Power Dissipation vs. Throughput
In impulse mode, the AD7951 automatically reduces its power
consumption at the end of each conversion phase. During the
acquisition phase, the operating currents are very low, which allows
a significant power savings when the conversion rate is reduced
(see Figure 32). This feature makes the AD7951 ideal for very
low power, battery-operated applications.
It should be noted that the digital interface remains active even
during the acquisition phase. To reduce the operating digital supply
currents even further, drive the digital inputs close to the power
rails (that is, OVDD and OGND).
1000
110 1000000
POWE R DISSI PATI ON (mW)
06396-032
100
10
100 1000 10000 100000
PDRE F = P DBUF = HIG H
WARP M ODE P OW E R
IMPULSE MO DE PO W ER
Figure 32. Power Dissipation vs. Sample Rate
Power Down
Setting PD = high powers down the AD7951, thus reducing
supply currents to their minimums as shown in Figure 23. When
the ADC is in power down, the current conversion (if any) is
completed and the digital bus remains active. To further reduce
the digital supply currents, drive the inputs to OVDD or OGND.
Power down can also be programmed with the configuration
register. See the Software Configuration section for details. Note
that when using the configuration register, the PD input is a
don’t care and should be tied to either high or low.
CONVERSION CONTROL
The AD7951 is controlled by the CNVST input. A falling edge
on CNVST is all that is necessary to initiate a conversion. Detailed
timing diagrams of the conversion process are shown in Figure 33.
Once initiated, it cannot be restarted or aborted, even by the
power-down input, PD, until the conversion is complete. The
CNVST signal operates independently of CS and RD signals.
BUSY
MODE CONVERT ACQUIREACQUIRE CONVERT
CNVST
t
1
t
2
t
4
t
3
t
5
t
6
t
7
t
8
0
6396-033
Figure 33. Basic Conversion Timing
Although CNVST is a digital signal, it should be designed with
special care with fast, clean edges, and levels with minimum
overshoot, undershoot, or ringing.
The CNVST trace should be shielded with ground and a low value
(such as 50 Ω) serial resistor termination should be added close
to the output of the component that drives this line.
For applications where SNR is critical, the CNVST signal should
have very low jitter. This can be achieved by using a dedicated
oscillator for CNVST generation, or by clocking CNVST with a
high frequency, low jitter clock, as shown in Figure 27.
AD7951 Data Sheet
Rev. B | Page 24 of 32
INTERFACES
DIGITAL INTERFACE
The AD7951 has a versatile digital interface that can be set up
as either a serial or a parallel interface with the host system. The
serial interface is multiplexed on the parallel data bus. The AD7951
digital interface also accommodates 2.5 V, 3.3 V, or 5 V logic. In
most applications, the OVDD supply pin is connected to the host
system interface 2.5 V to 5.25 V digital supply. Finally, by using
the OB/2C input pin, both twos complement or straight binary
coding can be used.
Two signals, CS and RD, control the interface. When at least
one of these signals is high, the interface outputs are in high
impedance. Usually, CS allows the selection of each AD7951 in
multicircuit applications and is held low in a single AD7951
design. RD is generally used to enable the conversion result on
the data bus.
RESET
The RESET input is used to reset the AD7951. A rising edge on
RESET aborts the current conversion (if any) and tristates the
data bus. The falling edge of RESET resets the AD7951 and
clears the data bus and configuration register. See Figure 34 for
the RESET timing details.
t
9
t
8
RESET
DATA
BUS
BUSY
CNVST
0
6396-034
Figure 34. RESET Timing
PARALLEL INTERFACE
The AD7951 is configured to use the parallel interface when
SER/PAR is held low.
Master Parallel Interface
Data can be continuously read by tying CS and RD low, thus
requiring minimal microprocessor connections. However, in
this mode, the data bus is always driven and cannot be used in
shared bus applications (unless the device is held in RESET).
Figure 35 details the timing for this mode.
t
1
BUSY
DATA
BUS PREVIOUS CONVERSION DATA NEW DATA
CNVST
CS = RD = 0
t
10
t
4
t
11
t
3
06396-035
Figure 35. Master Parallel Data Timing for Reading (Continuous Read)
Slave Parallel Interface
In slave parallel reading mode, the data can be read either after
each conversion, which is during the next acquisition phase, or
during the following conversion, as shown in Figure 36 and
Figure 37, respectively. When the data is read during the conver-
sion, it is recommended that it is read only during the first half
of the conversion phase. This avoids any potential feedthrough
between voltage transients on the digital interface and the most
critical analog conversion circuitry.
CURRENT
CONVERSION
t
13
t
12
BUSY
DATA
BUS
RD
CS
06396-036
Figure 36. Slave Parallel Data Timing for Reading (Read After Convert)
PREVIOUS
CONVERSION
t
13
t
12
t
3
BUSY
DATA
BUS
CNVST,
RD
CS = 0
t
4
t
1
06396-037
Figure 37. Slave Parallel Data Timing for Reading (Read During Convert)
Data Sheet AD7951
Rev. B | Page 25 of 32
8-Bit Interface (Master or Slave)
The BYTESWAP pin allows a glueless interface to an 8-bit bus.
As shown in Figure 38, when BYTESWAP is low, the LSB byte is
output on D[7:0] and the MSB is output on D[13:8]. When
BYTESWAP is high, the LSB and MSB bytes are swapped; the
LSB is output on D[13:8] and the MSB is output on D[7:0]. By
connecting BYTESWAP to an address line, the 14-bit data can
be read in two bytes on either D[13:8] or D[7:0]. This interface
can be used in both master and slave parallel reading modes.
CS
RD
BYTESWAP
PI NS D[ 13:8]
PINS D[ 7:0] HI-Z
HI-Z HI GH BYT E LOW BYTE
LOW BY TE HIGH BYTE HI-Z
HI-Z
t
12
t
12
t
13
06396-038
Figure 38. 8-Bit and 14-Bit Parallel Interface
SERIAL INTERFACE
The AD7951 has a serial interface (SPI-compatible) multiplexed
on the data pins D[13:0]. The AD7951 is configured to use the
serial interface when SER/PAR is held high.
Data Interface
The AD7951 outputs 14 bits of data, MSB first, on the SDOUT
pin. This data is synchronized with the 14 clock pulses provided
on the SDCLK pin. The output data is valid on both the rising
and falling edge of the data clock.
Serial Configuration Interface
The AD7951 can be configured through the serial configuration
register only in serial mode, as the serial configuration pins are
also multiplexed on the data pins D[13:10]. Refer to the Hardware
Configuration section and Software Configuration section for
more information.
MASTER SERIAL INTERFACE
The pins multiplexed on D[8:0] and used for master serial
interface are: DIVSCLK[0], DIVSCLK[1], EXT/INT, INVSYNC,
INVSCLK, RDC, SDOUT, SDCLK and SYNC.
Internal Clock (SER/PAR = High, EXT/INT = Low)
The AD7951 is configured to generate and provide the serial
data clock, SDCLK, when the EXT/INT pin is held low. The
AD7951 also generates a SYNC signal to indicate to the host
when the serial data is valid. The SDCLK, and the SYNC signals
can be inverted, if desired using the INVSCLK and INVSYNC
inputs, respectively. Depending on the input, RDC, the data can
be read during the following conversion or after each conversion.
Figure 39 and Figure 40 show detailed timing diagrams of these
two modes.
Read During Convert (RDC = High)
Setting RDC = high, allows the master read (previous
conversion result) during conversion mode. Usually, because
the AD7951 is used with a fast throughput, this mode is the
most recommended serial mode. In this mode, the serial clock
and data toggle at appropriate instances, minimizing potential
feedthrough between digital activity and critical conversion
decisions. In this mode, the SDCLK period changes since the
LSBs require more time to settle and the SDCLK is derived
from the SAR conversion cycle. In this mode, the AD7951
generates a discontinuous SDCLK of two different periods and
the host should use an SPI interface.
Read After Convert (RDC = Low, DIVSCLK[1:0] = [0 to 3])
Setting RDC = low allows the read after conversion mode.
Unlike the other serial modes, the BUSY signal returns low
after the 14 data bits are pulsed out and not at the end of the
conversion phase, resulting in a longer BUSY width (refer to
Table 4 for BUSY timing specifications). The DIVSCLK[1:0]
inputs control the SDCLK period and SDOUT data rate. As a
result, the maximum throughput cannot be achieved in this
mode. In this mode, the AD7951 also generates a discontinuous
SDCLK; however, a fixed period and hosts supporting both SPI
and serial ports can also be used.
AD7951 Data Sheet
Rev. B | Page 26 of 32
BUSY
SYNC
SDCLK
SDOUT
123 121314
D13 D12 D2 D1 D0
X
RDC/SDIN = 0 INVSCLK = INVS Y NC = 0
CNVST
CS, RD
EXT/INT = 0
t
23
t
22
t
16
t
15
t
14
t
29
t
19
t
21
t
20
t
18
t
28
t
30
t
24
t
25
t
26
t
27
t
3
06396-039
Figure 39. Master Serial Data Timing for Reading (Read After Convert)
EXT/INT = 0 RDC/SDIN = 1 INVSCLK = I NV S Y NC = 0
D13 D12 D2 D1 D0X
123 121314
BUSY
SYNC
SDCLK
SDOUT
CNVST
CS, RD
t
23
t
18
t
15
t
14
t
17
t
3
t
22
t
16
t
1
t
25
t
26
t
24
t
27
t
19
t
20
t
21
06396-040
Figure 40. Master Serial Data Timing for Reading (Read Previous Conversion During Convert)
Data Sheet AD7951
SLAVE SERIAL INTERFACE
The pins multiplexed on D[19:2] used for slave serial
interface are: EXT/INT, INVSCLK, SDIN, SDOUT,
SDCLK and RDERROR.
External Clock (SER/PAR = High, EXT/INT = High)
Setting the EXT/INT = high allows the AD7951 to accept an
externally supplied serial data clock on the SDCLK pin. In this
mode, several methods can be used to read the data. The
external serial clock is gated by CS. When CS and RD are both
low, the data can be read after each conversion or during the
following conversion. A clock can be either normally high or
normally low when inactive. For detailed timing diagrams, see
Figure 42 and Figure 43.
While the AD7951 is performing a bit decision, it is important
that voltage transients be avoided on digital input/output pins,
or degradation of the conversion result may occur. This is
particularly important during the last 450 ns of the conversion
phase because the AD7951 provides error correction circuitry
that can correct for an improper bit decision made during the
first part of the conversion phase. For this reason, it is recom-
mended that any external clock provided is a discontinuous
clock that transitions only when BUSY is low or, more importantly,
that it does not transition during the last 450 ns of BUSY high.
External Discontinuous Clock Data Read After
Conversion
Though the maximum throughput cannot be achieved using
this mode, it is the most recommended of the serial slave modes.
Figure 42 shows the detailed timing diagrams for this method.
After a conversion is complete, indicated by BUSY returning low,
the conversion result can be read while both CS and RD are low.
Data is shifted out MSB first with 14 clock pulses and, depending
on the SDCLK frequency, can be valid on the falling and rising
edges of the clock.
One advantage of this method is that conversion performance is
not degraded because there are no voltage transients on the digital
interface during the conversion process. Another advantage is
the ability to read the data at any speed up to 40 MHz, which
accommodates both the slow digital host interface and the fastest
serial reading.
Daisy-Chain Feature
Also in the read after convert mode, the AD7951 provides a
daisy-chain feature for cascading multiple converters together
using the serial data input pin, SDIN. This feature is useful for
reducing component count and wiring connections when
desired, for instance, in isolated multiconverter applications.
See Figure 42 for the timing details.
An example of the concatenation of two devices is shown in
Figure 41.
Simultaneous sampling is possible by using a common CNVST
signal. Note that the SDIN input is latched on the opposite edge
of SDCLK used to shift out the data on SDOUT (SDCLK falling
edge when INVSCLK = low). Therefore, the MSB of the
upstream converter follows the LSB of the downstream
converter on the next SDCLK cycle. In this mode, the 40 MHz
SDCLK rate cannot be used since the SDIN to SDCLK setup
time, t33, is less than the minimum time specified. (SDCLK to
SDOUT delay, t32, is the same for all converters when
simultaneously sampled). For proper operation, the SDCLK edge
for latching SDIN (or ½ period of SDCLK) needs to be:
3332
SDCLK
ttt +=
2/1
Or the max SDCLK frequency needs to be:
)(2
1
3332
SDCLK tt
f+
=
If not using the daisy-chain feature, the SDIN input should
always be tied either high or low.
SCLK
SDOUTRDC/SDIN
AD7951
#1
(DOWNSTREAM)
AD7951
#2
(UPSTREAM)
BUSY
OUT
BUSYBUSY
DATA
OUT
SCLK
RDC/SDIN SDOUT
SCLK IN
CNVST IN
CNVST
CS
CNVST
CS
CS IN
06396-041
Figure 41. Two AD7951 Devices in a Daisy-Chain Configuration
External Clock Data Read During Previous Conversion
Figure 43 shows the detailed timing diagrams for this method.
During a conversion, while both CS and RD are low, the result
of the previous conversion can be read. The data is shifted out,
MSB first, with 14 clock pulses, and depending on the SDCLK
frequency, can be valid on both the falling and rising edges of
the clock. The 14 bits have to be read before the current
conversion is complete; otherwise, RDERROR is pulsed high
and can be used to interrupt the host interface to prevent
incomplete data reading.
To reduce performance degradation due to digital activity, a fast
discontinuous clock of at least 40 MHz is recommended to ensure
that all the bits are read during the first half of the SAR
conversion phase.
The daisy-chain feature should not be used in this mode since
digital activity occurs during the second half of the SAR
conversion phase, likely resulting in performance degradation.
Rev. B | Page 27 of 32
AD7951 Data Sheet
Rev. B | Page 28 of 32
External Clock Data Read After/During Conversion
It is also possible to begin to read data after conversion and
continue to read the last bits after a new conversion has been
initiated. This method allows the full throughput and the use of a
slower SDCLK frequency. Again, it is recommended to use a
discontinuous SDCLK whenever possible to minimize potential
incorrect bit decisions. For the different modes, the use of a slower
SDCLK such as 20 MHz in warp mode, 15 MHz in normal mode
and 13 MHz in impulse mode can be used.
SDIN
SDOUT D0
1 2 3 13 14
BUSY
EXT/INT = 1 INVSCLK = 0
CS
SDCLK 4
D2 D1
15 16
SER/ PAR = 1 RD = 0
12
D13 D12 D11 X13 X12
17
X0
X2 X1
X13 X12 X11 Y13 Y12
t
31
t
31
X*
t
32
t
16
t
33
t
34
t
37
t
35
t
36
*A DISCO NTI NUOUS SDCLK IS RECOM MENDED.
0
6396-042
Figure 42. Slave Serial Data Timing for Reading (Read After Convert)
SDOUT D0
123
BUSY
EXT/INT = 1 INVSCLK = 0
CS
SDCLK 13
D1
SER/PAR = 1 RD = 0
14
D13 D12
t
31
t
31
t
32
t
16
t
37
t
35
t
36
CNVST
X*
X* X* X* X* X*
t
27
*A DISCO NT INUO US SDCLK I S RECOM MENDED.
06396-043
DATA = SDIN
Figure 43. Slave Serial Data Timing for Reading (Read Previous Conversion During Convert)
Data Sheet AD7951
Rev. B | Page 29 of 32
HARDWARE CONFIGURATION
The AD7951 can be configured at any time with the dedicated
hardware pins WARP, IMPULSE, BIPOLAR, TEN, OB/2C, and
PD for parallel mode (SER/PAR = low) or serial hardware mode
(SER/ PAR = high, HW/SW = high). Programming the AD7951
for mode selection and input range configuration can be done
before or during conversion. Like the RESET input, the ADC
requires at least one acquisition time to settle as indicated in
Figure 44. See Table 6 for pin descriptions. Note that these
inputs are high impedance when using the software
configuration mode.
SOFTWARE CONFIGURATION
The pins multiplexed on D[13:10] used for software configura-
tion are: HW/SW, SCIN, SCCLK, and SCCS. The AD7951 is
programmed using the dedicated write-only serial configurable
port (SCP) for conversion mode, input range selection, output
coding, and power-down using the serial configuration register.
See Table 9 for details of each bit in the configuration register.
The SCP can only be used in serial software mode selected with
SER/PAR = high and HW/SW = low since the port is multiplexed
on the parallel interface.
The SCP is accessed by asserting the port’s chip select, SCCS,
and then writing SCIN synchronized with SCCLK, which (like
SDCLK) is edge sensitive depending on the state of INVSCLK.
See Figure 45 for timing details. SCIN is clocked into the con-
figuration register MSB first. The configuration register is an
internal shift register that begins with Bit 8, the start bit. The 9th
SPPCLK edge updates the register and allows the new settings to be
used. As indicated in the timing diagram, at least one acquisition
time is required from the 9th SCCLK edge. Bits [1:0] are reserved
bits and are not written to while the SCP is being updated.
The SCP can be written to at any time, up to 40 MHz, and it is
recommended to write to while the AD7951 is not busy
converting, as detailed in Figure 45. In this mode, the full
1 MSPS is not attainable because the time required for SCP access
is (t31 + 9 × 1/SCCLK + t8) minimum. If the full throughput is
required, the SCP can be written to during conversion, however,
it is not recommended to write to the SCP during the last 450 ns
of conversion (BUSY = high), or performance degradation can
result. In addition, the SCP can be accessed in both serial master
and serial slave read during and read after convert modes.
Note that at power up, the configuration register is undefined.
The RESET input clears the configuration register (sets all bits
to 0), thus placing the configuration to 0 V to 5 V input, normal
mode, and twos complemented output.
Table 9. Configuration Register Description
Bit Name Description
8 START START bit. With the SCP enabled (SCCS = low),
when START is high, the first rising edge of SCCLK
(INVSCLK = low) begins to load the register with
the new configuration.
7 BIPOLAR Input Range Select. Used in conjunction with
Bit 6, TEN, per the following:
Input Range BIPOLAR TEN
0 V to 5 V Low Low
0 V to 10 V Low 1
±5 V High Low
±10 V High High
6 TEN Input Range Select. See Bit 7, BIPOLAR.
5 PD Power Down.
PD = low, normal operation.
PD = high power down the ADC. The SCP is
accessible while in power down. To power up the
ADC, write PD = low on the next configuration
setting.
4 IMPULSE Mode Select. Used in conjunction with Bit 3,
WARP, per the following:
Mode WARP IMPULSE
Normal Low Low
Impulse Low High
Warp High Low
Normal High High
3 WARP Mode Select. See Bit 4, IMPULSE.
2 OB/2C Output Coding
OB/2C = low, use twos complement output.
OB/2C = high, use straight binary output.
1 RSV Reserved.
0 RSV Reserved.
WARP,
IMPULSE
BUSY
HW/ S W = 0
CNVST
BIPOLAR,
TEN
t
8
SER/PAR = 0, 1PD = 0
t
8
0
6396-044
Figure 44. Hardware Configuration Timing
AD7951 Data Sheet
Rev. B | Page 30 of 32
SCIN
S
CCL
K
WARPTEN
123 67
BUSY
HW/ SW = 0 INVSCLK = 0
CNVST
SCCS
t
8
t
36
t
35
t
37
4
PD
5
BIPOLAR
IMPULSE
OB/2C X
89
SER/ PAR = 1
BIP = 0 OR 1
TEN = 0 OR 1
IMPULSE = 0 OR 1
WARP = 0 OR 1 PD = 0
t
33
t
34
t
31
X
t
31
06396-045
START
Figure 45. Serial Configuration Port Timing
MICROPROCESSOR INTERFACING
The AD7951 is ideally suited for traditional dc measurement
applications supporting a microprocessor, and ac signal
processing applications interfacing to a digital signal processor.
The AD7951 is designed to interface with a parallel 8-bit or
14-bit wide interface, or with a general-purpose serial port or
I/O ports on a microcontroller. A variety of external buffers can
be used with the AD7951 to prevent digital noise from coupling
into the ADC.
SPI Interface
The AD7951 is compatible with SPI and QSPI digital hosts and
DSPs such as Blackfin® ADSP-BF53x and ADSP-218x/ADSP-219x.
Figure 46 shows an interface diagram between the AD7951 and
the SPI-equipped ADSP-219x. To accommodate the slower
speed of the DSP, the AD7951 acts as a slave device, and data must
be read after conversion. This mode also allows the daisy-chain
feature. The convert command could be initiated in response to
an internal timer interrupt.
The reading process can be initiated in response to the end-of-
conversion signal (BUSY going low) using an interrupt line of
the DSP. The serial peripheral interface (SPI) on the ADSP-219x
is configured for master mode (MSTR) = 1, clock polarity bit
(CPOL) = 0, clock phase bit (CPHA) = 1, and SPI interrupt enable
(TIMOD) = 0 by writing to the SPI control register (SPICLTx).
It should be noted that to meet all timing requirements, the SPI
clock should be limited to 17 Mbps, allowing it to read an ADC
result in less than 1 μs. When a higher sampling rate is desired,
use one of the parallel interface modes.
BUSY
CS
SDOUT
SCLK
CNVST
AD7951*
PFx
SPIxSEL (PFx)
MISOx
SCKx
PFx OR TFSx
ADSP-219x*
*ADDITIONAL PINS O M IT TED F OR CL ARITY.
DVDD
SER/PAR
EXT/INT
RD
INVSCLK
06396-046
Figure 46. Interfacing the AD7951 to SPI Interface
Data Sheet AD7951
APPLICATION INFORMATION
LAYOUT GUIDELINES
While the AD7951 has very good immunity to noise on the
power supplies, exercise care with the grounding layout. To
facilitate the use of ground planes that can be easily separated,
design the printed circuit board that houses the AD7951 so that
the analog and digital sections are separated and confined to
certain areas of the board. Digital and analog ground planes
should be joined in only one place, preferably underneath the
AD7951, or as close as possible to the AD7951. If the AD7951 is
in a system where multiple devices require analog-to-digital
ground connections, the connections should still be made at one
point only, a star ground point, established as close as possible to
the AD7951.
To prevent coupling noise onto the die, avoid radiating noise,
and to reduce feedthrough:
• Do not run digital lines under the device.
• Do run the analog ground plane under the AD7951.
• Shield fast switching signals, like CNVST or clocks, with
digital ground to avoid radiating noise to other sections of
the board, and never run them near analog signal paths.
• Avoid crossover of digital and analog signals.
• Run traces on different but close layers of the board, at right
angles to each other, to reduce the effect of feedthrough through
the board.
The power supply lines to the AD7951 should use as large a trace
as possible to provide low impedance paths and reduce the effect of
glitches on the power supply lines. Good decoupling is also
important to lower the impedance of the supplies presented to
the AD7951, and to reduce the magnitude of the supply spikes.
Decoupled ceramic capacitors, typically 100 nF, should be placed
on each of the power supplies pins, AVDD, DVDD, and OVDD,
VCC, and VEE. The capacitors should be placed close to, and
ideally right up against, these pins and their corresponding ground
pins. Additionally, low ESR 10 µF capacitors should be located
in the vicinity of the ADC to further reduce low frequency ripple.
The DVDD supply of the AD7951 can either be a separate supply
or come from the analog supply, AVDD, or from the digital
interface supply, OVDD. When the system digital supply is noisy,
or fast switching digital signals are present, and no separate supply
is available, it is recommended to connect the DVDD digital supply
to the analog supply AVDD through an RC filter, and to connect
the system supply to the interface digital supply OVDD and the
remaining digital circuitry. See Figure 27 for an example of this
configuration. When DVDD is powered from the system supply,
it is useful to insert a bead to further reduce high frequency spikes.
The AD7951 has four different ground pins: REFGND, AGND,
DGND, and OGND.
• REFGND senses the reference voltage and, because it carries
pulsed currents, should be a low impedance return to the
reference.
• AGND is the ground to which most internal ADC analog
signals are referenced; it must be connected with the least
resistance to the analog ground plane.
• DGND must be tied to the analog or digital ground plane
depending on the configuration.
• OGND is connected to the digital system ground.
The layout of the decoupling of the reference voltage is important.
To minimize parasitic inductances, place the decoupling capacitor
close to the ADC and connect it with short, thick traces.
Rev. B | Page 31 of 32
AD7951 Data Sheet
Rev. B | Page 32 of 32
OUTLINE DIMENSIONS
COMP LI ANT TO JEDE C S TANDARDS MS-026-BBC
TOP VIEW
(PINS DOWN)
1
12 13 25
24
36
37
48
0.27
0.22
0.17
0.50
BSC
LEAD P ITCH
1.60
MAX
0.75
0.60
0.45
VIEW A
PIN 1
0.20
0.09
1.45
1.40
1.35
0.08
COPLANARITY
VIEW A
RO TAT E D 9 0° CCW
SEATING
PLANE
7°
3.5°
0°
0.15
0.05
9.20
9.00 S Q
8.80
7.20
7.00 SQ
6.80
051706-A
Figure 47. 48-Lead Low Profile Quad Flat Package [LQFP]
(ST-48)
Dimensions shown in millimeters
COM PLI ANT TO JEDE C S T ANDARDS MO-22 0-V KKD- 2
1
48
12
13
37
36
24
25
5.25
5.10 SQ
4.95
0.50
0.40
0.30
0.30
0.23
0.18
0.80 MAX
0.65 TY P
5.50 REF
COPLANARITY
0.08
0.20 REF
1.00
0.85
0.80 0.05 M AX
0.02 NOM
SEATING
PLANE
12° MAX
TOP VIEW
0.60 MAX
0.60 MAX
PIN 1
INDICATOR 0.50
REF
PIN 1
INDICATOR
0.25 M IN
7.10
7.00 S Q
6.90
6.85
6.75 SQ
6.65
06-05-2012-A
FOR PROPE R CONNECTI ON OF
THE EXPOSED PAD, REFER TO
THE P IN CONF IG URATI ON AND
FUNCTI ON DESCRIP TI ONS
SECTION OF THIS DATA SHEET.
EXPOSED
PAD
Figure 48. 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
7 mm × 7 mm Body, Very Thin Quad
(CP-48-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
AD7951BCPZ −40°C to +85°C 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-48-1
AD7951BCPZRL −40°C to +85°C 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-48-1
AD7951BSTZ −40°C to +85°C 48-Lead Low Profile Quad Flat Package [LQFP] ST-48
AD7951BSTZRL −40°C to +85°C 48-Lead Low Profile Quad Flat Package [LQFP] ST-48
1 Z = RoHS Compliant Part.
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registered trademarks are the property of their respective owners.
D06396-0-5/15(B)
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