100354FC - National Semiconductor

TL/F/10610

100354 Low Power 8-Bit Register with Cut-Off Drivers

July 1992

100354

Low Power 8-Bit Register with Cut-Off Drivers

General Description

The 100354 contains eight D-Type edge triggered, master/

slave flip-flops with individual inputs (Dn), true outputs (Qn),

a clock input (CP), an output enable pin (OEN), and a com-

mon clock enable pin (CEN). Data enters the master when

CP is LOW and transfers to the slave when CP goes HIGH.

When the CEN input goes HIGH it overrides all other inputs,

disables the clock, and the Q outputs maintain the last

state.

A Q output follows its D input when the OEN pin is LOW. A

HIGH on OEN holds the outputs in a cut-off state. The cut-

off state is designed to be more negative than a normal ECL

LOW level. This allows the output emitter-followers to turn

off when the termination supply is b2.0V, presenting a high

impedance to the data bus. This high impedance reduces

termination power and prevents loss of low state noise mar-

gin when several loads share the bus.

The 100354 outputs are designed to drive a doubly termi-

nated 50Xtransmission line (25Xload impedance). All in-

puts have 50 kXpull-down resistors.

Features

YCut-off drivers

YDrives 25Xload

YLow power operation

Y2000V ESD protection

YVoltage compensated operating range eb

4.2V to

b5.7V

YAvailable to industrial grade temperature range

Logic Symbol

TL/F/10610–1

Pin Names Description

D0–D7Data Inputs

CEN Clock Enable Input

CP Clock Input

(Active Rising Edge)

OEN Output Enable Input

Q0–Q7Data Outputs

Connection Diagrams

24-Pin DIP

TL/F/10610–2

24-Pin Quad Cerpak

TL/F/10610–3

28-Pin PCC

TL/F/10610–4

C1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.

Absolute Maximum Ratings

Above which the useful life may be impaired. (Note 1)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales

Office/Distributors for availability and specifications.

Storage Temperature (TSTG)b65§Ctoa

150§C

Maximum Junction Temperature (TJ)

Ceramic a175§C

Plastic a150§C

VEE Pin Potential to Ground Pin b7.0V to a0.5V

Input Voltage (DC) VEE to a0.5V

Output Current (DC Output HIGH) b100 mA

ESD (Note 2) t2000V

Note 1: Absolute maximum ratings are those values beyond which the de-

vice may be damaged or have its useful life impaired. Functional operation

under these conditions is not implied.

Note 2: ESD testing conforms to MIL-STD-883, Method 3015.

Recommended Operating

Conditions

Case Temperature (TC)

Commercial 0§Ctoa

85§C

Industrial b40§Ctoa

85§C

Military b55§Ctoa

125§C

Supply Voltage (VEE)b5.7V to b4.2V

Commercial Version

DC Electrical Characteristics

VEE eb

4.2V to b5.7V, VCC eVCCA eGND, TCe0§Ctoa

85§C (Note 3)

Symbol Parameter Min Typ Max Units Conditions

VOH Output HIGH Voltage b1025 b955 b870 mV VIN eVIH (Max) Loading with

VOL Output LOW Voltage b1830 b1705 b1620 or VIL (Min) 25Xto b2.0V

VOHC Output HIGH Voltage b1035 mV VIN eVIH (Min) Loading with

VOLC Output LOW Voltage b1610 or VIL (Max) 25Xto b2.0V

VOLZ Cutoff LOW Voltage b1950 mV VIN eVIH (Min) OEN eHIGH

or VIL (Max)

VIH Input HIGH Voltage b1165 b870 mV Guaranteed HIGH Signal

for All Inputs

VIL Input LOW Voltage b1830 b1475 mV Guaranteed LOW Signal

for All Inputs

IIL Input LOW Current 0.50 mAV

IN eVIL (Min)

IIH Input HIGH Current 240 mAV

IN eVIH (Max)

IEE Power Supply Current Inputs Open

b202 b105 mA VEE eb

4.2V to b4.8V

b209 b105 VEE eb

4.2V to b5.7V

Note 3: The specified limits represent the ‘‘worst case’’ value for the parameter. Since these values normally occur at the temperature extremes, additional noise

immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to

guarantee operation under ‘‘worst case’’ conditions.

Commercial Version (Continued)

DIP AC Electrical Characteristics

VEE eb

4.2V to b5.7V, VCC eVCCA eGND

Symbol Parameter TCe0§CT

25§CT

85§CUnits Conditions

Min Max Min Max Min Max

fMax Toggle Frequency 250 250 250 MHz

Figures 1

and

tPLH Propagation Delay 1.40 3.00 1.40 3.00 1.50 3.10 ns

Figures 1

and

tPHL CP to Output (Note 1)

tPZH Propagation Delay 1.60 4.20 1.60 4.20 1.60 4.20 ns

Figures 3

and

tPHZ OEN to Output 1.00 2.70 1.00 2.70 1.00 2.70 (Note 1)

tTLH Transition Time 0.45 2.00 0.45 2.00 0.45 2.00 ns

Figures 1

and

tTHL 20% to 80%, 80% to 20%

tSSetup Time

Dn1.10 1.10 1.10

CEN (Disable Time) 0.40 0.40 0.40 ns

Figures 2

and

CEN (Release Time) 1.10 1.10 1.10

tHHold Time

Dn0.10 0.10 0.10 ns

Figures 1

and

tpw(H) Pulse Width High

CP 2.00 2.00 2.00 ns

Figures 1

and

Note 1: The propagation delay specified is for single output switching. Delays may vary up to 300 ps with multiple outputs switching.

PCC and Cerpak AC Electrical Characteristics

VEE eb

4.2V to b5.7V, VCC eVCCA eGND

Symbol Parameter TCe0§CT

25§CT

85§CUnits Conditions

Min Max Min Max Min Max

fMax Toggle Frequency 250 250 250 MHz

Figures 1

and

tPLH Propagation Delay 1.40 2.80 1.40 2.80 1.50 2.90 ns

Figures 1

and

tPHL CP to Output (Note 2)

tPZH Propagation Delay 1.60 4.00 1.60 4.00 1.60 4.00 ns

Figures 3

and

tPHZ OEN to Output 1.00 2.50 1.00 2.50 1.00 2.50 (Note 2)

tTLH Transition Time 0.45 1.90 0.45 1.90 0.45 1.90 ns

Figures 1

and

tTHL 20% to 80%, 80% to 20%

tSSetup Time

Dn1.00 1.00 1.00

CEN (Disable Time) 0.30 0.30 0.30 ns

Figures 2

and

CEN (Release Time) 1.00 1.00 1.00

tHHold Time

Dn0.00 0.00 0.00 ns

Figures 1

and

tpw(H) Pulse Width High

CP 2.00 2.00 2.00 ns

Figures 1

and

tOSHL Maximum Skew Common Edge PCC Only

Output-to-Output Variation ps (Note 1)

Clock to Output Path 280 280 280

tOSLH Maximum Skew Common Edge PCC Only

Output-to-Output Variation ps (Note 1)

Clock to Output Path 340 340 340

tOST Maximum Skew Opposite Edge PCC Only

Output-to-Output Variation ps (Note 1)

Clock to Output Path 340 340 340

tPS Maximum Skew PCC Only

Pin (Signal) Transition Variation ps (Note 1)

Clock to Output Path 250 250 250

Note 1: Output-to-Output Skew is defined as the absolute value of the difference between the actual propagation delay for any outputs within the same packaged

device. The specifications apply to any outputs switching in the same direction either HIGH to LOW (tOSHL), or LOW to HIGH (tOSLH), or in oppostie directions both

HL and LH (tOST). Parameters tOST and tPS guaranteed by design.

Note 2: The propagation delay specified is for single output switching. Delays may vary up to 300 ps with multiple outputs switching.

Industrial Version

PCC DC Electrical Characteristics

VEE eb

4.2V to b5.7V, VCC eVCCA eGND, TCeb

40§Ctoa

85§C (Note 1)

Symbol Parameter TCeb

40§CT

to a85§CUnits Conditions

Min Max Min Max

VOH Output HIGH Voltage b1085 b870 b1025 b870 mV VIN eVIH (Max) Loading with

VOL Output LOW Voltage b1830 b1575 b1830 b1620 or VIL (Min) 50Xto b2.0V

VOHC Output HIGH Voltage b1095 b1035 mV VIN eVIH (Min) Loading with

VOLC Output LOW Voltage b1565 b1610 or VIL (Max) 50Xto b2.0V

VOLZ Cutoff LOW Voltage b1900 b1950 mV VIN eVIH (Min) OEN eHIGH

or VIL (Max)

VIH Input HIGH Voltage b1170 b870 b1165 b870 mV Guaranteed HIGH Signal

for All Inputs

VIL Input LOW Voltage b1830 b1480 b1830 b1475 mV Guaranteed LOW Signal

for All Inputs

IIL Input LOW Current 0.50 0.50 mAV

IN eVIL (Min)

IIH Input HIGH Current 240 240 mAV

IN eVIH (Max)

IEE Power Supply Current Inputs Open

b202 b105 b202 b105 mA VEE eb

4.2V to b4.8V

b209 b105 b209 b105 VEE eb

4.2V to b5.7V

Note 1: The specified limits represent the ‘‘worst case’’ value for the parameter. Since these values normally occur at the temperature extremes, additional noise

immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to

guarantee operation under ‘‘worst case’’ conditions.

PCC AC Electrical Characteristics

VEE eb

4.2V to b5.7V, VCC eVCCA eGND

Symbol Parameter TCeb

40§CT

25§CT

85§CUnits Conditions

Min Max Min Max Min Max

fMax Toggle Frequency 250 250 250 MHz

Figures 1

and

tPLH Propagation Delay 1.40 2.80 1.40 2.80 1.50 2.90 ns

Figures 1

and

tPHL CP to Output (Note 2)

tPZH Propagation Delay 1.50 4.10 1.60 4.00 1.60 4.00 ns

Figures 3

and

tPHZ OEN to Output 1.00 2.50 1.00 2.50 1.00 2.50 (Note 2)

tTLH Transition Time 0.45 1.90 0.45 1.90 0.45 1.90 ns

Figures 1

and

tTHL 20% to 80%, 80% to 20%

tSSetup Time

Dn1.00 1.00 1.00

CEN (Disable Time) 0.30 0.30 0.30 ns

Figures 2

and

CEN (Release Time) 1.00 1.00 1.00

tHHold Time

Dn0.00 0.00 0.00 ns

Figures 1

and

tpw(H) Pulse Width High

CP 2.00 2.00 2.00 ns

Figures 1

and

Note 2: The propagation delay specified is for single output switching. Delays may vary up to 300 ps with multiple outputs switching.

Military VersionÐPreliminary

DC Electrical Characteristics

VEE eb

4.2V to b5.7V, VCC eVCCA eGND, TCeb

55§Ctoa

125§C

Symbol Parameter Min Max Units TCConditions Notes

VOH Output HIGH Voltage b1025 b870 mV 0§Ctoa

125§C

b1085 b870 mV b55§CV

IN eVIH (Max) Loading with 1, 2, 3

VOL Output LOW Voltage b1830 b1620 mV 0§Ctoa

125§Cor VIL (Min) 25Xto b2.0V

b1830 b1555 mV b55§C

VOHC Output HIGH Voltage b1035 mV 0§Ctoa

125§C

b1085 mV b55§CV

IN eVIH (Min) Loading with 1, 2, 3

VOLC Output LOW Voltage b1610 mV 0§Ctoa

125§Cor VIL (Max) 25Xto b2.0V

b1555 mV b55§C

VOLZ Cutoff LOW Voltage b1950 mV 0§Ctoa

125§CV

IN eVIH (Min) OEN eHIGH 1, 2, 3

b1850 b55§Cor VIL (Max)

VIH Input HIGH Voltage b1165 b870 mV b55§Ctoa

125§CGuaranteed HIGH Signal 1, 2, 3, 4

for All Inputs

VIL Input LOW Voltage b1830 b1475 mV b55§Ctoa

125§CGuaranteed LOW Signal 1, 2, 3, 4

for All Inputs

IIL Input LOW Current 0.50 mAb55§Ctoa

125§VEE eb

4.2V 1, 2, 3

VIN eVIL (Min)

IIH Input HIGH Current 240 mA0

Ctoa

125§CV

EE eb

5.7V 1, 2, 3

340 mAb55§CVIN eVIH (Max)

IEE Power Supply Current b55§Cto Inputs Open

b215 b85 mA a125§CVEE eb

4.2V to b4.8V 1, 2, 3

b225 b85 VEE eb

4.2V to b5.7V

Note 1: F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals b55§C), then testing

immediately without allowing for the junction temperature to stabilize due to heat dissipation after power-up. This provides ‘‘cold start’’ specs which can be

considered a worst case condition at cold temperatures.

Note 2: Screen tested 100% on each device at b55§C, a25§C, and a125§C, Subgroups 1, 2, 3, 7, and 8.

Note 3: Sample tested (Method 5005, Table I) on each manufactured lot at b55§C, a25§C, and a125§C, Subgroups A1, 2, 3, 7, and 8.

Note 4: Guaranteed by applying specified input condition and testing VOH/VOL.

Military VersionÐPreliminary (Continued)

AC Electrical Characteristics

VEE eb

4.2V to b5.7V, VCC eVCCA eGND

Symbol Parameter TCeb

55§CT

25§CT

125§CUnits Conditions Notes

Min Max Min Max Min Max

fMax Toggle Frequency 200 250 200 MHz

Figures 1

and

tPLH Propagation Delay 0.9 3.70 1.0 3.20 1.20 3.90 ns

Figures 1

and

1, 2, 3, 5

tPHL CP to Output

tPZH Propagation Delay 1.20 5.0 1.60 4.20 1.40 4.30 ns

Figures 3

and

1, 2, 3, 5

tPHZ OEN to Output 0.70 3.0 0.70 2.80 0.70 3.20

tTLH Transition Time 0.40 2.50 0.40 2.40 0.40 2.70 ns

Figures 1

and

tTHL 20% to 80%, 80% to 20%

tSSetup Time

Dn1.30 1.30 1.30

CEN (Disable Time) 0.60 0.60 0.60 ns

Figures 2

and

CEN (Release Time) 1.30 1.30 1.30

tHHold Time

Dn0.30 0.30 0.30 ns

Figures 1

and

tpw(H) Pulse Width HIGH

CP 2.4 2.4 2.4 ns

Figures 1

and

Note 1: F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals b55§C), then testing

immediately after power-up. This provides ‘‘cold start’’ specs which can be considered a worst case condition at cold temperatures.

Note 2: Screen tested 100% on each device at a25§C, temperature only, Subgroup A9.

Note 3: Sample tested (Method 5005, Table I) on each manufactured lot at a25§C, Subgroup A9, and at a125§C and b55§C temperatures, Subgroups A10 and

A11.

Note 4: Not tested at a25§C, a125§C, and b55§C temperature (design characterization data).

Note 5: The propagation delay specified is for single output switching. Delays may vary up to 300 ps with multiple outputs switching.

Test Circuitry

TL/F/10610–5

Notes:

VCC,V

CCA ea

2V, VEE eb

2.5V

L1 and L2 eequal length 50Ximpedance lines

RTe50Xterminator internal to scope

Decoupling 0.1 mF from GND to VCC and VEE

All unused outputs are loaded with 25Xto GND

CLeFixture and stray capacitance s3pF

FIGURE 1. Toggle Frequency Test Circuit

TL/F/10610–6

Notes:

VCC,V

CCA ea

2V, VEE eb

2.5V

L1 and L2 eequal length 50Ximpedance lines

RTe50Xterminator internal to scope

Decoupling 0.1 mF from GND to VCC and VEE

All unused outputs are loaded with 25Xto GND

CLeFixture and stray capacitance s3pF

FIGURE 2. AC Test Circuit

TL/F/10610–7

Notes:

VCC,V

CCA ea

2V, VEE eb

2.5V

L1 and L2 eequal length 50Ximpedance lines

RTe50Xterminator internal to scope

Decoupling 0.1 mF from GND to VCC and VEE

All unused outputs are loaded with 25Xto GND

CLeFixture and stray capacitance s3pF

FIGURE 3. AC Test Circuit

Switching Waveforms

TL/F/10610–8

FIGURE 4. Propagation Delay (Clock) and Transition Times

TL/F/10610–9

FIGURE 5. Setup and Pulse Width Times

TL/F/10610–10

FIGURE 6. Data Setup and Hold Time

Notes:

tsis the minimum time before the transition of the clock that information must be present at the data input.

this the minimum time after the transition of the clock that information must remain unchanged at the data input.

TL/F/10610–11

Note: The output AC measurement point for cut-off propagation delay

testing ethe 50% voltage point between active VOL and VOH.

FIGURE 7. Cutoff Times

Ordering Information

The device number is used to form part of a simplified purchasing code where a package type and temperature range are

defined as follows:

100354 D C QB

Device Type (Basic) Special Variation

QB eMilitary grade device with

Package Code environmental and burn-in

DeCeramic DIP processing.

FeQuad Cerpak

PePlastic DIP Temperature Range

QePlastic Leaded Chip Carrier (PCC) C eCommercial (0§Ctoa

85§C)

IeIndustrial (b40§Ctoa

85§C)

(PCC only)

MeMilitary (b55§Ctoa

125§C)

Physical Dimensions inches (millimeters)

24-Lead Ceramic Dual-In-Line Package (D)

NS Package Number J24E

Physical Dimensions inches (millimeters) (Continued)

24-Lead Plastic Dual-in-Line Package (P)

NS Package Number N24E

28-Lead Plastic Chip Carrier (Q)

NS Package Number V28A

100354 Low Power 8-Bit Register with Cut-Off Drivers

Physical Dimensions inches (millimeters) (Continued) Lit. Ý114922

28-Lead Quad Cerpak (F)

NS Package Number W24B

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failure to perform, when properly used in accordance support device or system, or to affect its safety or

with instructions for use provided in the labeling, can effectiveness.

be reasonably expected to result in a significant injury

to the user.

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