100354 Low Power 8-Bit Register with Cut-Off Drivers General Description The 100354 contains eight D-Type edge triggered, master/ slave flip-flops with individual inputs (Dn), true outputs (Qn), a clock input (CP), an output enable pin (OEN), and a common clock enable pin (CEN). Data enters the master when CP is LOW and transfers to the slave when CP goes HIGH. When the CEN input goes HIGH it overrides all other inputs, disables the clock, and the Q outputs maintain the last state. A Q output follows its D input when the OEN pin is LOW. A HIGH on OEN holds the outputs in a cut-off state. The cutoff state is designed to be more negative than a normal ECL LOW level. This allows the output emitter-followers to turn off when the termination supply is b2.0V, presenting a high impedance to the data bus. This high impedance reduces termination power and prevents loss of low state noise margin when several loads share the bus. The 100354 outputs are designed to drive a doubly terminated 50X transmission line (25X load impedance). All inputs have 50 kX pull-down resistors. Features Y Y Y Y Y Y Cut-off drivers Drives 25X load Low power operation 2000V ESD protection Voltage compensated operating range e b4.2V to b 5.7V Available to industrial grade temperature range Logic Symbol Pin Names D0 -D7 CEN CP OEN Q0 -Q7 Description Data Inputs Clock Enable Input Clock Input (Active Rising Edge) Output Enable Input Data Outputs TL/F/10610 - 1 Connection Diagrams 24-Pin DIP 24-Pin Quad Cerpak TL/F/10610 - 3 28-Pin PCC TL/F/10610 - 4 TL/F/10610-2 C1995 National Semiconductor Corporation TL/F/10610 RRD-B30M105/Printed in U. S. A. 100354 Low Power 8-Bit Register with Cut-Off Drivers July 1992 Absolute Maximum Ratings Recommended Operating Conditions Above which the useful life may be impaired. (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. b 65 C to a 150 C Storage Temperature (TSTG) Maximum Junction Temperature (TJ) Ceramic Plastic VEE Pin Potential to Ground Pin Input Voltage (DC) Output Current (DC Output HIGH) ESD (Note 2) Case Temperature (TC) Commercial Industrial Military 0 C to a 85 C b 40 C to a 85 C b 55 C to a 125 C Supply Voltage (VEE) a 175 C a 150 C b 5.7V to b 4.2V b 7.0V to a 0.5V VEE to a 0.5V b 100 mA t 2000V Note 1: Absolute maximum ratings are those values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: ESD testing conforms to MIL-STD-883, Method 3015. Commercial Version DC Electrical Characteristics VEE e b4.2V to b5.7V, VCC e VCCA e GND, TC e 0 C to a 85 C (Note 3) Symbol Parameter Min Typ Max Output HIGH Voltage b 1025 b 955 b 870 VOL Output LOW Voltage b 1830 b 1705 b 1620 VOHC Output HIGH Voltage b 1035 VOLC Output LOW Voltage b 1610 VOLZ Cutoff LOW Voltage b 1950 mV VIH Input HIGH Voltage b 1165 b 870 mV Guaranteed HIGH Signal for All Inputs VIL Input LOW Voltage b 1830 b 1475 mV Guaranteed LOW Signal for All Inputs IIL Input LOW Current IIH Input HIGH Current IEE Power Supply Current VOH 0.50 b 202 b 209 Units Conditions mV VIN e VIH (Max) or VIL (Min) Loading with 25X to b2.0V mV VIN e VIH (Min) or VIL (Max) Loading with 25X to b2.0V VIN e VIH (Min) or VIL (Max) OEN e HIGH mA VIN e VIL (Min) 240 mA VIN e VIH (Max) b 105 b 105 mA Inputs Open VEE e b4.2V to b4.8V VEE e b4.2V to b5.7V Note 3: The specified limits represent the ``worst case'' value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to guarantee operation under ``worst case'' conditions. 2 Commercial Version (Continued) DIP AC Electrical Characteristics VEE e b4.2V to b5.7V, VCC e VCCA e GND Symbol TC e 0 C Parameter Min Max TC e a 25 C TC e a 85 C Min Min Max Conditions MHz Figures 1 and 4 fMax Toggle Frequency 250 tPLH tPHL Propagation Delay CP to Output 1.40 3.00 1.40 3.00 1.50 3.10 ns Figures 1 and 4 (Note 1) tPZH tPHZ Propagation Delay OEN to Output 1.60 1.00 4.20 2.70 1.60 1.00 4.20 2.70 1.60 1.00 4.20 2.70 ns Figures 3 and 7 (Note 1) tTLH tTHL Transition Time 20% to 80%, 80% to 20% 0.45 2.00 0.45 2.00 0.45 2.00 ns Figures 1 and 4 tS Setup Time Dn CEN (Disable Time) CEN (Release Time) tH tpw(H) 250 Units Max 250 1.10 0.40 1.10 1.10 0.40 1.10 1.10 0.40 1.10 ns Figures 2 and 5 Dn 0.10 0.10 0.10 ns Figures 1 and 6 CP 2.00 2.00 2.00 ns Figures 1 and 4 Hold Time Pulse Width High Note 1: The propagation delay specified is for single output switching. Delays may vary up to 300 ps with multiple outputs switching. 3 PCC and Cerpak AC Electrical Characteristics VEE e b4.2V to b5.7V, VCC e VCCA e GND Symbol TC e 0 C Parameter Min Max TC e a 25 C TC e a 85 C Min Min Max Conditions MHz Figures 1 and 4 Figures 1 and 4 (Note 2) fMax Toggle Frequency 250 tPLH tPHL Propagation Delay CP to Output 1.40 2.80 1.40 2.80 1.50 2.90 ns tPZH tPHZ Propagation Delay OEN to Output 1.60 1.00 4.00 2.50 1.60 1.00 4.00 2.50 1.60 1.00 4.00 2.50 ns Figures 3 and 7 (Note 2) tTLH tTHL Transition Time 20% to 80%, 80% to 20% 0.45 1.90 0.45 1.90 0.45 1.90 ns Figures 1 and 4 tS Setup Time Dn CEN (Disable Time) CEN (Release Time) tH Hold Time tpw(H) Pulse Width High tOSHL tOSLH tOST tPS 250 Units Max 250 1.00 0.30 1.00 1.00 0.30 1.00 1.00 0.30 1.00 ns Figures 2 and 5 Dn 0.00 0.00 0.00 ns Figures 1 and 6 CP 2.00 2.00 2.00 ns Figures 1 and 4 ps PCC Only (Note 1) ps PCC Only (Note 1) ps PCC Only (Note 1) ps PCC Only (Note 1) Maximum Skew Common Edge Output-to-Output Variation Clock to Output Path Maximum Skew Common Edge Output-to-Output Variation Clock to Output Path Maximum Skew Opposite Edge Output-to-Output Variation Clock to Output Path Maximum Skew Pin (Signal) Transition Variation Clock to Output Path 280 280 340 340 340 340 250 250 280 340 340 250 Note 1: Output-to-Output Skew is defined as the absolute value of the difference between the actual propagation delay for any outputs within the same packaged device. The specifications apply to any outputs switching in the same direction either HIGH to LOW (tOSHL), or LOW to HIGH (tOSLH), or in oppostie directions both HL and LH (tOST). Parameters tOST and tPS guaranteed by design. Note 2: The propagation delay specified is for single output switching. Delays may vary up to 300 ps with multiple outputs switching. 4 Industrial Version PCC DC Electrical Characteristics VEE e b4.2V to b5.7V, VCC e VCCA e GND, TC e b40 C to a 85 C (Note 1) Symbol TC e b40 C Parameter Min TC e 0 to a 85 C Max Min Units Conditions Max VOH Output HIGH Voltage b 1085 b 870 b 1025 b 870 VOL Output LOW Voltage b 1830 b 1575 b 1830 b 1620 VOHC Output HIGH Voltage b 1095 VOLC Output LOW Voltage VOLZ Cutoff LOW Voltage VIH Input HIGH Voltage VIL Input LOW Voltage IIL Input LOW Current IIH Input HIGH Current IEE Power Supply Current b 1035 mV VIN e VIH (Max) or VIL (Min) Loading with 50X to b2.0V mV VIN e VIH (Min) or VIL (Max) Loading with 50X to b2.0V OEN e HIGH b 1565 b 1610 b 1900 b 1950 mV VIN e VIH (Min) or VIL (Max) b 1170 b 870 b 1165 b 870 mV Guaranteed HIGH Signal for All Inputs b 1830 b 1480 b 1830 b 1475 mV Guaranteed LOW Signal for All Inputs mA VIN e VIL (Min) 240 mA VIN e VIH (Max) b 105 b 105 mA 0.50 0.50 240 b 202 b 209 b 105 b 105 b 202 b 209 Inputs Open VEE e b4.2V to b4.8V VEE e b4.2V to b5.7V Note 1: The specified limits represent the ``worst case'' value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to guarantee operation under ``worst case'' conditions. PCC AC Electrical Characteristics VEE e b4.2V to b5.7V, VCC e VCCA e GND Symbol Parameter TC e b40 C TC e a 25 C TC e a 85 C Min Min Min Max Max Conditions MHz Figures 1 and 4 fMax Toggle Frequency 250 tPLH tPHL Propagation Delay CP to Output 1.40 2.80 1.40 2.80 1.50 2.90 ns Figures 1 and 4 (Note 2) tPZH tPHZ Propagation Delay OEN to Output 1.50 1.00 4.10 2.50 1.60 1.00 4.00 2.50 1.60 1.00 4.00 2.50 ns Figures 3 and 7 (Note 2) tTLH tTHL Transition Time 20% to 80%, 80% to 20% 0.45 1.90 0.45 1.90 0.45 1.90 ns Figures 1 and 4 tS Setup Time Dn CEN (Disable Time) CEN (Release Time) tH Hold Time tpw(H) Pulse Width High 250 Units Max 250 1.00 0.30 1.00 1.00 0.30 1.00 1.00 0.30 1.00 ns Figures 2 and 5 Dn 0.00 0.00 0.00 ns Figures 1 and 6 CP 2.00 2.00 2.00 ns Figures 1 and 4 Note 2: The propagation delay specified is for single output switching. Delays may vary up to 300 ps with multiple outputs switching. 5 Military VersionPreliminary DC Electrical Characteristics VEE e b4.2V to b5.7V, VCC e VCCA e GND, TC e b55 C to a 125 C Parameter Min Max Units TC VOH Symbol Output HIGH Voltage b 1025 b 870 mV 0 C to a 125 C VOL Output LOW Voltage VOHC VOLC VOLZ Output HIGH Voltage b 1085 b 870 mV b 55 C b 1830 b 1620 mV 0 C to a 125 C b 1830 b 1555 mV b 55 C b 1035 mV 0 C to a 125 C b 1085 mV b 55 C b 1610 mV 0 C to a 125 C b 1555 mV b 55 C Output LOW Voltage Cutoff LOW Voltage b 1950 0 C to a 125 C mV b 1850 VIH Input HIGH Voltage VIL Input LOW Voltage IIL Input LOW Current IIH Input HIGH Current IEE b 55 C Conditions Notes VIN e VIH (Max) or VIL (Min) Loading with 25X to b2.0V 1, 2, 3 VIN e VIH (Min) or VIL (Max) Loading with 25X to b2.0V 1, 2, 3 VIN e VIH (Min) or VIL (Max) OEN e HIGH 1, 2, 3 b 1165 b 870 mV b 55 C to a 125 C Guaranteed HIGH Signal for All Inputs 1, 2, 3, 4 b 1830 b 1475 mV b 55 C to a 125 C Guaranteed LOW Signal for All Inputs 1, 2, 3, 4 mA b 55 C to a 125 VEE e b4.2V VIN e VIL (Min) 1, 2, 3 VEE e b5.7V VIN e VIH (Max) 1, 2, 3 Inputs Open VEE e b4.2V to b4.8V VEE e b4.2V to b5.7V 1, 2, 3 0.50 240 mA 0 C to a 125 C 340 mA b 55 C b 85 b 85 mA b 55 C to a 125 C Power Supply Current b 215 b 225 Note 1: F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals b 55 C), then testing immediately without allowing for the junction temperature to stabilize due to heat dissipation after power-up. This provides ``cold start'' specs which can be considered a worst case condition at cold temperatures. Note 2: Screen tested 100% on each device at b 55 C, a 25 C, and a 125 C, Subgroups 1, 2, 3, 7, and 8. Note 3: Sample tested (Method 5005, Table I) on each manufactured lot at b 55 C, a 25 C, and a 125 C, Subgroups A1, 2, 3, 7, and 8. Note 4: Guaranteed by applying specified input condition and testing VOH/VOL. 6 Military VersionPreliminary (Continued) AC Electrical Characteristics VEE e b4.2V to b5.7V, VCC e VCCA e GND Symbol Parameter TC e b55 C TC e a 25 C TC e a 125 C Min Min Min Max Max Conditions Notes MHz Figures 1 and 4 4 fMax Toggle Frequency 200 tPLH tPHL Propagation Delay CP to Output 0.9 3.70 1.0 3.20 1.20 3.90 ns Figures 1 and 4 1, 2, 3, 5 tPZH tPHZ Propagation Delay OEN to Output 1.20 0.70 5.0 3.0 1.60 0.70 4.20 2.80 1.40 0.70 4.30 3.20 ns Figures 3 and 7 1, 2, 3, 5 tTLH tTHL Transition Time 20% to 80%, 80% to 20% 0.40 2.50 0.40 2.40 0.40 2.70 ns Figures 1 and 4 4 tS Setup Time Dn CEN (Disable Time) CEN (Release Time) tH tpw(H) 250 Units Max 200 1.30 0.60 1.30 1.30 0.60 1.30 1.30 0.60 1.30 ns Figures 2 and 5 4 Dn 0.30 0.30 0.30 ns Figures 1 and 6 4 CP 2.4 2.4 2.4 ns Figures 1 and 4 4 Hold Time Pulse Width HIGH Note 1: F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals b 55 C), then testing immediately after power-up. This provides ``cold start'' specs which can be considered a worst case condition at cold temperatures. Note 2: Screen tested 100% on each device at a 25 C, temperature only, Subgroup A9. Note 3: Sample tested (Method 5005, Table I) on each manufactured lot at a 25 C, Subgroup A9, and at a 125 C and b 55 C temperatures, Subgroups A10 and A11. Note 4: Not tested at a 25 C, a 125 C, and b 55 C temperature (design characterization data). Note 5: The propagation delay specified is for single output switching. Delays may vary up to 300 ps with multiple outputs switching. 7 Test Circuitry Notes: VCC, VCCA e a 2V, VEE e b 2.5V L1 and L2 e equal length 50X impedance lines RT e 50X terminator internal to scope Decoupling 0.1 mF from GND to VCC and VEE All unused outputs are loaded with 25X to GND CL e Fixture and stray capacitance s 3 pF TL/F/10610 - 5 FIGURE 1. Toggle Frequency Test Circuit Notes: VCC, VCCA e a 2V, VEE e b 2.5V L1 and L2 e equal length 50X impedance lines RT e 50X terminator internal to scope Decoupling 0.1 mF from GND to VCC and VEE All unused outputs are loaded with 25X to GND CL e Fixture and stray capacitance s 3 pF TL/F/10610 - 6 FIGURE 2. AC Test Circuit Notes: VCC, VCCA e a 2V, VEE e b 2.5V L1 and L2 e equal length 50X impedance lines RT e 50X terminator internal to scope Decoupling 0.1 mF from GND to VCC and VEE All unused outputs are loaded with 25X to GND CL e Fixture and stray capacitance s 3 pF TL/F/10610 - 7 FIGURE 3. AC Test Circuit 8 Switching Waveforms TL/F/10610 - 8 FIGURE 4. Propagation Delay (Clock) and Transition Times TL/F/10610 - 9 FIGURE 5. Setup and Pulse Width Times TL/F/10610 - 10 FIGURE 6. Data Setup and Hold Time Notes: ts is the minimum time before the transition of the clock that information must be present at the data input. th is the minimum time after the transition of the clock that information must remain unchanged at the data input. TL/F/10610 - 11 Note: The output AC measurement point for cut-off propagation delay testing e the 50% voltage point between active VOL and VOH. FIGURE 7. Cutoff Times 9 Ordering Information The device number is used to form part of a simplified purchasing code where a package type and temperature range are defined as follows: 100354 D Device Type (Basic) C QB Special Variation QB e Military grade device with environmental and burn-in processing. Package Code D e Ceramic DIP F e Quad Cerpak P e Plastic DIP Q e Plastic Leaded Chip Carrier (PCC) Temperature Range C e Commercial (0 C to a 85 C) I e Industrial (b40 C to a 85 C) (PCC only) M e Military (b55 C to a 125 C) Physical Dimensions inches (millimeters) 24-Lead Ceramic Dual-In-Line Package (D) NS Package Number J24E 10 Physical Dimensions inches (millimeters) (Continued) 24-Lead Plastic Dual-in-Line Package (P) NS Package Number N24E 28-Lead Plastic Chip Carrier (Q) NS Package Number V28A 11 100354 Low Power 8-Bit Register with Cut-Off Drivers Physical Dimensions inches (millimeters) (Continued) Lit. Y 114922 28-Lead Quad Cerpak (F) NS Package Number W24B LIFE SUPPORT POLICY NATIONAL'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation 1111 West Bardin Road Arlington, TX 76017 Tel: 1(800) 272-9959 Fax: 1(800) 737-7018 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 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