MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module>
PS11032
FLAT-BASE TYPE
INSULATED TYPE
Jan. 2000
PS11032 INTEGRATED FUNCTIONS AND FEATURES
• Converter bridge for 3 phase AC-to-DC power conversion.
• 3 phase IGBT inverter bridge configured by the latest 3rd.
generation IGBT and diode technology.
• Inverter output current capability IO (Note 1):
Type name,LotNo.
30292827262524232221
60
4.5
9
25
63±1
(69)
36
45.72
24
5.08
0.4
0.6
1.2
0.6
74±1
50.7±0.8
15
3.5
3±0.5
16.5±0.5
8.5±0.5
16.5±0.5
25±0.5 (25.7)
2255.5
4440
4-R3
2-R4.5
2-R2.25
16
15
14
13
12
11
10
98
7
6543
21
Terminals Assignment :
1. CBU+
2. CBU–
3. CBV+
4. CBV–
5. CBW+
6. CBW–
7. VD
8. UP
9. VP
10. WP
11. UN
12. VN
13. WN
14. FO
15. Vamp
16. GND
21. P1
22. R
23. S
24. T
25. N1
26. P2
27. U
28. V
29. W
30. N2
APPLICATION
Acoustic noise-less 0.2kW/200V AC Class 3 phase inv erters, motor control applications, and
motors with built-in small size inverter package
PACKAGE OUTLINES
MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Po wer Module>
PS11032
FLAT-BASE TYPE
INSULATED TYPE
INTEGRATED DRIVE, PROTECTION AND SYSTEM CONTROL FUNCTIONS:
• P-Side IGBTs : Drive circuit, high-level-shift circuit, bootstrap circuit supply scheme for Single Control-Power-Source drive, and un-
der voltage (UV) protection.
• N-Side IGBTs : Drive circuit, DC-Link current sense and amplifier circuits for overcurrent protection, control-supply under-voltage
protection (UV), and fault output (FO) signaling circuit.
• Fault Output : N-side IGBT short circuit (SC), over-current (OC), and control supply under-voltage (UV).
• Inverter Analog Current Sense : N-Side IGBT DC-Link Current Sense.
• Input Interface : 5V CMOS/TTL compatible, Schmitt Trigger input, and Arm-Shoot-Through interlock protective function.
Type Name
PS11032 IO (100%)
1.5Arms IO
(150%; 60sec)
2.25Arms
Motor Rating
0.2 kW/200V AC
(Note 1) : The inverter output current is assumed to be sinu-
soidal and the peak current value of each of the
above loading cases is defined as : IOP = IO × √2,
TC < 100°C
(Fig. 1)
MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module>
PS11032
FLAT-BASE TYPE
INSULATED TYPE
Jan. 2000
W
V
N2
T
S
R
P1
P2
U
VD
UP
VP
WP
UN
VN
WN
FO
V(amp)
GND
Input signal conditioning
(Inter lock circuit)
Level shifter
Drive circuit Drive circuit
UV Protection
–+
UV Protection
Fo Circuit
OC/SC Prot ection
N1
INTERNAL FUNCTIONS BLOCK DIAGRAM
ConditionSymbol Item Ratings Unit
Applied between P2-N2
Applied between P2-N2, Surge-value
Applied between P2-U.V.W, U.V.W-N2
Applied between P2-U.V.W, U.V.W-N2
TC = 25°C, “( )” means IC peak value
VCC
VCC(surge)
VP or VN
VP(S) or
VN(S)
±Ic(±Icp)
Supply voltage
Supply voltage (surge)
Each output IGBT collector-emitter static voltage
Each output IGBT collector-emitter
switching voltage
Each output IGBT collector current
450
500
600
600
±4 (±8)
V
V
V
V
A
MAXIMUM RATINGS (Tj = 25°C)
INVERTER PART
ConditionSymbol Item Ratings Unit
3φ rectifying circuit
1 cycle at 60Hz, peak value non-repetitive
Value for one cycle of surge current
VRRM
Ea
IO
IFSM
I2t
Repetitive peak reverse voltage
Recommended AC input voltage
DC output current
Surge (non-repetitive) forward current
I2t for fusing
800
220
10
100
42
V
Vrms
A
A
A2s
CONVERTER PART
Symbol Item Ratings Unit
VD, VDB
VCIN
VFO
IFO
Iamp
Supply voltage
Input signal voltage
Fault output supply voltage
Fault output current
DC-Link IGBT current signal Amp output current
–0.5 ~ 20
–0.5 ~ +7.5
–0.5 ~ +7.5
15
1
V
V
V
mA
mA
CONTROL PAR T
(Fig. 2)
MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module>
PS11032
FLAT-BASE TYPE
INSULATED TYPE
Jan. 2000
ConditionSymbol Item Ratings Unit
(Note 2)
—
(Fig. 3)
60 Hz sinusoidal AC applied between all terminals and
the base plate for 1 minute.
Mounting screw: M4
Tj
Tstg
TC
VISO
—
Junction temperature
Storage temperature
Module case operating temperature
Isolation voltage
Mounting torque
–20 ~ +125
–40 ~ +125
–20 ~ +100
2500
0.98 ~ 1.47
°C
°C
°C
Vrms
N·m
TOTAL SYSTEM
(Note 2) : The indicated values are specified considering the safe operation of all the parts within the ASIPM. The max. ratings for the ASIPM
power chips (IGBT & FWDi) is Tj < 150.
Condition
Symbol Item Ratings
Inverter IGBT (1/6)
Inverter FWDi (1/6)
Converter Di (1/6)
Case to fin thermal, grease applied (1 Module)
Rth(jc)Q
Rth(jc)F
Rth(jc)FR
Rth(cf)
Junction to case Thermal
Resistance
Contact Thermal Resistance
Min. °C/W
°C/W
°C/W
°C/W
THERMAL RESISTANCE
Typ. Max.
—
—
—
—
—
—
—
—
6.1
6.1
4.8
0.074
Unit
Short circuit endurance
(Output, Arm, and Load Short Circuit Modes)
Switching SOA
Tj = 25°C, Input = ON, Ic = 4A, VD = VDB = 15V
(Shunt voltage drop not included)
Tj = 25°C, –IC = 4A
Tj = 25°C, IFR = 5A
VR = VRRM, Tj = 125°C
1/2 Bridge inductive, Input = 5V ↔ 0V
VCC = 300V, IC = 4A, Tj = 125°C
VD = 15V, VDB = 15V
Note: ton, toff include delay time of the internal control
circuit.
Condition
Symbol Item Ratings
Min.
V
V
V
mA
µs
µs
µs
µs
µs
Typ. Max.
—
—
—
—
0.3
—
—
—
—
—
—
—
—
0.6
0.43
1.6
0.5
0.12
2.9
2.9
1.5
8
1.5
0.8
2.5
1.2
—
• No destruction
• FO output by protection operation
• No destruction
• No protecting operation
• No FO output
ELECTRICAL CHARACTERISTICS (Tj = 25°C, VD = 15V, VDB = 15V unless otherwise noted)
Collector-emitter saturation
voltage
FWDi forward voltage
Converter diode voltage
Converter diode reverse current
Switching times
FWDi reverse recovery time
VCE(sat)
VEC
VFR
IRRM
ton
tc(on)
toff
tc(off)
trr
(Fig. 3)
TC
CASE TEMPERATURE MEASUREMENT POINT
@VCC ≤ 400V, Input = 5V → 0V (One-Shot)
–20°C ≤ Tj (start) ≤ 125°C, 13.5V ≤ VD = VDB ≤ 16.5V
@VCC ≤ 400V, Input = 5V ↔ 0V, Tj ≤ 125°C
IC < OC trip level, 13.5V ≤ VD = VDB ≤ 16.5V
Units
MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module>
PS11032
FLAT-BASE TYPE
INSULATED TYPE
Jan. 2000
V
V
V
V/µs
V
V
µs
°C
kHz
µs
400
16.5
16.5
+1
0.8
5.0
—
100
15
—
—
13.5
13.5
–1
0
4.0
2.2
—
—
1
Applied across P2-N2 terminals
Applied between VD-GND
Applied between CBU+ & CBU–, CBV+ & CBV–, CBW+ & CBW–
Applied between UP • VP • WP • UN • VN • WN and
GND
Relates to corresponding inputs
TC ≤ 100°C, Tj ≤ 125°C
Tj = 25°C, VD = 15V, Vin = 5V
Tj = 25°C, VD = VDB = 15V, Vin = 5V
Applied between input terminal-inside power supply
TC ≤ 100°C, Tj ≤ 125°C
Relates to corresponding inputs
TC = –20°C ~ +100°C (Note 3)
Relates to corresponding input (Fig. 6)
IC = IOP(100%) VD = 15V
IC = IOP(200%) Tj = 25°C (Fig. 4)
IC = IOP(250%) VD = 15V
IC = 0A (Fig. 4)
Tj = 25°C (Fig. 5)
Tj = 25°C (Fig. 5)
Tj = 25°C (Fig. 5)
Tj = 25°C (Fig. 5)
TC = Tj = 25°C (Fig. 5)
Tj = 25°C (Note 4)
Open collector output (Note 4)
Circuit current (Average)
Circuit current (Average)
Input on threshold voltage
Input off threshold voltage
Input pull-up resistor
PWM input frequency
Arm shoot-through blocking time
Input interlock sensing
Inverter DC-Link IGBT current sense voltage
output signal
Inverter DC-Link IGBT current sense voltage
output limit
Over current trip level
Over current delay time
Short circuit trip level
Short circuit delay timeTrip level
Reset level
Trip level
Reset level
Delay time
Fault output pulse width
Fault output current
Condition
Symbol Item Ratings
ID
IDB
Vth(on)
Vth(off)
Ri
fPWM
tdead
tint
Vamp(100%)
Vamp(200%)
Vamp(250%)
Vamp(0)
OC
tOC
SC
tSC
UVD
UVDr
UVDB
UVDBr
tdV
tFO
IFo(H)
IFo(L)
Min. mA
mA
V
V
kΩ
kHz
µs
ns
V
V
V
mV
A
µs
A
µs
V
V
V
V
µs
ms
µA
mA
Typ. Max.
—
—
0.8
2.5
—
1
2.2
—
1.5
3.0
5.0
—
4.3
—
—
—
11.0
11.5
10.1
10.6
—
1.0
—
—
—
—
1.4
3.0
50
—
—
100
2.0
4.0
—
50
5.3
10
8.0
2
12.0
12.5
10.8
11.3
10
1.8
—
—
50
5
2.0
4.0
—
15
—
—
2.5
5.0
—
100
8.0
—
—
—
13.0
13.5
11.6
12.1
—
—
1
15
Unit
ELECTRICAL CHARACTERISTICS (Tj = 25°C, VD = 15V, VDB = 15V unless otherwise noted)
(Note 3) : The dead-time has to be set externally by the CPU; it is not part of the ASIPM internal functions.
(Note 4) : Fault output signaling is given only when the internal OC, SC, & UV protection circuits are activated.
The OC, SC and UV protection (and fault output) operate for the lower arms only. The OC and SC protection Fault output is given
in a pulse format while that of UV protection is maintained throughout the duration of the under-voltage condition.
Condition
Symbol Item Ratings
VCC
VD
VDB
∆VD, VDB
VCIN(ON)
VCIN(OFF)
tdead
TC
fPWM
tXX
Supply voltage
Supply voltage
Supply voltage
Supply voltage ripple
Input on voltage
Input off voltage
Arm shoot-through blocking time
Module case operating temperature
PWM Input frequency
Allowable minimum input on-pulse width
Min.
RECOMMENDED OPERATING CONDITIONS
Typ. Max.
300
15.0
15.0
—
—
—
—
—
—
—
Unit
Supply circuit under
voltage protection
200
1
2
3
4
5
300
1000
0
Vamp (V)
Vamp
(200%)
Vamp
(100%)
V
D
= 15V
Tj = 25°C
Vamp
Actual Load Peak Current (%), (I
C
= I
O
✕ 2)
(Fig. 4)
INVERTER DC-LINK IGBT CURRENT ANALOGUE
SIGNALING OUTPUT (TYPICAL)
MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module>
PS11032
FLAT-BASE TYPE
INSULATED TYPE
Jan. 2000
SC
Ic(A)
OC
tw (µs)
Over current trip level
Collector current
Short circuit trip level
102
0
CURRENT ABNORMALITY PROTECTIVE FUNCTIONS
ARM-SHOOT-THROUGH INTER-LOCK PROTECTIVE FUNCTION
(Fig. 7)
Protection is achieved by monitoring and filtering the N-side
DC-Bus current. The over-current protection is activated (after al-
lowing a filtering time of 10 µs) when the line current reaches
250% of the rated load-current IO (rms). Similarly, the short circuit
protection is activated (after allowing a filtering time of 2 µs) when
the line current reaches twice the rated collector-current (IC).
When a current trip-level is exceeded (OC or SC), all the N-side
IGBTs are intercepted (turned OFF) and a fault-signal is output.
After the fault-signal output duration (1.8 ms - typ.), the intercep-
tion is Reset at the following OFF input signal. However, since the
fault may be repetitive, it is recommended to stop the system after
the fault-signal is received and check the f ault. The trip-level set-
tings described above are summarized in the following figure:
(Fig. 5)
P-Side Input Signal : V
CIN(p)
N-Side Input Signal : V
CIN(n)
ON
ON
P-Side IGBT Gate : V
GE(p)
N-Side IGBT Gate : V
GE(n)
a1 b4
b3
b2
b1
a4
a3
a2
0
0
(Fig. 6)
RECOMMENDED I/O INTERFACE CIRCUIT
Description:
(1) During the ON-State of either of the upper-arm or the lower-arm IGBT, the inter-lock protection circuit blocks any erroneous ON pulses (re-
sulting from input noise) from triggering the other arm IGBT and thus it prevents the arm-shoot-through situation.
(2) When two ON-signals are received for both the upper and the lower arms, the signal received first will be passed to the IGBT and the sec-
ond signal will be blocked. The second signal will be passed to its corresponding IGBT immediately after the first signal is OFF.
Note: This protective function provides no fault signaling output. The Dead-Time has to be set using the micro-controller (CPU).
b1. N-side normal ON-signal ⇒ N-side IGBT gate turns ON.
b2. Simultaneous ON-signals ⇒ P-side IGBT gate remains OFF.
b3. N-side receives OFF-signal ⇒ N-side IGBT gate turns OFF.
b4. Immediately after (b3) ⇒ P-side IGBT gate turns ON.
Operation:
a1. P-side normal ON-signal ⇒ P-side IGBT gate turns ON.
a2. N-side erroneous ON-signal ⇒ N-side IGBT gate remains OFF.
a3. While P-side ON-signal remains ⇒ P-side IGBT gate remains ON.
a4. N-side normal ON-signal ⇒ N-side IGBT gate turns ON.
U
P
,V
P
,W
P
,U
N
,V
N
,W
N
Fo
V(amp)
GND(Logic)
ASIPM
5V
V
D
(15V)
CPU
R
R
5.1kΩ
5V
10kΩ
0.1nF
0.1nF
