LTC2226H
1
2226hfc
TYPICAL APPLICATION
FEATURES
APPLICATIONS
DESCRIPTION
12-Bit, 25Msps
125°C ADC in LQFP
The LTC
®
2226H is a 12-bit 25Msps, low power 3V A/D
converter designed for digitizing high frequency, wide
dynamic range signals. The LTC2226H is perfect for
demanding imaging and communications applications
with AC performance that includes 71.4dB SNR and 90dB
SFDR.
DC specs include ±0.3LSB INL (typ), ±0.3LSB DNL (typ)
and no missing codes over temperature. The transition
noise is a low 0.25LSBRMS.
A single 3V supply allows low power operation. A separate
output supply allows the outputs to drive 0.5V to 3.6V
logic.
A single-ended CLK input controls converter operation. An
optional clock duty cycle stabilizer allows high performance
at full speed for a wide range of clock duty cycles.
Typical INL, 2V Range
n Sample Rate: 25Msps
n –40°C to 125°C Operation
n Single 3V Supply (2.8V to 3.5V)
n Low Power: 75mW
n 71.4dB SNR
n 90dB SFDR
n No Missing Codes
n Flexible Input: 1VP-P to 2VP-P Range
n 575MHz Full Power Bandwidth S/H
n Clock Duty Cycle Stabilizer
n Shutdown and Nap Modes
n Pin Compatible Family
n LTC2246H (14-Bit), LTC2226H (12-Bit)
n 48-Pin (7mm × 7mm) LQFP Package
n Automotive
n Industrial
n Wireless and Wired Broadband Communication
–
+
INPUT
S/H
CORRECTION
LOGIC OUTPUT
DRIVERS
12-BIT
PIPELINED
ADC CORE
CLOCK/DUTY
CYCLE
CONTROL
FLEXIBLE
REFERENCE
D11
•
•
•
D0
CLK
REFH
REFL
ANALOG
INPUT
2226 TA01
OVDD
OGND
CODE
0
INL ERROR (LSB)
3072
2226 TA01b
1024 2048 4096
1.00
0.75
0.50
0.25
0
–0.25
–0.50
–0.75
–1.00
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
LTC2226H
2
2226hfc
CONVERTER CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS
Supply Voltage (VDD) ..................................................4V
Digital Output Ground Voltage (OGND) ........ –0.3V to 1V
Analog Input Voltage (Note 3) .......–0.3V to (VDD + 0.3V)
Digital Input Voltage ......................–0.3V to (VDD + 0.3V)
Digital Output Voltage ................ –0.3V to (OVDD + 0.3V)
Power Dissipation .............................................1500mW
Operating Temperature Range................ –40°C to 125°C
Storage Temperature Range ................... –65°C to 150°C
OVDD = VDD (Notes 1, 2)
PARAMETER CONDITIONS MIN TYP MAX UNITS
Resolution (No Missing Codes) l12 Bits
Integral Linearity Error Differential Analog Input (Note 5) l–1.5 ±0.3 1.5 LSB
Differential Linearity Error Differential Analog Input l–0.8 ±0.15 0.8 LSB
Offset Error (Note 6) l–15 ±2 15 mV
Gain Error External Reference l–3 ±0.5 3 %FS
Offset Drift ±10 µV/°C
Full-Scale Drift Internal Reference ±30 ppm/°C
External Reference ±5 ppm/°C
Transition Noise SENSE = 1V 0.25 LSBRMS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 4)
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
GND
AIN+
AIN–
GND
REFH
REFH
REFL
REFL
GND
VDD
VDD
VDD
13
14
15
16
17
18
19
20
21
22
23
24
GND
CLK
GND
SHDN
OE
GND
NC
NC
D0
D1
D2
GND
48
47
46
45
44
43
42
41
40
39
38
37
GND
VDD
VDD
VCM
VCM
SENSE
MODE
OF
D11
D10
D9
GND
GND
D8
D7
D6
GND
OVDD
OGND
GND
D5
D4
D3
GND
TOP VIEW
LX PACKAGE
48-LEAD (7mm × 7mm) PLASTIC LQFP
TJMAX = 150°C, θJA = 53°C/W
ORDER INFORMATION
LEAD FREE FINISH PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC2226HLX#PBF LTC2226LX 48-Lead (7mm × 7mm) Plastic LQFP –40°C to 125°C
LEAD BASED FINISH PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC2226HLX LTC2226LX 48-Lead (7mm × 7mm) Plastic LQFP –40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
LTC2226H
3
2226hfc
ANALOG INPUT
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VIN Analog Input Range (AIN+ – AIN–) 2.8V < VDD < 3.5V (Note 7) l±0.5V to
±1V
V
VIN, CM Analog Input Common Mode (AIN+ + AIN–)/2 Differential Input (Note 7)
Single Ended Input (Note 7)
l
l
1
0.5
1.5
1.5
1.9
2
V
V
IIN Analog Input Leakage Current 0V < AIN+, AIN– < VDD l–10 10 µA
ISENSE SENSE Input Leakage 0V < SENSE < 1V l–10 10 µA
IMODE MODE Pin Leakage l–10 10 µA
tAP Sample-and-Hold Acquisition Delay Time 0 ns
tJITTER Sample-and-Hold Acquisition Delay Time Jitter 0.2 psRMS
CMRR Analog Input Common Mode Rejection Ratio 80 dB
The l denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at TA = 25°C. (Note 4)
DYNAMIC ACCURACY
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
SNR Signal-to-Noise Ratio 5MHz Input
12.5MHz Input
70MHz Input
l
69.6
71.4
71.2
70.9
dB
dB
dB
SFDR Spurious Free Dynamic Range
2nd or 3rd Harmonic
5MHz Input
12.5MHz Input
70MHz Input
l
74
90
90
85
dB
dB
dB
SFDR Spurious Free Dynamic Range
4th Harmonic or Higher
5MHz Input
12.5MHz Input
70MHz Input
l
78
90
90
90
dB
dB
dB
S/(N+D) Signal-to-Noise Plus Distortion Ratio 5MHz Input
12.5MHz Input
70MHz Input
l
69.1
71.4
71.2
70.8
dB
dB
dB
IMD Intermodulation Distortion fIN1 = 4.3MHz, fIN2 = 4.6MHz 90 dB
The l denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 4)
INTERNAL REFERENCE CHARACTERISTICS
PARAMETER CONDITIONS MIN TYP MAX UNITS
VCM Output Voltage IOUT = 0 1.475 1.500 1.525 V
VCM Output Tempco ±25 ppm/°C
VCM Line Regulation 2.8V < VDD < 3.5V 3 mV/V
VCM Output Regulation –1mA < IOUT < 1mA 4 W
TA = 25°C. (Note 4)
DIGITAL INPUTS AND DIGITAL OUTPUTS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
LOGIC INPUTS (CLK, OE, SHDN)
VIH High Level Input Voltage VDD = 3V l2 V
VIL Low Level Input Voltage VDD = 3V l0.8 V
IIN Input Current VIN = 0V to VDD l–10 10 µA
CIN Input Capacitance (Note 7) 3 pF
The l denotes the specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C. (Note 4)
LTC2226H
4
2226hfc
POWER REQUIREMENTS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VDD Analog Supply Voltage (Note 9) l2.8 3 3.5 V
OVDD Output Supply Voltage (Note 9) l0.5 3 3.6 V
IVDD Supply Current l25 30 mA
PDISS Power Dissipation l75 90 mW
PSHDN Shutdown Power SHDN = H, OE = H, No CLK 2 mW
PNAP Nap Mode Power SHDN = H, OE = L, No CLK 15 mW
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 8)
TIMING CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fSSampling Frequency (Note 9) l1 25 MHz
tLCLK Low Time Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
(Note 7)
l
l
18.9
5
20
20
500
500
ns
ns
tHCLK High Time Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
(Note 7)
l
l
18.9
5
20
20
500
500
ns
ns
tAP Sample-and-Hold Aperture Delay 0 ns
tDCLK to DATA Delay CL = 5pF (Note 7) l1.4 2.7 6 ns
Data Access Time After OE↓CL = 5pF (Note 7) l4.3 12 ns
BUS Relinquish Time (Note 7) l3.3 10 ns
Pipeline Latency 5 Cycles
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 4)
DIGITAL INPUTS AND DIGITAL OUTPUTS
The l denotes the specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
LOGIC OUTPUTS
OVDD = 3V
COZ Hi-Z Output Capacitance OE = High (Note 7) 3 pF
ISOURCE Output Source Current VOUT = 0V 50 mA
ISINK Output Sink Current VOUT = 3V 50 mA
VOH High Level Output Voltage IO = –10µA
IO = –200µA
l
2.7
2.995
2.99
V
V
VOL Low Level Output Voltage IO = 10µA
IO = 1.6mA
l
0.005
0.09
0.4
V
V
OVDD = 2.5V
VOH High Level Output Voltage IO = –200µA 2.49 V
VOL Low Level Output Voltage IO = 1.6mA 0.09 V
OVDD = 1.8V
VOH High Level Output Voltage IO = –200µA 1.79 V
VOL Low Level Output Voltage IO = 1.6mA 0.09 V
LTC2226H
5
2226hfc
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to ground with GND and OGND
wired together (unless otherwise noted).
Note 3: When these pin voltages are taken below GND or above VDD, they
will be clamped by internal diodes. This product can handle input currents
of greater than 100mA below GND or above VDD without latchup.
Note 4: VDD = 3V, fSAMPLE = 25MHz, input range = 2VP-P with differential
drive, unless otherwise noted.
Note 5: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 6: Offset error is the offset voltage measured from –0.5 LSB when
the output code flickers between 0000 0000 0000 and 1111 1111 1111.
Note 7: Guaranteed by design, not subject to test.
Note 8: VDD = 3V, fSAMPLE = 25MHz, input range = 1VP-P with
differential drive.
Note 9: Recommended operating conditions.
TYPICAL PERFORMANCE CHARACTERISTICS
Typical INL, 2V Range, 25Msps
Typical DNL, 2V Range, 25Msps
8192 Point FFT, fIN = 5MHz, –1dB,
2V Range, 25Msps
8192 Point FFT, fIN = 30MHz,
–1dB, 2V Range, 25Msps
8192 Point FFT, fIN = 70MHz,
–1dB, 2V Range, 25Msps
8192 Point FFT, fIN = 140MHz,
–1dB, 2V Range, 25Msps
ELECTRICAL CHARACTERISTICS
CODE
0
INL ERROR (LSB)
3072
2226H G01
1024 2048 4096
1.00
0.75
0.50
0.25
0
–0.25
–0.50
–0.75
–1.00
CODE
0
DNL ERROR (LSB)
3072
2226H G02
1024 2048 4096
1.00
0.75
0.50
0.25
0
–0.25
–0.50
–0.75
–1.00
FREQUENCY (MHz)
0
AMPLITUDE (dB)
2226H G03
2 4 6 8 10 12
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
FREQUENCY (MHz)
0
AMPLITUDE (dB)
2226H G04
2 4 6 8 10 12
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
FREQUENCY (MHz)
0
AMPLITUDE (dB)
2226H G05
2 4 6 8 10 12
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
FREQUENCY (MHz)
0
AMPLITUDE (dB)
2226H G06
2 4 6 8 10 12
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
LTC2226H
6
2226hfc
TYPICAL PERFORMANCE CHARACTERISTICS
8192 Point 2-Tone FFT,
fIN = 10.9MHz and 13.8MHz,
–1dB, 2V Range, 25Msps
Grounded Input Histogram,
25Msps
SNR vs Input Frequency, –1dB,
2V Range, 25Msps
SFDR vs Input Frequency, –1dB,
2V Range, 25Msps
SNR and SFDR vs Sample Rate,
2V Range, fIN = 5MHz, –1dB
SNR vs Input Level, fIN = 5MHz,
2V Range, –1dB
SFDR vs Input Level, fIN = 5MHz,
2V Range, 25Msps
IVDD vs Sample Rate, 5MHz Sine
Wave Input, –1dB
IOVDD vs Sample Rate, 5MHz Sine
Wave Input, –1dB, OVDD = 1.8V
FREQUENCY (MHz)
0
AMPLITUDE (dB)
2226H G07
2 4 6 8 10 12
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
CODE
COUNT
2050
2226H G08
2048 2049
70000
60000
50000
40000
30000
20000
10000
0
61758
1607
2155
INPUT FREQUENCY (MHz)
0
SNR (dBFS)
70
71
200
2226H G09
69
68 50 100 150
72
INPUT FREQUENCY (MHz)
0
100
95
90
85
80
75
70
65
150
2226H G10
50 100 200
SFDR (dBFS)
SAMPLE RATE (Msps)
0
SNR AND SFDR (dBFS)
110
100
90
80
70
60 40 50
2226H G11
10 20 30
SNR
SFDR
INPUT LEVEL (dBFS)
–60 –50
SNR (dBc AND dBFS)
–40 –20–30 –10 0
2227H G12
80
70
60
50
40
30
20
10
0
dBFS
dBc
INPUT LEVEL (dBFS)
–60 –50 –40 –20–30 –10 0
SFDR (dBc AND dBFS)
2226H G13
120
110
100
90
80
70
60
50
40
30
20
dBFS
dBc
90dBc SFDR
REFERENCE LINE
SAMPLE RATE (Msps)
0
35
30
25
20
15
30
2226 G14
10 20 255 15 35
IVDD (mA)
2V RANGE
1V RANGE
SAMPLE RATE (Msps)
IOVDD (mA)
2226H G15
3
2
1
0020 305 15 35
10 25
LTC2226H
7
2226hfc
PIN FUNCTIONS
GND (Pins 1, 4, 9, 13, 15, 18, 24, 25, 29, 32, 36, 37,
48): ADC Power Ground.
AIN+ (Pin 2): Positive Differential Analog Input.
AIN- (Pin 3): Negative Differential Analog Input.
REFH (Pins 5, 6): ADC High Reference. Bypass to Pins 7,
8 with a 0.1µF ceramic chip capacitor as close to the pin
as possible. Also bypass to Pins 7, 8 with an additional
2.2µF ceramic chip capacitor and to GND with a 1µF ce-
ramic chip capacitor.
REFL (Pin 7, 8): ADC Low Reference. Bypass to Pins 5, 6
with a 0.1µF ceramic chip capacitor as close to the pin as
possible. Also bypass to Pin 5, 6 with an additional 2.2µF
ceramic chip capacitor and to ground with a 1µF ceramic
chip capacitor.
VDD (Pins 10, 11, 12, 46, 47): 3V Supply. Bypass to GND
with 0.1µF ceramic chip capacitors.
CLK (Pin 14): Clock Input. The input sample starts on the
positive edge.
SHDN (Pin 16): Shutdown Mode Selection Pin. Connecting
SHDN to GND and OE to GND results in normal operation
with the outputs enabled. Connecting SHDN to GND and
OE to VDD results in normal operation with the outputs at
high impedance. Connecting SHDN to VDD and OE to GND
results in nap mode with the outputs at high impedance.
Connecting SHDN to VDD and OE to VDD results in sleep
mode with the outputs at high impedance.
If the clock duty cycle stabilizer is used, a >1µs high pulse
should be applied to the SHDN pin once the power supplies
are stable at power up.
OE (Pin 17): Output Enable Pin. Refer to SHDN pin func-
tion.
NC (Pins 19, 20): Do not connect these pins.
D0–D11 (Pins 21-23, 26-28, 33-35, 38-40): Digital Out-
puts. D11 is the MSB.
OGND (Pin 30): Output Driver Ground.
OVDD (Pin 31): Positive Supply for the Output Drivers.
Bypass to ground with 0.1µF ceramic chip capacitor.
OF (Pin 41): Over/Under Flow Output. High when an over
or under flow has occurred.
MODE (Pin 42): Output Format and Clock Duty Cycle
Stabilizer Selection Pin. Connecting MODE to GND selects
offset binary output format and turns the clock duty cycle
stabilizer off. 1/3 VDD selects offset binary output format
and turns the clock duty cycle stabilizer on. 2/3 VDD selects
2’s complement output format and turns the clock duty
cycle stabilizer on. VDD selects 2’s complement output
format and turns the clock duty cycle stabilizer off.
SENSE (Pin 43): Reference Programming Pin. Connecting
SENSE to VCM selects the internal reference and a ±0.5V
input range. VDD selects the internal reference and a ±1V
input range. An external reference greater than 0.5V and
less than 1V applied to SENSE selects an input range of
±VSENSE. ±1V is the largest valid input range.
VCM (Pins 44, 45): 1.5V Output and Input Common
Mode Bias. Bypass to ground with 2.2µF ceramic chip
capacitor.
LTC2226H
8
2226hfc
FUNCTIONAL BLOCK DIAGRAM
Figure 1. Functional Block Diagram
TIMING DIAGRAM
SHIFT REGISTER
AND CORRECTION
DIFF
REF
AMP
REF
BUF
2.2µF
1µF 1µF
0.1µF
INTERNAL CLOCK SIGNALSREFH REFL
CLOCK/DUTY
CYCLE
CONTROL
RANGE
SELECT
1.5V
REFERENCE
FIRST PIPELINED
ADC STAGE
FIFTH PIPELINED
ADC STAGE
SIXTH PIPELINED
ADC STAGE
FOURTH PIPELINED
ADC STAGE
SECOND PIPELINED
ADC STAGE
REFH REFL
CLK OE
MODE
OGND
OVDD
2226H F01
INPUT
S/H
SENSE
VCM
AIN–
AIN+
2.2µF
THIRD PIPELINED
ADC STAGE
OUTPUT
DRIVERS
CONTROL
LOGIC
SHDN
OF
D11
D0
•
•
•
tAP
N + 1
N + 2 N + 4
N + 3 N + 5
N
ANALOG
INPUT
tH
tD
tL
N – 4 N – 3 N – 2 N – 1
CLK
D0-D11, OF
2226H TD01
N – 5 N
LTC2226H
9
2226hfc
DYNAMIC PERFORMANCE
Signal-to-Noise Plus Distortion Ratio
The signal-to-noise plus distortion ratio [S/(N + D)] is
the ratio between the RMS amplitude of the fundamen-
tal input frequency and the RMS amplitude of all other
frequency components at the ADC output. The output is
band limited to frequencies above DC to below half the
sampling frequency.
Signal-to-Noise Ratio
The signal-to-noise ratio (SNR) is the ratio between the
RMS amplitude of the fundamental input frequency and
the RMS amplitude of all other frequency components
except the first five harmonics and DC.
Total Harmonic Distortion
Total harmonic distortion is the ratio of the RMS sum
of all harmonics of the input signal to the fundamental
itself. The out-of-band harmonics alias into the frequency
band between DC and half the sampling frequency. THD
is expressed as:
THD = 20Log V22+V32+V42+...Vn2
( )
/V1
( )
where V1 is the RMS amplitude of the fundamental fre-
quency and V2 through Vn are the amplitudes of the second
through nth harmonics. The THD calculated in this data
sheet uses all the harmonics up to the fifth.
Intermodulation Distortion
If the ADC input signal consists of more than one spectral
component, the ADC transfer function nonlinearity can
produce intermodulation distortion (IMD) in addition to
THD. IMD is the change in one sinusoidal input caused
by the presence of another sinusoidal input at a different
frequency.
If two pure sine waves of frequencies fa and fb are applied
to the ADC input, nonlinearities in the ADC transfer function
can create distortion products at the sum and difference
frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3, etc.
The 3rd order intermodulation products are 2fa + fb, 2fb
+ fa, 2fa – fb and 2fb – fa. The intermodulation distortion
APPLICATIONS INFORMATION
is defined as the ratio of the RMS value of either input tone
to the RMS value of the largest 3rd order intermodulation
product.
Spurious Free Dynamic Range (SFDR)
Spurious free dynamic range is the peak harmonic or spuri-
ous noise that is the largest spectral component excluding
the input signal and DC. This value is expressed in decibels
relative to the RMS value of a full scale input signal.
Input Bandwidth
The input bandwidth is that input frequency at which the
amplitude of the reconstructed fundamental is reduced
by 3dB for a full scale input signal.
Aperture Delay Time
The time from when CLK reaches mid-supply to the
instant that the input signal is held by the sample and
hold circuit.
Aperture Delay Jitter
The variation in the aperture delay time from conversion
to conversion. This random variation will result in noise
when sampling an AC input. The signal to noise ratio due
to the jitter alone will be:
SNRJITTER = –20log (2π • fIN • tJITTER)
CONVERTER OPERATION
As shown in Figure 1, the LTC2226H is a CMOS pipelined
multistep converter. The converter has six pipelined ADC
stages; a sampled analog input will result in a digitized
value five cycles later (see the Timing Diagram section).
For optimal AC performance the analog inputs should be
driven differentially. For cost sensitive applications, the
analog inputs can be driven single-ended with slightly
worse harmonic distortion. The CLK input is single-ended.
The LTC2226H has two phases of operation, determined
by the state of the CLK input pin.
Each pipelined stage shown in Figure 1 contains an ADC,
a reconstruction DAC and an interstage residue amplifier.
In operation, the ADC quantizes the input to the stage and
the quantized value is subtracted from the input by the
LTC2226H
10
2226hfc
APPLICATIONS INFORMATION
DAC to produce a residue. The residue is amplified and
output by the residue amplifier. Successive stages operate
out of phase so that when the odd stages are outputting
their residue, the even stages are acquiring that residue
and vice versa.
When CLK is low, the analog input is sampled differentially
directly onto the input sample-and-hold capacitors, inside
the “Input S/H” shown in the block diagram. At the instant
that CLK transitions from low to high, the sampled input is
held. While CLK is high, the held input voltage is buffered
by the S/H amplifier which drives the first pipelined ADC
stage. The first stage acquires the output of the S/H dur-
ing this high phase of CLK. When CLK goes back low, the
first stage produces its residue which is acquired by the
second stage. At the same time, the input S/H goes back to
acquiring the analog input. When CLK goes back high, the
second stage produces its residue which is acquired by the
third stage. An identical process is repeated for the third,
fourth and fifth stages, resulting in a fifth stage residue
that is sent to the sixth stage ADC for final evaluation.
Each ADC stage following the first has additional range to
accommodate flash and amplifier offset errors. Results
from all of the ADC stages are digitally synchronized such
that the results can be properly combined in the correction
logic before being sent to the output buffer.
SAMPLE/HOLD OPERATION AND INPUT DRIVE
Sample/Hold Operation
Figure 2 shows an equivalent circuit for the LTC2226H
CMOS differential sample-and-hold. The analog inputs are
connected to the sampling capacitors (CSAMPLE) through
NMOS transistors. The capacitors shown attached to
each input (CPARASITIC) are the summation of all other
capacitance associated with each input.
During the sample phase when CLK is low, the transistors
connect the analog inputs to the sampling capacitors and
they charge to and track the differential input voltage. When
CLK transitions from low to high, the sampled input voltage
is held on the sampling capacitors. During the hold phase
when CLK is high, the sampling capacitors are disconnected
from the input and the held voltage is passed to the ADC
core for processing. As CLK transitions from high to low,
Figure 2. Equivalent Input Circuit
the inputs are reconnected to the sampling capacitors to
acquire a new sample. Since the sampling capacitors still
hold the previous sample, a charging glitch proportional
to the change in voltage between samples will be seen
at this time. If the change between the last sample and
the new sample is small, the charging glitch seen at the
input will be small. If the input change is large, such as
the change seen with input frequencies near Nyquist, then
a larger charging glitch will be seen.
Single-Ended Input
For cost sensitive applications, the analog inputs can be
driven single-ended. With a single-ended input the har-
monic distortion and INL will degrade, but the SNR and
DNL will remain unchanged. For a single-ended input, AIN+
should be driven with the input signal and AIN– should
be connected to VCM or a low noise reference voltage
between 1V and 1.5V.
Common Mode Bias
For optimal performance the analog inputs should be driven
differentially. Each input should swing ±0.5V for the 2V
range or ±0.25V for the 1V range, around a common mode
voltage of 1.5V. The VCM output pin (Pins 44, 45) may be
used to provide the common mode bias level. VCM can be
tied directly to the center tap of a transformer to set the DC
input level or as a reference level to an op amp differential
driver circuit. The VCM pins must be bypassed to ground
close to the ADC with a 2.2µF or greater capacitor.
VDD
VDD
15Ω
15Ω
CPARASITIC
1pF
CPARASITIC
1pF
CSAMPLE
4pF
CSAMPLE
4pF
LTC2226H
AIN+
AIN–
CLK
2226H F02
LTC2226H
11
2226hfc
Input Drive Impedance
As with all high performance, high speed ADCs, the dy-
namic performance of the LTC2226H can be influenced by
the input drive circuitry, particularly the second and third
harmonics. Source impedance and reactance can influence
SFDR. At the falling edge of CLK, the sample-and-hold
circuit will connect the 4pF sampling capacitor to the input
pin and start the sampling period. The sampling period
ends when CLK rises, holding the sampled input on the
sampling capacitor. Ideally the input circuitry should be
fast enough to fully charge the sampling capacitor during
the sampling period 1/(2FENCODE); however, this is not
always possible and the incomplete settling may degrade
the SFDR. The sampling glitch has been designed to be
as linear as possible to minimize the effects of incomplete
settling.
For the best performance, it is recommended to have a
source impedance of 100W or less for each input. The
source impedance should be matched for the differential
inputs. Poor matching will result in higher even order
harmonics, especially the second.
Input Drive Circuits
Figure 3 shows the LTC2226H being driven by an RF
transformer with a center tapped secondary. The secondary
center tap is DC biased with VCM, setting the ADC input
signal at its optimum DC level. Terminating on the trans-
former secondary is desirable, as this provides a common
mode path for charging glitches caused by the sample and
hold. Figure 3 shows a 1:1 turns ratio transformer. Other
turns ratios can be used if the source impedance seen
by the ADC does not exceed 100W for each ADC input.
A disadvantage of using a transformer is the loss of low
frequency response. Most small RF transformers have
poor performance at frequencies below 1MHz.
Figure 4 demonstrates the use of a differential amplifier to
convert a single ended input signal into a differential input
signal. The advantage of this method is that it provides
low frequency input response; however, the limited gain
bandwidth of most op amps will limit the SFDR at high
input frequencies.
Figure 5 shows a single-ended input circuit. The impedance
seen by the analog inputs should be matched. This circuit
is not recommended if low distortion is required.
The 25W resistors and 12pF capacitor on the analog
inputs serve two purposes: isolating the drive circuitry
from the sample-and-hold charging glitches and limiting
the wideband noise at the converter input.
APPLICATIONS INFORMATION
Figure 3. Single-Ended to Differential Conversion
Using a Transformer
Figure 4. Differential Drive with an Amplifier
Figure 5. Single-Ended Drive
25Ω
25Ω 25Ω
25Ω
0.1µF
AIN+
AIN–
12pF
2.2µF
VCM
LTC2226H
ANALOG
INPUT
0.1µF T1
1:1
T1 = MA/COM ETC1-1T
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
2226H F03
25Ω
25Ω
12pF
2.2µF
VCM
LTC2226H
2226H F04
––
++
CM
ANALOG
INPUT
HIGH SPEED
DIFFERENTIAL
AMPLIFIER AIN+
AIN–
25Ω
0.1µF
ANALOG
INPUT
VCM
AIN+
AIN–
1k
12pF
2226H F05
2.2µF
1k
25Ω
0.1µF
LTC2226H
LTC2226H
12
2226hfc
Reference Operation
Figure 6 shows the LTC2226H reference circuitry consist-
ing of a 1.5V bandgap reference, a difference amplifier and
switching and control circuit. The internal voltage reference
can be configured for two pin selectable input ranges of
2V (±1V differential) or 1V (±0.5V differential). Tying the
SENSE pin to VDD selects the 2V range; tying the SENSE
pin to VCM selects the 1V range.
The 1.5V bandgap reference serves two functions: its
output provides a DC bias point for setting the common
mode voltage of any external input circuitry; additionally,
the reference is used with a difference amplifier to gener-
ate the differential reference levels needed by the internal
ADC circuitry. An external bypass capacitor is required
for the 1.5V reference output, VCM. This provides a high
frequency low impedance path to ground for internal and
external circuitry.
The difference amplifier generates the high and low
reference for the ADC. High speed switching circuits are
connected to these outputs and they must be externally
bypassed.
Other voltage ranges in-between the pin selectable ranges
can be programmed with two external resistors as shown
in Figure 7. An external reference can be used by apply-
ing its output directly or through a resistor divider to
SENSE. It is not recommended to drive the SENSE pin
with a logic device. The SENSE pin should be tied to the
appropriate level as close to the converter as possible. If
the SENSE pin is driven externally, it should be bypassed
to ground as close to the device as possible with a 1µF
ceramic capacitor.
APPLICATIONS INFORMATION
Figure 6. Equivalent Reference Circuit
Figure 7. 1.5V Range ADC
Figure 8. CLK Drive Using an LVDS or PECL to CMOS Converter
VCM
REFH
SENSE
TIE TO VDD FOR 2V RANGE;
TIE TO VCM FOR 1V RANGE;
RANGE = 2 • VSENSE FOR
0.5V < VSENSE < 1V
1.5V
REFL
2.2µF
2.2µF
INTERNAL ADC
HIGH REFERENCE
BUFFER
0.1µF
2226H F06
LTC2226H
4Ω
DIFF AMP
1µF
1µF
INTERNAL ADC
LOW REFERENCE
1.5V BANDGAP
REFERENCE
1V 0.5V
RANGE
DETECT
AND
CONTROL
VCM
SENSE
1.5V
0.75V
2.2µF
12k
1µF
12k
2226H F07
LTC2226H
CLK
100Ω
0.1µF
4.7µF
FERRITE
BEAD
CLEAN
SUPPLY
IF LVDS USE FIN1002 OR FIN1018.
FOR PECL, USE AZ1000ELT21 OR SIMILAR
2226H F08
LTC2226H
LTC2226H
13
2226hfc
Input Range
The input range can be set based on the application.
The 2V input range will provide the best signal-to-noise
performance while maintaining excellent SFDR. The 1V
input range will have better SFDR performance, but the
SNR will degrade by 3.8dB.
Driving the Clock Input
The CLK input can be driven directly with a CMOS or TTL
level signal. A differential clock can also be used along
with a low-jitter CMOS converter before the CLK pin (see
Figure 8).
The noise performance of the LTC2226H can depend on the
clock signal quality as much as on the analog input. Any
noise present on the clock signal will result in additional
aperture jitter that will be RMS summed with the inherent
ADC aperture jitter.
Maximum and Minimum Conversion Rates
The maximum conversion rate for the LTC2226H is 25Msps.
For the ADC to operate properly, the CLK signal should
have a 50% (±5%) duty cycle. Each half cycle must have at
least 18.9ns for the ADC internal circuitry to have enough
settling time for proper operation.
An optional clock duty cycle stabilizer circuit can be used
if the input clock has a non 50% duty cycle. This circuit
uses the rising edge of the CLK pin to sample the analog
input. The falling edge of CLK is ignored and the internal
falling edge is generated by a phase-locked loop. The
input clock duty cycle can vary and the clock duty cycle
stabilizer will maintain a constant 50% internal duty cycle.
If the clock is turned off for a long period of time, the duty
cycle stabilizer circuit will require a hundred clock cycles
for the PLL to lock onto the input clock. To use the clock
duty cycle stabilizer, the MODE pin should be connected
to 1/3VDD or 2/3VDD using external resistors.
If the clock duty cycle stabilizer is used, a >1µs high pulse
should be applied to the SHDN pin once the power supplies
are stable at power up.
The lower limit of the LTC2226H sample rate is determined
by droop of the sample-and-hold circuits. The pipelined
architecture of this ADC relies on storing analog signals on
small valued capacitors. Junction leakage will discharge
the capacitors. The specified minimum operating frequency
for the LTC2226H is 1Msps.
DIGITAL OUTPUTS
Table 1 shows the relationship between the analog input
voltage, the digital data bits, and the overflow bit.
Digital Output Buffers
APPLICATIONS INFORMATION
Table 1. Output Codes vs Input Voltage
AIN+ – AIN–
(2V Range)
OF
D11 – D0
(Offset Binary)
D11 – D0
(2’s Complement)
>+1.000000V
+0.999512V
+0.999024V
1
0
0
11 11 1111 1111
11 11 1111 1111
11 11 1111 1110
0111 1111 1111
0111 1111 1111
0111 1111 1110
+0.000488V
0.000000V
–0.000488V
–0.000976V
0
0
0
0
10 00 0000 0001
10 00 0000 0000
01 11 1111 1111
01 11 1111 1110
00 00 0000 0001
00 00 0000 0000
11 11 1111 1111
11 11 1111 1110
–0.999512V
–1.000000V
<–1.000000V
0
0
1
0000 0000 0001
0000 0000 0000
0000 0000 0000
1000 0000 0001
1000 0000 0000
1000 0000 0000
Figure 9 shows an equivalent circuit for a single output
buffer. Each buffer is powered by OVDD and OGND, isolated
from the ADC power and ground. The additional
N-channel transistor in the output driver allows operation
down to low voltages. The internal resistor in series with
the output makes the output appear as 50W to external
circuitry and may eliminate the need for external damping
resistors.
LTC2226H
14
2226hfc
APPLICATIONS INFORMATION
Table 2. MODE Pin Function
MODE PIN
OUTPUT FORMAT
CLOCK DUTY
CYCLE STABILIZER
0 Offset Binary Off
1/3VDD Offset Binary On
2/3VDD 2’s Complement On
VDD 2’s Complement Off
Overflow Bit
When OF outputs a logic high the converter is either over-
ranged or underranged.
Output Driver Power
Separate output power and ground pins allow the output
drivers to be isolated from the analog circuitry. The power
supply for the digital output buffers, OVDD, should be tied
to the same power supply as for the logic being driven.
For example if the converter is driving a DSP powered
by a 1.8V supply, then OVDD should be tied to that same
1.8V supply.
As with all high speed/high resolution converters, the
digital output loading can affect the performance. The
digital outputs of the LTC2226H should drive a minimal
capacitive load to avoid possible interaction between the
digital outputs and sensitive input circuitry. The output
should be buffered with a device such as an ALVCH16373
CMOS latch. For full speed operation the capacitive load
should be kept under 10pF.
Lower OVDD voltages will also help reduce interference
from the digital outputs.
Data Format
Using the MODE pin, the LTC2226H parallel digital output
can be selected for offset binary or 2’s complement format.
Connecting MODE to GND or 1/3VDD selects offset binary
output format. Connecting MODE to 2/3VDD or VDD selects
2’s complement output format.
An external resistor divider can be used to set the 1/3VDD
or 2/3VDD logic values. Table 2 shows the logic states for
the MODE pin.
Figure 9. Digital Output Buffer
LTC2226H
2226H F09
OVDD
VDD VDD
0.1µF
43Ω TYPICAL
DATA
OUTPUT
OGND
OVDD 0.5V
TO 3.6V
PREDRIVER
LOGIC
DATA
FROM
LATCH
OE
LTC2226H
15
2226hfc
APPLICATIONS INFORMATION
OVDD can be powered with any voltage from 500mV up to
3.6V. OGND can be powered with any voltage from GND
up to 1V and must be less than OVDD. The logic outputs
will swing between OGND and OVDD.
Output Enable
The outputs may be disabled with the output enable pin,
OE. OE high disables all data outputs including OF.
Sleep and Nap Modes
The converter may be placed in shutdown or nap modes
to conserve power. Connecting SHDN to GND results in
normal operation. Connecting SHDN to VDD and OE to VDD
results in sleep mode, which powers down all circuitry
including the reference and typically dissipates 1mW. When
exiting sleep mode it will take milliseconds for the output
data to become valid because the reference capacitors
have to recharge and stabilize. Connecting SHDN to VDD
and OE to GND results in nap mode, which typically dis-
sipates 15mW. In nap mode, the on-chip reference circuit
is kept on, so that recovery from nap mode is faster than
that from sleep mode, typically taking 100 clock cycles. In
both sleep and nap modes, all digital outputs are disabled
and enter the Hi-Z state.
Grounding and Bypassing
The LTC2226H requires a printed circuit board with a clean,
unbroken ground plane. A multilayer board with an internal
ground plane is recommended. Layout for the printed
circuit board should ensure that digital and analog signal
lines are separated as much as possible. In particular, care
should be taken not to run any digital track alongside an
analog signal track or underneath the ADC.
High quality ceramic bypass capacitors should be used at
the VDD, OVDD, VCM, REFH, and REFL pins. Bypass capaci-
tors must be located as close to the pins as possible. Of
particular importance is the 0.1µF capacitor between REFH
and REFL. This capacitor should be placed as close to the
device as possible (1.5mm or less). A size 0402 ceramic
capacitor is recommended. The large 2.2µF capacitor be-
tween REFH and REFL can be somewhat further away. The
traces connecting the pins and bypass capacitors must be
kept short and should be made as wide as possible.
The LTC2226H differential inputs should run parallel and
close to each other. The input traces should be as short
as possible to minimize capacitance and to minimize
noise pickup.
LTC2226H
16
2226hfc
PACKAGE DESCRIPTION
LX Package
48-Lead Plastic LQFP (7mm × 7mm)
(Reference LTC DWG # 05-08-1760 Rev Ø)
LX48 LQFP 0907 REVØ
0° – 7°
11° – 13°
0.45 – 0.75
1.00 REF
11° – 13°
9.00 BSC
A A
7.00 BSC
1
2
7.00 BSC
9.00 BSC
48
1.60
MAX
1.35 – 1.45
0.05 – 0.150.09 – 0.20 0.50
BSC 0.17 – 0.27
GAUGE PLANE
0.25
NOTE:
1. PACKAGE DIMENSIONS CONFORM TO JEDEC #MS-026 PACKAGE OUTLINE
2. DIMENSIONS ARE IN MILLIMETERS
3. DIMENSIONS OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.25mm ON ANY SIDE, IF PRESENT
4. PIN-1 INDENTIFIER IS A MOLDED INDENTATION, 0.50mm DIAMETER
5. DRAWING IS NOT TO SCALE
SEE NOTE: 4
C0.30 – 0.50
R0.08 – 0.20
7.15 – 7.25
5.50 REF
1
2
5.50 REF
7.15 – 7.25
48
PACKAGE OUTLINE
RECOMMENDED SOLDER PAD LAYOUT
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
SECTION A – A
0.50 BSC
0.20 – 0.30
1.30 MIN
LTC2226H
17
2226hfc
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER
C 01/11 Removed Tape and Reel information from Order Information section 2
(Revision history begins at Rev C)
LTC2226H
18
2226hfc
RELATED PARTS
PART NUMBER DESCRIPTION COMMENTS
LTC1748 14-Bit, 80Msps, 5V ADC 76.3dB SNR, 90dB SFDR, 48-Pin TSSOP Package
LTC1750 14-Bit, 80Msps, 5V Wideband ADC Up to 500MHz IF Undersampling, 90dB SFDR
LT1993-2 High Speed Differential Op Amp 800MHz BW, –70dBc Distortion at 70MHz, 6dB Gain
LT1994 Low Noise, Low Distortion Fully Differential Input/Output
Amplifier/Driver
Low Distortion: –94dBc at 1MHz
LTC2202 16-Bit, 10Msps, 3.3V ADC, Lowest Noise 150mW, 81.6dB SNR, 100dB SFDR, 48-Pin QFN
LTC2208 16-Bit, 130Msps, 3.3V ADC, LVDS Outputs 1250mW, 78dB SNR, 100dB SFDR, 64-Pin QFN
LTC2220-1 12-Bit, 185Msps, 3.3V ADC, LVDS Outputs 910mW, 67.7dB SNR, 80dB SFDR, 64-Pin QFN
LTC2224 12-Bit, 135Msps, 3.3V ADC, High IF Sampling 630mW, 67.6dB SNR, 84dB SFDR, 48-Pin QFN
LTC2225 12-Bit, 10Msps, 3V ADC, Lowest Power 60mW, 71.3dB SNR, 90dB SFDR, 32-Pin QFN
LTC2226 12-Bit, 25Msps, 3V ADC, Lowest Power 75mW, 71.4dB SNR, 90dB SFDR, 32-Pin QFN
LTC2227 12-Bit, 40Msps, 3V ADC, Lowest Power 120mW, 71.4dB SNR, 90dB SFDR, 32-Pin QFN
LTC2228 12-Bit, 65Msps, 3V ADC, Lowest Power 205mW, 71.3dB SNR, 90dB SFDR, 32-Pin QFN
LTC2229 12-Bit, 80Msps, 3V ADC, Lowest Power 211mW, 70.6dB SNR, 90dB SFDR, 32-Pin QFN
LTC2236 10-Bit, 25Msps, 3V ADC, Lowest Power 75mW, 61.8dB SNR, 85dB SFDR, 32-Pin QFN
LTC2237 10-Bit, 40Msps, 3V ADC, Lowest Power 120mW, 61.8dB SNR, 85dB SFDR, 32-Pin QFN
LTC2238 10-Bit, 65Msps, 3V ADC, Lowest Power 205mW, 61.8dB SNR, 85dB SFDR, 32-Pin QFN
LTC2239 10-Bit, 80Msps, 3V ADC, Lowest Power 211mW, 61.6dB SNR, 85dB SFDR, 32-Pin QFN
LTC2245 14-Bit, 10Msps, 3V ADC, Lowest Power 60mW, 74.4dB SNR, 90dB SFDR, 32-Pin QFN
LTC2246 14-Bit, 25Msps, 3V ADC, Lowest Power 75mW, 74.5dB SNR, 90dB SFDR, 32-Pin QFN
LTC2247 14-Bit, 40Msps, 3V ADC, Lowest Power 120mW, 74.4dB SNR, 90dB SFDR, 32-Pin QFN
LTC2248 14-Bit, 65Msps, 3V ADC, Lowest Power 205mW, 74.3dB SNR, 90dB SFDR, 32-Pin QFN
LTC2249 14-Bit, 80Msps, 3V ADC, Lowest Power 222mW, 73dB SNR, 90dB SFDR, 32-Pin QFN
LTC2250 10-Bit, 105Msps, 3V ADC, Lowest Power 320mW, 61.6dB SNR, 85dB SFDR, 32-Pin QFN
LTC2251 10-Bit, 125Msps, 3V ADC, Lowest Power 395mW, 61.6dB SNR, 85dB SFDR, 32-Pin QFN
LTC2252 12-Bit, 105Msps, 3V ADC, Lowest Power 320mW, 70.2dB SNR, 88dB SFDR, 32-Pin QFN
LTC2253 12-Bit, 125Msps, 3V ADC, Lowest Power 395mW, 70.2dB SNR, 88dB SFDR, 32-Pin QFN
LTC2254 14-Bit, 105Msps, 3V ADC, Lowest Power 320mW, 72.4dB SNR, 88dB SFDR, 32-Pin QFN
LTC2255 14-Bit, 125Msps, 3V ADC, Lowest Power 395mW, 72.5dB SNR, 88dB SFDR, 32-Pin QFN
LTC2284 14-Bit, Dual, 105Msps, 3V ADC, Low Crosstalk 540mW, 72.4dB SNR, 88dB SFDR, 64-Pin QFN
LT5512 DC-3GHz High Signal Level Downconverting Mixer DC to 3GHz, 21dBm IIP3, Integrated LO Buffer
LT5514 Ultralow Distortion IF Amplifier/ADC Driver
with Digitally Controlled Gain
450MHz to 1dB BW, 47dB OIP3, Digital Gain Control
10.5dB to 33dB in 1.5dB/Step
LT5515 1.5GHz to 2.5GHz Direct Conversion Quadrature Demodulator High IIP3: 20dBm at 1.9GHz,
LT5516 800MHz to 1.5GHz Direct Conversion Quadrature Demodulator High IIP3: 21.5dBm at 900MHz,
LT5517 40MHz to 900MHz Direct Conversion Quadrature Demodulator High IIP3: 21dBm at 800MHz,
LT5522 600MHz to 2.7GHz High Linearity Downconverting Mixer 4.5V to 5.25V Supply, 25dBm IIP3 at 900MHz,
NF = 12.5dB, 50W Single-Ended RF and LO Ports
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com
LINEAR TECHNOLOGY CORPORATION 2007
LT 0111 REV C • PRINTED IN USA
