D1U54P-W-450-12-HxxC Series
54mm 1U Front End AC-DC
Power Supply Converter
D1U54P-W-450-12-HXXC.A04
Page 4 of
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STATUS AND CONTROL SIGNALS
Signal Name
Description Interface Details
INPUT_OK (AC Source)
Link to connector pin
The signal output is driven high when input source is available and within acceptable limits. The
output is driven low to indicate loss of input power.
There is a minimum of 1ms pre-warning time before the signal is driven low prior to the PWR_OK
signal going low. The power supply must ensure that this interface signal provides accurate status
when AC power is lost.
Pulled up internally via 10K to VDD*.
A logic high >2.0Vdc
A logic low <0.8Vdc
Driven low by internal CMOS buffer
(open drain output).
PW_OK (Output OK)
Link to connector pin
The signal is asserted, driven high, by the power supply to indicate that the main output is valid.
Should a main output or standby output fault occur, the PW_OK signal will de-assert + driven low.
& 3.3V Standby output products do not de-assert the PW_OK signal during OCP event on the
output.
PW_OK output is driven low to indicate that the Main output is outside of lower limit of regulation.
Pulled up internally via 10K to VDD*.
A logic high >2.0Vdc
A logic low <0.8Vdc
Driven low by internal CMOS buffer
(open drain output).
SMB_ALERT
(FAULT/WARNING)
Link to connector pin
The signal output is driven low to indicate that the power supply has detected a warning or fault and
is intended to alert the system. This output must be driven high when the power is operating
correctly (within specified limits).
The signal will revert to a high level when the warning/fault stimulus (that caused the alert) is
removed. As reported by PMBus Status_x Registers, with exception of Status_CML.
Pulled up internally via 10K to VDD*.
A logic high >2.0Vdc
A logic low <0.8Vdc
Driven low by internal CMOS buffer
(Power Supply Absent)
The signal is used to detect the presence (installation) of a PSU by the host system. The signal is
connected to PSU logic +VSB_Return within the power module.
Passive connection to +VSB_Return.
A logic low <0.8Vdc
PS_ON
(Power Supply
Enable/Disable
Link to connector pin
This signal is pulled up internally to the internal housekeeping supply (within the power supply). The
power supply main 12Vdc output will be enabled when this signal is pulled low to +VSB_Return.
In the low state the signal input shall not source more than 1mA of current. The 12Vdc output will be
disabled when the input is driven higher than 2.4V, or open circuited. Cycling this signal shall clear
latched fault conditions.
Pulled up internally via 10K to VDD*.
A logic high >2.0Vdc
A logic low <0.8Vdc
Input is via CMOS Schmitt trigger
PS_KILL
Link to connector pin
This signal is used during hot swap to disable the main output during hot swap extraction. The input i
pulled up internally to VDD* (within the power supply).
The signal is provided on a short (lagging pin) and should be connected to +VSB_Return.
Pulled up internally via 10K to VDD*.
A logic high >2.0Vdc
A logic low <0.8Vdc
Input is via CMOS Schmitt trigger
ADDR (Address Select)
Link to connector pin
An analog input that is used to set the address of the internal slave devices (EEPROM and
microprocessor) used for digital communications.
Connection of a suitable resistor to +VSB_Return, in conjunction with an internal resistor divider
chain, will configure the required address. See configuraiton table for details.
DC voltage between the limits of 0 and
+3.3Vdc.
SCL (Serial Clock)
Link to connector pin
A serial clock line compatible with PMBusTM Power Systems Management Protocol Part 1 – General
Requirements Rev 1.1.
No additional internal capacitance is added that would affect the speed of the bus.
The signal is provided with a series isolator device to disconnect the internal power supply bus in the
event that the power module is unpowered,
** VIL is 0.8V maximum
VOL is 0.4V maximum when sinking
3mA
VIH is 2.1V minimum
SDA (Serial Data)
Link to connector pin
A serial data line compatible with PMBusTM Power Systems Management Protocol Part 1 – General
Requirements Rev 1.1.
The signal is provided with a series isolator device to disconnect the internal power supply bus in the
event that the power module is unpowered,
IL
VOL is 0.4V maximum when sinking
3mA
VIH is 2.1V minimum
V1_SENSE
V1SENSE_RTN
Remote sense connections intended to be connected at and sense the voltage at the point of load.
The voltage sense will interact with the internal module regulation loop to compensate for voltage
drops due to connection resistance between the output connector and the load.
If remote sense compensation is not required then the voltage can be configured for local sense
by:
1. V1_SENSE directly connected to power gold fingers P1-P8 (inclusive)
2. V1_SENSE_RTN directly connected to gold fingers P9 to P16 (inclusive)
Compensation for a up to 0.12Vdc
total connection drop (output and
return connections).
ISHARE
Link to connector pin
-
Bus
The current sharing signal is connected between sharing units (forming an ISHARE bus). It is an
input and/or an output (bi-directional analog bus) as the voltage on the line controls the current
share between sharing units.
A power supply will respond to a change in this voltage but a power supply can also change the
voltage depending on the load drawn from it.
On a single unit the voltage on the pin (and the common ISHARE bus would read 8VDC at 100%
load (module capability). For two identical units sharing the same 100% load this would read
Analogue voltage:
+8V maximum; 10K to +12V_RTN
*VDD is an internal voltage rail derived from VSB and an internal housekeeping rail (“diode ORed”) and is compatible with the voltage tolerances of VSB).
**For robust PMBus communications, it is recommended SDA and SCA lines be pulled up via external resistors to a voltage of 3.3V or greater.