AT7908EJLSB - Atmel Corporation

4268B–AERO–10/04

Features

•Designed in Accordance with CAN Specification 2.0B

•CAN 2.0B Protocol Functions

•4 Different Data Rates Using an Internal Programmable Prescaler

– 1 Mbit/s, 500 kbit/s, 250 kbit/s, 125 kbit/s

•16 MHz Cycle Frequency

•Power-down: Sleep Mode

•CAN Bus Line Arbitration

•All Required CAN Functions:

•Error Handling:

– Stuff Bit Generation

– CRC Generation

– Acknowledge Generation

– Remote Frame

•1 TX Buffer and 3 RX Buffer

•3 Individual Acceptance Filtering

•Interrupt Outputs Can be Generated for the Following Events

– Telegram Sent Successfully

– Telegram Received Successfully

– Receive Buffer Overflow

– Bus Off Condition

– Error Passive Condition

•Technology: Atmel MG2RTP Radiation Hardened Sea of Gate 0.5 um

•Type: Semi-Custom Digital 5V

•Operating Frequency: 16 MHz (Test Frequency is 10MHz)

•Maximum Frequency: 18 MHz

•No Single Event Latch-up below a LET Threshold of 80 MeV/mg/cm2

•Tested up to a Total Dose of 300 Krads(si) According to MIL STD 883 Method 1019

•QML-Q and V with SMD 5962-03A06

•Package: MLCC 44 pins

Description

The AT7908 E is a CAN contr oller stand-alone device f or space ap plication . Redun-

dant structures and special techniques are implemented in order to make the device

SEU tolerant. The AT7908E CAN core provides all CAN 2.0B protocol functions

except the ov erload frame gen eration. It include s the acceptance filtering. The c ore

incorporates error-handling capabilities, the stuff bit generation, CRC, multiple sample

points and remote frame generation. The AT7908E provides a programmable MCU 8-

bit general-purpose interface to connect receive and tr ansmit buffer, c ontrol register

and status register to CPU.

The AT7908E was designed by Aurelia Microelettronica S.p.A., Italy, and the chip is

known as CASA (CAN ASIC for Space Application).

CAN Controller

for Space

Application

AT7908E

2AT7908E 4268B–AERO–10/04

Signal Pins Description

Note: Abbreviations: O = output, I = input, IO = bi-directional I/O, AL = Active Low, AH = Active

High.

Pin Number Signal

Name Type Note Description

9 Mode I - CMOS Interface operational mode

8 Cs I - CMOS AH Chip select signal

11 Wr I - CMOS AL Write signal

13 Rd I - CMOS AL Read signal

10 ALE I - CMOS AH Address latch enable

23 Xtalin I - CMOS In put to internal oscillators or clock

input from external oscillator

22 Xtalout IO - CMOS Output from internal oscillator

16 Reset I - CMOS AL reset signal

5, 4, 3, 2, 44, 43,

42, 41 addr<7:0> I - CMOS Input address(mode1) or output

address(mode 0)

38, 37, 36, 35, 33,

32, 31, 30 Data<7: 0> IO - CMOS Address data bus

25 Int O - CMOS AL interrupt request

27 Can_tx O - CMOS tx signal

19 Can_rx I - CMOS rx signal

14 sena I - CMOS AH scan enable

15 test I - CMOS AH input signal to increase testability

26 hatrig O - CMOS AH Output signal to trigger the message

matching

20 hasync O - CMOS AH Output synchronization signal

AT7908E

4268B–AERO–10/04

Oscillator Xtalin and Xtalout are IOs of an internal inverting oscillator. To use the internal oscillator,

the quartz must be connected between Xtalin and Xtalout pins.

To dr ive th e dev ice with an e xterna l cl ock sour ce, X tali n mus t be driv en by cl ock s igna l

and Xtalout must be le ft un conn ected. The maxi mum oper ati ng frequ enc y of the os ci lla-

tor, in open-loop mode(without crystal) with 6 pF load on Xtalout at worst co ndition

(Process slow, temperature = 145°C, Power supply = 4.5V ) is 60 MHz.

The IO level of Xtalin and Xtalout are CMOS levels.

The inte rnal cl oc k c ou ld be p ut on off c on di tion wit h ex ter na l p ins S ENA = lo gic al valu e

1 and TEST = logical value 0.

Reset Specification The reset pin must be driven low for at least 3 clock cycles ( 190 ns at 16 MHz).

The reset signal must be driven low at power on of the AT7908E for at least 200 ns to

avoid abnormal start condition of the AT7908E device.

4AT7908E 4268B–AERO–10/04

Electrical Characteristics

DC Characteristic s

Specified at VDD = +5V +/– 10%

Note: 1. According to the following buffers: BOUT6, BIOC6 @ VDD = 4.5V

Absolute Maximum Ratings

Ambient temperature under bias (TA)... Military –55 to +125°C

Junction temperature .....................................................175°C

Storage temperature .........................................–65 to +150°C

Power Dissipation: ..........................................0.3W

Themal Resistance Junction to Case: ...........5.1°C/W

TTL/CMOS :

Supply voltage ........................................... VDD –0.5V to +6V

I/O voltage ............................................. –0.5V to VDD + 0.5V

*NOTICE: Stresses above those listed may cause perma-

nent damages to the device. Exposure to abso-

lute maximum rating conditions for extended

period may affect device reliabili ty.

Symbol Parameter Min Typ Max Unit Conditions

VIL Input LOW voltage

CMOS input 0 0.3VDD V

VIH Input HIGH voltage

CMOS input 0.7VDD VDD V

VOL Output LOW voltage

CMOS Output 0.4 V IOL = +6 mA (1)

VOH Output HIGH voltage

CMOS Output 3.9 V IOH = -6 mA (1)

IL Input Leakage current

NO Pull up/down +/- 1 +/- 5 µA

IOZ 3-State Output Leakage current +/-1 +/-5 µA

IOS Output Short circuit current

IOSN

IOSP 24

18 mA

BOUT6

VOUT = 4.5V

VOUT = VSS

AT7908E

4268B–AERO–10/04

AC Characteristic s

Tj = 125 °C, Process typical (all values in ns)

Power Consumption

Technology MG2RTP 0.5 µm 3 Metal Layers Sea of Gate.

Matrix: MG2 –044: 33K usable gates.

Package: MLCC_J44: Ceramic Multi layer Package

Application The cor e arc hitec ture h as b een i mple mented t aking i nto a cco unt th e ty pica l co nstrai nts

of a space application:

• No Single Event Latch-up below a LET Threshold of 80 MeV/mg/cm2

• Tested up to a Total Dose of 300 Krads(si) According to MIL STD 883 Method 1019

• Design using the SEU hardened flip flops

• Sleep mode for low power consumption

• Insertion of test structures (internal scan chain) to reach a fault coverage > 95%

according to ESA specification

Output Signals Buffer Description Load Tp

Xt a lin to Output High Tp

Xtalin to Output Low Set Up

or Ho ld

Can_tx

Int

Hasync

Hatrig

BOUT6: Output buffer with 6

mA drive 75 pF

26 19

Set u p Da ta < 7 :0>/Ale

Hold Data<7:0>/Al e BIOC6: Bi-directional Buffer

CMOS input 75 pF 5

Parameter Max Min Note

DC Curent

Dissipation 50 mA @ 5V - CLK frequency = 16 MHz

6AT7908E 4268B–AERO–10/04

Functional

Description The AT7908E i s an integ rated device tha t perfor ms seri al commun icati ons acco rdin g to

the CAN protocol. The CAN protocol uses a multi-master bus configuration to transfer

data packets between nodes on a network. It supports both, standard and extended,

message frame formats as CAN Specification 2.0B. It can transmit and receive with 29

identifier bits and it can filter the first eleven bits of the receiving message (the filtering

function is performed only on eleven bits).

The AT790 8E has one tra nsmit buffer and three receivi ng buffers. T he filtering function

is individual for every RX message buffer. Every RX message buffer is formed by an

identifier (29 bits long), by the data and by the status register that store the status of the

receiver buffer. The identifier per mits to filter the rec eiving message to gether with the

global mask that implements the don’t care condition. A message is accepted and

stored in the RX mes sage buffer only if the identifier of the incoming message (first

eleven bits) matches the identifier in the RX message buffer. If the receiving message

matches more than one identifier, the message is stored in the lowest numbered mes-

sage buffer .

The AT7908E implements a global acceptance-masking feature for the message

filtering.

The AT7908E was developed to have a programmable general-purpose MCU interface.

The MCU inte rface per mits to progr am the in ternal re giste r of the AT79 08E and to read

out the status of the controller and the received messages. The schematic representa-

tion of the AT7908E is shown in Fig. 1.

Figure 1. Block Schematic of AT7908E

To transmit a CAN m essage , the MC U must write in the int erface interna l regis ters th e

data and the configuration signals. The message bus (0 to 101) goes to can_tx that

generates the output signal to the transceiver can_tx and the signals for crc_calculator

and for error_counters.

The crc_calculator block calculates the CRC on the received message and, if the CAN

is in Transmission State, sends the CRC to can_tx. If the CAN is rec eiving the me s-

sage, the CRC is sent to can_rx (CRC<0:14>) that checks if the calculated CRC

matches the received CRC.

CAN

Transmitter

can_tx

CRC

Calculator

crc_calculator

CAN

Receiver

can_rx

Error

Counters

error counters

Synchronizer

Stuff

Handler

Error_frame_gen

Mode s ena t est

MCU

INTERFACE

ALE

addr<7:0>

data_add<7

:0>

XTALIN

reset

xtalout

int

cantx canrx hatrig hasync

AT7908E

4268B–AERO–10/04

The error_counters block is a counter that receives signals from can_tx and can_rx to

calculate the error state of th e CAN. If the number of er rors is highe r than 127 , the

AT7908E will be on the erro r passive state. If error counters is higher than 255, the

AT7908E will be on the bus-off state.

The synchronizer block synchronizes the controller with the can_rx incoming signal

and generates the internal clock and reset signals for the other blocks of the controller.

The stuff handler block handles the stuff bit generation, compliant with the standard

BOSCH 2.0 B specific ation. error_frame_gen block g enerates the err or frame on the

bus.

In the next sections, the interface block, the internal registers and the operational modes

of the AT7908E will be described.

Transmission of Message To tra nsmit a mes sage on the bus, the c ontro ller m ust p rogr am the con figurati on re gis-

ters of the AT7908E (interrupt generator configuration, data rate, bit timing

configuration , message len gth) and the transmit b uffer. After this, the controller must

write i n the intern al regi ster t he bi t (Tx req=1) to sta rt th e tr ansmis sion. A t thi s point, the

Transmit message buffer is sent to the bus line. At every moment the external MCU can

readout the status of the controller (error condition, bus-off condition, transmission

active or transmission OK).

Incoming Message The inc omin g mess age pa sses th rough the glo bal ma sk a nd is checke d with th e iden ti-

fier of the first receiver message buffer. If the message is accepted, the data will be

stored in th e firs t me ss ag e bu ffer and the sta tus of th e r eceiv er me ssage objec ts will b e

updated with the infor mati on o f the recei ved m essa ge: l ength of messag e, ex tend ed or

standar d fram e messag e, rec eptio n OK or over run cond ition . The in coming mess age is

stored in the message buffer at the end of the END of FRAME field (7 recessive bits).

If the inc oming m es sa ge is a r emo te fram e r equ est fr om anot her CAN nod e, the incom-

ing remote request will not be stored on the RX message buffer.

Remote Frame The AT79 08E support s remote frame features. To send on the bus a remote fr ame

request, the MCU must write two internal bits of SETUP register (TMRMR=1 and

TXRM=0). The arbitration registers of the transmitter message buffer must have the

identifier for the remote frame request. The start of the remote frame request will be per-

formed when the transmission request is set by the MCU on the AT7908E. The

AT790 8E that re ceives a RE MOTE FR AME reque st (RTR bit = recess ive) that ma tches

the id entifie r stored on own TX_arb itrati on registe r (filter ing func tionalit y with don’ t care

feature) send on the bus the TX message buffer as an answer to the remote frame

request. To answer the remote frame request, the AT7908E must be pre-programmed

with two bits of the internal registe r: TMRMR=0 and TX RM=1. The TX arbitr ation regis-

ter must be initialized with the message identifier to which to answer and the transmitter

data bu ffer mu st be load ed with the data to be sent as the answ er to the r emote fr ame

request. The transmission request must be set as:

Answer to remote request if

for i = 28 down to 18

(“MsgID(i)” XOR” TX_arbitration (i) )AND “Accept. Mask(i)” = 0

Filterin g of Messag e The filtering func tion is implemented with a glob al mask and the arbitratio n register of

the receiver message buffers. The Global Mask permits to define the don’t care bit on

the filtering operation. The incoming message ID (msg_ID(28:18) is checked (xor) with

8AT7908E 4268B–AERO–10/04

the identifie r stored in the message buffers ( RXn_ARB0, RXn_ARB1) . The result is

masker able (logic AND operation) with global mask (FILTER_AM_0, FILTER_AM_1).

Message Valid if

for i = 28 downto 18

(“MsgID(i)” XOR” RXn_arbitration (i) )AND “Accept. Mask(i)” = 0

If the inco mi ng m es sage i s f il tered o ut fr om the firs t me ss ag e bu ffer , th e arbi tr ation fi el d

of the incoming messag e is checked with the i dentifier of the second message b uffer,

and if filtered out, with the identifier of the third message buffer. The global mask feature

(used to a ccept a se t o f incom ing mess ages ) p ermits that the i ncom ing messag e could

match wi th all the three- messag es buffers but the received message is stored on the

lowest numbered message buffer .

Interrupt Generation The interrupt generation on the INT pin can be programmed by the external MCU writing

the internal configuration register. Interrupt can be generated for:

• Either message correctly transmitted

• Or message correctly received ( data frame, not remote frame reception).

• Or overrun condition on the rx message buffer

• Or bus-off condition

• Or error passive condition

In the SETUP register, it is possible to configure which kind of interrupt will be generated

by the AT7908E device.

Fault Confinement and Error

Counters The two internal error counters are readable from the external MCU to check the error

status of th e CAN c ont roll er . The er ror cou nter op er ates ac co rd in g to the Fault Confine-

ment rules of the CAN Specification 2.0B, exception included. This means that if there is

only one node of the AT7908E connected on the BUS and this node starts to transmit

message, it meets the error passive condition but not the bus-off condition, because the

transmitte r erro r counte r wil l no long er be increme nted fo r ackno wledge error when i t is

in error passive state.

Trigger Match Function The trigger match function is a feature implemented to generate the HATRIG signal (a

pulse for a clock cycle) if the Identifier of the incoming message matches the

TRIG GER_M ATCH regi ster va lue. The in comin g mess age iden tifier( msg_id2 8 down to

msg_id18) is checked with the TM28 down to the TM18 bits of the TRIGGER_MATCH

regist ers. Thi s functio n is in depende nt from the filtrat ion of mes sage and from the i nter-

rupt generation. The HATRIG signal, together with the CAN node, regularly generating

the appropriate frame, could be used to force the bus switching in a system with two

physical bus used as nominal and redundant.

AT7908E

4268B–AERO–10/04

Detailed Pin Description

Internal Register

Description

MODE

Input pin to select the operational mode of the interface:

mode = 0 : 8 bits of the data bus multiplexed with the lowest 8 bits of the address(register mapped between

8000Hex and 804Chex)

mode = 1 : 8 bits not multiplexed with the address data bus ( register mapped between 00 Hex and 4C Hex)

CS Chip select pin to write or read the internal register. A high level on this pin enables the CPU to access the

AT7908E.

WR Pin to write the internal register. A low level on this pin enables the writing of the AT7908E register (if CS signal is

HIGH).

RD Pin to read the internal register . A low level on this pin enables the readout of the AT7908E register (if CS signal is

HIGH).

ALE Address-latch-enable. Used in mode=0.

XTALIN Input pin for the clock. XTA LIN, with XTALOUT, are the crystal connections for the internal oscillator.

XTALOUT Input output pin. This pin could be used as the input, together with XTALIN, for the internal oscillator or as the

clock output to drive the CPU.

RESET Reset signal for the AT7908E. To reset the AT7908E, this signal must be set low.

DATA<7:0> Bi-directional bus: Multiplexed data/address bus in the mode 0 or data bus in the mode1.

ADDR<7:0> Highest input address in the mode0 or lowest input address in the mode 1.

INT Output pin for the interrupt request to the MCU. This pin is active low (interrupt generation) and will be kept low

until the MCU clears the interrupt request on AT7908E.

CAN_TX Serial output pin to the CAN transceiver (dominant=‘0’, recessive=‘1’)

CAN_RX Serial input from the CAN transceiver (dominant=‘0’, recessive=‘1’ ).

SENA Input signal to enable the scan-test (with test = 1) or to put the AT7908E on power down mode (with test signal =

0). To use the AT7908E in normal functional mode, thi s signal must be logical 0.

TEST

Input signal to increase the testability. This pin will be used in the test modality. Test = 1 => test mode (used by the

manufacturer that executes the test of the device. Test = 0 => functional mode ( if SENA =0) or power down

mode ( if SENA =1).

HATRIG

Output signal that will be set high (duration of the pulse = 13 clock cycles) if the received message arbi tr ati on

matches the TRIGGER_MATCH register (independently from the matching between the arbitration of the

incoming message and the identifier of the message buffers). This pin could be used for the bus switching in a

system with two physical buses (nom inal and redundant).

HASYNC Output signal that could be used to advise that the node started to transmit a message or started to receive a

message (duration of the pulse = 13 clock cycles).

Type

R = read

R/W =

read/write Address

Hex Register function ( bit7… bit0)

SETUP_0 R/W 00 BPR1 BPR0 Gensync

Tx Gensync

Rx Errint Overint Rxint Txint

SETUP_1 R/W 01 Disabled TXRM TXEM TMRMR TXDLC3 TXDLC1 TXDLC1 TXDLC0

SETUP_2 R/W 02 PS2_3 PS2_2 PS2_1 PS2_0 PS1_3 PS1_2 PS1_1 PS1_0

SETUP_3 R/W 03 RxClr Reset IntClr AbortTx Txreq RSJ2 RSJ1 RSJ0

SETUP_RX R/W 04 reserved reserved reserved Reserved reserved Rxclr3 Rxclr2 Rxclr1

10 AT7908E 4268B–AERO–10/04

STATUS R 05 SyncTx SyncRx Rxbuf1 Rxbuf0 TxOK TxActive ErrPass BusOff

STATUS_RX R 06 reserved Rxovr3 Rxovr2 Rxovr1 reserved RXOK3 RXOK2 RXOK1

FILTER_AM_0 R/W 07 Filter Mask: AM28:AM21

FILTER_AM_1 R/W 08 Filter Mask: AM20:AM18 & 3 reserved bit

ERR_COUNT_TX R 09 Transmitter error counter

ERR_COUNT_RX R 0A Receiver error counter

TRIG_MATCH_0 R/W 0B Trigger match register TM28..TM21

TRIG_MATCH_1 R/W 0 C Trigger match register TM20, TM19, TM18 & 5 reserved bit

TX_ARB_0 R/W 10 Tx Arbitration register – T XARB28:TXARB21

TX_ARB_1 R/W 11 Tx Arbitration register – T XARB20:TXARB13

TX_ARB_2 R/W 12 Tx Arbitration register – T XARB12:TXARB5

TX_ARB_3 R/W 13 Tx Arbitration register - TXARB4: TXARB0 & 3 re served bit

TX_MESSAGE_0 R/W 14 Tx Data byte 0

TX_MESSAGE_1 R/W 15 Tx Data byte 1

TX_MESSAGE_2 R/W 16 Tx Data byte 2

TX_MESSAGE_3 R/W 17 Tx Data byte 3

TX_MESSAGE_4 R/W 18 Tx Data byte 4

TX_MESSAGE_5 R/W 19 Tx Data byte 5

TX_MESSAGE_6 R/W 1A Tx Data byte 6

TX_MESSAGE_7 R/W 1B Tx Data byte 7

RX1_ARB_0 R/W 20 Rx1 buffer Arbi tration register – RX1ARB28:RX1ARB21

RX1_ARB_1 R/W 21 Rx1 buffer Arbi tration register – RX1ARB20:RX1ARB13

RX1_ARB_2 R 22 Rx1 buffer Arbit ration register – RX1ARB12:RX1ARB5

RX1_ARB_3 R 23 Rx1 bu ffer Arbitrati on register- RX1ARB4:RX1ARB0 & 3 reserved bit

RX1_MESSAGE_0 R 24 Rx1 buffer Data byte 0

RX1_MESSAGE_1 R 25 Rx1 buffer Data byte 1

RX1_MESSAGE_2 R 26 Rx1 buffer Data byte 2

RX1_MESSAGE_3 R 27 Rx1 buffer Data byte 3

RX1_MESSAGE_4 R 28 Rx1 buffer Data byte 4

RX1_MESSAGE_5 R 29 Rx1 buffer Data byte 5

RX1_MESSAGE_6 R 2A Rx1 buffer Data byte 6

RX1_MESSAGE_7 R 2B Rx1 buffer Data byte 7

RX1_STATUS R2C

RX1

reserved RX1

Extfr Rx1

DLC3 Rx1

DLC2 Rx1

DLC1 Rx1

DLC0

RX2_ARB_0 R/W 30 Rx2 buffer Arbi tration register – RX2ARB28:RX2ARB21

RX2_ARB_1 R/W 31 Rx2 buffer Arbi tration register – RX2ARB20:RX2ARB13

RX2_ARB_2 R 32 Rx2 buffer Arbit ration register – RX2ARB12:RX2ARB5

RX2_ARB_3 R 33 Rx2 buffer Arbit ration register- RX2ARB4: RX2ARB0 & 3 reserved bit

RX2_MESSAGE_0 R 34 Rx2 buffer Data byte 0

RX2_MESSAGE_1 R 35 Rx2 buffer Data byte 1

RX2_MESSAGE_2 R 36 Rx2 buffer Data byte 2

RX2_MESSAGE_3 R 37 Rx2 buffer Data byte 3

RX2_MESSAGE_4 R 38 Rx2 buffer Data byte 4

AT7908E

4268B–AERO–10/04

Setup Registers The five 8 bits SETUP regis ters are used to set sp ecific CAN conf igurations . The 5 bits

shown in grey on SETUP_3 regi ster and the 3 bits on SETU P_RX register are not writ-

ten directly inside the interface but are used to perform reset or other actions.

SETUP_0 : Txint: active high, the AT7908E genera tes the in ter rupt on t he INT li ne af ter a succ ess-

ful transmission.

Rxint: active high, the AT7908E generates one interrupt on the INT line after a success-

ful data frame reception.

Overint: active high, the AT7908E generates the interrupt on the INT line if the receiver

buffer (number n) has not been cleared(with RxClr) before the next valid mes sage for

the same receiver buffer.

Errint: active high, the AT7908E generates the interrupt on the INT line if there’s an

error condition on the CAN Controller (bus-off or error-passive).

GensyncRx: the AT7908E generates a pulse on the hasync output signal when a

receiving message is detected.

GensyncTx: the AT7908E gener ates a pu lse o n the hasync outpu t sig nal w hen a sync

pulse on the transmitting message is detected.

BPR0-BPR1: 2 bits to program the CAN clock pre-scaler (4 different system clocks of

the CAN Core ). In the next ta ble, it is poss ible to see the di fferent va lues of the sys tem

clock depending on the bits BPR0 and BPR1.

RX2_MESSAGE_5 R 39 Rx2 buffer Data byte 5

RX2_MESSAGE_6 R 3A Rx2 buffer Data byte 6

RX2_MESSAGE_7 R 3B Rx2 buffer Data byte 7

RX2_STATUS R3C

RX2

reserved RX3

Reserved RX2

Extfr Rx2

DLC3 Rx2

DLC2 Rx2

DLC1 Rx2

DLC0

RX3_ARB_0 R/W 40 Rx3 buffer Arbi tration register – RX3ARB28:RX3ARB21

RX3_ARB_1 R/W 41 Rx3 buffer Arbi tration register – RX3ARB20:RX3ARB13

RX3_ARB_2 R 42 Rx3 buffer Arbit ration register – RX3ARB12:RX3ARB5

RX3_ARB_3 R 43 Rx3 bu ffer Arbitrati on register- RX3ARB4:RX3ARB0 & 3 reserved bit

RX3_MESSAGE_0 R 44 Rx3 buffer Data byte 0

RX3_MESSAGE_1 R 45 Rx3 buffer Data byte 1

RX3_MESSAGE_2 R 46 Rx3 buffer Data byte 2

RX3_MESSAGE_3 R 47 Rx3 buffer Data byte 3

RX3_MESSAGE_4 R 48 Rx3 buffer Data byte 4

RX3_MESSAGE_5 R 49 Rx3 buffer Data byte 5

RX3_MESSAGE_6 R 4A Rx3 buffer Data byte 6

RX3_MESSAGE_7 R 4B Rx3 buffer Data byte 7

RX3_STATUS R4C

RX3

reserved RX3

Extfr Rx3

DLC3 Rx3

DLC2 Rx3

DLC1 Rx3

DLC0

12 AT7908E 4268B–AERO–10/04

SETUP_1: TXDLC<3:0>: length of the transmitted message.

TMRMR: Active High, establishes if the transmitted message is a remote frame (if

TXRM=0).

TXEM: active high, it establishes if the transmitted message is an extended frame.

TXRM: Active high, it establishes if the controller answers to the remote frame request

(if TMRMR=0).

Disabled: active high, by setting this bit, the CAN controller is disabled and discon-

nected from the bus . T his co nditio n cou ld be used to s et the other regis ters s afely . The

error counter values, when this bit is active, will be frozen at the last value.

SETUP_2: PS1_3 … PS1_0: these 4 bits are the phase segment length 1 (acceptable value 1:15).

The default value of this register (value after reset) is 9 decimal.

PS2_3 … PS2_0: these 4 bits are the phase segment length 2 (acceptable value 1:8).

The default value of this register (value after reset) is 5 decimal.

SETUP_3 : RSJ_2 … RS J_0 : 3 bi ts for the r e-sync hron iz ati on jum p ( correc t v al ue 1:4). T h e de fault

value is 2.

Txreq: when this bi t is se t hi gh, th e A T7 908 E s end s o n the CAN b us the m es sage c on-

tained in the TX buffer. This bit must be written from the MCU to start the transmission.

AbortTx: this bit must be set to inform the interface that the transmission request has to

be aborted. The error counter values are not reset when this bit is set.

IntClr: this bit resets the INT si gnal of the device and clears th e SyncTx and SyncRx

bits of the STATUS register.

Reset: acti ve hi gh, th is s ignal m ust b e se t to r eset the CAN con troller. The error c ondi-

tion is cleared and also the counter values.

RxClr: active high, this bit is set to clear all RXOKn and RXOVRn bits on the status reg-

ister of the receiver message buffers (STATUS_RX).

SETUP_RX Register RxClr3: active high, this bit is set to clear the RXOK3 and RXOVR3 bits on the status

read out op eration of the rec eived message oth erwise, at the next reception on th e

same RX message buffer, an overrun cond iti on is raised .

RxClr2: active high, this bit is set to clear the RXOK2 and RXOVR2 bits on the status

tion of the received message otherwise, at the next reception on the same RX message

buffer, an overrun condition is raised.

BPR0 BPR1 System clock frequency

00f

osc

01f

osc/2

10f

osc/4

11f

osc/8

AT7908E

4268B–AERO–10/04

RxClr1: active high, this bit is set to clear the RXOK1 and RXOVR1 bits on the status

tion of the received message otherwise, at the next reception on the same RX message

buffer, an overrun condition is raised.

Status Register s

STATUS_0 BusOff: this bit indicates that the CAN controller has reached a bus off condition.

ErrPass: this bit indicates that the CAN controller has reached an error passive

condition.

TxActive: this bit signals that there is an active transmission.

TxOK: this bit indicates that the transmission has been successfully terminated. This bit

is reset automatically when the TXREQ bit on the SETUP_3 register is set.

Rxbuf1:Rxbuf0: these bits indicate which receiver buffer received a message:

00 : mes sage fil ter ed out

01 : mes sage re ce iv ed by RX1 buffer

10 : mes sage re ce iv ed by RX2 buffer

11 : mes sage re ce iv ed by RX3 buffer

SyncRx: this bit indicates that a pulse on the sync bit of the received message has been

generated.

SyncTx: this bit indicates that a pulse on the sync bit of the transmitted message has

been generated.

STATUS_RX: RXOVR3: This bit indicates an overrun condition (a new message received on the mes-

sage buffer 3 with RXOK3 not cleared).

RXOVR2: This bit indicates an overrun condition (a new message received on the mes-

sage buffer 2 with RXOK2 not cleared).

RXOVR1: This bit indicates an overrun condition (a new message received on the mes-

sage buffer 1 with RXOK1 not cleared).

RXOK3: Th is bit indi ca tes (activ e hi gh) that the dat a fra me mes s age has bee n recei ve d

correctly by the third message buffer.

RXOK2: Th is bit indi ca tes (activ e hi gh) that the dat a fra me mes s age has bee n recei ve d

correctly by the second message buffer.

RXOK1: Th is bit indi ca tes (activ e hi gh) that the dat a fra me mes s age has bee n recei ve d

correctly by the first message buffer.

Filter Register s The 2 filter registers are used (together with the arbitration register of the receiver buff-

ers or th e arbitr ation registe rs of the trans mit buffer to an swer to the rem ote r equest ) to

filter out the mes sages that are not interesti ng for the receiving softwar e. The filtering

function is implemented only on 11 bits of the identifier (message_id28 downto

message_id18) but works for both, extended and standard messages. The filtering func-

tion is:

Message Valid if:

for i = 28 downto 18

(“MsgID(i)” XOR “RXnARB(i)” )AND “AM(i)” = 0

14 AT7908E 4268B–AERO–10/04

The Me ssag e ID bi ts that are check ed wi th the arbitr ation of the recei ver bu ffer bit s ar e

the corresponding bits on the Acceptance Mask only if set to 1.

This filtering function is implemented for every message buffer.

TX Message Buffer The AT7908E CAN controller has one transmitter buffer. The transmitter buffer is com-

posed of 12 registers of 8 bits. The firsts 4 registers are used for the arbitration part that

could be of 11 or 29 bits. If the message to transmit is a standard message, the

AT7908E will send on the bus the identifier from ARB28 to ARB18. The other 8 registers

contain the data byte of the message:

TX_ARB0: bits 28 down to 21 of the arbitration of the transmitter

buffer(TXARB28:TXARB21)

TX_ARB1: bits 20 down to 13 of the arbitration of the transmitter

buffer(TXARB20:TXARB13)

TX_ARB2: bits 12 down to 5 of the arbitration of the transmitter buffer (TXARB12:TXARB5)

TX_ARB3: bits 4 down to 0 of the arbitration of the transmitter buffer (TXARB4:TXARB0)

TX_Message_0: first 8 bits data of the transmitter buffer

TX_Message_1: second 8 bits data of the transmitter buffer

TX_Message_2: third 8 bits data of the transmitter buffer

TX_Message_3: fourth 8 bits data of the transmitter buffer

TX_Message_4: fifth 8 bits data of the transmitter buffer

TX_Message_5: sixth 8 bits data of the transmitter buffer

TX_Message_6: seventh 8 bits data of the transmitter buffer

TX_Message_7: eighth 8 bits data of the transmitter buffer

RX Message Buffers The AT 7908E CAN controller has three receiver message buffers. The incoming data

frame message will be stored on the message object that matches the incoming ID ( see

filtering functionality). If the incoming ID matches more than one ID of the mess age

object, the me ss ag e wi ll b e sto re d i n the lo wes t n umb er ed me ss ag e o bje ct . T he i nc om-

ing remote request is not stored on the message buffer.

The structure of the message buffer is:

RXn_STATUS: Status register of the message object n

RXn_ARB0: bits 28 down to 21 of the arbitration of the message object n

RXn_ARB1: bits 20 down to 13 of the arbitration of the message object n

RXn_ARB2: bits 12 down to 5 of the arbitration of the message object n

RXn_ARB3: bits 4 down to 0 of the arbitration of the message object n

RXn_Message_0: first 8 bits data of the message object n

RXn_Message_1: second 8 bits data of the message object n

RXn_Message_2: third 8 bits data of the message object n

RXn_Message_3: fourth 8 bits data of the message object n

RXn_Message_4: fifth 8 bits data of the message object n

RXn_Message_5: sixth 8 bits data of the message object n

AT7908E

4268B–AERO–10/04

RXn_Message_6: seventh 8 bits data of the message object n

RXn_Message_7: eighth 8 bits data of the mess age objec t n

The following bit composes the RXn_STATUS register of the message buffer:

RXn_DLC3:RXn_DLC0: length of the received message

(length = RXn_DLC0 +2 x RXn_DLC1 + 4 x RXn_DLC2 + 8 x RXn_DLC3)

RXn_extfr: if this bit is high, the received message has an extended identifier.

Error Counters Registers The AT7908E has two internal counters for the RX and TX errors. The values of these

counters are stored into two registers that can be read from the MCU.

Trigger Match Registers The Trigger Match registers are implemented to generate a pulse on the HATRIG output

signal wh en the rec eived messa ge arbitratio n match the Trigger Match registe rs (see

the trigger match functionality).

Bit Timing A bit period is composed of the following three segments:

Synchronizati on se gme nt

Timing segment 1

Timing segment 2

The sampling point is at the end of time segment 1.

Input signal

Figure 2. Bit Time Segments

During the Sy nc segmen t (1 system clock cycle = tscl) the e dge of the input sign al is

expected.

The Timing segment 1 is programmable from 2 to 16 tscl (see register SETUP_2:

PS1_3:PS1_0: TSEG1 =PS1+1) and the end of this segment indicates the sample

point.

The Timing segment 2 is programmable from 1 to 8 tscl (register SETUP_2:

PS2_3:PS2_0) and this period is used to have extra time for the internal processing

after the sample point.

The resynchronization Jump Width is us ed to compe nsate phase shi fts betw een the

oscillator frequency of the different CAN nodes on the network. This value is program-

mabl e (s ee r egi ster SETU P_3: R SJ_ 2:RS J_0) from 1 t o 4 tscl a nd t he v alu e in dica tes the

number of system clock pulses by which the bit period must be shortened or lengthened

for resynch ronization. If the fa lling edge of the incoming signal is on the TIMING s eg-

ment 1, then the Bit period is lengthened (the sample point will be at TSEG1 +RSJ). If

the falling edge of the incoming signal is on the Timing segment 2, then the bit period

SYNC Timing Segment 1 Timing Segment 2

16 AT7908E 4268B–AERO–10/04

will b e shor tened ( TSEG2 is shor tened o f RSJ v alue) . The re synchr onizati on mecha-

nism is shown in fig. 3 and fig. 4.

Figure 3. Lengthening a Bit Period

Figure 4. Shorteni ng a Bit Period

The Bit rate of the message on the bus will be:

fosc/(BPR(baud rate prescaler)x(TSEG1 +TSEG2+1)) =

= fosc /(BPR(baud rate prescaler) x ( PS1 +PS2 +2))

The TSEG1 and TSEG2 lengths must be programmed to respect these conditions:

TSEG1 ≥ TSEG2 => PS1 +1 ≥ PS2

TSEG2 ≥ RSJ => PS2 ≥ RSJ

SYNC Timing Segment 1 RSJ Timing

Segment 2

Sample point

Input signal

SYNC Timing Segment 1 Timing Segment 2 RSJ

Sample point

Input signal

Tseg2 will be shortened

of RSJ value

AT7908E

4268B–AERO–10/04

Interf ace Block

Description The AT7908E provides a programmable (with external pin) MCU interface. Two modes

can be selected. The first operational mode is an interface with 8-bit multiplexed

address data bus (mode = 0) and an internal register addressable with 16-bit of address.

In this operational mode, the AT7908E registers are mapped between 8000Hex and

804CHex.

The second operational mode (mode =1) is implemented with 8 bit not multiplexed

address and data buses. In this mode the internal registers are accessible with 8-bit and

are mapped between 00Hex and 4C Hex.

The pins for the interface block are:

Operational Mode 0 This operational mode is selected with MODE pin = 0.

The bus Dat a_addr <7 :0> mus t be conne cted to the data/addr ess bus of the MC U. The

ALE si gnal i s used to l atch t he addr ess . This la tched add re ss will be the a ddres s of th e

AT7908E internal registers. The bus addr (7:0) will contain the highest address gener-

ated by the MCU. The internal AT7908E registers will be accessed only if the 16-bit

address generated by the MCU is between 8000 Hex and 804C Hex (the internal Chip

Selec t wil l be gener ated ). Mor eover, to wr ite in t he regis ter or to re ad from th e re gist er,

the micro-controller must generate the CS (active high), WR, RD and ALE signals and

must drive the Data_addr and addr buses. The s ignal WR must be low for, at least, 3

clock cycles. The data is latched at the rising edge of the clock when CS = 1, WR = 0

and RD = 1.

A write cycle is reported in Fig. 5.

Mode

Selection of the interface modality. This pin must be 0 to use 8 bits

multiplexed data address (lowest ) to map the AT7908E on the highest

address space (8000Hex to 804C Hex). If MODE = 1, the data and

addresses are not multiplexed and the registers are mapped on the lowest

address space.

Data <7:0> bi-directional 8-bi t addres s (low addres s in mode 0) data bus

ALE Input Address Latch Enable used for mode 0.

CS Input Chip select to enable the internal registers access (active high).

WR Input Write signal to write the internal registers (ac tive l ow).

RD Input Read signal to readout the internal registers (active low).

Addr <7:0>

Input highest address in mode 0 (used with low address to map the

AT7908E register between 8000Hex and 804Chex address space) or input

lowest address in mode 1

18 AT7908E 4268B–AERO–10/04

Figure 5. Mode 0 Write Cycle

In Fig. 6 are repr esented the signals to readout the internal register of AT7908E i n

mode 0

Figure 6. Mode 0 Read Cycle

In mode 0, the interna l registers of the AT79 08E are mappe d between 8000 Hex and

804C Hex and the lowest 8-bit address are multiplexed with the data.

MODE

Data

Addr

ALE

Clock

ADD

DATA

Data write in the internal register

HIGH ADDRESS =80 Hex

ADDR DATA

High Address = 80 Hex

MODE

Data

Addr

ALE

ADDR

HIGH ADDRESS =80 Hex

DATA

HIGH ADDRESS = 80 Hex

DATA

AT7908E

4268B–AERO–10/04

Operational Mode 1 This operational mode is selected with mode pin = 1.

This interface operational mode is used to write the AT7908E registers and to readout

from the A T 790 8E w ith two differ en t 8- bi t dat a an d address bu se s. The ALE i npu t pi n is

not used and the in ternal re gisters are mapped between 0 0Hex and 4C Hex. The Ad dr

bus will be used as the 8 bits address for the internal registers. To write data on the

intern al regist ers, the MCU m ust co ntrol the CS , WR and RD signals of the AT 7908E

and must drive the addr and data buses. The signal WR must be low for, at least, 3

clock cycles. The data is latched at the rising edge of the clock when CS = 1, WR = 0

and RD = 1. The fig. 7 shows the write cycle in the operational mode 1.

Figure 7. Mode 1 Write Cycle

Fig. 8 shows a read cycle . To readout the da ta fr om the AT79 08E internal r egi ste rs, the

MCU must drive CS=1, RD=0, WR=1.

Data write

MODE

Data

Addr

Clock

DATA

LOW ADDRESS

DATA

LOW ADDRESS

20 AT7908E 4268B–AERO–10/04

Figure 8. Mode 1 Read Cycle

Timing In t his pa ragraph are provided the AC spe ci fi ca t ion for th e A T7908E inte rface s ign als i n

both operational modes.

AC Specification for 8 bit

Multiplexed Mode (mode =0) Conditions: VCC = 5V ±10%, VSS = 0V, Ta = -55°C to +125 °C, Cl = 80 pF ,

Tclk = 100 ns

Note: 1. Guaranteed, not tested.

MODE

Data

Addr

Clock

DATA

LOW ADDRESS

Symbol Parameter Min Max Note

tAVLL A ddress valid to ALE low 4 ns Mode 0

tLLAX Address Hold after ALE low 4 ns Mode 0

tLHLL (*) ALE HIGH Time Tclk Mode 0

tLLRL (*) ALE low to RD low 2 Tclk Mode 0

tCHRL CS high to RD low 100 ns Mode 0

tDVWH] (*) Input Data valid to WR High 3 Tclk Mode 0, mode 1

tWHQX (*) Input data hold after WR high 10 ns Mode 0, mode 1

tWLWH (*) WR pulse width 3 Tclk Mode 0, mode 1

tWHLH (*) WR high to next ALE high Tclk

tWS WR setup time before clock -3 ns Mode 0, mode 1

tWH (*) WR hold time after clock 7 ns Mode 0, mode 1

tRLRH (*) RD pulse width 3 Tclk Mode 0, mode 1

tRLDV (*) RD low to data valid 6 ns 82 ns Mode 0, mode 1

tRHDZ (*) Data float after RD High 4 ns 20 ns Mode 0, mode 1

AT7908E

4268B–AERO–10/04

Figure 9. Timing information for interface signals

Inte rface Internal

Structure This paragraph is in tended to explain the implem entation of the interface internal

structure.

In the Figure 10, one can see the realization of the two operational modes and the

access to the AT7908E internal registers.

Data

ALE

Data

Xtalin

ADDR

DATA

tAVLL

LHLL

tLLAX

tLLRL

tRLDV

tRHDZ

tCHRL

tRLRH

tWLWR

tWHLH

ADDR

DAT

A in

tDVWH tWHQX

tWS

twh

DATA

ADDR

22 AT7908E 4268B–AERO–10/04

Figure 10. Interface Block Scheme

The MCU 80C32 gen er ate s DATA<7:0>, ADDR<7:0> ( hig hes t 8-bit address for the 16-

bit external data access), and ALE to latch the lowest addre ss, WR, CS and RD

signals.

The external data bus is connected to the internal latch block of the AT7908E. The ALE

signal latches and extracts the ADDR_LATCH (lowest 8-bit address). The

ADDR_LATCH is used to address the internal registers in mode 0 and to generate, with

ADDR<7:0> (highest 8-bit address), the internal chip select signal (CS_INT). In mode 0,

the access to the internal registers is selected by CS_IN T and CS; in mode 1, th e

access is selec ted by CS. In mode 1, moreover, the address of the internal register is

ADDR<7:0>. Th e two di ffer en t op erati ona l m ode s are estab li sh ed b y the mode pin that

is the selector for the two multiplexers in Figure 5. In Figure 5 are reported, in addition,

the other two blocks of the AT7908E device: the AT7908E registers and the AT7908E

CAN_CORE.

DATA_ADDR<7:0>

LATCH

DECODER

ADDR<7:0>

ADDR_LATCH<7:0>

CS_INT

MODE

CASA2

ADDR_REG<7:0>

CS_CASA

ALE CASA2

CAN_CORE

AT7908E

4268B–AERO–10/04

Address Table In the nex t tab le , one c an s ee how the MCU c an add re ss the RAM o r the internal r egi s-

ter of the AT7908E in the operational mode 0.

ADDRESS Generated by the MCU

(15 down to 0) Device

0000 – 7FFF Hex 32 Kword of External RAM

8000 – 800C Hex AT7908E internal register 00 – 0C Hex

(Configuration and status register)

8010 – 801B Hex AT7908E internal regist er 10 – 1B Hex

Transmitter message buffer

8020 – 802C Hex AT7908E internal regist er 20 – 2C Hex

First receiver message object

8030 – 803C Hex AT7908E internal regist er 30 – 3C Hex

Second receiver message object

8040 – 804C Hex AT7908E internal regist er 40 – 4C Hex

Third receiver message object

24 AT7908E 4268B–AERO–10/04

Optional Features

Internal Clock Frequency The actual inte rnal sys tem clock can be the external clock divided by 1, 2, 4, or 8. If the

bit time length is (default configuration) 16 system clock pulses (see PS1, PS2 program-

mable bit timing registers), it is possible to have four different data rates by the pre-

scaler programming.

AT7908E Operational

Mode The AT7908E device could be put on three different operational modes:

• Functional Mode

• Test mode

• Power down mode

Functional Mode This mode is the normal operational mode for the AT7908E device. The two input pins

test and sena must be put on logical value 0.

Test Mode This mode is used by the chip manufacturer to test the AT7908E. The input pin test

must be logical value 1 and sena input pin could be logical values 0 or 1 according to

the execution of the scan chain test or not.

Power Down Mode This mod e cou ld be us ed to p ut the AT 7 908E d evic e on the s le ep mod e ( int ernal c lo ck

is off). To put the AT7908E in this mode, the test input pin must be 0 and sena input pin

must be 1 .

AT7908E

4268B–AERO–10/04

Application Notes

Registers Value After

Reset In the next table are reported the registers value after reset of the AT7908E device:

Hex Reset Value ( bit7… bit0)

SETUP_0 00 BPR1 BPR0 GensyncTx GensyncRx Errint Overint Rxint Txint

000 0 000 0

SETUP_1 01 Disabled TXRM TXEM TMRMR TXDLC3 TXDLC1 TXDLC1 TXDLC0

100 0 000 0

SETUP_2 02 PS2_3 PS2_2 PS2_1 PS2_0 PS1_3 PS1_2 PS1_1 PS1_0

010 1 100 1

SETUP_3 03 RxClr Reset IntClr AbortTx Txreq RSJ2 RSJ1 RSJ0

000 0 001 0

SETUP_RX 04 Reserved Reserved Reserved Reserved Reserved Rxclr3 Rxclr2 Rxclr1

XXX X X00 0

STATUS 05 SyncTx SyncRx Rxbuf1 Rxbuf0 TxOK TxActive ErrPass BusOff

000 0 000 0

STATUS_RX 06 reserved Rxovr3 Rxovr2 Rxovr1 Reserved RXOK3 RXOK2 RXOK1

000 0 000 0

FILTER_AM_0 07 00000000

FILTER_AM_1 08 00000000

ERR_COUNT_TX 09 00000000

ERR_COUNT_RX 0A 00000000

TRIG_MATCH_0 0B 00000000

TRIG_MATCH_1 0C 00000000

TX_ARB_0 10 00000000

TX_ARB_1 11 00000000

TX_ARB_2 12 00000000

TX_ARB_3 13 00000000

TX_MESSAGE_0 14 00000000

TX_MESSAGE_1 15 00000000

TX_MESSAGE_2 16 00000000

TX_MESSAGE_3 17 00000000

TX_MESSAGE_4 18 00000000

TX_MESSAGE_5 19 00000000

TX_MESSAGE_6 1A 00000000

TX_MESSAGE_7 1B 00000000

RX1_ARB_0 20 00000000

RX1_ARB_1 21 00000000

RX1_ARB_2 22 00000000

26 AT7908E 4268B–AERO–10/04

RX1_ARB_3 23 00000000

RX1_MESSAGE_0 24 00000000

RX1_MESSAGE_1 25 00000000

RX1_MESSAGE_2 26 00000000

RX1_MESSAGE_3 27 00000000

RX1_MESSAGE_4 28 00000000

RX1_MESSAGE_5 29 00000000

RX1_MESSAGE_6 2A 00000000

RX1_MESSAGE_7 2B 00000000

RX1_STATUS 2C reserved reserved Reserved RX1_e

xtfr Rx1_DLC3 Rx1_DLC2 Rx1_DLC1 Rx1_DLC0

XXX 00 0 0 0

RX2_ARB_0 30 00000000

RX2_ARB_1 31 00000000

RX2_ARB_2 32 00000000

RX2_ARB_3 33 00000000

RX2_MESSAGE_0 34 00000000

RX2_MESSAGE_1 35 00000000

RX2_MESSAGE_2 36 00000000

RX2_MESSAGE_3 37 00000000

RX2_MESSAGE_4 38 00000000

RX2_MESSAGE_5 39 00000000

RX2_MESSAGE_6 3A 00000000

RX2_MESSAGE_7 3B 00000000

RX2_STATUS 3C reserved reserved Reserved RX2_e

xtfr Rx2_DLC3 Rx2_DLC2 Rx2_DLC1 Rx2_DLC0

XXX 00 0 0 0

RX3_ARB_0 40 00000000

RX3_ARB_1 41 00000000

RX3_ARB_2 42 00000000

RX3_ARB_3 43 00000000

RX3_MESSAGE_0 44 00000000

RX3_MESSAGE_1 45 00000000

RX3_MESSAGE_2 46 00000000

RX3_MESSAGE_3 47 00000000

RX3_MESSAGE_4 48 00000000

RX3_MESSAGE_5 49 00000000

RX3_MESSAGE_6 4A 00000000

Hex Reset Value ( bit7… bit0)

AT7908E

4268B–AERO–10/04

RX3_MESSAGE_7 4B 00000000

RX3_STATUS 4C reserved reserved Reserved RX3_e

xtfr Rx3_DLC3 Rx3_DLC2 Rx3_DLC1 Rx3_DLC0

XXX 00 0 0 0

Hex Reset Value ( bit7… bit0)

AT7908E

4268B–AERO–10/04

Configuration Flow The following flow diagram explains the action that the MCU must perform to program

the AT7908E CAN controller to send or to receive CAN message.

Figure 11. Operating Flow Diagram

In the examples of the followings paragraph the different operations are referred to the

number reported on flow diagram. After the commands, the old register and the new

reset

Device

Configuration

(1)

Transmit buffer

Initialisation

(2)

Receiver

message

object

configuration

(3)

START TX

(5)

SET START

TRANSMISSION

(6)

Enable BUS

Connection

(4)

INT by CASA2

(7)

Change

Configuration

(10)

Disable BUS

CONNECTION

(11)

yes

READ STATUS

(& recei ver buffer)

(8)

Yes

Clea r IN T an d receive

STATUS

(9)

Yes

29 AT7908E 4268B–AERO–10/04

Initialization and Transmission of the Data Frame with the INT Generation and Behavior of the

MCU After the Interrupt is Received

Configuration of all the setup registers after the RESET signal.

Operation 1 Table 1. write reg 00 H, data =01Hex

(SETUP_0 register) system clock = external clock, enable transmission completed

interrupt

Table 2. write reg 02 H, data =69Hex

(SETUP_2 register) Time segment 2 = 6 pulse of system clock; Time segment 1 = 8

pulse of system clock.

SETUP_3 register will be not written ( default configuration)

Operation 2 After SETUP registers is necessary to configure TX message object:

Table 3. write reg 10 H, data =AA Hex

write reg 11 H, data =AA Hex

(TX_ARB_0= and TX_ARB_1 registers) identifier of message that will be transmitted =

10101010101

SETUP_0

BPR1 BPR0 Gens

yncTx Gens

yncRx Errint Overint Rxint Txint

0000 0 0 0 0

SETUP_0

BPR1 BPR0 Gens

yncTx Gens

yncRx Errint Overint Rxint Txint

0000 0 0 0 1

SETUP_2 PS2_3 PS2_2 PS2_1 PS2_0 PS1_3 PS1_2 PS1_1 PS1_0

0101 1 0 0 1

SETUP_2 PS2_3 PS2_2 PS2_1 PS2_0 PS1_3 PS1_2 PS1_1 PS1_0

0110 1 0 0 1

TX_ARB_0 00000000

TX_ARB_1 00000000

TX_ARB_0 10101010

TX_ARB_1 10101010

AT7908E

4268B–AERO–10/04

Table 4. write reg 14 H, data =00Hex

Table 5. write reg 15 H, data =FF Hex

Table 6. write reg 16 H, data =0FHex

Table 7. write reg 17 H, data =F0Hex

Table 8. write reg 18 H, data =AA Hex

TX_MESSAGE_0 00000000

TX_MESSAGE_1 00000000

TX_MESSAGE_1 11111111

TX_MESSAGE_2 00000000

TX_MESSAGE_2 00001111

TX_MESSAGE_3 00000000

TX_MESSAGE_3 11110000

TX_MESSAGE_4 00000000

TX_MESSAGE_4 10101010

31 AT7908E 4268B–AERO–10/04

Table 9. write reg 19 H, data =55Hex

Table 10. write reg 1A H, data =66Hex

Table 11. write reg 1B H, data =99Hex

(TX_MESSAG E _n registers) Setting of data message that must be transmitted

When TX message objec t initiali zed,the MCU must c onnect the A T7908E to the CA N

bus.

Operation 4 Table 12. write reg 01 H, data =08Hex

(SETUP_1 r egister) AT79 08E connected t o BUS, d ata frame(no remote frame), stan-

dard message, length of message = 8 byte.

Setting of the transmission request

TX_MESSAGE_5 00000000

TX_MESSAGE_5 01010101

TX_MESSAGE_6 00000000

TX_MESSAGE_6 01100110

TX_MESSAGE_7 00000000

TX_MESSAGE_7 10011001

SETUP_1 Disabled TXRM TXEM TMRM

RTXDLC

3TXDLC

1TXDLC

1 0000000

SETUP_1 Disabled TXRM TXEM TMRM

RTXDLC

3TXDLC

1TXDLC

0 0001000

AT7908E

4268B–AERO–10/04

Operations 5 and 6 Table 13. write reg 03 H, data =0Ahex (1)

(SETUP_3 register) Resynchronisation jump length = 2 system clock and transmission

request.

Then, the AT790 8E starts to transmi t the messag e until an ack nowledge co mes from

another CAN node. The next figure illustrates the standard CAN format on the CAN

BUS:

Figure 12. DATA frame

STATUS register before TX request:

STATUS register after start of transmission:

STATUS register after completion of correct transmission:

1. The five Gra y bit ar e not up dated a fter settin g (Txr eq). The se bit are not wr itten inside th e

registers.

SETUP_3 RxClr Reset IntClr Abort

Tx Txreq RSJ2 RSJ1 RSJ0

0 0000010

SETUP_3 RxClr Reset IntClr Abort

Tx Txreq RSJ2 RSJ1 RSJ0

0 0000010

STATUS SyncTx Sync

Rx Rxbuf

1Rxbuf

0TxOK

TxActiv

eErrPas

sBusOff

0 0000000

STATUS SyncTx Sync

Rx Rxbuf

1Rxbuf

0TxOK

TxActiv

eErrPas

sBusOff

0 0000100

End of

Frame

Data Frame

SOF ACK

INT

Generation

33 AT7908E 4268B–AERO–10/04

Operation 7

At this point, the AT7908E sends an interrupt generation ;INT signal (Active low).

The MCU clears the int erru pt genera tion, setting the IntClr bit on the SETUP_3 register .

Now we assume that the MCU receives the INT signal and it wants to program the

AT7908E to send the same data frame on the CAN bus.

Operation 8 Table 14. read reg 05 H

(MCU read status register after INT received)

Operations 5, 6, 9, and 10 Table 15. write reg 03 H, data =2AHex

(SETUP_3 register) Clear INT signal and start new transmission(TXREQ)Resynchroni-

sation jump length = 2 system clock and transmission request.

After this setting, the INT signal becomes high (interrupt request disabled), the AT7908E

starts a new transmission and the STATUS register is automatically updated as follows:

STATUS SyncTx Sync

Rx Rxbuf

1Rxbuf

0TxOK

TxActiv

eErrPas

sBusOff

0 0001000

STATUS SyncTx Sync

Rx Rxbuf

1Rxbuf

0TxOK

TxActiv

eErrPas

sBusOff

0 0001000

SETUP_3 RxClr Reset IntClr Abort

Tx Txreq RSJ2 RSJ1 RSJ0

0 0000010

SETUP_3 RxClr Reset IntClr Abort

Tx Txreq RSJ2 RSJ1 RSJ0

0 0000010

STATUS SyncTx Sync

Rx Rxbuf

1Rxbuf

0TxOK

TxActiv

eErrPas

sBusOff

0 0001000

STATUS SyncTx Sync

Rx Rxbuf

1Rxbuf

0TxOK

TxActiv

eErrPas

sBusOff

0 0000100

AT7908E

4268B–AERO–10/04

Initialisation of the Receiver Message Objects and the Filtering Function

In this pa ra gr aph is repo rt ed a n ex am ple about c on fig ur ati on o f the AT 79 08E to re ce iv e

message with the filtering function. In this example the MCU, after configuration of the

AT790 8E, waits for Inter rupt (from the AT 7908E) and the n the MCU reads the status

registers, the RX message object and it clears the interrupt request and the receiver

status.

Configuration of the AT7908E:

Operation 1 Table 16. Write reg 00 H, data = 0FHex

(SETUP_0 register) system clock = external clock, all interrupts enabled (rx completed,

tx completed, overrun, err or state).

SETUP_2 register will be not written ( default configuration)

SETUP_3 register will be not written ( default configuration)

Receive r Mess age Obje ct and Fil ter in g funct ion configur at ion

Operation 3 Table 17. write reg 07 H, data =FF Hex

write reg 08 H, data =FF Hex

(FILTER _AM_0, FILT ER_AM_ 1 regist ers) Global mask s et to check all bits of in co ming

identifier.

SETUP_0 BPR1 BPR0 Gensy

ncTx Gensy

ncRx Errint Overint Rxint Txint

0 0000000

SETUP_0 BPR1 BPR0 Gensy

ncTx Gensy

ncRx Errint Overint Rxint Txint

0 0001111

FILTER_AM_0 00000000

FILTER_AM_1 00000000

FILTER_AM_0 11111111

FILTER_AM_1 11111111

35 AT7908E 4268B–AERO–10/04

Table 18. write reg 20 H, data =55Hex

write reg 21 H, data =55Hex

(RX1_ARB_0, RX1_ARB_1 registers)Set the identifier for receiver message object 1(ID

=01010101010)

Table 19. write reg 30 H, data =AA Hex

write reg 31 H, data =AA Hex

(RX2_AR B_0 , RX 2_A RB _1 registers )Set t he i den tifi er for rec ei ve r mes sa ge o bj ect 2(ID

=10101010101)

Table 20. write reg 40 H, data =FF Hex

write reg 41 H, data =FF Hex

(RX3_ARB_0, RX3_ARB_1 registers)Set the identifier for receiver message object 3 (ID

=11111111111)

RX1_ARB_0 00000000

RX1_ARB_1 00000000

RX1_ARB_0 01010101

RX1_ARB_1 01010101

RX2_ARB_0 00000000

RX2_ARB_1 00000000

RX2_ARB_0 10101010

RX2_ARB_1 10101010

RX3_ARB_0 00000000

RX3_ARB_1 00000000

RX3_ARB_0 11111111

RX3_ARB_1 11111111

AT7908E

4268B–AERO–10/04

Operation4

Table 21. write reg 01 H, data =00Hex

(SETUP_1 register) AT7908E connected to BUS, data frame(no remote frame), standard message

At this point, the AT7908E is ready to receive a message from the other CAN nodes and

to generate an interrupt if the message has been received.

When the A T7 908 E re ce ives a mes s age ( for e xa mpl e w ith Ide nti fie r = 111 111 1111 1) , i t

stores the message in the receiver message object that satisfies the filtering function (in

this case , the RX3 message object). In th e following tables ar e reported the S TATUS

registers before and after message receiving (Rxbuf0 and Rxbuf1 bits, after the

received me ssa ge, con tai n the ind icati on ab out the receiv er me ssag e obj ec t tha t sto re d

the message incoming).

Table 22. STATUS regi ster before receiving.

Table 23. STATUS register after received message

Operations 5 and 7

Table 24. Automatically update of STATUS_RX register

SETUP_1 Disabled TXRM TXEM TMRMR TXDLC3 TXDLC1 TXDLC1 TXDLC0

1 0000000

SETUP_1 Disabled TXRM TXEM TMRMR TXDLC3 TXDLC1 TXDLC1 TXDLC0

0 0000000

STATUS SyncTx SyncRx Rxbuf1 Rxbuf0 TxOK TxActive ErrPass BusOff

0 0000000

STATUS SyncTx SyncRx Rxbuf1 Rxbuf0 TxOK TxActive ErrPass BusOff

0 0110000

STATUS_RX reserved Rxovr3 Rxovr2 Rxovr1 Reserved RXOK3 RXOK2 RXOK1

0 0000000

STATUS_RX Reserved Rxovr3 Rxovr2 Rxovr1 Reserved RXOK3 RXOK2 RXOK1

0 0000100

37 AT7908E 4268B–AERO–10/04

Table 25. Automatically update of RX3_STATUS register

The arbitration registers of the RX3 message object will store the arbitration of the

received mess age and the data re gister s of th e RX3 m essage ob ject wi ll st ore the da ta

of the rec eived mess age. At the en d of frame, the INT will be gener ated and the action

that the MCU mus t perform could be the followings (thes e operations are only read

operations and the internal registers of the AT7908E are not updated):

Operation 8 read reg 06 H

(STAT US_ RX r eg ister ) reado ut of A T 790 8E sta tus _r x: rxok 3, rx ok 2, rxo k1 ind ic ate s th e

message object that received the message(if 00 the message is not received). For

example : reg 06 = 04Hex => the message has been received correctly on message

object 3.

read reg 4C H

(RX3_STATUS register)readout of message object 3 status. Is possible to check

extende d or st andar d fra me of rec eiv ed m essage a nd l ength of r ece ive d mess age. For

example : reg 4C = 08Hex, standard frame, length =8.

read reg 40 H

read reg 41 H

(RX3_ARB_n registers)readout of stored message identifier

read reg 44 H

read reg 45 H

read reg 46 H

read reg 47 H

read reg 48 H

read reg 49 H

read reg 4A H

read reg 4B H

(RX_3_MESSAGE_n register)readout of stored message data.

After the read out of the received message, the MCU must clear the receiver message

object status (principally Rxok bit) and the INT signal setting RXCLRn bit in the

RX3_STATUS RX3

Reserved RX3

reserved RX3

extfr Rx3

DLC3 Rx3

DLC2 Rx3

DLC1 Rx3

DLC0

X XX00000

RX3_STATUS RX3

Reserved RX3

reserved RX3

extfr Rx3

DLC3 Rx3

DLC2 Rx3

DLC1 Rx3

DLC0

X XX01000

AT7908E

4268B–AERO–10/04

SETUP _RX r egiste r and th e Int Clr bit in the S ETUP _3 regi ster ( see how t o cle ar inte r-

rupt in the precedent paragraph).

Operation 5 and 6

Table 26. write reg 03 H, data =22Hex

(SETUP_3 register) Resynchronisation jump length = 2 system clock and clear interrupt

Operation 9

Table 27. write reg 04 H, data =04Hex

(SETUP_RX register)Clear rx ok and rx overrun bit of receiver message objects 3

After this operation, the RX3OK bit in STATUS_RX register will be cleared

If the MCU doesn’t clear the receiver message object status (principally the Rxok bit )

and the AT7908E receives a new message on the same message object (for example

the RX3 message object), the message will be stored in the message object; INT will be

generated (OVERRUN condition) and the STATUS_RX will be updated as following:

SETUP_3 RxClr Reset IntClr AbortTx Txreq RSJ2 RSJ1 RSJ0

0 0000010

SETUP_3 RxClr Reset IntClr AbortTx Txreq RSJ2 RSJ1 RSJ0

0 0000010

SETUP_RX Reserved Reserved Reserved Reserved Reserved Rxclr3 Rxclr2 Rxclr1

X XXX X 0 0 0

SETUP_RX Reserved Reserved Reserved Reserved Reserved Rxclr3 Rxclr2 Rxclr1

X XXX X 0 0 0

STATUS_RX reserved Rxovr3 Rxovr2 Rxovr1 reserved RXOK3 RXOK2 RXOK1

X 000x100

STATUS_RX reserved Rxovr3 Rxovr2 Rxovr1 reserved RXOK3 RXOK2 RXOK1

X 0000000

39 AT7908E 4268B–AERO–10/04

Setti n g to answ er to

remote frame request In this example is reported a typical configuration to answer to the remote frame

request.

Operation 1

Table 28. write reg 00 H, data =01Hex

(SETUP_0 register) system clock = external clock, transmitter interrupts enabled .

SETUP_2 register will be not written ( default configuration)

SETUP_3 register will be not written ( default configuration)

After the SETUP registers, it is necessary to configure the TX message object:

Operation 2 Table 29. write reg 10 H, data =AA Hex

write reg 11 H, data =AA Hex

(TX_ARB_0= and TX_ARB_1 registers) identifier of message that will be transmit-

ted = 10101010101

STATUS_RX reserved Rxovr3 Rxovr2 Rxovr1 reserved RXOK3 RXOK2 RXOK1

x 000x100

STATUS_RX reserved Rxovr3 Rxovr2 Rxovr1 reserved RXOK3 RXOK2 RXOK1

x 1000100

SETUP_0 BPR1 BPR0 Gensync

Tx Gensync

Rx Errint Overint Rxint Txint

0 0000000

SETUP_0 BPR1 BPR0 Gensync

Tx Gensync

Rx Errint Overint Rxint Txint

0 0000001

TX_ARB_0 00000000

TX_ARB_1 00000000

TX_ARB_0 10101010

TX_ARB_1 10101010

AT7908E

4268B–AERO–10/04

Table 30. write reg 14 H, data =00H

Table 31. write reg 15 H, data =FF Hex

Table 32. write reg 16 H, data =0FHex

Table 33. write reg 17 H, data =F0Hex

Table 34. write reg 18 H, data =AA Hex

TX_MESSAGE_0 00000000

TX_MESSAGE_1 00000000

TX_MESSAGE_1 11111111

TX_MESSAGE_2 00000000

TX_MESSAGE_2 00001111

TX_MESSAGE_3 00000000

TX_MESSAGE_3 11110000

TX_MESSAGE_4 00000000

TX_MESSAGE_4 10101010

41 AT7908E 4268B–AERO–10/04

Table 35. write reg 19 H, data =55 Hex

Table 36. write reg 1A H, data =66Hex

Table 37. write reg 1B H, data =99Hex

(TX_MESSAGE_n registers) Setting of data message that must be transmitted as

answer to remote frame request.

Operation 4

Table 38. write reg 01 H, data =48Hex

(SETUP_1 register) AT7908E connected to BUS ,setting to answer to remote frame request, standard message, length of

message = 8 byte.

To be ready to answer to a remote frame request, the MCU must set the Txreq bit on the

SETUP_3 register. After the Txreq setting, the AT7908E waits for a remote frame

reques t that m atches (see the fi lte ri ng functio nal ity ) the iden tifi er st or ed on the TX_ ARB

regist er s.

TX_MESSAGE_5 00000000

TX_MESSAGE_5 01010101

TX_MESSAGE_6 00000000

TX_MESSAGE_6 01100110

TX_MESSAGE_7 00000000

TX_MESSAGE_7 10011001

SETUP_1 Disabled TXRM TXEM TMRMR TXDLC3 TXDLC1 TXDLC1 TXDLC0

1 0000000

SETUP_1 Disabled TXRM TXEM TMRMR TXDLC3 TXDLC1 TXDLC1 TXDLC0

0 1001000

AT7908E

4268B–AERO–10/04

Operations 5 and 6

Table 39. write reg 03 H, data =0AHex

(SETUP_3 register) Resynchronisation jump length = 2 system clock and transmission request.

After this setting, the AT7908E waits for a remote frame request and the STATUS regis-

ter will be not updated.

If the request arrives, the AT7908E will send an acknowledge and then starts to transmit

the data frame in reply to the remote frame request. The STATUS register, during the

answer, will be automatically updated (TX_active bit become 1).

At the end of the transmission, the AT7908E will send the INT to the MCU that can read

out the STATUS register to check that all is OK.

Setting to send remote frame request

In this paragraph will be described the procedure to send a remote frame request.

After the Dev ice configuration, the MCU must initialize the transmit buffe r to send the

remote frame request and the receiver buffers to receive the remote frame answer.

The config ur ati on of all the set up regis ter s after RESE T si gna l.

Operation 1

Table 40. write reg 00 H, data =02Hex

(SETUP_0 register) system clock = external clock, enable receiving completed interrupt

SETUP_3 RxClr Reset IntClr AbortTx Txreq RSJ2 RSJ1 RSJ0

0 0000010

SETUP_3 RxClr Reset IntClr AbortTx Txreq RSJ2 RSJ1 RSJ0

0 0000010

STATUS SyncTx SyncRx Rxbuf1 Rxbuf0 TxOK TxActive ErrPass BusOff

0 0000000

STATUS SyncTx SyncRx Rxbuf1 Rxbuf0 TxOK TxActive ErrPass BusOff

0 0000100

SETUP_0 BPR1 BPR0 Gensync

Tx Gensync

Rx Errint Overint Rxint Txint

0 0000000

43 AT7908E 4268B–AERO–10/04

SETUP_2 register will be not written (default configuration)

SETUP_3 register will be not written (default configuration)

After the SETUP registers, it is necessary to configure the TX message object:

Operation 2 Table 41. write reg 10 H, data =AA Hex

write reg 11 H, data =AA Hex

(TX_ARB_0= and TX_ARB_1 registers) identifier of message that will be transmit-

ted = 10101010101

Setting of the RX mess age buffers (the incoming ans wer to the remote frame request

will be stored on the RX message buffer that matches the incoming Identifier,

10101010101 in this case).

Operation 3 Table 42. write reg 07 H, data =FF Hex

write reg 08 H, data =FF Hex

(FILTER _AM_0, FILT ER_AM_ 1 regist ers) Global mask s et to check all bits of in co ming

identifier.

SETUP_0 BPR1 BPR0 Gensync

Tx Gensync

Rx Errint Overint Rxint Txint

0 0000010

TX_ARB_0 00000000

TX_ARB_1 00000000

TX_ARB_0 10101010

TX_ARB_1 10101010

FILTER_AM_0 00000000

FILTER_AM_1 00000000

FILTER_AM_0 11111111

FILTER_AM_1 11111111

AT7908E

4268B–AERO–10/04

Table 43. write reg 20 H, data =55Hex

write reg 21 H, data =55Hex

(RX1_ARB_0, RX1_ARB_1 registers) Set the identifier for receiver message object

1(ID =01010101010)

Table 44. write reg 30 H, data =AA Hex

write reg 31 H, data =AA Hex

(RX2_AR B_0 , RX 2_A RB _1 registers )Set t he i den tifi er for rec ei ve r mes sa ge o bj ect 2(ID

=10101010101)

Table 45. write reg 40 H, data =FF Hex

write reg 41 H, data =FF Hex

(RX3_ARB_0, RX3_ARB_1 registers)Set the identifier for receiver message object 3 (ID

=11111111111)

RX1_ARB_0 00000000

RX1_ARB_1 00000000

RX1_ARB_0 01010101

RX1_ARB_1 01010101

RX2_ARB_0 00000000

RX2_ARB_1 00000000

RX2_ARB_0 10101010

RX2_ARB_1 10101010

RX3_ARB_0 00000000

RX3_ARB_1 00000000

RX3_ARB_0 11111111

RX3_ARB_1 11111111

45 AT7908E 4268B–AERO–10/04

Operation 4

Table 46. write reg 01 H, data = 10Hex

(SETUP_1 reg ister) AT7908E c onnected to BUS, remote frame request, s tandard mess age, length of data can be any

value.

Transmission request

Operation 5 and 6

Table 47. write reg 03 H, data =0AHex

(SETUP_3 register) Resynchronisation jump length = 2 system clock and transmission request.

At this po int , the A T 790 8E st arts to tr ansmi t th e r em ote fr ame request u ntil an ackno w l-

edge comes from another CAN node.

In the next figure is reported the standard CAN format on the CAN BUS for the

REMOTE FRAME request.

Figure 13. Remote frame

SETUP_1 Disabled TXRM TXEM TMRMR TXDLC3 TXDLC1 TXDLC1 TXDLC0

1 0000000

SETUP_1 Disabled TXRM TXEM TMRMR TXDLC3 TXDLC1 TXDLC1 TXDLC0

0 0010000

SETUP_3

RxClr Reset IntClr AbortTx Txreq RSJ2 RSJ1 RSJ0

0 0000010

SETUP_3 RxClr Reset IntClr AbortTx Txreq RSJ2 RSJ1 RSJ0

0 0000010

Control Field End of

Frame

ACKSOF

TxOK bit Updated

AT7908E

4268B–AERO–10/04

Table 48. STATUS register before the TX request:

Table 49. STATUS register after start of transmission:

Table 50. STATUS register after end of completed correctly transmission:

At this point, the AT7908E waits for a remote frame answer. If the remote frame answer

arrives, the behavior of the AT7908E, from all points of view, is the same as for a normal

receiving message (see paragraph 6.2.3).

STATUS SyncTx SyncRx Rxbuf1 Rxbuf0 TxOK TxActive ErrPass BusOff

0 0000000

STATUS SyncTx SyncRx Rxbuf1 Rxbuf0 TxOK TxActive ErrPass BusOff

0 0000100

STATUS SyncTx SyncRx Rxbuf1 Rxbuf0 TxOK TxActive ErrPass BusOff

0 0001000

47 AT7908E 4268B–AERO–10/04

Package

Mechanical

Characteristics 44 Pin Multilayer Ceramic Package (MLCC)

Dimension: 17.14 x 17.14 mm

Pin to Pin Spacing : 1.27 mm

AT7908E

4268B–AERO–10/04

Pin Assignment

PIN Number Signal Name Note

1 VCCA1 Power for array

2 Addr[4]

3 Addr[5]

4 Addr[6]

5 Addr[7]

6 VSSB1 Ground for periphery

7 VCCB2 Power for periphery

8Cs

9 Mode

10 Ale

11 Wr

12 VSSA1 Ground for Array

13 Rd

14 Sena

15 Test

16 Reset

17 VSSB2 Ground for periphery

18 VCCB3 Power for periphery

19 Can_rx

20 Hasync

21 ---------- Not connected

22 Xtalout

23 Xtalin

24 VCCA2 Power for array

25 Int

26 Hatrig

27 Can_tx

28 VSSB3 Ground for periphery

29 VCCB4 Power for periphery

30 Data[0]

31 Data[1]

32 Data[2]

33 Data[3]

34 VSSA2 Ground for Array

35 Data[4]

36 Data[5]

37 Data[6]

49 AT7908E 4268B–AERO–10/04

Note: VCCA1 = VCCA2 = VCCB1 = VCCB2 = VCCB3 = VCCB4 = 5V

VSSA1 = VSSA2 = VSSB1 = VSSB2 = VSSB3 = VSSB4 = 0V

Ordering Information

38 Data[7]

39 VSSB4 Ground for periphery

40 VCCB1 Power for periphery

41 Addr[0]

42 Addr[1]

43 Addr[2]

44 Addr[3]

PIN Number Signal Name Note

Part Number Temperatue Range Quality Flow

AT7908EJL-E 25°C Engineering Sample

AT7908EJL-2 -55°C to +125°C Standard Mil.

5962-03A06QXC -55°C to +125°C QML Q

5962-03A06VXC -55°C to +125°C QML V

AT7908EJLSB(1) -55°C to +125°C SCC B

Note: 1. Contact Atmel for availability

Printed on recycled paper.

Disclaimer: Atmel Corporation makes no warranty for the use of its products, other t han those expressly contained in t he Company’s standard

warranty which is detailed in Atmel’s Ter ms and Condit ions locate d on the Company’s web site. The Company assumes no responsibility for any

errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and

does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are

granted by the Company in connection wit h the sale of Atmel products, expressly or by imp lication. Atmel’s products are not authorized for use

as critical components in life support devic es or systems.

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