© 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN7383 Half-Bridge Gate-Drive IC
February 2007
FAN7383 Rev. 1.0.3
FAN7383
Half-Bridge Gate-Drive IC
Features
Floating Channel Designed for Bootstrap Operation to
+600V.
Typically 350mA/650mA Sourcing/Sinking Current
Driving Capability for Both Channels
Extended Allowable Negative VS Swing to -9.8V for
Signal Propagation at VDD=VBS=15V
High-Side Output in Phase of IN Signal
Built-in UVLO Functions for Both Channels
Built-in Common-Mode dv/dt Noise Canceling Circu it
Typically Internal 330ns Minimum Dead-Time
Programmable Tu rn-On Delay Time Control
(Dead-Time)
Applications
SMPS
Motor Drive Inverter
Fluorescent Lamp Ballast
HID Ballast
Description
The FAN7383 is a half-bridge gate-drive IC with
shutdown and programmable dead-time control
functions for driving MOSFETs and IGBTs that operate
up to +600V.
Fairchild’s high voltage process and common-mode
noise canceling technique give stable operation of high-
side drivers under high-dv/dt noise circumstances.
An advanced level-shift circuit allows high-side gate
driver operation up to VS= -9.8V (typical) for VBS=15V.
The UVLO circuits for both channels prevent malfunction
when VDD and VBS are lower than the specified
threshold voltage.
Output drivers typically source/sink 350mA/650mA,
respectively, which is suitable for all kin ds of half and full
bridge inverter.
Ordering Information
Note:
1. These devices passed wave soldering test by JESD22A-111.
1
14-SOP
Part Number Package Pb-Free Operating Temperature Range Packing Method
FAN7383M(1) 14-SOP Yes -40°C ~ 125°C Tube
FAN7383MX(1) Tape & Reel
FAN7383 Half-Bridge Gate-Drive IC
© 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN7383 Rev. 1.0.3 2
Typical Application Circuit
Figure 1. Application Circuit for Half-Bridge Switching Power Supply
Figure 2. Application Circuit for Full-Bridge DC Motor Driver
VDD
VDC
PWM
Shutdown
LO1
GND
VB
VS
HO1
VDD
SD
IN
DT
NC
9
10
8
11
14
12
13
6
5
7
4
1
3
2
LO2
NC
NC
HO2
PWM IC
Control
RDT
DBOOT
CBOOT
RHON
RHOFF
RLON
RLOFF
RBOOT
FAN7383 Rev.01
Forward
VDC
VCC
M
Reverse
DC Motor
Controller
PHA
PHB
HO1
VS
LO2
VB
VDD
GND
IN
FAN7383
DT
LO1
HO2
SD
SD
HO1
VS
LO2
VB
VDD
GND
IN
FAN7383
DT
LO1
HO2
SD
FAN7383 Rev.01
FAN7383 Half-Bridge Gate-Drive IC
© 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN7383 Rev. 1.0.3 3
Internal Block Diagram
Figure 3. Functional Block Diagram of FAN7383
UVLO
DRIVER
PULSE
GENERATOR
2
4
7
14
11
IN
VDD
GND
LO1
VB
HO1
VS
R
R
SQ
DRIVER
HS(ON/OFF)
LS(ON/OFF) DELAY
DT
UVLO
1
3
HO2
LO2
SCHMITT
TRIGGER INPUT
SHOOT THOUGH
PREVENTION
DEAD-TIME
{ DTMIN=330nsec }
NOISE
CANCELLER
SD
5
13
12
6
FAN7383 Rev:01
FAN7383 Half-Bridge Gate-Drive IC
© 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN7383 Rev. 1.0.3 4
Pin Configuration
Figure 4. Pin Configuration (Top View)
Pin Definitions
Pin # Name Description
1 IN Logic Input for Gate Driver
2SD
Logic Input for Shutdown (Active Low)
3 DT Programmable Dead-Time Control with External Resistor
4V
DD Low-Side Supply Voltage
5 LO1 Low-Side Driver Source Output
6 LO2 Low-Side Driver Sink Output
7 GND Ground
8 N.C. Not connected
9 N.C. Not connected
10 N.C. Not connected
11 VSHigh-Side Floating Supply Return
12 HO2 High-Side Driver Sink Output
13 HO1 High-Side Driver Source Output
14 VBHigh-Side Floating Supply
LO2
LO1
GND
NC
VS
FAN7383
IN
VDD
HO2
HO1
VB
DT
NC
NC
1
2
3
4
5
6
7
14
13
12
11
10
9
8
SD
FAN7383 Rev:00
FAN7383 Half-Bridge Gate-Drive IC
© 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN7383 Rev. 1.0.3 5
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the part s to these levels is not recommended. In
addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only. TA = 25°C unless otherwise specified.
Notes:
2. When mounted on 76.2 x 114.3 x 1.6mm PCB. (FR-4 glass epoxy material).
3. Please refer to:
JESD51-2: Integral circuits thermal test method environmental conditions - Natural convection
JESD51-3: Low effective thermal conductivity test board for leaded surface mount packages
4. Do not exceed PD under any circumstances.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol Parameter Min. Max. Unit
VSHigh-side offset voltage VB-25 VB+0.3 V
VBHigh-side floating supply voltage -0.3 625 V
VHO High-side floating output voltag e HO1, HO2 VS-0.3 VB+0.3 V
VDD Low-side and logic fixed supply voltage -0.3 25 V
VLO Low-side output voltage LO1, LO2 -0.3 VDD+0.3 V
VIN Logic input voltage (IN) -0.3 VDD+0.3 V
VSD Shutdown logic input voltage -0.3 VDD+0.3 V
VDT Dead-time control voltage -0.3 5.0 V
GND Logic ground VDD-25 VDD+0.3 V
dVS/dt Allowable offset voltage slew rate 50 V/ns
PD(2)(3)(4) Power dissipation 1.0 W
θJA Thermal resistance, junction-to-ambient 110 °C/W
TJJunction temperature 150 °C
TSTG Storage temperature 150 °C
Symbol Parameter Condition Min. Max. Unit
VBHigh-side floating supply voltage VS+15 VS+20 V
VSHigh-side floating supply offset voltage 6-VDD 600 V
VDD Low-side supply voltage 15 20 V
VHO High-side (HO) output voltage VS VBV
VLO Low-side (LO) output voltage GND VDD V
VIN Logic input voltage (IN) GND VDD V
TAAmbient temperature -40 125 °C
FAN7383 Half-Bridge Gate-Drive IC
© 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN7383 Rev. 1.0.3 6
Electrical Characteristics
VBIAS (VDD, VBS) = 15.0V, RDT = GND, TA = 25°C, unless otherwise specified. The VIN and IIN parameters are
referenced to GND. The VO and IO parameters are referenced to VS and GND and are applicable to the respective
outputs HO and LO.
Note:
5.This parameter guaranteed by design.
Symbol Parameter Condition Min. Typ. Max. Unit
SUPPLY CURRENT SECTION
IQBS Quiescent VBS supply current VIN=0V or 5V 35 90
μA
IQDD Quiescent VDD supply current VIN=0V or 5V, RDT=0Ω650 900
ISD(5) VDD supply current at shutdown mode SD=GND 650 900
IPBS Operating VBS supply current fIN=20kHz,rms valu e 400 700
IPDD Operating VDD supply current fIN=20kHz,rms value, RDT=0Ω950 1200
ILK Offset supply leakage current VB=VS=600V 10
POWER SUPPLY SECTION
VDDUV+
VBSUV+
VDD and VBS supply under-voltage
positive going threshold 10.7 11.6 12.5
V
VDDUV-
VBSUV-
VDD and VBS supply under-voltage
negative goi ng threshold 10.0 10.8 11.6
VDDUVH
VBSUVH
VDD and VBS supply under-voltage
lockout hysteresis 0.8
GATE DRIVER OUTPUT SECTION
VOH High-level output voltage, VBIAS-VOIO=20mA 1.0 V
VOL Low-level output voltage, VO0.6 V
IO+ Output high short-circuit pulse current VO=0V, VIN=5V with PW<10µs 250 350 mA
IO- Output low short-circuit pulsed current VO=15V, VIN=0V with PW<10µs 500 650 mA
VSAllowable negative VS pin voltage for IN
signal propagation to HO -9.8 -7.0 V
LOGIC INPUT SECTION (INPUT AND SHUTDOWN)
VIH Logic "1" input voltage 2.9 V
VIL Logic "0" input voltage 1.2 V
IIN+ Logic "1" input bias current VIN=5V 50 100 μA
IIN- Logic "0" input bias current VIN=0V 2.0 μA
SD+ Shutdown "1" inpu t voltage 1.2 V
SD- Shutdown "0" input voltage 2.9 V
RPD Input pull- do w n resi sta n c e 100 KΩ
FAN7383 Half-Bridge Gate-Drive IC
© 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN7383 Rev. 1.0.3 7
Dynamic Electrical Characteristics
VBIAS (VDD, VBS) = 15.0V, VS = GND, CL=1000pF, RDT = GND, and TA = 25°C, unless otherwise specified.
Note:
5.These parameters guaranteed by design.
Symbol Parameter Conditions Min. Typ. Max. Unit
tON Turn-on propagation delay VS=0V 500 670
ns
tOFF Turn-off propagation delay VS=0V or 600V(5) 170 250
tRTurn-on rise time 50 100
tFTurn-off fall time 30 80
tSD(5) Shutdown propagation delay 100 180
DT1,
DT2 Dead-time LO OFF to HO ON and HO
OFF to LO ON RDT=0Ω250 330 420 ns
RDT=200KΩ1.20 1.68 2.30 µs
DMT Dead-time matching RDT=0Ω060
ns
RDT=200KΩ0150
FAN7383 Half-Bridge Gate-Drive IC
© 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN7383 Rev. 1.0.3 8
Typical Characteristics
Figure 5. VDD/VBS UVLO (+) vs. Temperature Figure 6. VDD/VBS UVLO (-) vs. Temperature
Figure 7. VDD Quiescent Current vs. Temperature Figure 8. VBS Quiescent Current vs. Temperature
Figure 9. VDD Operating Current vs. Temperature Figure 10. VBS Operating Current vs. Temperature
-40 -20 0 20 40 60 80 100 120
10.8
11.0
11.2
11.4
11.6
11.8
12.0
VDDUV+ ,VBSUV+ [V]
Temperature [°C] -40 -20 0 20 40 60 80 100 120
10.0
10.2
10.4
10.6
10.8
11.0
11.2
11.4
11.6
VDDUV- ,VBSUV- [V]
Temperature [°C]
-40 -20 0 20 40 60 80 100 120
200
400
600
800
1000
IQDD [μA]
Temperat ure [° C] -40-200 20406080100120
0
20
40
60
80
100
IQBS [μA]
Temperature [°C]
-40 -20 0 20 40 60 80 100 120
400
600
800
1000
1200
1400
1600
IPDD [μA]
Temperat ure [° C] -40 -20 0 20 40 60 80 100 120
0
200
400
600
800
IPBS [μA]
Temperat ure [° C]
FAN7383 Half-Bridge Gate-Drive IC
© 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN7383 Rev. 1.0.3 9
Typical Characteristics (Continued)
Figure 11. Logic Input Current vs. Temperature Figure 12. Logic Input High Voltage vs. Temperature
Figure 13. Logic Input Low Voltage vs. Temperature Figure 14. SD Positive Threshold vs. Temperature
Figure 15. SD Negative Threshold vs. Temperature Figure 16. Rising Time vs. Temperature
-40 -20 0 20 40 60 80 100 120
0
20
40
60
80
100
IIN+ [μA]
Temperat ure [° C] -40-200 20406080100120
0.0
0.5
1.0
1.5
2.0
2.5
3.0
VIH [V]
Temperature [°C]
-40 -20 0 20 40 60 80 100 120
0.0
0.5
1.0
1.5
2.0
2.5
3.0
VIL [V]
Temperature [°C] -40-200 20406080100120
0.0
0.5
1.0
1.5
2.0
2.5
3.0
SD+ BAR [V]
Temperature [°C]
-40-200 20406080100120
0.0
0.5
1.0
1.5
2.0
2.5
3.0
SD- BAR [V]
Temperature [°C] -40 -20 0 20 40 60 80 100 120
0
20
40
60
80
100
tR [nsec]
Temperat ure [° C]
FAN7383 Half-Bridge Gate-Drive IC
© 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN7383 Rev. 1.0.3 10
Typical Characteristics (Continued)
Figure 17. Falling Time vs. Temperature Figure 18. Turn-on Delay Time vs. Temperature
Figure 19. Turn-off Falling Time vs. Temperature Figure 20. Dead-Time (RDT=0kΩ) vs. Temperature
Figure 21. Dead Time (RDT=200kΩ) vs. Temperature Figure 22. RDT vs. Dead Time
-40 -20 0 20 40 60 80 100 120
0
20
40
60
80
tF [nsec]
Temperature [°C] -40 -20 0 20 40 60 80 100 120
200
300
400
500
600
700
tON [nsec]
Temperat ure [° C]
-40-200 20406080100120
0
50
100
150
200
250
300
tOFF [nsec]
Temperature [°C] -40-200 20406080100120
240
280
320
360
400
DT1, RDT= 0Ω [nsec]
Temperature [°C]
-40 -20 0 20 40 60 80 100 120
1.2
1.4
1.6
1.8
2.0
2.2
2.4
DT1, RDT= 200kΩ [nsec]
Temperature [°C] 0 20 40 60 80 100 120 140 160 180 200
0.0
0.4
0.8
1.2
1.6
2.0
Deadtime [μS]
RDT [kohm]
FAN7383 Half-Bridge Gate-Drive IC
© 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN7383 Rev. 1.0.3 11
Typical Characteristics (Continued)
Figure 23. Allowable Negative VS Voltage for Signal
Propagation to High Side vs. Temperature
-40 -20 0 20 40 60 80 100 120
-14
-12
-10
-8
-6
VS [V]
Temperat ure [° C]
FAN7383 Half-Bridge Gate-Drive IC
© 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN7383 Rev. 1.0.3 12
Switching Time Definitions
Figure 24. Switching Time Test Circuit
Figure 25. Input / Output Waveforms
Figure 26. Switching Time Waveform Definitions
+15V
SD
LO1
GND
VB
VS
HO1
VDD
SD
IN
FAN7383 10μF 100nF
1nF
1nF
+15V 100nF10μF
DT
NC
9
10
8
11
14
12
13
6
5
7
4
1
3
2
LO2
NC
NC
HO2
HO1, 2
LO1, 2
FAN7383 Rev:00
IN
HO1, 2
LO1, 2
SD
DT1 DT2 DT1DT2 DT1
Shutdown Shutdown FAN7383 Rev:00
IN
HO1, 2
LO1, 2
10%
90%
50% 50%
90%
10%
tOFF
tOFF
tON
tON
FAN7383 R ev:00
FAN7383 Half-Bridge Gate-Drive IC
© 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN7383 Rev. 1.0.3 13
Figure 27. Shutdown Waveform Definition
Figure 28. Dead-Time Waveform Definition
90%
50%
tSD
HO or LO
SD
FAN7383 Rev:00
HO
10%
90%
DT1
LO
90%
10%
DT2
MDT= DT1-DT2
FAN7383 Rev:00
FAN7383 Half-Bridge Gate-Drive IC
© 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN7383 Rev. 1.0.3 14
Typical Application Information
1. Normal Operating Consideration
The FAN7383 is a single PWM input half-bridge gate-
drive IC with programmable dead-time and shutdown
function.
The dead-time is set with a resisto r (RDT) at the DT pin.
The wide dead-time programming range provides the
flexibility to optimi ze drive signal timing for a selection of
switching devices (MOSFET or IGBT) and applications.
The turn-on time delay circuitry (Dead-Time)
accommodates resistor values fro m 0Ω to 200kΩ with a
dead-time proportional to the RDT resistance.
Grounding the DT pin programs the FAN7383 to drive
both outputs with minimum dead time.
If the SD pin voltage decrease below 1.2V in normal
operation, the IC enters the shutdown mode.
2. Under-Voltage Lockout (UVLO)
The FAN7383 has an under-voltage lockout (UVLO)
protection circuitry for high and low side channels to
prevent malfunction when VDD or VBS is lower than the
specified threshold voltage. The UVLO circuitry monitors
the supply voltage (VDD) and b ootstrap capacitor voltage
(VBS) independently.
3. Layout Consideration
For optimum performance of high- and low-side gate
drivers, cannot be achieved without taking due
considerations must be taken during printed circuit board
(PCB) layout.
3.1 Supply Capacitors
If the output stages are able to quickly turn on the
switching device with high value of current, the supply
capacitors must be placed as close as possible to the
device pins (VDD and GND for the ground-tied supply, VB
and VS for the floating supply) to minimize parasitic
inductance and resistance.
3.2 Gate Drive Loop
Current loops behave like an antenna, able to receive
and transmit noise. To reduce the noise coupling/
emission and improve the power switch turn-on and off
performances, gate drive loops must be reduced as
much as possible.
3.3 Ground Plane
Ground plane must not be placed under or nearby the
high-voltage floating side to minimize noise coupling.
FAN7383 Half-Bridge Gate-Drive IC
© 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN7383 Rev. 1.0.3 15
Package Dimensions
14-SOP
Dimensions are in millimeters unless otherwise noted.
Figure 29. 14-Lead Small Outline Package (SOP)
January 2001, Rev. A
8.56
±0.20
0.337
±0.008
1.27
0.050
5.72
0.225
1.55
±0.10
0.061
±0.004
0.05
0.002
6.00
±0.30
0.236
±0.012
3.95
±0.20
0.156
±0.008
0.60
±0.20
0.024
±0.008
8.70
0.343 MAX
#1
#7 #8
0~8°
#14
0.47
0.019
()
1.80
0.071
MAX0.10
MAX0.004
MAX
MIN
+
0.10
-0.05
0.20
+
0.004
-0.002
0.008
+
0.10
-0.05
0.406
+
0.004
-0.002
0.016
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HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE
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As used herein:
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which, (a) are intended for surgical implant into the body or
(b) support or sustain life, and (c) whose failure to perform
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to
result in a significant injury of the user.
2. A critical component in any component of a life support,
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PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification Product Status Definition
Advance Information Formative or In Design This datasheet contains the design specifications for product
development. Specifications may change in any manner without notice.
Preliminary First Production This datasheet contains preliminary data; supplementary data will be
published at a later date. Fairchild Semiconductor reserves the right to
make changes at any time without notice to improve design.
No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor
reserves the right to make changes at any time without notice to improve
design.
Obsolete Not In Production This datasheet contains specifications on a product that has been
discontinued by Fairchild Semiconductor. The datasheet is printed for
reference information only.
Rev. I23
FAN7383 Half-Bridge Gate-Drive IC
© 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN7383 Rev. 1.0.3 16
