MT45W4MW16BCGB-708WTTR - Micron Technology

Products and specifications discussed herein are subject to change by Micron without notice.

64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory

Features

PDF: 09005aef8247bd51/Source: 09005aef8247bd83 Micron Technology, Inc., reserves the right to change products or specifica tions without notice.

Async/Page/Burst CellularRAM® 1.5 Memory

MT45W4MW16BCGB

Features

• Si ngle device supports asynchr o nous, page, and

burst operations

•V

CC, VCCQ voltages:

–1.7–1.95V VCC

–1.7–3.3V VCCQ1

• Random access time: 70ns

• Burst mode READ and WRITE access

–4, 8, 16, or 32 words or continuous burst

–Burst wrap or sequential

–MAX clock rate: 133 MHz1 (tCLK = 7.5ns)

–Burst initial latency: 37.5ns (5 clocks) at 133 MHz

–tACLK: 5.5ns at 133 MHz

• Page mode read access

–16-word page size

–Interpage read access: 70ns

–Intrapage read access: 20ns

•Low power consumption

–Asynchronous READ: <25mA

–Intrap age READ: <15 mA

–Initial access , burst READ:

(37.5ns [5 clocks] at 133 MHz) <45mA

–Continuous burst READ: <40mA

–Standby: <50µA (TYP at 25°C)

–Deep power-down (DPD): <3µA (TYP)

•Low-power features

–On-chip temperature-compensated refresh (TCR)

–Partial-array refresh (PAR)

–DPD mode

Options Designator

• Configuration: MT45W4MW16BC

4 Meg x 16

VCC core voltage supply:

1.7–1.95V

VCCQ I/O voltage supply:

1.7–3.3V1

•Package

54-ball VFBGA (“green”) GB

•Access time

70ns -70

• Frequency: 133 MHz 13

104 MHz 1

80 MHz 8

Figure 1: 54-Ball VFBGA Ball Assignment

Notes: 1. The 3.3V I/O voltage and 133 MHz clock fre-

quency exceed the Ce llularRAM 1.5 Work-

group spec ification.

Part Num ber Example:

MT45W4MW16BCGB-701LWT

Options (continued) Designator

• Standby power at 85°C

–Standard: 140µA (MAX) None

–Low power: 120µA (MAX) L

• Operating temperature range

–Wireless (–30°C to +85°C) WT

–Industrial (–40°C to +85°C) IT

1 2 3 4 5 6

Top view

(Ball down)

LB#

DQ8

DQ9

VSSQ

VCCQ

DQ14

DQ15

A18

WAIT

OE#

UB#

DQ10

DQ11

DQ12

DQ13

A19

CLK

A17

A21

A14

A12

ADV#

CE#

DQ1

DQ3

DQ4

DQ5

WE#

A11

RFU

CRE

DQ0

DQ2

VCC

VSS

DQ6

DQ7

A20

RFU

A16

A15

A13

A10

RFU

PDF: 09005aef8247bd51/Source: 09005aef8247bd83 Micron Technology, Inc., reserves the right to change products or specifica tions without notice.

64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory

Table of Contents

Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

Part-Numbering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Valid Part Number Combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Device Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Power-Up Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Bus Operating Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Asynchronous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Page Mode READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Burst Mode Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Mixed-Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

WAIT Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

LB#/UB# Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

Low-Power Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Standby Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Temperature-Compensated Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Partial-Array Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Deep Power-Down Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Access Using CRE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Software Access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Bus Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

Burst Wrap (BCR[3]) Default = No Wrap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

Drive Strength (BCR[5:4]) Default = Outputs Use Half- Drive Strengt h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

WAIT Configuration (BCR[8]) Default = WAIT Transitions One Clock Before Data Valid/Invalid . . . . . . . . .27

WAIT Polarity (BCR[10]) Default = WAIT Active HIGH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Latency Counter (BCR[13:11]) Default = Three Clock Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Initial Access Latency (BCR[14]) Default = Variable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Operating Mode (BCR[15]) Default = Asynchronous Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Refresh Configuration Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Partial-Array Refresh (RCR[2:0]) Default = Full Array Refresh. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Deep Power-Down (RCR[4]) Default = DPD Disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Page Mode Operation (RCR[7]) Default = Disabled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Device Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Timing Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

Timing Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69

PDF: 09005aef8247bd51/Source: 09005aef8247bd83 Micron Technology, Inc., reserves the right to change products or specifica tions without notice.

64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory

List of Figur es

List of Figures

Figure 1: 54-Ball VFBGA Ball Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

Figure 2: Fun cti onal Block D iagram – 4 Meg x 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

Figure 3: Part Number Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Figure 4: Power-Up Initialization Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Figure 5: READ Operation (ADV# LOW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Figure 6: WRITE Operation (ADV# LOW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Figure 7: Page Mode READ Operation (ADV# LOW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Figure 8: Burst Mode READ (4-Word Burst) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Figure 9: Burst Mode WRITE (4-Word Burst) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Figure 10: Wired-OR WAIT Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

Figure 11: Refresh Collision During Variable-Latency READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

Figure 12: Configuration Register WRITE, Asynchronous Mode Followed by READ ARRAY . . . . . . . . . . . . . . . .19

Figure 13: Configuration Register WRITE, Synchronous Mode Followed by READ ARRAY Operation . . . . . . .20

Figure 14: Register READ, Asynchronous Mode Followed by READ ARRAY Operation . . . . . . . . . . . . . . . . . . . .21

Figure 15: Register READ, Syn chronous Mode Followed by READ ARRAY Operation . . . . . . . . . . . . . . . . . . . . .22

Figure 16: Load Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Figure 17: Read Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Figure 18: Bus Configuration Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

Figure 19: WAIT Configuration (BCR[8] = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Figure 20: WAIT Configuration (BCR[8] = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Figure 21: WAIT Configuration During Burst Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Figure 22: Latency Counter (Variable Initial Latency, No Refresh Collision) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Figure 23: Latency Counter (Fixed Latency) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Figure 24: Refresh Configuration Register Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Figure 25: Typical Refresh Current vs. Temperature (ITCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Figure 26: AC Input/Output Reference Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

Figure 27: AC Output Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

Figure 28: Initialization Period . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

Figure 29: DPD Entry and Exit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

Figure 30: Asy nchronous READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

Figure 31: Asy nchronous READ Using ADV# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

Figure 32: Page Mode READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

Figure 33: Single-Access Burst READ Operation – Variable Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46

Figure 34: 4-Word Burst READ Operation – Variable Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

Figure 35: Single-Acc es s Bu rs t REA D Ope r ati o n – Fixed Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48

Figure 36: 4-Word Burst READ Operation – Fixed Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

Figure 37: READ Burst Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

Figure 38: Burst READ at End-of-R ow (Wrap Off) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

Figure 39: CE#-Controlled Asynchronous WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52

Figure 40: LB#/UB#-Controlled Asynchronous WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

Figure 41: WE#-Controlled Asynchronous WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

Figure 42: WE#-Controlled Asynchronous WRITE Using ADV# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

Figure 43: Burst WRITE Operation – Variable Latency Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56

Figure 44: Burst WRITE Operation – Fixed Latency Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

Figure 45: Burst WRITE at End of Row (Wrap Off) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58

Figure 46: Burst WRITE Followed by Burst READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

Figure 47: Burst READ Interrupted by Burst READ or WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

Figure 48: Burst WRITE Interrupted by Burst WRITE or READ – VariableLatency Mode . . . . . . . . . . . . . . . . . .61

Figure 49: Burst WRITE Interrupted by Burst WRITE or READ – Fixed Latency Mode . . . . . . . . . . . . . . . . . . . . .62

Figure 50: Asynchronous WRITE Followed by Burst READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63

Figure 51: Asynchronous WRITE (ADV# LOW) Followed by Burst READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64

Figure 52: Burst READ Followed by Asynchronous WRITE (WE#-Controlled) . . . . . . . . . . . . . . . . . . . . . . . . . . . .65

Figure 53: Burst READ Followed by Asynchronous WRITE Using ADV# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66

Figure 54: Asynchronous WRITE Followed by Asynchronous READ – ADV# LOW . . . . . . . . . . . . . . . . . . . . . . . .67

Figure 56: 54-Ball VFBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69

PDF: 09005aef8247bd51/Source: 09005aef8247bd83 Micron Technology, Inc., reserves the right to change products or specifica tions without notice.

64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory

List of Tables

Table 1: VFBGA Ball Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

Table 2: Bus Operations – Asynchronous Mode (BCR[15] = 1; Default). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

Table 3: Bus Operations – Burst Mode (BCR[15] = 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Table 4: Sequence and Burst Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

Table 5: Drive Strength . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Table 6: Variable Latency Configuration Codes (BCR [14] = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Table 7: Fixed Latency Configuration Codes (BCR[14] = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Table 8: 64Mb Address Patterns for PAR (RCR[4] = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Table 9: Device Identification Register Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Table 10: Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Table 11: Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Table 12: Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Table 13: Partial-Array Refres h Spec ifications and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Table 14: Deep Power-Down Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Table 15: Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

Table 16: Asynchronous READ Cycle Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

Table 17: Burst READ Cycle Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

Table 18: Asynchronous WRITE Cycle Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

Table 19: Burst WRITE Cycle Tim ing Requ irem e n ts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

Table 20: Initialization Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

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64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory

General Description

Micron® CellularRAM® products ar e hig h-s pe ed, CMOS memory devices deve loped for

low-po wer, portable applications. The MT45W4MW1 6BCG B is a 64Mb DRAM core

device, organized as 4 Meg x 16 bits. This device includes an industry-standard burst

mode Flash interface that dramatically incre a ses read/write bandw idth compared with

other low-po wer SRAM or pseudo-SRAM (PSRAM) offerings.

For seamless operation on a burst Flash bus, CellularRAM products incorporate a trans-

parent self refresh mechanism. The hidden refresh re quires no additional support from

the system memory controller and has no significant impac t on de vic e read/write

performance.

Two user-accessible control registers define device operation. The bus configuration

bus and is nearly identical to its counterpart on burst mode Flash devices. The refresh

configuration register (RCR) is used to control how refresh is performed on the DRAM

array. These registers are automatically loaded with default settings duri ng power-up

and can be updated anytime during normal operatio n.

S p ecial attention has been focused on stand by current consumption during self refresh.

CellularRAM products include three mechanisms to minimize standby current. Partial-

array refresh (PAR) enables the system to limit refr esh to only that part of the DRAM

array that contains essential data. Temperature-compensated refresh (TCR) uses an on-

chip sensor to adjust the refresh rate to match the device temperature— the refresh rate

decreases at lower temperatures to minimize current consumption during standby.

Deep power-down (DPD) enables the system to halt the r efresh operation altogether

when no vital information is stored in the device. The system configurable r efr esh mech-

anisms are accessed through the RCR.

This CellularRAM device is co mpliant with the industry-standar d CellularRAM 1.5

feature set established by the CellularRAM Workgroup. I t includes su pport for bot h vari-

able and fixed latency, with three output-device drive-strength settings, additional wrap

options, and a device ID register (DIDR).

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64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory

General Description

Figure 2: Functional Block Diagram – 4 Meg x 16

Note: Functional block diagrams ill ustrate simplified device operation. For detailed information,

see ball descriptions in Table 1 on page 7; bus operations in Table 2 on page 8, Table 3 on

page 9, and Table 2 on page 8; and timing diagrams starting on page 42.

A[21:0] Input/

output

MUX

and

buffers

Control

logic

4,096K x 16

DRAM

memory

array

CE#

WE#

OE#

CLK

ADV#

CRE

WAIT

LB#

UB#

DQ[7:0]

DQ[15:8]

Address decode

logic

Refresh configuration

Device ID register

(DIDR)

Bus configuration

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64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory

General Description

Note: The CLK and ADV# inputs can be tied to VSS if the device is always oper ating in asynchro-

nous or page mo de. WAIT will be asserted, but should be ignored during asynchronous

and page mode operations.

Table 1: VFBGA Ball Descriptions

VFBGA

Assignment Symbol Type Description

E3, H6, G2, H1,

D3, E4, F4, F3,

G4, G3, H5, H4,

H3, H2, D4, C4,

C3, B4, B3, A5,

A4, A3

A[21:0] Input Address in puts: Inputs for addresse s during READ and WRITE operations.

Addresses are internally latched during READ and WRITE cycles. The address lines

are also used to define the value to be loaded into the BCR or the RCR.

J2 CLK Input Clock: Synchronizes the memory to the system operating frequency during

synchronous o perations. When configured for synchronous operation, the address

is latched on the first rising CLK edge when ADV# is active. CLK must be static

LOW during asynchronous access READ and WRITE operations and during PAGE

READ ACCESS operations.

J3 ADV# Input Address valid: Indicates that a valid address is present on the address inputs.

Addresses ca n be latched on the rising edge of ADV# during asynchronous READ

and WRITE operat ions. ADV# can be held LOW du ring asynchronous READ and

WRITE operations.

A6 CRE Input Control register enable: When CRE is HIGH, WRITE operations load the RCR or

BCR, and READ operations access the RCR, BCR, or DIDR.

B5 CE# Input Chip enable: Activates the device when LOW. When CE# is HIGH, the device is

disabled and goes into standby or DPD mode.

A2 OE# Input Output enable: Enables the output buffers when LOW. When OE# is HIGH, the

output buffers are disabled.

G5 WE# Input Write enable: Determines whether a given cycle is a WRITE cycle. If WE# is LOW,

the cycle is a WRITE either to a configuration register or to the memory array.

A1 LB# Input Lower byte enable. DQ[7:0]

B2 UB# Input Upper byte enable. DQ[15:8]

G1, F1, F2, E2,

D2, C2, C1, B1,

G6, F6, F5, E5,

D5, C6, C5, B6

DQ[15:0] Input/

Output Data inputs/outputs.

J1 WAIT Output Wait: Prov ides data-valid feedback during burst READ and WRITE operations. The

signal is gated by CE#. WAIT is used to arbitrate collisions between refresh and

READ/WRITE operations. W AIT is asserted at the end of a row unless wrapping

within the burst length. WAIT is asserted and shoul d be ignored during

asynchronous and page mode operations. WAIT is High-Z when CE# is HIGH.

J4, J5, J6 RFU – Reserved for future use.

D6 VCC Supply Device power supply (1.7–1.95V): Power supply for device core operati on.

E1 VCCQ Supply I/O power supply (1.7–3.3V): Power supply for input/output buffers.

E6 VSS Supply VSS must be connected to ground.

D1 VSSQ Supply VSSQ must be connected to ground.

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64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory

General Description

Notes: 1. CLK must be LOW during asynchronous read and asynchronous write modes and to achieve

standby power duri ng standby and DPD modes. CLK must be static (HIGH or LOW) during

burst suspend.

2. The WAIT polarity is configured throug h the bus configuration register (BCR[10]).

3. When LB# and UB# are in select mode (LOW), DQ[15:0] are enabled. When only LB# is in

select mode, DQ[7:0] are enabled. When only UB# is in the select mode, DQ[15:8] are

enabled.

Table 2: Bus Operations – Asynchronous Mode (BCR[15] = 1; Default)

Mode Power CLK1ADV# CE# OE# WE# CRE LB#/

UB# WAIT2DQ[15:0]3Notes

Read Active L L L L H L L Low-Z Data-out 4

Write Active L L L X L L L Low-Z Data-in 4

Standby Standby L X H X X L X High-Z High-Z 5, 6

No operation Idle L X L X X L X Low-Z X 4, 6

Configuration

reg. out

DPD Deep power-down L X H X X X X High-Z High-Z 7

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64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory

General Description

Notes: 1. CLK must be LOW during asynchronous read and asynchronous write modes and to achieve

standby power duri ng standby and DPD modes. CLK must be static (HIGH or LOW) during

burst suspend.

2. The WAIT polarity is configured throug h the bus configuration register (BCR[10]).

3. When LB# and UB# are in select mode (LOW), DQ[15:0] are enabled. When only LB# is in

select mode, DQ[7:0] are enabled. When only UB# is in the select mode, DQ[15:8] are

enabled.

4. The device will consume active power in this mode whenever addresses are changed.

5. When the device is in standby mode, addres s inputs and data inputs/outputs are internally

isolated from any external influence.

6. VIN = VCCQ or 0V; all device balls must be static (unswitched) to achieve standby current.

7. DPD is initiated when CE# transitions from LOW to HIGH after writing RCR[4] to 0. DPD is

maintained until CE# transitions from HIGH to LOW and is held LOW for tDPDX.

8. Burst mode operation is initiali zed through the bus configuration register (BCR[15]).

9. Initial cycle. Following cycles are the same as BURST CONTINUE. CE# must stay LOW for the

equivalent of a single-word burst (as indicated by WAIT).

Table 3: Bus Operations – Burst Mode (BCR[15] = 0)

Mode Power CLK1ADV# CE# OE# WE# CRE LB#/

UB# WAIT2DQ[15:0]3Notes

Asynchronous

read Active L L L L H L L Low-Z Data-out 4

Asynchronous

write Active L L L X L L L Low-Z Data-in 4

Standby Standby L X H X X L X High-Z High-Z 5, 6

No operation Idle L X L X X L X Low-Z X 4, 6

Initial burst

read Active L L X H L L Low-Z X 4, 8

Initial burst

write Active L L H L L X Low-Z X 4, 8

Burst

continue Active H L X X X L Low-Z Data-in or

data-out 4, 8

Burst suspend Active X X L H X X X Low-Z High-Z 4, 8

Configuration

out 8, 9

DPD Deep power-down L X H X X X X High-Z High-Z 7

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64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory

Part-Numbering Information

Micron CellularRAM devices are available in several different configurations and densi-

ties (see Figure 3).

Figure 3: Part Number Chart

Valid Part Number Combinations

After building the part number from the part numbering chart above, visit the Micron

Web site at www.micron.com/support/designsupport/tools/fbga/decoder to verify that

the part number is offered and val id. If the device required is not on this list, contact the

factory.

Device Marking

Due to the size of the package, the Micron standard part number is not printed on the

top of the device. Instead, an abbreviated device mark consisting of a five-digit alphanu-

meric code is used. The abbreviated device marks are cr oss-referenced to the Micron

part numbers at www.micron.com/support/decoder. To view the location of the abbre-

viated mark on the device, refer to customer service note CSN-11, “Product Mark/

Label,” at www.micron.com/support/designsupport/documents/csn.

MT 45

W 4M W 16 BC GB

-70 8 WT ES

Micron Technology

Product Family

45 = PSRAM/CellularRAM memory

Operating Core Voltage

W = 1.7–1.95V

Address Locations

M = Megabits

Operating Voltage

W = 1.7–3.3V1

Bus Configuration

16 = x16

READ/WRITE Operation Mode

BC = Asynchronous/page/burst

Package Codes

GB = 54-ball VFBGA “green” (6 x 9 grid, 0.75mm pitch, 6.0mm x 8.0mm x 1.0mm)

Production Status

Blank = Production

ES = Engineering sample

MS = Mechanical sample

Operating Temperature

WT = –30°C to +85°C

IT = –40° to +85°C

Standby Power Options

Blank = Standard

L = Low power

Frequency

8 = 80 MHz

1 = 104 MHz

13 = 133 MHz

Access/Cycle Time

70 = 70ns

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64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory

Functional Description

In general, the MT45W4MW16BCGB device is a high -d ensity alterna tive to SRA M an d

PSRAM products, popular in low-power, portable applications.

The MT45W4MW16BCGB contains a 67,108,864-bit DRAM core , organized as 4,194,304

addresses by 16 bits. The device implements the same high-speed bus interface found

on burst mode Flash products.

The CellularRAM bus interface supports both asynchronous and burst mode transfers.

Page mode accesses are also included as a bandwidth-enhancing extension to the asyn-

chronous read protocol.

Power-Up Initialization

CellularRAM products include an on-chip voltage sensor used to launch the power-up

initialization process. I nitialization will configure the BCR and the R CR with their default

settings (see Figure 18 on page 25 and Figure 24 on page 31). VCC and VCCQ must be

applied simultaneously. When they reach a stable level at or above 1.7V, the device will

require 150µs to complete its self-initialization process. During the initialization period,

CE# should remain HIGH. When initialization is complete, the device is ready for

normal operation.

Figure 4: Power-Up Initialization Timing

Bus Operating Modes

The MT45W4MW16BCGB CellularRAM product incorporates a burst mode in terface

found on Flash products targeting low-power, wireless applications. This bus interface

supports asynchronous, page mode, and burst mode read and write transfers. The

specific in te rface suppor ted is defined by the value loaded into th e B C R. Page mode is

controlled by the refresh configuration register (RCR[7]).

Asynchronous Mode

CellularRAM products power up in the asynchronous operating mode. This mode uses

the industry-standard SRAM control bus (CE#, OE#, WE#, LB#/UB#). READ operations

(Figure 5 on page 12) are initi a ted by bringing CE#, OE#, and LB#/ UB# LOW while

keeping WE# HIGH. Valid data will be driven out of the I/Os after the specified access

time has elapsed. WRITE operations (Figure 6 on page 12) occur when CE#, WE#, and

LB#/UB# are driven LOW. During asynchronous WRITE operations, the OE# level is a

“Don’t Care,” and WE# will override OE#. The data to be written is latched on the rising

edge of CE#, WE#, or LB#/UB# (whichever occurs first). Asynchronous operations (page

mode disabled) can use the ADV input to latch the addre ss or can drive AD V L O W during

the entire REA D/WRITE operation.

During asynchronous operation, the CLK input must be held static LOW. WAIT will be

driven while the device is enabled, and its st ate should be ignored. WE# LOW time must

be limited to tCEM.

Vcc

VccQ Device initialization

Vcc = 1.7V Device ready for

normal operation

tPU > 150µs

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64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory

Bus Operating Modes

Figure 5: READ Operation (ADV# LOW)

Note: ADV must remain LOW for page mode operation.

Figure 6: WRITE Operation (ADV# LOW)

Valid address

Data

CE#

Don’t Care

Valid data

OE#

WE#

LB#/UB#

tRC = READ cycle time

Address

Valid address

Data

CE#

Don’t Care

Valid data

OE#

WE#

LB#/UB#

tWC = WRITE cycle time

Address

< tCEM

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64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory

Bus Operating Modes

Page Mode READ Operation

Page mode is a performance-enhancing extension to the legacy asynchronous READ

operation. In page-mode-capable products, an initial asynchronous read access is

performed, and then adjacent addresses can be read quickly by simply changing the

low-order address. Addresses A[3:0] are used to determine the members of the 16-

addre ss Ce llularRAM page . Any change in addresses A[4] or higher will initiate a new tAA

access time. Figure 7 shows the timing for a page mode access. Page mode takes adv a n-

tage of the fact that adjacent addresses can be read in a shorter period of time than

random addresses. WRITE operations do not include comparable page mode function-

ality.

During asynchronous page m ode operation, the CLK input must be held L O W. CE# must

be driven HIGH upon completion of a page mode access. WAIT will be driven while the

device is enabled, and its state should be ignored. Page mode is enabled by setting

R C R[7] to HIGH. ADV must be driven LOW during all page mode read accesses.

Due to refresh considerations, CE# must not remain LOW longer than tCEM.

Figure 7: Page Mode READ Operation (ADV# LOW)

Burst Mode Operation

Burst mode operations enable high-s pe ed synchronous READ and WRITE operations.

Burst operations consist of a multiclock sequence that must be performed in an ordered

fashion. After CE# goes LOW, the address to access is latched on the rising edge of the

next clock that ADV# is LOW. During this first clock rising edge, WE# indicates whether

the operation is going to be a READ (WE# = HIGH, Figure8 on page 14) or a WRITE

(WE# = LOW, Figure9 on page 15).

The size of a burst can be specified in the BCR either as a fixed-length or continuous.

Fixed-length bursts consist of 4, 8, 16, or 32 words . Continuous bursts have the ability to

start at a specified address and burst to the end of the 128-word row.

The latency count stored in the BCR defines the number of clock cycles that elapse

before the initial data value is transferred between the processor and the CellularRAM

device. The initial latency for READ operations can be configured as fixed or variable

Data

CE#

Don’t Care

OE#

WE#

LB#/UB#

Address Add[0] Add[1] Add[2] Add[3]

D[1] D[2] D[3]

tAA tAPA

< tCEM

tAPA tAPA

D[0]

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64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory

Bus Operating Modes

(WRITE oper ations always use fixed l atency). Variable latency allo ws the C ellul arRA M to

be configured for minimum latency at high clock frequencies, but the controller must

monitor WAIT to detect any conflict with refresh cycles.

Fixed latency outputs the first data word after the worst-case access delay, including

allowance for r efresh collisions. The initial latency time and clock speed determine the

latency count setting. Fixed latency is used when the controller cannot monitor WAIT.

Fixed latency also provides improved performance at lower clock frequencies.

The W AIT output asserts when a burst is initiated and de-asserts to indicate when data is

to be transferred into or out of memory. W AIT will again be asserted at the boundary of

the 128-word row, unless wrapping within the burst length.

To access other devices on the same bus wi th out the timing penalty of the initial latency

for a new burst, burst mode can be suspended. Bursts are suspended by stopping CLK.

CLK can be stoppe d HIGH or LO W. If another device will use the data bus while the burst

is suspended, OE# should be taken HIGH to disable the CellularRAM outputs; otherwise,

OE# can remain LOW. Note that the WAIT output will continue to be active and, as a

result, no other devices should directly share the WAIT connection to the controller. To

continue the burst sequence, OE# is taken LOW, and then CLK is restarted after valid

data is available on the bus.

The CE# LOW time is limited by refresh considerations. CE# must not stay LOW longer

than tCEM. If a burst suspension will cause CE# to remain LOW for longer than tCEM,

CE# should be taken HIGH and the burst should be r estarted with a new CE# LO W/AD V#

LOW cycle.

Figure 8: Burst Mode READ (4-Word Burst)

Note: Nondefault BCR settings for burst mode READ (4-word burst): fixed or variable latency;

latency code 2 (3 clocks); WAIT active LOW ; W AIT asserted during delay. Figure 8 is repre-

sentative of variable latency with no refresh collision or fixed-latency access.

A[21:0]

ADV#

CE#

OE#

D1 D2 D3

WE#

WAIT

DQ[15:0]

LB#/UB#

Latency code 2 (3 clocks)

CLK

UndefinedDon’t Care

READ burst identified

(WE# = HIGH)

Valid

address

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64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory

Bus Operating Modes

Figure 9: Burst Mode WRITE (4-Word Burst)

Note: Nondefault BCR settings for burst mode WRITE (4-word burst): fixed or variable latency;

latency code 2 (3 clocks); WAIT active LOW; WAIT asserted during delay.

Mixed-Mode Operation

The device supports a combination of synchronous READ and asynchronous READ and

WRITE operations when the BCR is configured for synchronous operation. The asyn-

chronous READ and WRITE operations require that the clock (CLK) remain LOW during

the entire sequence. The ADV# signal can be used to latch the target addr ess, or it can

remain LOW during the entire WRITE operation. CE# can remain LOW when transi-

tioning between mixed-mode operations with fixed latency enabled; however, the CE#

LO W time must not ex ceed tCEM. M ixed-mode operati on facilitates a seamless interface

to legacy burs t mode Flash memory controllers. See Figure50 on page 63 for the “Asyn-

chronous WRITE Followed by Burst READ” timing diagram.

WAIT Operation

The WAIT output on a CellularRAM device typically is connected to a shared, system-

level WAIT signal (see Figure 10 on page 16). The shared WAIT signal is used by the

processor to coordinate tr ansactions with multiple memory devices on the synchronous

bus.

A[21:0]

ADV#

CE#

OE#

D1 D2 D3

WE#

WAIT

DQ[15:0]

LB#/UB#

Valid

address

Latency code 2 (3 clocks)

CLK

Don’t Care

WRITE burst identified

(WE# = LOW)

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64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory

Bus Operating Modes

Figure 10: Wired-OR WAIT Configuration

When a READ or WRITE operation has been initiated, WAIT goes active to indicate that

the CellularRA M device requires additional time before data can be transferred. For

READ operations, WAIT will remain active until valid data is output from the device. For

WRITE operations, WAIT will indicate to the memory controller when data will be

accepted into the CellularRAM device. When WAIT transitions to an inactive state, the

data burst will progress on successive clock edge s.

During a burst cycle, CE# must remain asserted until the first data is valid. Bringing CE#

HIGH during this initial latency may cause data corrup tion.

When variable initial access latency is used (BCR[14] = 0), the WAIT output performs an

arbitration role for READ operations launch e d whil e an on-c hip refres h is in p rogress. If

a collision occurs , WAIT is asserted for additional clock cycles until the refresh has

completed (see Fig ur e11 on page17). When the refresh operation has completed, the

READ operation will continue norm all y.

WAIT will be asserted but should be ignored duri ng asynchronous READ, WRITE, and

PR OGRAM operations.

By using fixed initial latency (BCR[14] = 1), this CellularRAM device can be used in burst

mode without monitoring the WAIT signal. However, WAIT can still be used to deter-

mine when valid data is av ailab le at the start of the burst and at the end of a row. If W AIT

is not monitored, the controller must stop burst accesses at row boundaries on its own.

LB#/UB# Operation

The LB# enable and UB# enable signals support byte-wide data WRITEs. During WRITE

operations, any disabled by tes will not be transferred to the RAM array, and the internal

value will remain unchanged. During an asynchronous WRITE cycle, the data to be

written is latched on the rising edge of CE#, WE#, LB#, or UB#, whichever occurs first.

LB#/UB# must be L OW during READ cycles.

When both LB# and U B# are disabled (HI GH) during an operation, the device will

disable the data bus from receiving or transmitting data. Although the device will seem

to be deselecte d, it remains in an active mode as long as CE# remains LOW.

CellularRAM External

pull-up/

pull-down

resistor

Processor

READY

Other

device

WAIT

Other

device

WAIT

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64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory

Bus Operating Modes

Figure 11: Refresh Collision During Variable-Latency READ Operation

Note: Nondefault BCR settings for refresh collision during variable-latency READ operation:

latency code 2 (3 clocks); WAIT active LOW; WAIT asserted during delay.

A[21:0]

ADV#

CE#

OE#

WE#

WAIT

DQ[15:0]

CLK VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VOH

VOL

VOH

VOL

D2D1 D3

Valid

address

Additional WAIT states inserted to allow refresh completion

LB#/UB#

Undefined Don’t Care

High-Z

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64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory

Low-Power Operation

Standby Mode Operation

During standby, the device current consumption is reduced to the level necessary to

perform the DRAM refresh operation. Standby operation occurs when CE# is HIGH.

The device will enter a reduced power state upon completion of a READ or WRITE oper-

ation or when the address and control inputs remain static for an extended period of

time. This mode will continue until a change occurs to the address or control inputs.

Temperature-Compensated Refresh

Temperature-compensated refresh (TCR) allows for adequate refresh at differe nt

temperatures. This CellularRAM device includes an on-chip temperature sensor that

automatically adjusts the refresh rate according to the operating temperature.

Partial-Array Refresh

Partial-array r ef resh (PAR) restricts refresh operation to a portion of the total memory

array. This feature enables the device to reduce standby curre nt by refreshing only that

part of the memory array required by the host system. The refresh options are full array,

one-half array, one-quarter array, one-eighth array, or none of the array. The mapping of

these partitions can start either at the beginning or the end of the address map (see

Table 8 on page 32). READ and WRITE operations to addr ess r anges r eceiving r efresh will

not be affected. Data stored in address es not receivi n g refresh will become corrupted .

When reenabling additional portions of the array, the new portions are available imme-

diately upon writing to the RCR.

Deep Power-Down Operation

Deep power-down (DPD) operation disables all refresh-related activity. This mode is

used if the system does not require the stor age provided by the CellularRAM device. Any

stor ed data will become corrupted when DPD is enabled. When r efr esh activity has been

reenabled by rewriting, the CellularRAM device will require 150µs to perform an initial-

ization procedure before normal operations can resume. During this 150µs period, the

current consumption will be higher than the specified stand by levels but considerably

lower than the active current specification.

DPD can be enabled by writing to the RCR using CRE or the software access sequence;

DPD starts when CE# goes HIGH. DPD i s disabled the next time CE# goes LO W and stays

LOW for at least 10µs.

Registers

Two user-acce ssible configurati o n registers define the device operation. The bus config-

uration r egister (BCR) defines how the CellularRAM inter acts with the system memory bus

and is nearly identical to its counterpart on burst mode Flash devices. The r efr esh configu-

ration register (RCR) i s used to control how refresh is performed on the DRAM array.

These registers are automatically loaded with defaul t setti n gs during power-up and can

be updated any time the devices are operating in a standby state.

The DIDR provides information on the device manufacturer, the CellularRAM genera-

tion, and the specific devic e confi guration. The DIDR is read-only.

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64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory

Registers

Access Using CRE

The reg isters can be accessed either using a synchronous or an asynchronous operation

when the control r egiste r enable (CRE) input is HIGH (see Figur es12 through 15). When

CRE is LOW, a READ or WRITE operation will access the memory array. The configura-

tion register values are written via addresses A[21:0]. In an asynchronous WRITE, the

values are latched into the configur ation register on the rising ed ge of ADV#, CE#, or

WE#, whichever occurs first; LB# and UB# are “Don’t Care.” The BCR is accessed when

A[19:18] are 10b; the RCR is accessed when A[19:18] are 00b. The DIDR is read when

A[19:18] are 01b. For reads, address inputs other than A[19:18] are “Don’t Care,” and

memory array immediately after performing a configuration register READ and WRITE

operation.

Figure 12: Configuration Register WRITE, Asynchronous Mode Followed by READ ARRAY

Notes: 1. A[19:18] = 00b to load RCR and A[19:18] = 10b to load BCR.

A[21:0]

(except A[19:18]) OPCODE Address

Address

Valid data

A[19:18]1

ADV#

CE#

OE#

WE#

LB#/UB#

DQ[15:0]

Initiate control register access

Write address bus value

to control register

CRE

tAVS tAVH

tAVH

tAVS

tVP

tVPH

tCBPH

tWP

tCW

Don’t Care

Select control register

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64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory

Registers

Figure 13: Configuration Register WRITE, Synchronous Mode Followed by READ ARRAY Operation

Notes: 1. Nondefault BCR settings for synchronous mode configuration register WRITE followed by

READ ARRAY operation: latency code 2 (3 clocks ); WAIT active LOW; WAIT asserted during

delay.

2. A[19:18 ] = 00b to load RCR and A[19:18] = 10b to load BCR.

3. CE# must remain LOW to complete a burst-of-one WRITE. WAIT must be monitored—addi-

tional WAIT cycles caused by refresh collisions require a corresponding number of addi-

tional CE# LOW cycle s .

CLK

A[21:0]

(except A[19:18])

A[19:18]2

CRE

ADV#

CE#

OE#

WE#

LB#/UB#

WAIT

DQ[15:0]

tSP

tHD

tCSP

tSP tHD

High-Z

Don’t Care

OPCODE Address

High-Z

tCEW

Latch control register value

Latch control register address

tCBPH

Valid

data

Address

Note 3

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64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory

Registers

Figure 14: Register READ, Asynchronous Mode Followed by READ ARRAY Operation

Notes: 1. A[19:18] = 00b to read RCR, 10b to read BCR, and 01b to read DIDR.

A[21:0]

(except A[19:18]) Address

Address

Valid data

Valid CR

A[19:18]1

ADV#

CE#

OE#

WE#

LB#/UB#

DQ[15:0]

Initiate register access

CRE

tAVH

tAVS tAA

tVP

tVPH

tCBPH

tCO

tOLZ

tBA

tLZ

tOE

tLZ

UndefinedDon’t Care

Select register

tAAVD

tAVS

tAA

tHZ

tOHZ

tBHZ

tAVH

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64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory

Registers

Figure 15: Register READ, Synchronous Mode Followed by READ ARRAY Operation

Notes: 1. Nondefault BCR settings for synchronous mode register READ followed by READ ARRAY

operation: latency code 2 (3 clocks); WAIT active LOW; WAIT asserted during delay.

2. A[19:18 ] = 00b to read RCR, 10b to read BCR, and 01b to read DIDR.

3. CE# must remain LOW to complete a burst-of-on e READ. WAIT must be monitored—addi-

tional WAIT cycles caused by refresh collisions require a corresponding number of addi-

tional CE# LOW cycle s .

CLK

A[21:0]

(except A[19:18])

A[19:18]2

CRE

ADV#

CE#

OE#

WE#

LB#/UB#

WAIT

DQ[15:0]

tSP

tHD

tHZ

tCSP

tKOH Undefined

Don’t Care

tSP

tHD

Address

Latch control register value

tOLZ

tCBPH

tBOE

Valid

data

Address

tACLK

tOHZ

High-Z

tABA

Valid

Note 3

Latch control register address

tCEW

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64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory

Registers

Software Access

Software access of the registers uses a sequence of asynchronous READ and asynchro-

nous WRITE operations . The contents of the configuration registers can be modified,

and all reg isters can be read using the software sequence.

The configuration registers are loaded using a four-step sequence consisting of two

asynchronous READ operations followed by two asynchronous WRITE operations (see

Figure16). The read sequence is virtually identical except that an asynchronous READ is

performed during the fourth operation (see Figure 17 on page 24). The address used

during all READ and WRITE operations is the highest address of the C el lularRA M devic e

being accessed (3FFFFFh for 64Mb); the contents of this address are not changed by

using this sequence.

The data value presented during the third operation (WRITE) in the sequence defines

whether the BCR, RCR, or the DIDR is to be accessed. If the data is 0000h, the sequence

will access the RCR; if the data is 0001h, the sequence will access the BCR; if the data is

0002h, the sequence will access the DIDR. Du ring the fourth operation, DQ[15:0]

transfer data into or out of bits 15:0 of the registers.

The use of the software sequence does not affect the ability to perform the standard

(CRE-controlled) method of loading the configuration registers. However, the software

nature of this access mechanism eliminates the need for CRE. If the software mecha-

nism is used, CRE can simply be tied to VSS. The port line often used for CRE control

purposes is no longer required.

Figure 16: Load Configuration Register

Address

(MAX) Address

(MAX)

XXXXh XXXXh

RCR: 0000h

BCR: 0001h

CR value

Address

CE#

OE#

WE#

LB#/UB#

Data

Don't Care

READ READ WRITE WRITE

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64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory

Registers

Figure 17: Read Configuration Register

Address

(MAX) Address

(MAX)

XXXXh XXXXh CR value

out

Address

CE#

OE#

WE#

LB#/UB#

Data

Don't Care

READ READ WRITE READ

RCR: 0000h

BCR: 0001h

DIDR: 0002h

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64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory

Registers

Bus Configuration Register

The BCR defines how the CellularRAM device interacts with the system memory bus.

Page mode operation is enabled by a bit contained in the RCR. Figure 18 defines the

control bits in the BCR. At power-up, the BCR is set to 9D1Fh.

The BCR is accessed with CRE HIGH and A[19:18] = 10b or through the register access

software sequence with DQ = 0001h on the third cy cle.

Figure 18: Bus Configuration Register Definition

Notes: 1. Burst wra p and length apply both to READ and WRITE operatio ns.

A13

13 12 11 0

Latency

Counter

Initial

Latency

3 2 1

WAIT

Polarity

WAIT

Configuration (WC)

Drive Strength Burst

Wrap (BW)

A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2

A1 A0

Operating Mode

Synchronous burst access mode

Asynchronous access mode (default)

BCR[12] BCR[11]

Latency Counter

BCR[13]

Code 8

Code 1–Reserved

Code 2

Code 3 (Default)

Code 4

Code 5

Code 6

Code 7–Reserved

WAIT Polarity

Active LOW

Active HIGH (default)

BCR[10]

WAIT Configuration

Asserted during delay

Asserted one data cycle before delay (default)

Drive Strength

Full

1/2 (default)

1/4

Reserved

BCR[5]

BCR[4]

Initial Access Latency

Variable (default)

Fixed

BCR[14]

Burst Wrap (Note 1)

Burst wraps within the burst length

Burst no wrap (default)

BCR[3]

BCR[1] BCR[0] Burst Length (Note 1)

BCR[2]

Burst

Length (BL)

Reserved Reserved

Operating

Mode

Reserved

21–20

A14 A15

A[17:16]

Select RCR

Select BCR

Select DIDR

19–18 17–16

Select

Reserved

A[19:18] A[21:20]

Reserved

Must be set to “0” Must be set to “0” Must be set to “0”

All must be set to “0”

BCR[8]

BCR[15]

BCR[19]

BCR[18]

Others

4 words

8 words

16 words

32 words

Continuous burst (default)

Reserved

Setting is ignored

(Default to “0”)

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64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory

Registers

Burst Length (BCR[2:0]) Default = Continuous Burst

Burst lengths define the number of words the device outputs during burst READ and

WRITE operations . The device supports a burst length of 4, 8, 16, or 32 words. The device

can also be set in continuous burst mode where data is accessed sequentially up to the

end of the row.

Burst Wrap (BCR[3]) Default = No Wrap

The burst-wrap option determines whether a 4-, 8-, 16-, or 32-word READ or WRITE

burst wraps within the burst length, or steps through sequential addresses. If the wrap

option is not enabled, the device accesses data from seque ntial addr esses up to the end

of the row.

Table 4: Sequence and Burst Length

Burst Wrap Starting

Address

4-Word

Burst

Length 8-Word

Burst Length 16-Word

Burst Length 32-Word

Burst Length Continuous Burs t

BCR[3] WRAP (Decimal) Linear Linear Linear Linear Linear

0Yes

0 0-1-2-3 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7-8-9-10-11-12-13-14-15 0-1-2-...-29-30-31 0-1-2-3-4-5-6-…

1 1-2-3-0 1-2-3-4-5-6-7-0 1-2-3-4-5-6-7-8-9-10-11-12-13-14-15-0 1-2-3-...-30-31-0 1-2-3-4-5-6-7-…

2 2-3-0-1 2-3-4-5-6-7-0-1 2-3-4-5-6-7-8-9-10-11-12-13-14-15-0-1 2-3-4-...-31-0-1 2-3-4-5-6-7-8-…

3 3-0-1-2 3-4-5-6-7-0-1-2 3-4-5-6-7-8-9-10-11-12-13-14-15-0-1-2 3-4-5-...-0-1-2 3-4-5-6-7-8-9-…

4 4-5-6-7-0-1-2-3 4-5-6-7-8-9-10-11-12-13-14-15-0-1-2-3 4-5-6-...-1-2-3 4-5-6-7-8-9-10-…

5 5-6-7-0-1-2-3-4 5-6-7-8-9-10-11-12-13-14-15-0-1-2-3-4 5-6-7-...-2-3-4 5-6-7-8-9-10-11-…

6 6-7-0-1-2-3-4-5 6-7-8-9-10-11-12-13-14-15-0-1-2-3-4-5 6-7-8-...-3-4-5 6-7-8-9-10-11-12-…

7 7-0-1-2-3-4-5-6 7-8-9-10-11-12-13-14-15-0-1-2-3-4-5-6 7-8-9-...-4-5-6 7-8-9-10-11-12-13-…

... ... ... ...

14 14-15-0-1-2-3-4-5-6-7-8-9-10-11-12-13 14-15-16-...-11-12-

13 14-15-16-17-18-19-20-

...

15 15-0-1-2-3-4-5-6-7-8-9-10-11-12-13-14 15-16-17-...-12-13-

14 15-16-17-18-19-20-21-

...

... ... ...

30 30-31-0-...-27-28-29 30-31-32-33-34-...

31 31-0-1-...-28-29-30 31-32-33-34-35-...

1No

0 0-1-2-3 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7-8-9-10-11-12-13-14-15 0-1-2-...--29-30-31 0-1-2-3-4-5-6-…

1 1-2-3-4 1-2-3-4-5-6-7-8 1-2-3-4-5-6-7-8-9-10-11-12-13-14-15-16 1-2-3-...-30-31-32 1-2-3-4-5-6-7-…

2 2-3-4-5 2-3-4-5-6-7-8-9 2-3-4-5-6-7-8-9-10-11-12-13-14-15-16-17 2-3-4-...-31-32-33 2-3-4-5-6-7-8-…

3 3-4-5-6 3-4-5-6-7-8-9-10 3-4-5-6-7-8-9-10-11-12-13-14-15-16-17-18 3-4-5-...-32-33-34 3-4-5-6-7-8-9-…

4 4-5-6-7-8-9-10-11 4-5-6-7-8-9-10-11-12-13-14-15-16-17-18-19 4-5-6-...-33-34-35 4-5-6-7-8-9-10-…

5 5-6-7-8-9-10-11-12 5-6-7-8-9-10-11-12-13-14-15-16-17-18-19-

20 5-6-7-...-34-35-36 5-6-7-8-9-10-11-…

6 6-7-8-9-10-11-12-13 6-7-8-9-10-11-12-13-14-15-16-17-18-19-20-

21 6-7-8-...-35-36-37 6-7-8-9-10-11-12-…

7 7-8-9-10-11-12-13-

14 7-8-9-10-11-12-13-14-...-17-18-19-20-21-22 7-8-9-...-36-37-38 7-8-9-10-11-12-13-…

... ... ... ...

14 14-15-16-17-18-19-...-23-24-25-26-27-28-29 14-15-16-...-43-44-

45 14-15-16-17-18-19-20-

…

15 15-16-17-18-19-20-...-24-25-26-27-28-29-30 15-16-17-...-44-45-

46 15-16-17-18-19-20-21-

…

... ... ...

30 30-31-32-...-59-60-

61 30-31-32-33-34-35-36-

...

31 31-32-33-...-60-61-

62 31-32-33-34-35-36-37-

...

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64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory

Registers

Drive Strength (BCR[5:4]) Default = Outputs Use Half-Drive Strength

The output driver strength can be altered to full, one-half, or one-quarter strength to

adjust for different data bus loading scenarios. The reduced-strength options are

intended for stacked chip (Flash + CellularRAM) environments when there is a dedicated

memory bus. The reduced-drive-strength option minimizes the noise genera ted on the

data bus during READ operations. Full output drive strength should be selected when

using a discrete CellularRAM device in a more heavily loaded data bus environment.

Outputs are configured at half-drive strength during testing. See Table 5 for additional

information.

WAIT Configuration (BCR[8]) Default = WAIT Transitions One Clock Before Data Valid/Invalid

The WAIT c onfig uration bit is used to determine when WAIT transitions between the

asserted and the de-asserted state with respect to valid data presented on the data bus.

The memory controller will use the WAIT signal to coordinate data transfer during

synchronous READ and WRITE operations. When BCR[8] = 0, data will be valid or invalid

on the clock edge immed ia tel y afte r WAIT transitions to the de-ass erted or asser te d

state, respectively (see Figures 19 and 21). When A8 = 1, the WAIT signal transitions one

clock period prior to the data bus going valid or invalid (see Figure20 on page 28 and

Figure 21 on page28).

WAIT Polarity (BCR[10]) Default = WAIT Active HIGH

The WAIT polarity bit indicates whether an asserted WAIT output should be HIGH or

LOW. This bit will determine whether the WAIT signal requires a pull-up or pull-down

resi stor to maintain the de-asserted state.

Figure 19: WAIT Configuration (BCR[8] = 0)

Note: Data valid/invalid immediately after WAIT transitions (BCR[8] = 0). See Figure 21 on

page 28.

Table 5: Drive Strength

BCR[5] BCR[4] Drive Strength Impedance Typ (Ω)Use Recommendation

0 0 Full 25–30 CL = 30pF to 50pF

0 1 1/2 (default) 50 CL = 15pF to 30pF, 104 MHz at light load

1 0 1/4 100 CL = 15pF or lower

11 Reserved

WAIT

DQ[15:0]

CLK

Data 0 Data 1

High-Z

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64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory

Registers

Figure 20: WAIT Configuration (BCR[8] = 1)

Note: Valid/invalid data delayed for one clock after WAIT transitions (BCR[8] = 1). See Figure 21

on page 28).

Figure 21: WAIT Configuration During Burst Operation

Note: Nondefault BCR setting: WAIT active LOW.

Latency Counter (BCR[13:11]) Default = Three Clock Latency

The latency counter bits determine how many clocks occur between the beginning of a

READ or WRITE operation and the first data value transferred. For allowable latency

codes, see Tables 6 and 7 on pages 29 and 30, respectively, and Figures 22 and 23 on

pages 29 and 30, respectively.

Initial Access Latency (BCR[14]) Default = Variable

Variable initial access latency outputs data aft er the number of clocks set by the latency

counter. However, WAIT must be monitored to detect delays caused by collisions with

refresh operations.

Fixed initial access latenc y output s the first data at a consistent time that allows for

worst-case r efresh collisions. The latency counter must be configured to match the

initial latency and the clock frequency. It is not necessary to monitor WAIT with fixed

initial latency. The burst begins after the number of clock cycles conf ig ured by the

latency counter (see Table 7 on page 30 and Figur e23 on page 30).

Operating Mode (BCR[15]) Default = Asynchronous Operation

The operating mode bit either selects synchronous burst operation or the default asyn-

chronous mode of operation.

WAIT

DQ[15:0]

CLK

Data 0

High-Z

WAIT

DQ[15:0]

CLK

D[0]

BCR[8] = 0

Data valid in current cycle

BCR[8] = 1

Data valid in next cycle

Don’t Care

D[2] D[3]

D[1]

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64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory

Registers

Notes: 1. Latency is the number of clock cycles from the initialization of a burst operation until data

appears. Data is transferred on the next clock cycle. READ latency can range from the nor-

mal latency to the value shown for refresh collision. WRITE latency is fixed at th e va lue

shown for normal latency.

Figure 22: Latency Counter (Variable Initial Latency, No Refresh Collision)

Table 6: Variable Latency Configuration Codes (BCR [14] = 0)

BCR[13:11] Latency

Configuration Code

Latency1Maximum Input CLK Frequency (MHz)

Normal Refresh Collision -7013 -701 -708

010 2 (3 clocks) 2 4 66 (15.0ns) 66 (15.0ns) 52 (19.2ns)

011 3 (4 clocks)—default 3 6 104 (9.62ns) 104 (9.62ns) 80 (12.5ns)

100 4 (5 clocks) 4 8 133 (7.5ns)

Others Reserved –––––

A[21:0]

ADV#

DQ[15:0]

CLK

Code 2

Valid

output Valid

output

Valid

output

Valid

output

Valid

output Valid

output

Valid

output

Valid

output

Code 3 (Default)

DQ[15:0]

Don’t Care Undefined

VIH

VIL

VIH

VIL

VIH

VIL

VOH

VOL

VOH

VOL

Valid

address

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64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory

Registers

Figure 23: Latency Counter (Fixed Latency)

Table 7: Fixed Latency Configuration Codes (BCR[14] = 1)

BCR[13:11] Latency

Configuration Code Latency Count (N)

Maximum Input CLK Frequency (MHz)

-7013 -70 -708

010 2 (3 clocks) 2 33 (30ns) 33 (30ns) 33 (30ns)

011 3 (4 clocks)—default 3 52 (19.2ns ) 52 (19.2 ns) 52 (19.2ns)

100 4 (5 clocks) 4 66 (15ns) 66 (15ns) 66 (15ns)

101 5 (6 clocks) 5 75 (13.3ns ) 75 (13.3 ns) 75 (13.3ns)

110 6 (7 clocks) 6 104 (9.62ns) 104 (9.62ns) 80 (12.5ns)

000 8 (9 clocks) 8 133 (7.5ns) 104 (9.62ns) 80 (12.5ns)

Others Reserved ––––

A[21:0]

ADV#

DQ[15:0]

(READ)

CLK

Valid

output Valid

output

Valid

output

Valid

output

Don’t Care Undefined

VIH

VIL

VIH

VIL

VIH

VIL

CE# VIH

VIL

VOH

VOL

tAADV

tAA

tCO

tACLK

tSP tHD

DQ[15:0]

(WRITE)

VOH

VOL

N-1

Cycles

Cycle N

Valid

input Valid

input

Burst identified

(ADV# = LOW)

Valid

address

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64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory

Registers

Refresh Configuration Register

The refresh configuration register (RCR) defines how the Cellul arRAM device performs

its transparent self refresh. Altering the refres h parameters can dramatically reduce

curr ent consumption during standby mode. Page mode control is also embedded into

the R CR. Figur e24 describes the contr ol bits used in the RCR. At po wer -up, the RCR is set

to 0010h.

The RCR is access ed with CRE HIGH and A[19:18] = 00b or through the register access

software sequence with DQ = 0000h on the third cycle (see “Registers” on page 18).

Partial-Array Refresh (RCR[2:0]) Default = Full Array Refresh

The PAR bits restrict refresh operation to a portion of the total memory array. This

feature allows the device to reduce standby current by refreshing only that part of the

memory array required by the host system. The refresh options are full array, one-half

array, one-quarter array, one-eighth array, or none of the array. The mapping of these

partitions can start either at the b eginning or the end of the address map (see Table 8 on

page 32).

Figure 24: Refresh Configuration Register Mapping

PAR

A4 A3 A2 A1 A0 Address Bus

4 5 1

3 0

Deep Power-Down

DPD enable

DPD disable (default)

RCR[4]

All must be set to “0”

A[17:8]

17–8

19–18

21–20

Select

Reserved Reserved Reserved Reserved

A[21:20] A[19:18]

Select RCR

Select BCR

Select DIDR

RCR[19]

All must be set to “0”

RCR[1]

RCR[0]

Refresh Coverage

Full array (default)

Bottom 1/2 array

Bottom 1/4 array

Bottom 1/8 array

RCR[2]

0 0

0 1

1 0

1 1

None of array

Top 1/2 array

Top 1/4 array

Top 1/8 array

DPD

Must be set to “0” Setting is ignored

(Default 00b)

Page

Page Mode Enable/Disable

Page mode disabled (default)

Page mode enable

RCR[7]

RCR[18]

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64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory

Registers

Deep Power-Down (RCR[4]) Default = DPD Disabled

The deep po wer -down bit enables and disables all refresh-relate d activity. This mode is

used if the system does not require the stor age provided by the CellularRAM device. Any

stor ed data will become corrupted when DPD is enabled. When r efr esh activity has been

reenabled, the CellularRAM device will require 150µs to perform an initialization proce-

dure before normal operations can resume.

Deep power-down is enabled by setting RCR[4] = 0 and taking CE# HIGH. DPD can be

enabled using CRE or the software sequence to access the RCR. Taking CE# LOW for at

least 10µs disables DPD and sets RCR[4] = 1; it is not necessary to write to the RCR to

disable DPD. BCR and RCR values (other than RCR[4]) are preserved during DPD.

Page Mode Operation (RCR[7]) Default = Disabled

The page mode operation bit determines whether page mode is enabled for asynchro-

nous READ operations. In the power-up default state, page mode is disabled.

Table 8: 64Mb Address Patterns for PAR (RCR[4] = 1)

RCR[2] RCR[1] RCR[0] Active Section Address Space Size Density

0 0 0 Full die 000000h–3FFFFFh 4 Meg x 16 64Mb

0 0 1 One-half of die 000000h–1FFFFFh 2 Meg x 16 32Mb

0 1 0 One-quarter of die 000000h–0FFFFFh 1 Meg x 16 16Mb

0 1 1 One-eighth of die 000000h–07FFFFh 512K x 16 8Mb

1 0 0 None of die 0 0 Meg x 16 0Mb

1 0 1 One-half of die 200000h–3FFFFFh 2 Meg x 16 32Mb

1 1 0 One-quarter of die 300000h–3FFFFFh 1 Meg x 16 16Mb

1 1 1 One-eighth of die 380000h–3FFFFFh 512K x 16 8Mb

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64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory

Registers

Device Identification Register

The DIDR provides information on the device manufacturer, the CellularRAM genera-

tion, and the specific device configuration. Table 9 describes the bit fields in the DIDR.

The DIDR is accessed with CRE HIGH and A[19:18] = 01b or through the register access

software sequence with DQ = 0002h on the third cy cle.

Note: Vendors with 256-word row lengths for CellularRAM 1.5 devices will set DIDR[15 ] to 1b.

Table 9: Device Identification Register Mapping

Bit Field DIDR[15] DIDR[14:11] DIDR[10:8] DIDR[7:5] DIDR[4:0]

Field name Row length Device version Device density CellularRAM generation Vendor ID

Bit setting 0b Bit Setting Version 010b 010b 00011b

0000b 1st

0001b 2nd

0010b 3rd

(etc.) (etc.)

Meaning 128 words 64Mb CellularRAM 1.5 Micron

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64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory

Electrical Characteristics

Notes: 1. This exceeds the CellularRAM Workgroup 1.5 specification of –0.3V to VCCQ + 0.3V.

S tresses gr eater than those listed may cause permanent damage to the device . This is a

stress r ating only, and functional operation of the device at these or any other conditions

above those indicate d in the operational sections of this spe c ification is not implie d.

Exposure to absolute maximum rating conditions for extended periods may affect reli-

ability.

Table 10: Absolute Maximum Ratings

Parameter Rating

Voltage to any ball except VCC; VCCQ supply relative to VSS –0.5V to (4.0V or VCCQ + 0.3V, whichever is less)1

Voltage on VCC supply relative to VSS –0.2V to +2.45V

Voltage on VCCQ supply relative to VSS –0.2V to +4.0V

Storage temperature (plastic) –55°C to +150°C

Operating temperature (case)

Wireless –30°C to +85°C

–40°C to +85°C

Industrial

Soldering temperature and time

10s (solder ball only) +260°C

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64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory

Electrical Characteristics

Notes: 1. VCCQ (MAX) exceeds the CellularRAM Wo rkg roup specification of 1.95V.

2. Input signals may ove rshoot to VCCQ + 1.0V for periods less than 2ns during transitions.

3. Input signals may undershoot to VSS - 1.0V for periods less than 2ns during transitions.

4. BCR[5:4] = 01b (default setting of one-half dri ve strength).

Notes: 1. This parameter is specified with the outputs disabled to avoid external loading effects.

The user must add the current required to drive output capacitance expect ed in the actual

system.

2. Micron devices are fu lly compatible wi th the CellularRAM Workgroup specification for

ICCP1: –70 MAX of 18mA.

3. ISB (MAX) values are measured with P A R set to full array and at +85°C. To achieve low

standby current, all inputs must be driven either to VCCQ or VSS. ISB might be slightly higher

for up to 500ms after power-up or when entering standby mode.

4. ISB (TYP) is the average ISB at 25°C, and VCC = VCCQ = 1.8V. This parameter is verified during

characterization and is not 100 percent tested.

Table 11: Electrical Characteristics

Wireless temperature (–30º C < T C < +85ºC); Industrial temperature (–40ºC < TC < +85ºC)

Description Conditions Symbol Min Max Unit Notes

Supply voltage VCC 1.7 1.95 V

I/O supply voltage VCCQ1.73.3V1

Input high volt ag e VIH VCCQ - 0.4 VCCQ + 0.2 V 2

Input low voltage VIL –0.2 0.4 V 3

Output high voltage IOH = –0.2mA VOH 0.8 VCCQ– V4

Output low voltage IOL = +0.2mA VOL – 0.2 VCCQV 4

Input leakage current VIN = 0 to VCCQILI –1µA

Output leakage current OE# = VIH or

chip disabl ed ILO –1µA

Table 12: Operati n g Conditions

Wireless temperature (–30º C < T C < +85ºC); Industrial temperature (–40ºC < TC < +85ºC)

Operating Current Conditions Symbol Typ Max Unit Notes

Asynchronous random READ/WRITE VIN = VCCQ or 0V

chip enabled,

IOUT = 0

ICC1 –70 25 mA 1

Asynchronous page READ ICC1P –70 15 mA 1, 2

Initial access, burst READ/WRITE ICC2133 MHz 45 mA

104 MHz 35 mA 1

80 MHz 30

Continuous burst READ ICC3R 133 MHz 40 mA

104 MHz 30 mA 1

80 MHz 25

Continuous burst WRITE ICC3W 133 MHz 40 mA

104 MHz 35 mA 1

80 MHz 30

Standby current VIN = VCCQ or 0V

CE# = VCCQISB Standard 50 140 µA 3, 4

Low power (L) 120

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64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory

Electrical Characteristics

Note: IPAR (MAX) values are mea sured at 85°C. IPAR might be slightly higher for up to 500ms after

changes to the PAR array partition or when entering standby mode. To achieve low

standby current, all inputs must be driven eithe r to V CCQ or VSS.

Figure 25: Typical Refresh Current vs. Temperature (ITCR)

Note: IZZ (TYP) value applies across all operating temperatures and voltages.

Table 13: Partial-Array Refresh Specifications and Conditions

Description Conditions Symbol Array Partition Max Unit

Partial-array

refresh standby

current

VIN = VCCQ or 0V,

CE# = VCCQIPAR Standard power

(no designation) Full 140 µA

1/2 120

1/4 110

1/8 105

095

Low-power

option (L) Full 120 µA

1/2 105

1/4 95

1/8 90

085

Table 14: Deep Power-Down Specifications

Description Conditions Symbol Typ Max Unit

Deep power-down VIN = VCCQ or 0V;

VCC, VCCQ = 1.95V; +85°C IZZ 310µA

0 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 100

Temperature (°C)

ISB (µA)

PAR = Full array

PAR = 1/2 of array

PAR = 1/4 of array

PAR = 1/8 of array

PAR = None of array

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64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory

Electrical Characteristics

Notes: 1. These parameters are verified in device characterization and ar e not 100 percent tested.

Figure 26: AC Input/Output Reference Waveform

Notes: 1. AC test inputs are driven at V CCQ for a logic 1 and VSSQ for a logic 0. Input rise and fall

times (10 percent to 90 percent) < 1.6ns.

2. Input timing begins at VCCQ/2.

3. Output timing ends at VCCQ/2.

Figure 27: AC Output Load Circuit

Note: All tests are performed with the outputs configured for a default setting of half drive

strength (BCR[5:4] = 01b).

Table 15: Capacitance

Description Conditions Symbol Min Max Unit Notes

Input capacitance TC = +25°C; f = 1 MHz;

VIN = 0V CIN 2.0 6 pF 1

Input/output capacitance (DQ) CIO 3.5 6 pF 1

Output

Test points

Input

Q/2

DUT V

Q/2

30pF

Test point

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64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory

Timing Requirements

Notes: 1. Low-Z to High-Z timings are tested with the circuit shown in Figure 27 on page 37. The

High-Z timings measure a 100mV transition either from VOH or VOL toward VCCQ/2.

2. High-Z to Low-Z timings are tested with the circuit shown in Figure 27 on page 37. The

Low-Z timings measure a 100mV transition away from the High-Z (VCCQ/2) level either

toward V OH or VOL.

3. Page mode enabled only.

Table 16: Asynchronous READ Cycle Timing Requirements

All tests are performed with outputs configured for default setting of one-half drive strength

(BCR[5:4] = 01b).

Parameter Symbol

70ns

Unit NotesMin Max

Address access time tAA – 70 ns

ADV# access time tAADV – 70 ns

Page access time tAPA – 20 ns

Address hold from ADV# HIGH tAVH 2 – ns

Address setup to ADV# HIGH tAVS 5 – ns

LB#/UB# access time tBA – 70 ns

LB#/UB# disable to DQ High-Z output tBHZ – 8 ns 1

LB#/UB# enable to Low-Z output tBLZ 10 – ns 2

Maximum CE# pu lse width tCEM – 4 µs 3

CE# LOW to WAIT valid tCEW 1 7.5 ns

Chip select access time tCO – 70 ns

CE# LOW to ADV# HIGH tCVS 7 – ns

Chip disable to DQ and WAIT High-Z output tHZ – 8 ns 1

Chip enable to Low-Z output tLZ 10 – ns 2

Output enable to valid output tOE – 20 ns

Output hold from address change tOH 5 – ns

Output disable to DQ High-Z output tOHZ – 8 ns 1

Output enable to Low-Z output tOLZ 3 – ns 2

PAGE cycle time tPC 20 – ns

READ cycle time tRC 70 – ns

ADV# pulse wid t h L OW tVP 5 – ns

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64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory

Timing Requirements

Notes: 1. V alues are valid for tCLK (MIN) with no refresh collision: LC = 4 for -7013; LC = 3 for -701 and

-708.

2. A refr esh opportunity must be provided every tCEM. A refresh opportunity is satisfied by

either of the following two con dition s: a) cloc ked CE# HIGH o r b) C E# HIGH for long er than

15ns.

3. Low-Z to High-Z timings are tested with the circuit shown in Figure 27 on page 37. The

High-Z timings measure a 100mV transition either from VOH or VOL toward VCCQ/2.

4. High-Z to Low-Z timings are tested with the circuit shown in Figure 27 on page 37. The

Low-Z timings measure a 100mV transition away from the High-Z (VCCQ/2) level either

toward V OH or VOL.

Table 17: Burst READ Cycle Timing Requirements

All tests are performed with outputs configured for default setting of one-half drive strength

(BCR[5:4] = 01b)

Parameter Symbol

-7013

(133 MHz) -701

(104 MHz) -708

(80 MHz)

Unit NotesMin Max Min Max Min Max

Address access time (fixed latency) tAA – 70 – 70 – 70 ns

ADV# access time (fixed latency) tAADV – 70 – 70 – 70 ns

Burst to READ access time (variable latency) tABA – 35.5 – 35.9 – 46.5 ns 1

CLK to output

delay Variable LC = 4

Fixed LC = 8

tACLK – 5.5 – 7 – 9 ns

All other LCs –7– 7–9ns

Address hold from ADV# HIGH (fixed latency) tAVH 2 – 2 – 2 – ns

Burst OE# LOW to output delay tBOE – 20 – 20 – 20 ns

CE# HIGH between subsequent burst or

mixed-mode operations

tCBPH 5 – 5 – 6 – ns 2

Maximum CE# pu lse width tCEM – 4 – 4 – 4 µs 2

CE# LOW to WAIT valid tCEW 1 7.5 1 7.5 1 7.5 ns

CLK period tCLK 7.5 – 9.62 – 12.5 – ns

Chip select access time (fixed latency) tCO – 70 – 70 – 70 ns

CE# setup time to active CLK edge tCSP 2.5 – 3 – 4 – ns

Hold time from active CLK edge tHD 1.5 – 2 – 2 – ns

Chip disable to DQ and WAIT High-Z output tHZ – 7 – 7 – 7 ns 4

CLK rise or fall time tKHKL – 1.2 – 1.6 – 1.8 ns

CLK to WAIT

valid Variable LC = 4

Fixed LC = 8

tKHTL – 5.5 – 7 – 9 ns

All other LCs –7– 7–9ns

Output hold from CLK tKOH 2 – 2 – 2 – ns

CLK HIGH or LOW time tKP 3 – 3 – 4 – ns

Output disable to DQ High-Z output tOHZ – 7 – 7 7 ns 3

Output enable to Low-Z output tOLZ 3 – 3 – 3 – ns 4

Setup time to active CLK edge tSP 2 – 3 – 3 – ns

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64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory

Timing Requirements

Notes: 1. Low-Z to High-Z timings are tested with the circuit shown in Figure 27 on page 37. The

High-Z timings measure a 100mV transition either from VOH or VOL toward VCCQ/2.

2. High-Z to Low-Z timings are tested with the circuit shown in Figure 27 on page 37. The

Low-Z timings measure a 100mV transition away from the High-Z (VCCQ/2) level either

toward V OH or VOL.

3. WE# LOW time must be limited to tCEM (4µs).

Table 18: Asynchronous WRITE Cycle Timing Requirements

Parameter Symbol

70ns

Unit NotesMin Max

Address and ADV# LOW setup time tAS 0 – ns

Address hold from ADV# going HIGH tAVH 2 – ns

Address setup to ADV# going HIGH tAVS 5 – ns

Address valid to end of WRITE tAW 70 – ns

LB#/UB# select to end of WRITE tBW 70 – ns

CE# LOW to WAIT valid tCEW 1 7.5 ns

CE# HIGH between subsequent asynchronous operations tCPH 5 – ns

CE# LOW to ADV# HIGH tCVS 7 – ns

Chip enable to end of WRITE tCW 70 – ns

Data hold from WRITE time tDH 0 – ns

Data WRITE setup time tDW 20 – ns

Chip disable to WAIT High-Z output tHZ – 8 ns 1

Chip enable to Low-Z output tLZ 10 – ns 2

End WRITE to Low-Z output tOW 5 – ns 2

ADV# pulse wid t h tVP5–ns

ADV# setup to end of WRITE tVS 70 – ns

WRITE cycle time tWC 70 – ns

WRITE to DQ High-Z output tWHZ – 8 ns 1

WRITE pulse width tWP 45 – ns 3

WRITE pulse width HIGH tWPH 10 – ns

WRITE recovery time tWR 0 – ns

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64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory

Timing Requirements

Notes: 1. tAS is required if tCSP > 20ns.

2. A refr esh opportunity must be provided every tCEM. A refresh opportunity is satisfied by

either of the following two con dition s: a) cloc ked CE# HIGH o r b) C E# HIGH for long er than

15ns.

3. Low-Z to High-Z timings are tested with the circuit shown in Figure 27 on page 37. The

High-Z timings measure a 100mV transition either from VOH or VOL toward VCCQ/2.

Table 19: Burst WRITE Cycle Timing Requirements

Parameter Symbol

-7013

(133 Mhz) -701

(104 MHz) -708

(80 MHz)

Unit NotesMin Max Min Max Min Max

Address and ADV# LOW setup time tAS 0–0–0–ns1

Address hold from ADV# HIGH (fixed latency) tAVH 2–2–2–ns

CE# HIGH between subsequent burst or mixed-

mode operations

tCBPH 5–5 –6–ns2

Maximum CE# pu lse width tCEM –4–4–4µs2

CE# LOW to WAIT valid tCEW 1 7.5 1 7.5 1 7.5 ns

Clock period tCLK 7.5 – 9.62 – 12.5 – ns

CE# setup to CLK active edge tCSP 2.5 – 3 – 4 – ns

Hold time from active CLK edge tHD 1.5 – 2 – 2 – ns

Chip disable to WAIT High-Z output tHZ –7–8–8ns3

CLK rise or fall time tKHKL – 1.2 – 1.6 – 1.8 ns

CLK to WAIT valid Variable LC = 4

Fixed LC = 8

tKHTL –5.5– 7–9ns

All other LCs –7–7–9ns

CLK HIGH or LOW time tKP 3–3–4–ns

Setup time to active CLK edge tSP 2–3 –3–ns

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64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory

Timing Diagrams

Figure 28: Initi alization Period

Figure 29: DPD Entry and Exit Timing

Notes: 1. The CellularRAM Workgroup 1.5 specification for tDPD is a minimum of 150µs.

Table 20: Initi alization Timing Parameters

Parameter Symbol

70ns

Unit NotesMin Max

Time from DPD entry to DPD exit tDPD 10 – µs 1

CE# LOW time to exit DPD tDPDX 10 – µs

Initialization period tPU –150µs

tPU

Vcc, VccQ = 1.7V Vcc (MIN)

Device ready for

normal operation

CE#

DPD enabledWrite

RCR[4] = 0 DPD exit Device initialization Device ready for

normal operation

tDPD tDPDX tPU

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64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory

Timing Diagrams

Figure 30: Asynchronous READ

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VOH

VOL

VIH

VIL

A[21:0]

ADV#

CE#

LB#/UB#

OE#

WE#

WAIT

DQ[15:0]

Valid address

tAA

tHZ

tBA

High-Z High-Z

tRC

tCO tBHZ

tOHZ

tHZ

tOE

tCEW

Valid output

High-Z

Undefined

Don’t Care

tBLZ

tLZ

tOLZ

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64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory

Timing Diagrams

Figure 31: Asynchro nous READ Using ADV#

A[21:0]

ADV#

CE#

LB#/UB#

OE#

WE#

WAIT

DQ[15:0]

Valid address

tVPH

tAADV

tAA

tVP tHZ

tBA

High-Z High-Z

tCVS

tCO

tBLZ

tBHZ

tOHZ

tHZ

tLZ

tOE

tOLZ

Valid output

tAVH

tAVS

High-Z

Undefined

Don’t Care

tCEW

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VOH

VOL

VIH

VIL

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64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory

Timing Diagrams

Figure 32: Page Mode READ

A[3:0]

ADV#

CE#

LB#/UB#

OE#

WE#

WAIT

DQ[15:0]

Valid address

tAA

tHZ

tBA

High-Z High-Z

tCO

tCEM

tBLZ

tBHZ

tOHZ

tHZ

tLZ

tOE

tOLZ

tCEW

High-Z

Undefined

Don’t Care

A[21:4] Valid address

Valid

address Valid

address

tRC

Valid

Output

tAPA

tPC

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VOH

VOL

VOH

VOL

tOH

Valid

output Valid

output

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64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory

Timing Diagrams

Figure 33: Single-Acces s Burst READ Operation – Variable Latency

Note: Nondefault BCR settings: late ncy code 2 (3 clocks); WAIT active LOW ; WAIT asserted during

delay.

A[21:0]

VIH

VIL

ADV#

VIH

VIL

CE#

VIH

VIL

OE#

VIH

VIL

WE#

VIH

VIL

WAIT

DQ[15:0]

VOH

VOL

CLK

VIH

VIL

VOH

VOL

tSP

tCLK

tACLK

tCEW

tHD

Valid

output

Valid

address

High-Z

tKOH

tOHZ

tSP

LB#/UB#

VIH

VIL

tCSP tCEM

High-Z

tOLZ

tHD

tSP

tHZ

tKP tKP

tKHKL

tHD

tSP

Undefined

Don’t Care

READ burst identified

(WE# = HIGH)

tKHTL

tBOE

High-Z

tABA

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64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory

Timing Diagrams

Figure 34: 4-Word Burst READ Operation – Variable Latency

Note: Nondefault BCR settings: late ncy code 2 (3 clocks); WAIT active LOW ; WAIT asserted during

delay.

A[21:0] VIH

VIL

ADV# VIH

VIL

CE# VIH

VIL

OE# VIH

VIL

WE# VIH

VIL

WAIT

DQ[15:0]

VOH

VOL

CLK VIH

VIL

VOH

VOL

tSP

tCLK

tKHKL

tHD

Valid address

tKOH

tHZ

tHD

tSP

LB#/UB# VIH

VIL

tOLZ

tCBPH

tCSP

tCEM

tSP tHD

tOHZ

tHD

tKP tKP

Undefined

Don’t Care

READ burst identified

(WE# = HIGH)

tACLK

Valid output Valid output Valid output Valid output

High-Z

tKHTL

tCEW

High-Z

tBOE

tABA

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64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory

Timing Diagrams

Figure 35: Single-Access Burst READ Operation – Fixed Latency

Note: Nondefault BCR settings: fixed latency; latency code 4 (5 clocks); WAIT active LOW; WAIT

asserted during delay.

A[21:0]

VIH

VIL

ADV#

VIH

VIL

CE#

VIH

VIL

OE#

VIH

VIL

WE#

VIH

VIL

WAIT

DQ[15:0]

VOH

VOL

CLK

VIH

VIL

VOH

VOL

tCLK

tAVH

tCO

tAADV

tAA

tHD

Valid address

tKOH

tOHZ

tSP

LB#/UB#

VIH

VIL

tCSP

tCEM

tOLZ

tHD

tSP

tHZ

tKP tKP

tKHKL

tHD

tSP

Undefined

Don’t Care

READ burst identified

(WE# = HIGH)

tKHTL

tBOE

High-Z

tCEW

Valid output

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64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory

Timing Diagrams

Figure 36: 4-Word Burst READ Operation – Fixed Latency

Note: Nondefault BCR settings: fixed latency; latency code 2 (3 clocks); WAIT active LOW; WAIT

asserted during delay.

A[21:0] VIH

VIL

ADV# VIH

VIL

CE# VIH

VIL

OE# VIH

VIL

WE# VIH

VIL

WAIT

DQ[15:0]

VOH

VOL

CLK VIH

VIL

VOH

VOL

tAVH

tCLK

tKHKL

tCO

High-Z

tKOH

tHZ

tHD

tSP

LB#/UB# VIH

VIL

tOLZ

tCBPH

tCSP

tCEM

tSP tHD

tOHZ

tHD

tKP tKP

Undefined

Don’t Care

READ burst identified

(WE# = HIGH)

Valid output

Valid address

Valid output Valid output Valid output

High-ZHigh-Z

tAA

tKHTL

tACLK

tCEW

tBOE

tAADV

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64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory

Timing Diagrams

Figure 37: READ Burst Suspend

Notes: 1. Nondefault BCR settings for READ burst suspend: fixed or variable latency; latency code 2 (3

clocks); WAIT active LOW; WAIT asserted during delay.

2. CLK can be stopped LOW or HIGH but must be static, with no LOW-to-HIGH transitions dur-

ing burst suspend.

3. OE # can stay LOW during burst suspend. If OE# is LOW, DQ[15:0] will continue to output

valid data.

A[21:0] VIH

VIL

ADV# VIH

VIL

CE# VIH

VIL

OE# VIH

VIL

WE# VIH

VIL

WAIT

DQ[15:0]

VOH

VOL

CLK VIH

VIL

VOH

VOL

tSP tHD

tOLZ

tACLK

LB#/UB# VIH

VIL

tCLK

tSP

tCSP

tSP

tHD

tSP tHD

tKOH

Valid

output Valid

output

Undefined

Don’t Care

Valid address

High-Z

tCBPH

tCEM

tHZ

tOHZ

tBOE

tOLZ

High-Z

Note 3

Note 2

Valid outputValid output Valid output Valid output

Valid address

tBOE

High-Z

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64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory

Timing Diagrams

Figure 38: Burst READ at End-of-Row (Wrap Off)

Notes: 1. Nondefault BCR settings for burst READ at end of row: fixed or variable latency; WAIT

active LOW; WAIT asserted during delay.

2. For burst READs, CE# must go HIGH before the third CLK after the WAIT period begins

(before the third CLK after WAIT asserts with BCR[8] = 0 or before the fourth CLK after

WAIT asserts with BCR[8] = 1). Micron devices are fully compatible with the CellularRAM

Workgroup specification that requires CE# to go HIGH 1 cycle sooner than shown here.

A[21:0] VIH

VIL

ADV# VIH

VIL

CE# VIH

VIL

OE# VIH

VIL

WE# VIH

VIL

WAIT

DQ[15:0]

VOH

VOL

CLK VIH

VIL

VOH

VOL

tKHTL tHZ

tCLK

LB#/UB# VIH

VIL

Valid

output

Don’t Care

Valid

output

End of row

tHZ

Note 2

High-Z

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64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory

Timing Diagrams

Figure 39: CE#-Controlled Asynchronous WRITE

A[21:0]

ADV#

CE#

LB#/UB#

OE#

WE#

WAIT

DQ[15:0]

Valid address

High-Z High-Z

tWC

tCEW tHZ

Valid input

tAW

Don’t Care

tWR

tCW tCPH

tDW

DQ[15:0]

OUT

tWHZ

tBW

tLZ

tDH

tAS

tWP

tWPH

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VOH

VOL

VOH

VOL

High-Z

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64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory

Timing Diagrams

Figure 40: LB #/UB#-Controlled Asynchronous WRITE

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VOH

VOL

A[21:0]

ADV#

CE#

LB#/UB#

OE#

WE#

WAIT

DQ[15:0]

IN VIH

VIL

Valid address

High-Z

tWC

tCEW tHZ

Valid input

tAW

Don’t Care

tWR

tCW

tDW

DQ[15:0]

OUT VOH

VOL

tWHZ

tBW

tLZ

tDH

tAS

tWP

tWPH

High-Z

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64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory

Timing Diagrams

Figure 41: WE#-Controlle d Asynchronou s WRITE

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VOH

VOL

A[21:0]

ADV#

CE#

LB#/UB#

OE#

WE#

WAIT

DQ[15:0]

VIH

VIL

Valid address

tWC

tCEW tHZ

Valid input

tAW

Don’t Care

tWR

tDW

DQ[15:0]

OUT

VOH

VOL

tWHZ

tBW

tCW

tLZ

tWP

tDH

tOW

tAS

tWPH

High-Z

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64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory

Timing Diagrams

Figure 42: WE#-Controlle d Asynchronou s WRITE Using ADV#

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

A[21:0]

ADV#

CE#

LB#/UB#

OE#

WE#

WAIT

DQ[15:0]

IN VIH

VIL

Valid address

High-Z High-Z

tCEW tHZ

Valid input

tVS

Don’t Care

tDW

DQ[15:0]

OUT VOH

VOL

tWHZ

tBW

tLZ

tWP

tDH

tOW

tAS

tWPH

tAS

tVPH

tAVH

tAVS

tVP

High-Z

tAW

tCW

tCVS

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64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory

Timing Diagrams

Figure 43: Burst WRITE Operation – Variable Latency Mode

Notes: 1. Nondefault BCR settings for burst WRITE operation in variable latency mode: latency code 2

(3 clocks); WAIT active LOW; WAIT asserted during delay; burst length 4; burst wrap

enabled.

2. WAIT asserts for LC cycles for both fixed and variable latency.

LC = latency code (BCR[13:11]).

3. tAS required if tCSP > 20ns.

A[21:0] VIH

VIL

ADV# VIH

VIL

CE# VIH

VIL

OE# VIH

VIL

WE# VIH

VIL

WAIT

DQ[15:0]

VOH

VOL

CLK VIH

VIL

VIH

VIL

tKP

tSP

tAS3

tCSP

D3D2D1D0

Valid address

tHD

tSP

tHD

tSP

tHD

tSP

High-Z High-Z

LB#/UB# VIH

VIL

tSP tHD

tHD

Don’t Care

WRITE burst identified

(WE# = LOW)

tCBPH

tKHTL

tAS3

tHZ

tCEW

tKP tKHKL

Note 2

tCEM

tCLK

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64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory

Timing Diagrams

Figure 44: Burst WRITE Operation – Fixed Latency Mode

Notes: 1. Nondefault BCR settings for burst WRITE operation in fixed latency mode: fixed latency;

latency code 2 (3 clocks); WAIT active LOW; W AI T asserted du ri ng delay; burst length 4;

burst wrap enabled.

2. WAIT asserts for LC cycles for both fixed and variable latency.

LC = latency code (BCR[13:11]).

3. tAS required if tCSP > 20ns.

A[21:0] VIH

VIL

ADV# VIH

VIL

CE# VIH

VIL

OE# VIH

VIL

WE# VIH

VIL

WAIT

DQ[15:0]

VOH

VOL

CLK VIH

VIL

VIH

VIL

tKP

tSP

tAS3

tCSP

D3D2D1D0

Valid address

tHD

tSP

tHD

tSP

tHD

tSP

High-Z High-Z

LB#/UB# VIH

VIL

tSP tHD

tHD

Don’t Care

WRITE burst identified

(WE# = LOW)

tCBPH

tKHTL

tAS3

tHZ

tCEW

tKP tKHKL

Note 2

tCEM

tCLK

tAVH

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64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory

Timing Diagrams

Figure 45: Burst WRITE at End of Row (Wrap Off)

Notes: 1. Nondefault BCR settings for burst WRITE at end of row: fixed or variable latency; WAIT

active LOW; WAIT asserted during delay.

2. For burst WRITEs, CE# must go HIGH before the third CLK after the WAIT period begins

(before the third CLK after WAIT asserts with BCR[8] = 0 or before the fourth CLK after

WAIT asserts with BCR[8] = 1). Micron devices are fully compatible with the CellularRAM

Workgroup specification that requires CE# to go HIGH 1 cycle sooner than shown here.

3. Devices from different CellularRAM vendo rs c an assert W AIT so that the end-of-row data is

input 1 cycle before the WAIT period begins (as shown, solid line) or the same cycle that

asserts WAIT. This difference in behavior will not be noticed by controllers that monitor

WAIT or that use WAIT to abort on an end-of-row condition.

4. Micron devices are fu lly compatible wi th the CellularRAM Workgroup specification that

requires CE# to go HIGH 1 cycle sooner than shown here.

A[21:0] VIH

VIL

ADV# VIH

VIL

CE# VIH

VIL

OE#

VIH

VIL

WE#

VIH

VIL

WAIT

DQ[15:0]

VOH

VOL

CLK VIH

VIL

VIH

VIL

tKHTL

tHZ tHZ

tCLK

tSP tHD

Valid inputV alid input

Don’t Care

VIH

VIL

LB#/UB#

High-Z

Note 2

Note 3

Note 4

End of row

(A[6:0] = 7Fh)

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64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory

Timing Diagrams

Figure 46: Burst WRITE Followed by Burst READ

Notes: 1. Nondefault BCR settings for burst WRITE followed by burst READ: fixed or variable latency;

latency code 2 (3 clocks); WAIT active LOW; WAIT asserted during delay.

2. A refr esh opportunity must be provided every tCEM. A refresh opportunity is satisfied by

either of the following two conditions: a) clocked CE# HIGH, or b) CE# HIGH for longer than

15ns. CE# can stay LOW between burst READ and burst WRITE operations, but CE# must not

remain LOW longer than tCEM. See burst interrupt diagrams (Figures 47 through 49 on

pages 60 through 62) for cases where CE# stays LOW between bursts.

A[21:0] VIH

VIL

ADV# VIH

VIL

CE# VIH

VIL

OE# VIH

VIL

WE# VIH

VIL

WAIT

DQ[15:0]

IN/OUT

VOH

VOL

CLK VIH

VIL

VIH

VIL

tCLK

tSP

tCSP

D3D2D1D0

Valid address

tHD

tSP

tHD

tSP

tSP tHD

Valid address

tCSP tOHZ

tKOH

tACLK

Valid outputValid output Valid outputValid output

High-Z

High-Z VOH

VOL

LB#/UB# VIH

VIL

tHD

tSP tHD

tSP

tHD

High-Z

Undefined

Don’t Care

tCBPH

High-Z

tHD

tHD tSP

Note 2

tBOE

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64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory

Timing Diagrams

Figure 47: Burst READ Interrupted by Burst READ or WRITE

Notes: 1. Nondefault BCR settings for burst READ interrupted by burst READ or WRITE: fixed or vari-

able latency; latency code 2 (3 clocks); W A IT active LOW; WAIT asserted during delay. All

bursts shown for variable latency; no refresh collision.

2. Burst interrupt shown on first allowable clock (such as after the first data received by the

controller).

A[21:0] VIH

VIL

ADV# VIH

VIL

CE# VIH

VIL

OE#

2nd cycle READ VIH

VIL

OE#

2nd cycle WRITE VIH

VIL

WE# VIH

VIL

WAIT

DQ[15:0] OUT

2nd cycle READ

VOH

VOL

CLK VIH

VIL

DQ[15:0] IN

2nd cycle WRITE VIH

VIL

tHD

tSP

tSP tHD

tCLK

tOHZ

tKOH

tACLK

Valid

output

Valid

output Valid

output

Valid

output

LB#/UB#

2nd cycle READ VIH

VIL

LB#/UB#

2nd cycle WRITE VIH

VIL

tSP tHD

Undefined Don’t Care

tHD

tSP

tCSP

tSP tHD

Valid

address

tOHZ

tKOH

tACLK

Valid

output

High-Z

tBOE

tCEW

tSP tHD

tHD

tSP

VOH

VOL

tBOE

D2 D3 D1

High-Z

tCEM (Note 3)

Valid

address

READ burst interrupted with new READ or WRITE. See Note 2.

High-Z

tKHTL

High-Z

tHD

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64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory

Timing Diagrams

Figure 48: Burst WRITE Interrupted by Burst WRITE or READ – Variable Latency Mode

Notes: 1. Nondefault BCR settings for burst WRITE interrupted by burst WRITE or READ in variable

latency mode: fixed or variable latency; latency code 2 (3 clocks); WAIT active LOW; WAIT

asserted during delay. All bursts shown for variable latency; no refresh collision.

2. Burst interrupt shown on first allowable clock (such as after first data word written).

3. CE # can stay LOW between burst operations, but CE# must not remain LOW longer than

tCEM.

A[21:0] VIH

VIL

ADV# VIH

VIL

CE# VIH

VIL

OE#

2nd cycle WRITE VIH

VIL

OE#

2nd cycle READ VIH

VIL

WE# VIH

VIL

WAIT

DQ[15:0] IN

2nd cycle WRITE

DQ[15:0] OUT

2nd cycle READ

VOH

VOL

CLK VIH

VIL

VIH

VIL

tSP

tCSP

Valid

address

tHD

tSP

tHD

tSP

tSP tHD

Valid

address

tHD

High-Z

LB#/UB#

2nd cycle WRITE

LB#/UB#

2nd cycle READ

VIH

VIL

VIH

VIL

tHD

tSP tHD

tKHTL

tSP tHD

Undefined

Don’t Care

D2 D3 D1

tHD

tSP

tHD

tHD tSP

tOHZ

tSP tHD

tKOH

Valid

output

Valid

output Valid

output

Valid

output

High-Z

VOH

VOL

VOH

VOL

WRITE burst interrupted with new WRITE or READ. See Note 2.

Valid

address

tCEM (Note 3)

tCEW

High-Z High-Z

tACLK

tBOE

tCLK

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64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory

Timing Diagrams

Figure 49: Burst WRITE Interrupted by Burst WRITE or READ – Fixed Latency Mode

Notes: 1. Nondefault BCR settings for burst WRITE interrupted by burst WRITE or READ in fixed

latency mode: fixed latency; latency code 2 (3 clocks); WAIT active LOW; WAIT asserted dur-

ing delay.

2. Burst interrupt shown on first allowable clock (such as after first data word written).

3. CE # can stay LOW between burst operations, but CE# must not remain LOW longer than

tCEM.

A[21:0] VIH

VIL

ADV# VIH

VIL

CE# VIH

VIL

OE#

2nd cycle WRITE VIH

VIL

OE#

2nd cycle READ VIH

VIL

WE# VIH

VIL

WAIT

DQ[15:0] IN

2nd cycle WRITE

DQ[15:0] OUT

2nd cycle READ

VOH

VOL

CLK VIH

VIL

VIH

VIL

tCLK

tSP

tCSP

Valid

address

tHD

tSP

tHD

tSP

tHD

High-Z

LB#/UB#

2nd cycle WRITE

LB#/UB#

2nd cycle READ

VIH

VIL

VIH

VIL

tSP tHD

Undefined

Don’t Care

tHD

D2 D3 D1

tHD

tSP

tHD tSP

tOHZ

tKOH

tACLK

Valid

output

Valid

output Valid

output

Valid

output

High-Z

VOH

VOL

VOH

VOL

tKHTL

WRITE burst interrupted with new WRITE or READ. See Note 2.

Valid

address

tCEM (Note 3)

tHD

tCEW

High-Z High-Z

tAVH tAVH

Valid

address

tBOE

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64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory

Timing Diagrams

Figure 50: Asynchronous WRITE Followed by Burst READ

Notes: 1. Nondefault BCR settings for asynchronous WRITE followed by burst READ: fixed or variable

latency; latency code 2 (3 clocks); WAIT active LOW; WAIT asserted during delay.

2. When transitioning between asynchronous and variable-latency burst operations, CE# must

go HIGH. CE# can stay LOW when transitioning to fixed-latency burst READs. A refresh

opportunity must be provided every tCEM. A refresh opportunity is satisfied by either of the

following two conditions: a) clocked CE# HIGH or b) CE# HIGH for longer than 15ns.

tCLK

tSP tHD

tSP

Valid

address

tOHZ

tKOH

tACLK

High-Z

Valid address Valid address

tAVS tAVH tAW tWR

tVP tVS

A[21:0] VIH

VIL

ADV# VIH

VIL

OE# VIH

VIL

WE# VIH

VIL

WAIT

DQ[15:0]

IN/OUT

VOH

VOL

CLK VIH

VIL

VIH

VIL

VOH

VOL

CE# VIH

VIL

LB#/UB# VIH

VIL

tCW

tCVS

tWPH

tAS

tWC

tDH tDW

Data Data

High-Z

tHD

tSP

tSP tHD

tCSP

tWC

tBW

Valid

output Valid

output

Valid

output

Don’t Care Undefined

tHD

tBOE

tCBPH

tVPH

Note 2

tWP

tCEW

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64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory

Timing Diagrams

Figure 51: Asynchronous WRITE (ADV# LOW) Followed by Burst READ

Notes: 1. Nondefault BCR settings for asynchronous WRITE, with ADV# LOW, followed by burst

READ: fixed or variable latency; latency code 2 (3 clocks); WAIT active LOW; WAIT asserted

during delay.

2. When transitioning between asynchronous and variable-latency burst operations, CE# must

go HIGH. CE# can stay LOW when transitioning to fixed-latency burst READs. A refresh

opportunity must be provided every tCEM. A refresh opportunity is satisfied by either of the

following two conditions: a) clocked CE# HIGH or b) CE# HIGH for longer than 15ns.

tCLK

tSP tHD

tHD

Valid address

tCSP

tKOH

tACLK

High-Z

Valid address Valid address

A[21:0] VIH

VIL

ADV# VIH

VIL

OE# VIH

VIL

WE# VIH

VIL

WAIT

DQ[15:0]

IN/OUT

VOH

VOL

CLK VIH

VIL

VIH

VIL VOH

VOL

CE# VIH

VIL

LB#/UB# VIH

VIL tCW

tWPH

tWC

tDH tDW

Data Data

High-Z

tHD

tSP

tSP tHD

tWC tWC

tBW

tAW tWR tSP

Valid output Valid output Valid output Valid output

Undefined

Don’t Care

tBOE

tOHZ

tCEW

tCBPH

High-Z

Note 2

tWP

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64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory

Timing Diagrams

Figure 52: Burst READ Followed by Asynchronous WRITE (WE#-Controlled)

Notes: 1. Nondefault BCR settings for burst READ fo llo wed by asyn ch ro no us W E#-con trolled WRI TE:

fixed or variable latency; latency code 2 (3 clocks); WAIT active LOW; W AIT asserted during

delay.

2. When transitioning between asynchronous and variable-latency burst operations, CE# must

go HIGH. CE# can stay LOW when transitioning from fixed-latency burst READs. A refresh

opportunity must be provided every tCEM. A refresh opportunity is satisfied by either of the

following two conditions: a) clocked CE# HIGH or b) CE# HIGH for longer than 15ns.

A[21:0]

VIH

VIL

ADV#

VIH

VIL

CE#

VIH

VIL

OE#

VIH

VIL

WE#

VIH

VIL

WAIT

DQ[15:0]

VOH

VOL

CLK

VIH

VIL

VOH

VOL

tSP

tCLK

tACLK

tCEW

tHD

tAW

tCW

tWR

Valid output

Valid address

High-Z

tKOH tDW

tOHZ

tSP

LB#/UB#

VIH

VIL

tCSP

High-Z

tOLZ

tHD

tWP tWPH

tAS

tDH

tBW

tSP

tHZ

tHD

tSP

Undefined

Don’t Care

READ burst identified

(WE# = HIGH)

tHD

tKHTL

Valid input

High-Z

tCEW tHZ

tCBPH

Note 2

tBOE

Valid address

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64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory

Timing Diagrams

Figure 53: Burst READ Followed by Asynchronous WRITE Using ADV#

Notes: 1. Nondefault BCR settings for burst READ followed by asynchronous WRITE using ADV#: fixed

or variable latency; latency code 2 (3 clocks); WAIT active LOW; WAIT asserted during delay.

2. When transitioning between asynchronous and variable-latency burst operations, CE# must

go HIGH. CE# can stay LOW when transitioning from fixed-latency burst READs. A refresh

opportunity must be provided every tCEM. A refresh opportunity is satisfied by either of the

following two conditions: a) clocked CE# HIGH or b) CE# HIGH for longer than 15ns.

A[21:0]

VIH

VIL

ADV#

VIH

VIL

CE#

VIH

VIL

OE#

VIH

VIL

WE#

VIH

VIL

WAIT

DQ[15:0]

VOH

VOL

CLK

VIH

VIL

VOH

VOL

tSP

tCLK

tCEW

tHD

tVPH tVS

tAVS tAVH

tAW

tCW

Valid

output

Valid

address

High-Z

tKOH tDW

tOHZ

tSP

tHD tVP

LB#/UB#

VIH

VIL

tCSP

High-Z

tOLZ

tHD

tWP tWPH

tAS

tDH

tBW

tSP

tHZ

tSP

Undefined

Don’t Care

READ burst identified

(WE# = HIGH)

tKHTL

Valid

address

Valid

input

High-Z

tCEW tHZ

tCBPH

tACLK

tBOE

tAS

tHD

Note 2

PDF: 09005aef8247bd51/Source: 09005aef8247bd83 Micron Technology, Inc., reserves the right to change products or specifica tions without notice.

64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory

Timing Diagrams

Figure 54: Asynchronous WRITE Followed by Asynchronous READ – ADV# LOW

Notes: 1. When configured for synchr onous mode (BCR[15] = 0), CE# must remain HIGH for at least

5ns (tCPH) to schedule the appropriate refresh interval. Otherwis e, tCPH is only required

after CE#-controlled WRITEs.

Valid address Valid address

A[21:0] VIH

VIL

ADV# VIH

VIL

OE#

WE#

WAIT

DQ[15:0]

IN/OUT

VOH

VOL

VIH

VIL

VOH

VOL

CE#

LB#/UB# VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

tCW

tWPH

tWP

tAS tWC

tDH tDW

Data

High-Z

Valid address

tAA

tBHZ

tCPH

Valid

output

High-Z

tOE

tOLZ

tLZ

tBLZ

tOHZ

tHZ

tAW tWR

tBW

tHZ tHZ

Don’t Care Undefined

Data

Note 1

PDF: 09005aef8247bd51/Source: 09005aef8247bd83 Micron Technology, Inc., reserves the right to change products or specifica tions without notice.

64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory

Timing Diagrams

Figure 55: Asynchronous WRITE Followed by Asynchronous READ

Notes: 1. When configured for synchr onous mode (BCR[15] = 0), CE# must remain HIGH for at least

5ns (tCPH) to schedule the appropriate refresh interval. Otherwis e, tCPH is only required

after CE#-controlled WRITEs.

Valid address Valid address

tAVS tAVH

tVPH tVP tVS

A[21:0] VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

ADV#

OE#

WE#

WAIT

DQ[15:0]

IN/OUT

VOH

VOL

VIH

VIL

VOH

VOL

CE#

LB#/UB#

tCW

tWPH

tAS tWP

tWC

tDH tDW

Data Data

High-Z

Valid address

tAA

tBHZ

tCPH

Valid output

High-Z

tCVS

tOLZ

tLZ

tAS

tBLZ

tOHZ

tHZ

tAW tWR

tBW

Undefined

Don’t Care

Note 1

tOE

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900

prodmktg@micron.com www.micron.com Customer Comm ent Line: 800-932-4992

Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc. CellularRAM is a trademark of Micron

Te chnology, Inc., inside the U.S. and a trademark of Qimonda AG outside the U.S.

All other trademarks are the property of their respective owners.

This data sheet contains minimum and maximum limits specified over the complete power supply and temperature range

set forth herein. Although consider ed final, th es e specificat i o ns a re subject to change, as further pr oduct development and

data characterization sometimes occur.

64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory

Package Information

PDF: 09005aef8247bd51/Source: 09005aef8247bd83 Micron Technology, Inc., reserves the right to change products or specifica tions without notice.

Package Information

Figure 56: 54-Ball VFBGA

Notes: 1. All dimensions are in millimeters; MAX/MIN or typical (TYP) where noted.

2. Package width and length do not include mold protrusion; allowable mold protrusio n is

0.25mm per side.

3. The MT4 5W4MW16BCGB uses “green” packaging.

Ball A1 ID

0.70 ±0.05

Seating

plane

0.10 A

1.00 MAX

Ball A6 Ball A1

Ball A1 ID

0.75

TYP

0.75 TYP

1.875

3.75

6.00 ±0.10

3.00 ±0.05

Solder ball

diameter refers

to post-reflow

condition. The

pre-reflow

diameter is 0.35.

54X Ø0.37

Solder ball material:

96.5% Sn, 3% Ag, 0.5% Cu

Solder ball pad:

Ø0.30 solder mask defined

Mold compound: epoxy novolac

Substrate material: plastic laminate

6.00

3.00

4.00 ±0.05

8.00 ±0.10