Rev.3.00, Jul.13.2005, page 1 of 6
HD74LS156
Dual 2-line-to-4-line Decoders / Demultiplexers
(with open collector outputs) REJ03D0441–0300
Rev.3.00
Jul.13.2005
This circuit features dual 1-line-to-4-line demultiprex er with individual strobes and common binary-address input.
When both sections are enabled by the strobes, the common binary-address inputs sequentially select and route
associated input data to the appropriate output of each section. The individual strobes permit activating or inhibiting
each of the 4-bit sections as desired. Data applied to input 1C is inverted through its outputs. The inverter following
the 1C data input permits use as a 3-to-8-line decoder or 1-to-8-line demultiplex e r without ex ternal gating.
Features
• Ordering Information
Part Name Package Type Package Code
(Previous Code) Package
Abbreviation Taping Abbreviation
(Quantity)
HD74LS156P DILP-16 pin PRDP0016AE-B
(DP-16FV) P —
HD74LS156RPEL SOP-16 pin (JEDEC) PRSP0016DG-A
(FP-16DNV) FP EL (2,500 pcs/reel)
Note: Please consult the sales office for the above packa ge availability.
Pin Arrangement
(Top view)
V
CC
GND
Data 1C
Strobe 1G
Select Input B
1Y
3
1Y
2
1Y
1
1Y
0
Data 2C
Strobe 2G
2Y
3
Select Input A
2Y
2
2Y
1
2Y
0
15
161
2
3
4
5
6
7
14
89
10
11
12
13
1G
1C
2G
2C
1Y
3
A
B
A
B
A
B
A
B
1Y
2
1Y
1
1Y
0
2Y
3
2Y
2
2Y
1
2Y
0
Outputs
Outputs
HD74LS156
Rev.3.00, Jul.13.2005, page 2 of 6
Function Table
• 2-to-4-line Decoder / 1-to-4-line Demultiplexer
Inputs Outputs
Select Strobe Data
B A 1G 1C
1Y0 1Y1 1Y2 1Y3
X X H X H H H H
L L L H L H H H
L H L H H L H H
H L L H H H L H
H H L H H H H L
X X X L H H H H
Inputs Outputs
Select Strobe Data
B A 2G 2C
2Y0 2Y1 2Y2 2Y3
X X H X H H H H
L L L L L H H H
L H L L H L H H
H L L L H H L H
H H L L H H H L
X X X H H H H H
• 3-to-8-line Decoder / 1-to-8-line Demultiplexer
Inputs Outputs
Select Strobe or
Data (0) (1) (2) (3) (4) (5) (6) (7)
C*1 B A G*2 2Y0 2Y1 2Y2 2Y3 1Y0 1Y1 1Y2 1Y3
X X X H H H H H H H H H
L L L L L H H H H H H H
L L H L H L H H H H H H
L H L L H H L H H H H H
L H H L H H H L H H H H
H L L L H H H H L H H H
H L H L H H H H H L H H
H H L L H H H H H H L H
H H H L H H H H H H H L
Notes: 1. C; input 1C and 2C connected together
2. G; inputs 1G and 2G connected together
3. H; high level, L; low level, X; irrelevant
HD74LS156
Rev.3.00, Jul.13.2005, page 3 of 6
Block Diagram
Outputs
Strobe
1G
Data
1C
Select
B
Select
A
Data
2C
Strobe
2G
1Y0
1Y1
1Y2
1Y3
2Y0
2Y1
2Y2
2Y3
Absolute Maximum Ratings
Item Symbol Ratings Unit
Supply voltage VCC 7 V
Input voltage VIN 7 V
Power dissipation PT 400 mW
Storage temperature Tstg –65 to +150 °C
Note: Voltage value, unless otherwise noted, are with respect to network ground terminal.
Recommended Operating Conditions
Item Symbol Min Typ Max Unit
Supply voltage VCC 4.75 5.00 5.25 V
High level output voltage VOH — — 5.5 V
Low level output current IOL — — 8 mA
Operating temperature Topr –20 25 75 °C
Electrical Characteristics
(Ta = –20 to +75 °C)
Item Symbol min. typ.* max. Unit Condition
VIH 2.0 — — V
Input voltage VIL — — 0.8 V
Output current IOH — — 100 µA VCC = 4.75 V, VIH = 2 V, VIL = 0.8 V,
VOH = 5.5V
— — 0.4 IOL = 4 mA
Output voltage VOL — — 0.5 V IOL = 8 mA VCC = 4.75 V, VIH = 2 V,
VIL = 0.8 V
IIH — — 20 µA VCC = 5.25 V, VI = 2.7 V
IIL — — –0.4 mA VCC = 5.25 V, VI = 0.4 V
Input current II — — 0.1 mA VCC = 5.25 V, VI = 7 V
Supply current** ICC — 6.1 10 mA VCC = 5.25 V
Input clamp voltage VIK — — –1.5 V VCC = 4.75 V, IIN = –18 mA
Notes: * VCC = 5 V, Ta = 25°C
** ICC is measured with outputs open, A, B, and 1C inputs at 4.5 V, and 2C, 1G, and 2G inputs grounded.
HD74LS156
Rev.3.00, Jul.13.2005, page 4 of 6
Switching Characteristics
(VCC = 5 V, Ta = 25°C)
Item Symbol Inputs Output
Level of
logic min. typ. max. Unit Condition
tPLH A, B, 2C,
1G or 2G Y 2 — 25 40
tPHL A, B, 2C,
1G or 2G Y 2 — 34 51
tPLH A or B Y 3 — 31 46
tPHL A or B Y 3 — 34 51
tPLH 1C Y 3 — 32 48
Propagation
delay time
tPHL 1C Y 3 — 32 48
ns CL = 15 pF,
RL = 2 kΩ
Testing Method
Test Circuit
4.5V
1Y
0
1Y
1
1Y
2
1Y
3
2Y
0
2Y
1
2Y
3
1C
A
1G
B
2C
2G
Input
P.G.
Z
out
= 50Ω
See Testing Table
V
CC
2Y
2
R
L
C
L
Output
Note: CL includes probe and jig capacitance.
HD74LS156
Rev.3.00, Jul.13.2005, page 5 of 6
Waveform
t
PLH
t
PHL
V
OH
V
OL
0 V
3 V
V
OH
V
OL
t
PHL
t
PLH
10%
90%
1.3 V
1.3 V 1.3 V
1.3 V 1.3 V
1.3 V
10%
90%
Input
In phase output
Out of phase output
t
TLH
t
THL
Note: Input pulse; tTLH ≤ 15 ns, tTHL ≤ 6 ns, PRR = 1 MHz, duty cycle 50%
HD74LS156
Rev.3.00, Jul.13.2005, page 6 of 6
Package Dimensions
7.62
DP-16FV
RENESAS CodeJEITA Package Code Previous Code
MaxNomMin
Dimension in Millimeters
Symbol
Reference
19.2
6.3
5.06
MASS[Typ.]
1.05g
A
Z
b
D
E
A
b
c
θ
e
L
1
1
p
3
e
0.51
0.56
1.30
0.19 0.25 0.31
2.29 2.54 2.79
0
°
15
°
PRDP0016AE-BP-DIP16-6.3x19.2-2.54
20.32
7.4
0.40 0.48
1.12
2.54
1
p
1
3
1 8
16 9
e
b
A
LA
Z
e c
E
D
b
0.89
θ
( Ni/Pd/Au plating )
0.635
0.15
1.27
5.80 6.20
0.400.34
p
A
1
10.30
FP-16DNV
RENESAS CodeJEITA Package Code Previous Code
MaxNomMin
Dimension in Millimeters
Symbol
Reference
1.75
1.270.600.40
3.95
0.250.140.10
0.46
0.250.200.15
6.10
8
°
0
°
0.25
1.08
9.90
0.15g
MASS[Typ.]
1
E
1
1
2
L
Z
H
y
x
θ
c
b
A
E
D
b
c
e
e
L
A
P-SOP16-3.95x9.9-1.27 PRSP0016DG-A
Index mark
E
1
y
xM
p
*3
*2
*1
F
8
916
E
H
D
A
Zb
Terminal cross section
( Ni/Pd/Au plating )
p
b
c
Detail F
1
1
L
L
A
θ
NOTE)
1. DIMENSIONS"*1 (Nom)"AND"*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION"*3"DOES NOT
INCLUDE TRIM OFFSET.
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