NMOS linear image sensors are self-scanning photodiode arrays designed specifically as detectors for multichannel spectroscopy. The scanning
circuit is made up of N-channel MOS transistors, operates at low power consumption and is easy to handle. Each photodiode has a large active
area, high UV sensitivity yet very low noise, delivering a high S/N even at low light levels. NMOS linear image sensors also offer excellent output
linearity and wide dynamic range.
The photodiodes of S3902 series have a height of 0.5 mm and are arrayed in a row at a spacing of 50 µm. The photodiodes of S3903 series also
have a height of 0.5 mm but are arrayed at a spacing of 25 µm. The photodiodes are available in 3 different pixel quantities for each series: 128
(S3902-128Q), 256 (S3902-256Q, S3903-256Q), 512 (S3902-512Q, S3903-512Q) and 1024 (S3903-1024Q). Quartz glass is the standard window
material.
Features
l
Wide active area
Pixel pitch: 50 µm (S3902 series)
25 µm (S3903 series)
Pixel height: 0.5 mm
l
High UV sensitivity with good stability
l
Low dark current and high saturation charge allow a long
integration time and a wide dynamic range at room temperature
l
Excellent output linearity and sensitivity spatial uniformity
l
Lower power consumption: 1 mW Max.
l
Start pulse and clock pulses are CMOS logic compatible
Applications
l
Multichannel spectrophotometry
l
Image readout system
IMAGE SENSOR
NMOS linear image sensor
Current output, high UV sensitivity, excellent linearity, low power consumption
S3902/S3903 series
0.5 mm
1.0 µm
1.0 µm
400 µm
OXIDATION SILICON
N TYPE SILICON
P TYPE SILICON
S3902 SERIES: a=50 µm, b=45 µm
S3903 SERIES: a=25 µm, b=20 µm
b
a
KMPDC0020EA
Figure 1 Equivalent circuit
Vss
START st
CLOCK
CLOCK
1
2
ACTIVE
PHOTODIODE
SATURATION
CONTROL GATE
SATURATION
CONTROL DRAIN
DUMMY DIODE
DUMMY VIDEO
ACTIVE VIDEO
END OF SCAN
DEGITAL SHIFT REGISTER
(MOS SHIFT REGISTER)
Figure 2 Active area structure
KMPDA0107EA
■ Absolute maximum ratings
Parameter Symbol Value Unit
Input pulse (φ1, φ2, φst) voltage Vφ15 V
Power consumption *1P 1 mW
Operating temperature *
2Topr -40 to +65 °C
Storage temperature Tstg -40 to +85 °C
*1: Vφ=5.0 V
*2: No condensation
NMOS linear image sensor
S3902/S3903 series
■ Shape specifications
Parameter S3902-
128Q
S3902-
256Q
S3902-
512Q
S3903-
256Q
S3903-
512Q
S3903-
1024Q Unit
Number of pixels 128 256 512 256 512 1024 -
Package length 31.75 40.6 31.75 40.6 mm
Number of pin 22 22 -
Window material *3Quartz Quartz -
Weight 3.0 3.5 3.0 3.5 g
*3: Fiber optic plate is available.
■ Specifications (Ta=25 °C)
S3902 series S3903 series
Parameter Symbol Min. Typ. Max. Min. Typ. Max. Unit
Pixel pitch - -50- -25- µm
Pixel height - - 0.5 - - 0.5 -mm
Spectral response range
(10 % of peak) λ200 to 1000 200 to 1000 nm
Peak sensitivity wavelength λp-600 - - 600 -nm
Photodiode dark current *4ID- 0.08 0.15 - 0.04 0.08 pA
Photodiode capacitance *4Cph - 4 - - 2 - pF
Saturation exposure *4, *5Esat - 180 - - 180 - mlx · s
Saturation output charge *4Qsat -10 - - 5 - pC
Photo response non-uniformity *6PRNU--±3--±3 %
*4: Vb=2.0 V, Vφ=5.0 V
*5: 2856 K, tungsten lamp
*6: 50 % of saturation, excluding the start pixel and last pixel
■ Electrical characteristics (Ta=25 °C)
S3902 series S3903 series
Parameter Symbol Condition Min. Typ. Max. Min. Typ. Max. Unit
High Vφ1, Vφ2 (H) - 4.5 5 10 4.5 5 10 V
Clock pulse (φ1, φ2)
voltage Low Vφ1, Vφ2 (L) -0-0.40-0.4 V
High Vφs (H) -4.5 Vφ110 4.5 Vφ110 V
Start pulse (φst) voltage Low Vφs (L) - 0 - 0.4 0 - 0.4 V
Video bias voltage *7Vb - 1.5 Vφ - 3.0 Vφ - 2.5 1.5 Vφ - 3.0 Vφ - 2.5 V
Saturation control gate voltage Vscg - - 0 - - 0 - V
Saturation control drain voltage Vscd - - Vb - - Vb - V
Clock pulse (
φ
1,
φ
2) rise / fall time *8trφ1, trφ2
tfφ1, tfφ2- - 20 - - 20 -ns
Clock pulse (φ1, φ2) pulse width tpwφ1, tpwφ2-200- -200- - ns
Start pulse (φst) rise / fall time trφs, tfφs- - 20 - - 20 -ns
Start pulse (φ1, φ2) pulse width tpwφs-200- -200- - ns
Start pulse (φst) and clock pulse
(φ2) overlap tφov -200 - - 200 - - ns
Clock pulse space *8X1, X2- trf - 20 - - trf - 20 - - ns
Data rate *9f - 0.1 -2000 0.1 -2000 kHz
-70 (-128 Q) --
80 (-256 Q) -ns
-110 (-256 Q) --
120 (-512 Q) -nsVideo delay time tvd
50 % of
saturation
*9, *10 -140 (-512 Q) --
160 (-1024 Q) -ns
-21 (-128 Q) - - 27 (-256 Q) -pF
-36 (-256 Q) - - 50 (-512 Q) -pF
Clock pulse (φ1, φ2)
line capacitance Cφ5 V bias
-67 (-512 Q) - - 100 (-1024 Q) -pF
-12 (-128 Q) --
12 (-256 Q) -pF
-20 (-256 Q) --
24 (-512 Q) -pF
Saturation control gate (Vscg)
line capacitance Cscg 5 V bias
-35 (-512 Q) --
45 (-1024 Q) -pF
-7 (-128 Q) - - 10 (-256 Q) -pF
-11 (-256 Q) - - 16 (-512 Q) -pFVideo line capacitance CV2 V bias
-20 (-512 Q) - - 30 (-1024 Q) -pF
*7: Vφ is input pulse voltage (refer to figure 8)
*8: trf is the clock pulse rise or fall time. A clock pulse space of
rise time/fall time - 20 ns (nanoseconds) or more should be
input if the clock pulse rise or fall time is longer than 20 ns. (refer to figure 7)
*9: Vb=2.0 V, Vφ=5.0 V
*10: Measured with C7883 driver circuit.
NMOS linear image sensor
S3902/S3903 series
Figure 3 Dimensional outlines (unit: mm)
S3902-128Q, S3903-256Q S3902-256Q, S3903-512Q
0.51
25.4
2.54
3.0
31.75
10.4
5.2 ± 0.25.2 ± 0.2
3.2 ± 0.3
ACTIVE AREA
6.4 × 0.5
0.25
10.16
1.3 ± 0.2*
PHOTOSENSITIVE
SURFACE
* Optical distance from the outer surface
of the quartz window to the chip surface
0.51
25.4
2.54
3.0
ACTIVE AREA
12.8 × 0.5
6.4 ± 0.3
31.75
10.4
5.2 ± 0.25.2 ± 0.2
0.25
10.16
1.3 ± 0.2*
PHOTOSENSITIVE
SURFACE
* Optical distance from the outer surface
of the quartz window to the chip surface
KMPDA0108EA KMPDA0109EA
S3902-512Q, S3903-1024Q
0.51
25.4
3.0
40.6
10.4
5.2 ± 0.25.2 ± 0.2
12.8 ± 0.3
ACTIVE AREA
25.6 × 0.5
0.25
10.16
1.3 ± 0.2 *
PHOTOSENSITIVE
SURFACE
* Optical distance from the outer surface
of the quartz window to the chip surface
2.54
KMPDA0110EA
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
END OF SCAN
1
2
3
4
5
6
7
8
9
10
11
22
21
20
19
18
17
16
15
14
13
12
2
1
st
Vss
Vscg
NC
Vscd
Vss
ACTIVE VIDEO
DUMMY VIDEO
Vsub
Vss, Vsub and NC should be grounded.
KMPDC0056EA
Figure 4 Pin connection
NMOS linear image sensor
S3902/S3903 series
0.3
0.2
0.1
0200 400 600 800 1000 1200
WAVELENGTH (nm)
PHOTO SENSITIVITY (A/W)
(Ta=25 ˚C)
Terminal Input or output Description
φ1, φ2Input
(CMOS logic compatible)
Pulses for operating the MOS shift register. The video data rate is
equal to the clock pulse frequency since the video output signal is
obtained synchronously with the rise of φ2 pulse.
φst Input
(CMOS logic compatible)
Pulse for starting the MOS shift register operation. The time interval
between start pulses is equal to the signal accumulation time.
Vss - Connected to the anode of each photodiode. This should be
grounded.
Vscg Input Used for restricting blooming. This should be grounded.
Vscd Input Used for restricting blooming. This should be biased at a voltage
equal to the video bias voltage.
Active video Output
Video output signal. Connects to photodiode cathodes when the
address is on. A positive voltage should be applied to the video
line in order to use photodiodes with a reverse voltage. When the
amplitude of φ1 and φ2 is 5 V, a video bias voltage of 2 V is
recommended.
Dummy video Output
This has the same structure as the active video, but is not
connected to photodiodes, so only spike noise is output. This
should be biased at a voltage equal to the active video or left as an
open-circuit when not needed.
Vsub -Connected to the silicon substrate. This should be grounded.
End of scan Output
(CMOS logic compatible)
This should be pulled up at 5 V by using a 10 kΩ resistor. This is a
negative going pulse that appears synchronously with the φ2
timing right after the last photodiode is addressed.
NC -Should be grounded.
10–5
102
101
100
10–1
10–2
10–3
10–410–310–210–1100
OUTPUT CHARGE (pC)
EXPOSURE (lx · s)
(Typ. Vb=2 V, V
=5 V, light source: 2856 K)
S3903 SERIES
S3902 SERIES
SATURATION EXPOSURE
SATURATION
CHARGE
KMPDB0149EA
Figure 5 Spectral response (typical example) Figure 6 Output charge vs. exposure
KMPDB0117EA
■ Construction of image sensor
The NMOS image sensor consists of a scanning circuit made
up of MOS transistors, a photodiode array, and a switching
transistor array that addresses each photodiode, all integrated
onto a monolithic silicon chip. Figure 1 shows the circuit of a
NMOS linear image sensor.
The MOS scanning circuit operates at low power consump-
tion and generates a scanning pulse train by using a start
pulse and 2-phase clock pulses in order to turn on each ad-
dress sequentially. Each address switch is comprised of an
NMOS transistor using the photodiode as the source, the
video line as the drain and the scanning pulse input section
as the gate.
The photodiode array operates in charge integration mode
so that the output is proportional to the amount of light expo-
sure (light intensity × integration time).
Each cell consists of an active photodiode and a dummy
photodiode, which are respectively connected to the active
video line and the dummy video line via a switching transis-
tor. Each of the active photodiodes is also connected to the
saturation control drain via the saturation control transistor,
so that the photodiode blooming can be suppressed by
grounding the saturation control gate. Applying a pulse sig-
nal to the saturation control gate triggers all reset. (See “Aux-
iliary functions”.)
Figure 2 shows the schematic diagram of the photodiode
active area. This active area has a PN junction consisting of
an N-type diffusion layer formed on a P-type silicon substrate.
A signal charge generated by light input accumulates as a
capacitive charge in this PN junction. The N-type diffusion
layer provides high UV sensitivity but low dark current.
NMOS linear image sensor
S3902/S3903 series
■ Driver circuit
S3902/S3903 series do not require any DC voltage supply
for operation. However, the Vss, Vsub and all NC terminals
must be grounded. A start pulse φst and 2-phase clock pulses
φ1, φ2 are needed to drive the shift register. These start and
clock pulses are positive going pulses and CMOS logic com-
patible.
The 2-phase clock pulses φ1, φ2 can be either completely
separated or complementary. However, both pulses must not
be “High” at the same time.
A clock pulse space (X1 and X2 in Figure 7) of a “rise time/fall
time - 20” ns or more should be input if the rise and fall times
of φ1, φ2 are longer than 20 ns. The φ1 and φ2 clock pulses
must be held at “High” at least 200 ns. Since the photodiode
signal is obtained at the rise of each φ2 pulse, the clock pulse
frequency will equal the video data rate.
The amplitude of start pulse φst is the same as the φ1 and φ2
pulses. The shift register starts the scanning at the “High”
level of φst, so the start pulse interval determines the length of
signal accumulation time. The φst pulse must be held “High”
at least 200 ns and overlap with φ2 at least for 200 ns. To
operate the shift register correctly, φ2 must change from the
“High” level to the “Low” level only once during “High” level of
φst. The timing chart for each pulse is shown in Figure 7.
■ End of scan
The end of scan (EOS) signal appears in synchronization
with the φ2 timing right after the last photodiode is addressed,
and the EOS terminal should be pulled up at 5 V using a 10
kΩ resistor.
tvd
tpw
1
tpw
2
tpw
s
st V
s (H)
V
s (L)
V
1 (H)
V
1 (L)
V
2 (H)
V
2 (L)
1
2
END OF SCAN
st
1
2
tr
s tf
s
tr
1 tf
1
X1 X2
t
ov
tf
2
tr
2
ACTIVE VIDEO OUTPUT
KMPDC0022EA
Figure 7 Timing chart for driver circuit
■ Signal readout circuit
There are two methods for reading out the signal from an NMOS
linear image sensor. One is a current detection method using
the load resistance and the other is a current integration method
using a charge amplifier. In either readout method, a positive
bias must be applied to the video line because photodiode
anodes of NMOS linear image sensors are set at 0 V (Vss).
Figure 8 shows a typical video bias voltage margin. As the clock
pulse amplitude is higher, the video bias voltage can be set
larger so the saturation charge can be increased. The rise and
fall times of the video output waveform can be shortened if the
video bias voltage is reduced while the clock pulse amplitude is
still higher. When the amplitude of φ1, φ2 and φst is 5 V, setting
the video bias voltage at 2 V is recommended.
To obtain good linearity, using the current integration method is
advised. In this method, the integration capacitance is reset to
the reference voltage level immediately before each photodiode
is addressed and the signal charge is then stored as an integra-
tion capacitive charge when the address switch turns on. Fig-
ures 9 and 10 show a typical current integration circuit and its
pulse timing chart. To ensure stable output, the rise of a reset
pulse must be delayed at least 50 ns from the fall of φ2.
Hamamatsu provides the following driver circuits and related
products (sold separately).
KMPDB0043EA
Figure 8 Video bias voltage margin
4
0
6
8
10
45678 10
CLOCK PULSE AMPLITUDE (V)
VIDEO BIAS VOLTAGE (V)
2
9
MIN.
VIDEO BIAS RANGE
MAX.
RECOMMENDED BIAS
Product
name Type No. Content Feature
C7883 High-speed
driver circuit
C7883G C7883
+ C8225-01
High-speed operation
Single power supply
(+15 V) operation
Compact
C7884 Precision
driver circuit
C7884G C7884
+ C8225-01
Low noise
Good output linearity
Boxcar waveform output
C7884-01 High precision
driver circuit
Driver
circuit
C7884G-01 C7884-01
+ C8225-01
Ultra-low noise
Good output linearity
Boxcar waveform output
Pulse
generator C8225-01 C7883,
C7884 series
Cable A8226 C7883 to
C7885 series BNC, length 1 m
HAMAMATSU PHOTONICS K.K., Solid State Division
1126-1 Ichino-cho, Hamamatsu City, 435-8558 Japan, Telephone: (81) 053-434-3311, Fax: (81) 053-434-5184, www.hamamatsu.com
U.S.A.: Hamamatsu Corporation: 360 Foothill Road, P.O.Box 6910, Bridgewater, N.J. 08807-0910, U.S.A., Telephone: (1) 908-231-0960, Fax: (1) 908-231-1218
Germany: Hamamatsu Photonics Deutschland GmbH: Arzbergerstr. 10, D-82211 Herrsching am Ammersee, Germany, Telephone: (49) 08152-3750, Fax: (49) 08152-2658
France: Hamamatsu Photonics France S.A.R.L.: 8, Rue du Saule Trapu, Parc du Moulin de Massy, 91882 Massy Cedex, France, Telephone: 33-(1) 69 53 71 00, Fax: 33-(1) 69 53 71 10
United Kingdom: Hamamatsu Photonics UK Limited: 2 Howard Court, 10 Tewin Road, Welwyn Garden City, Hertfordshire AL7 1BW, United Kingdom, Telephone: (44) 1707-294888, Fax: (44) 1707-325777
North Europe: Hamamatsu Photonics Norden AB: Smidesvägen 12, SE-171 41 Solna, Sweden, Telephone: (46) 8-509-031-00, Fax: (46) 8-509-031-01
Italy: Hamamatsu Photonics Italia S.R.L.: Strada della Moia, 1/E, 20020 Arese, (Milano), Italy, Telephone: (39) 02-935-81-733, Fax: (39) 02-935-81-741
Information furnished by HAMAMATSU is believed to be reliable. However, no responsibility is assumed for possible inaccuracies or omissions.
Specifications are subject to change without notice. No patent rights are granted to any of the circuits described herein. ©2005 Hamamatsu Photonics K.K.
NMOS linear image sensor
S3902/S3903 series
Cat. No. KMPD1043E01
Oct. 2005 DN
Figure 9 Readout circuit example and timing chart
st
2
1
Vscg
Vss
Vsub
NC
EOS EOS
10 kΩ
+5 V
+2 V
+
+
–
RESET
10 pF
OP-AMP (JFET INPUT)
OPEN
DUMMY
VIDEO
ACTIVE
VIDEO
Vscd
st
2
1
KMPDC0023EA
50 ns MIN.
st
1, Reset
2
KMPDC0024EA
■ Anti-blooming function
If the incident light intensity is higher than the saturation charge level, even partially, a signal charge in excess of the saturation
charge cannot accumulate in the photodiode. This excessive charge flows out into the video line degrading the signal purity. To
avoid this problem and maintain the signal purity, applying the same voltage as the video bias voltage to the saturation control
drain and grounding the saturation control gate are effective. If the incident light intensity is extremely high, a positive bias should
be applied to the saturation control gate. The larger the voltage applied to the saturation control gate, the higher the function for
suppressing the excessive saturation charge will be. However, this voltage also lowers the amount of saturation charge, so an
optimum bias voltage should be selected.
■ Auxiliary functions
1) All reset
In normal operation, the accumulated charge in each photodiode is reset when the signal is read out. Besides this method that
uses the readout line, S3902/S3903 series can reset the photodiode charge by applying a pulse to the saturation control gate.
The amplitude of this pulse should be equal to the φ1, φ2 and φst pulses and the pulse width should be longer than 5 µs.
When the saturation control gate is set at the “High” level, all photodiodes are reset to the saturation control drain potential
(equal to video bias). Conversely, when the saturation control gate is set at the “Low” level (0 V), the signal charge accumulates
in each photodiode without being reset.
2) Dummy video
S3902/S3903 series have a dummy video line to eliminate spike noise contained in the video output waveform. Video signal
with lower spike noise can be obtained by differential amplification applied between the active video line and dummy video
line outputs. When not needed, leave this unconnected.
■ Handling precautions
1) Electrostatic countermeasures
NMOS linear image sensors are designed to resist static electrical charges. However, take sufficient cautions and countermea-
sures to prevent damage from static charges when handling the sensors.
2) Window
If dust or grime sticks to the surface of the light input window, it appears as a black blemish or smear on the image. Before using
the image sensor, the window surface should be cleaned. Wipe off the window surface with a soft cloth, cleaning paper or
cotton swab slightly moistened with organic solvent such as alcohol, and then lightly blow away with compressed air. Do not
rub the window with dry cloth or cotton swab as this may generate static electricity.
Output voltage Vout is
Vout [V] = Output charge [C]
10 × 10-12 [F]
shown in.
