LTC4300-1/LTC4300-2
1
sn430012 430012fs
The LTC
®
4300 series hot swappable 2-wire bus buffers
allow I/O card insertion into a live backplane without cor-
ruption of the data and clock busses. When the connection
is made, the LTC4300-1/LTC4300-2 provide bidirectional
buffering, keeping the backplane and card capacitances
isolated. Rise-time accelerator circuitry* allows the use of
weaker DC pull-up currents while still meeting rise-time
requirements. During insertion, the SDA and SCL lines are
precharged to 1V to minimize bus disturbances.
The LTC4300-1 incorporates a CMOS threshold digital
ENABLE input pin, which forces the part into a low current
mode when driven to ground and sets normal operation when
driven to V
CC
. It also includes an open drain READY output
pin, which indicates that the backplane and card sides are
connected together. The LTC4300-2 replaces the ENABLE
pin with a dedicated supply voltage pin, V
CC2
, for the card
side, providing level shifting between 3.3V and 5V systems.
Both the backplane and card may be powered with supply
voltages ranging from 2.7V to 5.5V, with no contraints on
which supply voltage is higher. The LTC4300-2 also replaces
the READY pin with a digital CMOS input pin, ACC, which
enables and disables the rise-time accelerator currents.
The LTC4300 is available in a small 8-pin MSOP package.
■
Hot Board Insertion
■
Servers
■
Capacitance Buffer/Bus Extender
■
Desktop Computer
, LTC and LT are registered trademarks of Linear Technology Corporation.
■
Bidirectional Buffer for SDA and SCL Lines
Increases Fanout
■
Prevents SDA and SCL Corruption During Live
Board Insertion and Removal from Backplane
■
Isolates Input SDA and SCL Lines from Output
■
Compatible with I
2
C
TM
, I
2
C Fast Mode and SMBus
Standards (Up to 400kHz Operation)
■
Small MSOP 8-Pin Package
■
Low I
CC
Chip Disable: <1µA (LTC4300-1)
■
READY Open Drain Output (LTC4300-1)
■
1V Precharge on all SDA and SCL Lines
■
Supports Clock Stretching, Arbitration and
Synchronization
■
5V to 3.3V Level Translation (LTC4300-2)
■
High Impedance SDA, SCL Pins for V
CC
= 0V
Hot Swappable
2-Wire Bus Buffers
I
2
C is a trademark of Philips Electronics N. V.
*U.S. Patent No. 6,650,174
R1
24k
V
CC
3.3V
R2
24k
ENABLE
SCLIN SCLOUT
SDAIN SDAOUT
15
4
67
32
8
GND
LTC4300-1READY
C1
0.01µF
C2* C4*
C5*
C3*
4300-1/2 TA01
R3
24k R4
24k
*CAPACITORS NOT REQUIRED
IF BUS IS SUFFICIENTLY LOADED
APPLICATIO S
U
FEATURES
TYPICAL APPLICATIO
U
DESCRIPTIO
U
Input–Output Connection tPLH
OUTPUT
SIDE
50pF
INPUT
SIDE
150pF
LTC4300-1/LTC4300-2
2
sn430012 430012fs
V
CC
to GND .................................................... –0.5 to 7V
V
CC2
to GND (LTC4300-2) .............................–0.5 to 7V
SDAIN, SCLIN, SDAOUT, SCLOUT.................–0.5 to 7V
READY, ENABLE (LTC4300-1)....................... –0.5 to 7V
ACC (LTC4300-2) ..........................................–0.5 to 7V
Operating Temperature Range
LTC4300-1C/LTC4300-2C ....................... 0°C to 70°C
LTC4300-1I/LTC4300-2I .................... –40°C to 85°C
Storage Temperature Range ................. –65°C to 125°C
Lead Temperature (Soldering, 10 sec)..................300°C
ORDER PART
NUMBER
MS8
PART MARKING
T
JMAX
= 125°C, θ
JA
= 200°C/W
Consult LTC marketing for parts specified with wider operating temperature ranges.
LTUB
LTUC
LTVJ
LTVK
LTC4300-1CMS8
LTC4300-1IMS8
LTC4300-2CMS8
LTC4300-2IMS8
ABSOLUTE AXI U RATI GS
W
WW
U
PACKAGE/ORDER I FOR ATIO
UUW
(Note 1)
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specfications are at TA = 25°C. VCC = 2.7V to 5.5V, unless otherwise noted.
1
2
3
4
ENABLE/V
CC2
*
SCLOUT
SCLIN
GND
8
7
6
5
V
CC
SDAOUT
SDAIN
READY/ACC*
TOP VIEW
MS8 PACKAGE
8-LEAD PLASTIC MSOP
*LTC4300-2
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Power Supply
V
CC
Positive Supply Voltage ●2.7 5.5 V
I
CC
Supply Current V
CC
= 5.5V, V
SDAIN
= V
SCLIN
= 0V, LTC4300-1 ●2.8 6 mA
I
SD
Supply Current in Shutdown Mode V
ENABLE
= 0V, LTC4300-1 0.1 µA
V
CC2
Card Side Supply Voltage LTC4300-2 ●2.7 5.5 V
I
VCC1
V
CC
Supply Current V
SDAIN
= V
SCLIN
= 0V, V
CC1
= V
CC2
= 5.5V, 1.8 3.6 mA
LTC4300-2
I
VCC2
V
CC2
Supply Current V
SDAOUT
= V
SCLOUT
= 0V, V
CC1
= V
CC2
= 5.5V, 1.2 2.4 mA
LTC4300-2
Start-Up Circuitry
V
PRE
Precharge Voltage SDA, SCL Floating ●0.8 1.0 1.2 V
t
IDLE
Bus Idle Time ●50 95 150 µs
V
EN
ENABLE Threshold Voltage LTC4300-1 0.5 • V
CC
0.9 • V
CC
V
V
DIS
Disable Threshold Voltage LTC4300-1, ENABLE Pin 0.1 • V
CC
0.5 • V
CC
V
I
EN
ENABLE Input Current ENABLE from 0V to V
CC
, LTC4300-1 ±0.1 ±1µA
t
PHL
ENABLE Delay, On-Off LTC4300-1 100 ns
READY Delay, Off-On LTC4300-1 10 ns
t
PLH
ENABLE Delay, Off-On LTC4300-1 80 µs
READY Delay, On-Off LTC4300-1 10 µs
I
OFF
READY OFF State Leakage Current LTC4300-1 ±0.1 µA
V
OL
READY Output Low Voltage I
PULLUP
= 3mA, LTC4300-1 ●0.4 V
LTC4300-1/LTC4300-2
3
sn430012 430012fs
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired
Note 2: I
PULLUPAC
varies with temperature and V
CC
voltage, as shown in
the Typical Performance Characteristics section.
Note 3: The connection circuitry always regulates its output to a higher
voltage than its input. The magnitude of this offset voltage as a function of
the pullup resistor and V
CC
voltage is shown in the Typical Performance
Characteristics section.
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specfications are at TA = 25°C. VCC = 2.7V to 5.5V, unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Rise-Time Accelerators
I
PULLUPAC
Transient Boosted Pull-Up Current Positive Transition on SDA,SCL, V
CC
= 2.7V, 1 2 mA
Slew Rate = 1.25V/µs (Note 2),
LTC4300-2, ACC = 0.7 • V
CC2
, V
CC2
= 2.7V
V
ACCDIS
Accelerator Disable Threshold LTC4300-2 0.3 • V
CC2
0.5 • V
CC2
V
V
ACCEN
Accelerator Enable Threshold LTC4300-2 0.5 • V
CC2
0.7 • V
CC2
V
I
VACC
ACC Input Current LTC4300-2 ±0.1 ±1µA
t
PDOFF
ACC Delay, On/Off LTC4300-2 5 ns
Input-Output Connection
V
OS
Input-Output Offset Voltage 10k to V
CC
on SDA, SCL, V
CC
= 3.3V (Note 3), ●0 75 150 mV
LTC4300-2, V
CC2
= 3.3V, V
IN
= 0.2V
f
SCL, SDA
Operating Frequency Guaranteed by Design, Not Subject to Test 0 400 kHz
C
IN
Digital Input Capacitance Guaranteed by Design, Not Subject to Test 10 pF
V
OL
Output Low Voltage, Input = 0V SDA, SCL Pins, I
SINK
= 3mA, V
CC
= 2.7V, ●0 0.4 V
V
CC2
= 2.7V, LTC4300-2
I
LEAK
Input Leakage Current SDA, SCL Pins = V
CC
= 5.5V, ±5µA
LTC4300-2, V
CC2
= 5.5V
Timing Characteristics
f
I2C
I
2
C Operating Frequency (Note 4) 0 400 kHz
t
BUF
Bus Free Time Between Stop (Note 4) 1.3 µs
and Start Condition
t
hD,STA
Hold Time After (Repeated) (Note 4) 0.6 µs
Start Condition
t
su,STA
Repeated Start Condition Setup Time (Note 4) 0.6 µs
t
su,STO
Stop Condition Setup Time (Note 4) 0.6 µs
t
hD, DAT
Data Hold Time (Note 4) 300 ns
t
su, DAT
Data Setup Time (Note 4) 100 ns
t
LOW
Clock Low Period (Note 4) 1.3 µs
t
HIGH
Clock High Period (Note 4) 0.6 µs
t
f
Clock, Data Fall Time (Notes 4, 5) 20 + 0.1 • C
B
300 ns
t
r
Clock, Data Rise Time (Notes 4, 5) 20 + 0.1 • C
B
300 ns
Note 4: Guaranteed by design, not subject to test.
Note 5: C
B
= total capacitance of one bus line in pF.
LTC4300-1/LTC4300-2
4
sn430012 430012fs
–50 –25 0 25 50 75 100
TEMPERATURE (°C)
IPULLUPAC (mA)
4300-1/2 G03
12
10
8
6
4
2
0
VCC = 2.7V
VCC = 5V
VCC = 3V
R
PULLUP
(Ω)
010,000 20,000 30,000 40,000
V
OUT
– V
IN
(mV)
4300-1/2 G04
300
250
200
150
100
50
0
V
CC
= 3.3V
V
CC
= 5V
T
A
= 25°C
V
IN
= 0V
IPULLUPAC vs Temperature Connection Circuitry VOUT – VIN
TYPICAL PERFOR A CE CHARACTERISTICS
UW
–50 –25 0 25 50 75 100
TEMPERATURE (°C)
t
PHL
(ns)
4300-1/2 G02
100
80
60
40
20
0
V
CC
= 2.7V
V
CC
= 3.3V
V
CC
= 5.5V
C
IN
= C
OUT
= 100pF
R
PULLUPIN
= R
PULLUPOUT
= 10k
Input – Output t
PHL
vs Temperature
(LTC4300-1)
–50 –25 0 25 50 75 100
TEMPERATURE (°C)
I
CC
(mA)
4300-1/2 G01
3.0
2.9
2.8
2.7
2.6
2.5
2.4
2.3
2.2
V
CC
= 5.5V
V
CC
= 2.7V
ICC vs Temperature (LTC4300-1)
LTC4300-1/LTC4300-2
5
sn430012 430012fs
ENABLE/V
CC2
(Pin 1): Chip Enable Pin/Card Supply Volt-
age. For the LTC4300-1, this is a digital CMOS threshold
input pin. Grounding this pin puts the part in a low current
(<1µA) mode. It also disables the rise-time accelerators,
disables the bus precharge circuitry, drives READY low,
isolates SDAIN from SDAOUT and isolates SCLIN from
SCLOUT. Drive ENABLE all the way to V
CC
for normal
operation. Connect ENABLE to V
CC
if this feature is not
being used. For the LTC4300-2, this is the supply voltage
for the devices on the card I
2
C busses. Connect pull-up
resistors from SDAOUT and SCLOUT to this pin. Place a
bypass capacitor of at least 0.01µF close to this pin for best
results.
SCLOUT (Pin 2): Serial Clock Output. Connect this pin to
the SCL bus on the card. See Figures 3 and 4 for bus pull-
up resistance and capacitance requirements.
SCLIN (Pin 3): Serial Clock Input. Connect this pin to the
SCL bus on the backplane. See Figures 3 and 4 for bus pull-
up resistance and capacitance requirements.
GND (Pin 4): Ground. Connect this pin to a ground plane
for best results.
READY/ACC (Pin 5): Connection Flag/Rise-Time Accel-
erator Control. For the LTC4300-1, this is an open-drain
NMOS output which pulls low when either ENABLE is low
or the start-up sequence described in the Operation sec-
tion has not been completed. READY goes high when
ENABLE is high and start-up is complete. Connect a 10k
resistor from this pin to V
CC
to provide the pull up. For the
LTC4300-2, this is a CMOS threshold digital input pin that
enables and disables the rise-time accelerators on all four
SDA and SCL pins. Drive ACC all the way to the V
CC2
supply
voltage to enable all four accelerators; drive ACC to ground
to turn them off.
SDAIN (Pin 6): Serial Data Input. Connect this pin to the
SDA bus on the backplane. See Figures 3 and 4 for bus
pull-up resistance and capacitance requirements.
SDAOUT (Pin 7): Serial Data Output. Connect this pin to
the SDA bus on the card. See Figures 3 and 4 for bus pull-
up resistance and capacitance requirements.
V
CC
(Pin 8): Main Input Power Supply from Backplane.
This is the supply voltage for the devices on the backplane
I
2
C busses. Connect pull-up resistors from SDAIN and
SCLIN to this pin. Place a bypass capacitor of at least
0.01µF close to this pin for best results.
PI FU CTIO S
UUU
LTC4300-1/LTC4300-2
6
sn430012 430012fs
100k
RCH1 100k
RCH3
–
+
5
–
+
0.5pF
READY
1ENABLE
UVLO
3SCLIN
4300-1 BD
CONNECT
STOP BIT AND BUS IDLE
4
4
GND
CONNECT
20pF
RD
SQB
0.5µA
0.55V
CC
/
0.45V
CC
–
+
–
+
0.55V
CC
/
0.45V
CC
2mA
95µs
DELAY
BACKPLANE-TO-CARD
CONNECTION
CONNECTCONNECT
2SCLOUT
6SDAIN BACKPLANE-TO-CARD
CONNECTION
CONNECT CONNECT
7SDAOUT
8V
CC
1V
PRECHARGE
100k
RCH2 100k
RCH4
SLEW RATE
DECTECTOR
2mA
SLEW RATE
DECTECTOR
2mA
SLEW RATE
DECTECTOR
2mA
SLEW RATE
DECTECTOR
CONNECT
ENABLE
2-Wire Bus Buffer and Hot Swap
TM
Controller
BLOCK DIAGRA
W
Hot Swap is a trademark of Linear Technology Corporation.
(LTC4300-1)
LTC4300-1/LTC4300-2
7
sn430012 430012fs
BLOCK DIAGRA
W
(LTC4300-2)
100k
RCH1 100k
RCH3
–
+
–
+
0.5pF
UVLO
3SCLIN
4300-2 BD
CONNECT CONNECT
STOP BIT AND BUS IDLE
4
4
GND
20pF
RD
SQB
0.5µA
0.55V
CC
/
0.45V
CC
–
+
–
+
0.55V
CC2
/
0.45V
CC2
2mA
95µs
DELAY
BACKPLANE-TO-CARD
CONNECTION
CONNECTCONNECT
2SCLOUT
6SDAIN
8V
CC
BACKPLANE-TO-CARD
CONNECTION
CONNECT CONNECT
7SDAOUT
1V
CC2
5ACC
1V
PRECHARGE
100k
RCH2 100k
RCH4
CONNECT
SLEW RATE
DECTECTOR
2mA
SLEW RATE
DECTECTOR
2mA
SLEW RATE
DECTECTOR
ACC
ACC
2mA
SLEW RATE
DECTECTOR
2-Wire Bus Buffer and Hot Swap Controller
LTC4300-1/LTC4300-2
8
sn430012 430012fs
OPERATIO
U
the waveforms on the backplane busses look slightly
different than the corresponding card bus waveforms, as
described here.
Input to Output Offset Voltage
When a logic low voltage, V
LOW1
, is driven on any of the
LTC4300’s data or clock pins, the LTC4300 regulates the
voltage on the other side of the chip (call it V
LOW2
) to a
slightly higher voltage, as directed by the following
equation:
V
LOW2
= V
LOW1
+ 50mV + (V
CC
/R) • 100
where R is the bus pull-up resistance in ohms. For ex-
ample, if a device is forcing SDAOUT to 10mV and if
V
CC
= 3.3V and the pull-up resistor R on SDAIN is 10k, then
the voltage on SDAIN = 10mV + 50mV + (3.3/10000) • 100
= 93mV. See the Typical Performance Characteristics
section for curves showing the offset voltage as a function
of V
CC
and R.
Propagation Delays
During a rising edge, the rise-time on each side is deter-
mined by the combined pull-up current of the LTC4300
boost current and the bus resistor and the equivalent
capacitance on the line. If the pull-up currents are the
same, a difference in rise-time occurs which is directly
proportional to the difference in capacitance between the
two sides. This effect is displayed in Figure 1 for V
CC
= 3.3V
and a 10k pull-up resistor on each side (50pF on one side
and 150pF on the other). Since the output side has less
capacitance than the input, it rises faster and the effective
t
PLH
is negative.
There is a finite propagation delay, t
PHL
, through the
connection circuitry for falling waveforms. Figure 2 shows
the falling edge waveforms for the same V
CC
, pull-up
resistors and equivalent capacitance conditions as used in
Figure 1. An external NMOS device pulls down the voltage
on the side with 150pF capacitance; the LTC4300 pulls
down the voltage on the opposite side, with a delay of
55ns. This delay is always positive and is a function of
supply voltage, temperature and the pull-up resistors and
equivalent bus capacitances on both sides of the bus. The
Typical Performance Characteristics section shows t
PHL
Start-Up
When the LTC4300 first receives power on its V
CC
pin,
either during power-up or during hot swapping, it starts in
an undervoltage lockout (UVLO) state, ignoring any activ-
ity on the SDA and SCL pins until V
CC
rises above 2.5V. For
the LTC4300-2, the part also waits for V
CC2
to rise above
2V. This ensures that the part does not try to function until
it has enough voltage to do so.
During this time, the 1V precharge circuitry is also active
and forces 1V through 100k nominal resistors to the SDA
and SCL pins. Because the I/O card is being plugged into
a live backplane, the voltage on the backplane SDA and SCL
busses may be anywhere between 0V and V
CC
. Precharging
the SCL and SDA pins to 1V minimizes the worst-case
voltage differential these pins will see at the moment of con-
nection, therefore minimizing the amount of disturbance
caused by the I/O card.
Once the LTC4300 comes out of UVLO, it assumes that
SDAIN and SCLIN have been hot swapped into a live
system and that SDAOUT and SCLOUT are being powered
up at the same time as itself. Therefore, it looks for either
a stop bit or bus idle condition on the backplane side to
indicate the completion of a data transaction. When either
one occurs, the part also verifies that both the SDAOUT
and SCLOUT voltages are high. When all of these condi-
tions are met, the input-to-output connection circuitry is
activated, joining the SDA and SCL busses on the I/O card
with those on the backplane.
Connection Circuitry
Once the connection circuitry is activated, the functional-
ity of the SDAIN and SDAOUT pins is identical. A low forced
on either pin at any time results in both pin voltages being
low. SDAIN and SDAOUT enter a logic high state only when
all devices on both SDAIN and SDAOUT force a high. The
same is true for SCLIN and SCLOUT. This important fea-
ture ensures that clock stretching, clock arbitration and the
acknowledge protocol always work, regardless of how the
devices in the system are tied to the LTC4300.
Another key feature of the connection circuitry is that it
provides bidirectional buffering, keeping the backplane
and card capacitances isolated. Because of this isolation,
LTC4300-1/LTC4300-2
9
sn430012 430012fs
as a function of temperature and voltage for 10k pull-up
resistors and 100pF equivalent capacitance on both sides
of the part. By comparison with Figure 2, the V
CC
= 3.3V
curve shows that increasing the capacitance from 50pF to
150pF results in a t
PHL
increase from 55ns to 75ns. Larger
output capacitances translate to longer delays (up to
150ns). Users must quantify the difference in propagation
times for a rising edge vs a falling edge in their systems
and adjust setup and hold times accordingly.
Rise-Time Accelerators
Once connection has been established, rise-time accelera-
tor circuits on all four SDA and SCL pins are activated.
These allow the user to choose weaker DC pull-up currents
on the bus, reducing power consumption while still meet-
ing system rise-time requirements. During positive bus
transitions, the LTC4300 switches in 2mA of current to
quickly slew the SDA and SCL lines once their DC voltages
exceed 0.6V. Using a general rule of 20pF of capacitance
for every device on the bus (10pF for the device and 10pF
for interconnect), choose a pull-up current so that the bus
will rise on its own at a rate of at least 1.25V/µs to
guarantee activation of the accelerators.
For example, assume an SMBus system with V
CC
= 3V, a
10k pull-up resistor and equivalent bus capacitance of
200pF. The rise-time of an SMBus system is calculated
from (V
IL(MAX)
– 0.15V) to (V
IH(MIN)
+ 0.15V), or 0.65V to
2.25V. It takes an RC circuit 0.92 time constants to
traverse this voltage for a 3V supply; in this case, 0.92 •
(10k • 200pF) = 1.85µs. Thus, the system exceeds the
maximum allowed rise-time of 1µs by 85%. However,
using the rise-time accelerators, which are activated at a
DC threshold of below 0.65V, the worst-case rise-time is:
(2.25V – 0.65V) • 200pF/1mA = 320ns, which meets the
1µs rise-time requirement.
READY Digital Output (LTC4300-1)
This pin provides a digital flag which is low when either
ENABLE is low or the start-up sequence described earlier
in this section has not been completed. READY goes high
when ENABLE is high and start-up is complete. The pin is
driven by an open drain pull-down capable of sinking 3mA
while holding 0.4V on the pin. Connect a resistor of 10k to
V
CC
to provide the pull-up. This feature is available for the
LTC4300-1 only.
ENABLE Low Current Disable (LTC4300-1)
Grounding the ENABLE pin disconnects the backplane
side from the card side, disables the rise-time accelera-
tors, drives READY low, disables the bus precharge cir-
cuitry and puts the part in a near-zero current state. When
the pin voltage is driven all the way to V
CC
, the part waits
for data transactions on both the backplane and card sides
to be complete (as described in the Start-Up section)
before reconnecting the two sides. This feature is available
for the LTC4300-1 only.
ACC Boost Current Enable (LTC4300-2)
Users having lightly loaded systems may wish to disable
the rise-time accelerators. Driving this pin to ground turns
off the rise-time accelerators on all four SDA and SCL pins.
Driving this pin to the V
CC2
voltage enables normal opera-
tion of the rise-time accelerators, as described in the Rise-
Time Accelerators section above. This feature is available
for the LTC4300-2 only.
OPERATIO
U
Figure 1. Input–Output Connection tPLH Figure 2. Input–Output Connection tPHL
OUTPUT
SIDE
50pF
INPUT
SIDE
150pF
INPUT
SIDE
150pF
OUTPUT
SIDE
50pF
LTC4300-1/LTC4300-2
10
sn430012 430012fs
Resistor Pull-Up Value Selection
The system pull-up resistors must be strong enough to
provide a positive slew rate of 1.25V/µs on the SDA and
SCL pins, in order to activate the boost pull-up currents
during rising edges. Choose maximum resistor value R
using the formula:
R ≤ (V
CC(MIN)
– 0.6) (800,000) / C
where R is the pull-up resistor value in ohms, V
CC(MIN)
is
the minimum V
CC
voltage and C is the equivalent bus
capacitance in picofarads (pF).
In addition, regardless of the bus capacitance, always
choose R ≤ 16k for V
CC
= 5.5V maximum, R ≤ 24k for
V
CC
␣ =␣ 3.6V maximum. The start-up circuitry requires logic
high voltages on SDAOUT and SCLOUT to connect the
backplane to the card, and these pull-up values are needed
to overcome the precharge voltage. See the curves in
Figures 3 and 4 for guidance in resistor pull-up selection.
Minimum SDA and SCL Capacitance Requirements
The LTC4300 I/O connection circuitry requires a minimum
capacitance loading on the SDA and SCL pins in order to
function properly. The value of this capacitance is a
function of V
CC
and the bus pull-up resistance. Estimate
the bus capacitance on both the backplane and the card
data and clock busses, and refer to Figures 3 and 4 to
choose appropriate pull-up resistor values. Note from the
APPLICATIO S I FOR ATIO
WUUU
figures that 5V systems must have at least 47pF capaci-
tance on their busses and 3.3V systems must have at least
22pF capacitance for proper operation of the LTC4300. For
applications with less capacitance, add a capacitor to
ground to ensure these minimum capacitance conditions.
Hot Swapping and Capacitance Buffering Application
Figures 5 through 8 illustrate the usage of the LTC4300 in
applications that take advantage of both its hot swapping
and capacitance buffering features. In all of these applica-
tions, note that if the I/O cards were plugged directly into
the backplane, all of the backplane and card capacitances
would add directly together, making rise- and fall-time
requirements difficult to meet. Placing a LTC4300 on the
edge of each card, however, isolates the card capacitance
from the backplane. For a given I/O card, the LTC4300 drives
the capacitance of everything on the card and the backplane
must drive only the capacitance of the LTC4300, which is
less than 10pF.
Figure 5 shows the LTC4300-1 in a CompactPCI
TM
con-
figuration. Connect VCC to the output of one of the
CompactPCI power supply hot swap circuits and connect
ENABLE to the short “board enable” pin. VCC is monitored
by a filtered UVLO circuit. With the VCC voltage powering
up after all other pins have established connection, the
UVLO circuit ensures that the backplane and card data and
clock busses are not connected until the transients asso-
Figure 3. Bus Requirements for 3.3V Systems Figure 4. Bus Requirements for 5V Systems
CBUS (pF)
0
RPULLUP (kΩ)
4300-1/2 F03
30
25
20
15
10
5
0100 200 300 400
RMAX = 24k
RISE-TIME > 300ns
RECOMMENDED
PULL-UP
CBUS (pF)
0
RPULLUP (kΩ)
4300-1/2 F04
0
0
5
10
15
20
100 200 300 400
RISE-TIME
> 300ns
RECOMMENDED
PULL-UP
RMAX = 16k
CompactPCI is a trademark of the PCI Industrial Computer Manufacturers Group.
LTC4300-1/LTC4300-2
11
sn430012 430012fs
APPLICATIO S I FOR ATIO
WUUU
ciated with hot swapping have settled. Owing to their small
capacitance, the SDAIN and SCLIN pins cause minimal dis-
turbance on the backplane busses when they make con-
tact with the connector.
Figure 6 shows the LTC4300-2 in a CompactPCI configu-
ration. The LTC4300-2 receives its V
CC
voltage from one
of the long “early power” pins. Because this power is not
switched, add a 5Ω to 10Ω resistor between the V
CC
pins
of the connector and the LTC4300-2, as shown in the
figure. In addition, make sure that the V
CC
bypassing on
the backplane is large compared to the 0.01µF bypass
capacitor on the card. Establishing early power V
CC
en-
sures that the 1V precharge voltage is present at the
SDAIN and SCLIN pins before they make contact. Connect
V
CC2
to the output of one of the CompactPCI power supply
hot swap circuits. V
CC2
is monitored by a filtered UVLO
circuit. With the V
CC2
voltage powering up after all other
pins have established connection, the UVLO circuit en-
sures that the backplane and card data and clock busses
are not connected until the transients associated with hot
swapping have settled.
Figure 7 shows the LTC4300-1 in a PCI application, where
all of the pins have the same length. In this case, connect
an RC series circuit on the I/O card between V
CC
and
ENABLE. An RC product of 10ms provides a filter to
prevent the LTC4300-1 from becoming activated until the
transients associated with hot swapping have settled.
Figure 8 shows the LTC4300-2 in an application where the
user has a custom connector with pins of three different
lengths available. Making V
CC2
the shortest pin ensures
that all other pins are firmly connected before V
CC2
receives any voltage. A filtered UVLO circuit on V
CC2
ensures that the V
CC2
pin is firmly connected before the
LTC4300-2 connects the backplane to the card.
Repeater/Bus Extender Application
Users who wish to connect two 2-wire systems separated
by a distance can do so by connecting two LTC4300-1s
back-to-back, as shown in Figure 9. The I
2
C specification
allows for 400pF maximum bus capacitance, severely
limiting the length of the bus. The SMBus specification
places no restriction on bus capacitance, but the limited
impedances of devices connected to the bus require
systems to remain small if rise- and fall-time specifica-
tions are to be met. The strong pull-up and pull-down
impedances of the LTC4300-1 are capable of meeting rise-
and fall-time specifications for one nanofarad of capaci-
tance, thus allowing much more interconnect distance. In
this situation, the differential ground voltage between the
two systems may limit the allowed distance, because a
valid logic low voltage with respect to the ground at one
end of the system may violate the allowed V
OL
specifica-
tion with respect to the ground at the other end. In
addition, the connection circuitry offset voltages of the
back-to-back LTC4300-1s add together, directly contrib-
uting to the same problem.
Systems with Disparate Supply Voltages (LTC4300-1)
In large 2-wire systems, the V
CC
voltages seen by devices
at various points in the system can differ by a few hundred
millivolts or more. This situation is well modelled by a
series resistor in the V
CC
line, as shown in Figure 10. For
proper operation of the LTC4300-1, make sure that
V
CC(BUS)
≥ V
CC(LTC4300)
– 0.5V.
5V to 3.3V Level Translator and Power Supply
Redundancy (LTC4300-2)
Systems requiring different supply voltages for the
backplane side and the card side can use the LTC4300-2,
as shown in Figure 11. The pull-up resistors on the card
side connect from SDAOUT to SCLOUT to V
CC2
, and those
on the backplane side connect from SDAIN and SCLIN to
V
CC
. The LTC4300-2 functions for voltages ranging from
2.7V to 5.5V on both V
CC
and V
CC2
. There is no constraint
on the voltage magnitudes of V
CC
and V
CC2
with respect to
each other.
This application also provides power supply redundancy.
If either the V
CC
or V
CC2
voltage falls below its UVLO
threshold, the LTC4300-2 disconnects the backplane from
the card, so that the side that is still powered can continue
to function.
LTC4300-1/LTC4300-2
12
sn430012 430012fs
Figure 5. Hot Swapping Multiple I/O Cards into a Backplane Using the LTC4300-1 in a CompactPCI System
STAGGERED CONNECTOR
R13
10k
R12
10k R14
10k
I/O PERIPHERAL CARD N
ENABLE
SDAIN
SCLIN
LTC4300-1
U3
V
CC
GND
CARDN_SCL
CARDN_SDA
SDAOUT
SCLOUT
READY
ENABLE
SDAIN
SCLIN
V
CC
GND
SDAOUT
SCLOUT
READY
ENABLE
SDAIN
SCLIN
V
CC
GND
SDAOUT
SCLOUT
READY
4300-1/2 F05
• • •
R9
10k
R8
10k R10
10k
I/O PERIPHERAL CARD 2
LTC4300-1
U2 CARD2_SCL
CARD2_SDA
STAGGERED CONNECTORSTAGGERED CONNECTOR
R5
10k
R4
10k R6
10k
I/O PERIPHERAL CARD 1
LTC4300-1
U1 CARD_SCL
CARD_SDA
R1
10k
V
CC
R2
10k
BACKPLANE
BACKPLANE
CONNECTOR
SDA
BD_SEL
SCL
NOTE: APPLICATION ASSUMES BUS CAPACITANCES WITHIN “PROPER OPERATION” REGION OF FIGURES 3 AND 4
C1
0.01µF
C3
0.01µF
C5
0.01µF
POWER SUPPLY
HOT SWAP
POWER SUPPLY
HOT SWAP
POWER SUPPLY
HOT SWAP
APPLICATIO S I FOR ATIO
WUUU
LTC4300-1/LTC4300-2
13
sn430012 430012fs
APPLICATIO S I FOR ATIO
WUUU
Figure 6. Hot Swapping Multiple I/O Cards into a Backplane Using the LTC4300-2 in a CompactPCI System
C1
0.01µF
C3
0.01µF
C5
0.01µFR13
10k
R12
10k R14
10k
I/O PERIPHERAL CARD N
V
CC
SDAIN
SCLIN
LTC4300-2
U3
V
CC2
GND
CARDN_SCL
CARDN_SDA
SDAOUT
SCLOUT
ACC
V
CC
SDAIN
SCLIN
V
CC2
GND
SDAOUT
SCLOUT
ACC
V
CC
SDAIN
SCLIN
V
CC2
GND
SDAOUT
SCLOUT
ACC
4300-1/2 F06
• • •
R9
10k
R8
10k R10
10k
I/O PERIPHERAL CARD 2
LTC4300-2
U2 CARD2_SCL
CARD2_SDA
R5
10k
R4
10k R6
10k
I/O PERIPHERAL CARD 1
LTC4300-2
U1
C2 0.01µF
5.1Ω
CARD_SCL
CARD_SDA
V
CC2
BACKPLANE
BACKPLANE
CONNECTOR
SDA
SCL
NOTE: APPLICATION ASSUMES BUS CAPACITANCES WITHIN “PROPER OPERATION” REGION OF FIGURES 3 AND 4
V
CC
BD_SEL
STAGGERED CONNECTORSTAGGERED CONNECTORSTAGGERED CONNECTOR
POWER SUPPLY
HOT SWAP
C4 0.01µF
5.1Ω
POWER SUPPLY
HOT SWAP
C6 0.01µF
5.1Ω
POWER SUPPLY
HOT SWAP
R1
10k R2
10k
LTC4300-1/LTC4300-2
14
sn430012 430012fs
APPLICATIO S I FOR ATIO
WUUU
Figure 7. Hot Swapping Multiple I/O Cards into a Backplane Using the LTC4300-1 in a PCI System
R3
100k
ENABLE
SDAIN
SCLIN
V
CC
GND
SDAOUT
SCLOUT
READY
ENABLE
SDAIN
SCLIN
V
CC
GND
SDAOUT
SCLOUT
READY
4300-1/2 F07
R9
10k
R8
10k R10
10k
I/O PERIPHERAL CARD 2
LTC4300-1
U2 CARD2_SCL
CARD2_SDA
R5
10k
R4
10k
I/O PERIPHERAL CARD 1
LTC4300-1
U1
C2 0.1µF
R7
100k
C4 0.1µF
CARD_SCL
CARD_SDA
R1
10k
V
CC
R2
10k
BACKPLANE
BACKPLANE
CONNECTOR
SDA
SCL
NOTE: APPLICATION ASSUMES BUS CAPACITANCES WITHIN “PROPER OPERATION” REGION OF FIGURES 3 AND 4
C1
0.01µF
C3
0.01µF
R6
10k
Figure 8. Hot Swapping Multiple I/O Cards into a Backplane Using the LTC4300-2 with a Custom Connector
STAGGERED CONNECTOR
V
CC
SDAIN
SCLIN
V
CC2
GND
SDAOUT
SCLOUT
ACC
V
CC
SDAIN
SCLIN
V
CC2
GND
SDAOUT
SCLOUT
ACC
4300-1/2 F08
R9
10k
R8
10k
I/O PERIPHERAL CARD 2
LTC4300-2
U2 CARD2_SCL
CARD2_SDA
STAGGERED CONNECTOR
R5
10k
R4
10k
I/O PERIPHERAL CARD 1
LTC4300-2
U1
C2 0.01µF
C4 0.01µF
CARD_SCL
CARD_SDA
R1
10k R2
10k
V
CC2
BACKPLANE
BACKPLANE
CONNECTOR
SDA
SCL
NOTE: APPLICATION ASSUMES BUS CAPACITANCES WITHIN “PROPER OPERATION” REGION OF FIGURES 3 AND 4
V
CC
C1
0.01µF
C3
0.01µFR10
10k
R6
10k
LTC4300-1/LTC4300-2
15
sn430012 430012fs
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
APPLICATIO S I FOR ATIO
WUUU
R1
10k
R3
5.1k
R5
10k R2
5.1k
V
CC
= 5V
R4
10k R7
10k R8
10k
2-WIRE SYSTEM 1
ENABLE
SDAIN
SCLIN
LTC4300-1
GND
V
CC
C1
0.01µF
SDAOUT
SCLOUT
READY
SCL1
TO OTHER
SYSTEM 1
DEVICES
SDA1
C2
0.01µF
R6
10k
2-WIRE SYSTEM 2
LTC4300-1
ENABLE
SDAIN
SCLIN
4300-1/2 F07
SDAOUT
SCLOUT
READY
LONG
DISTANCE
BUS
V
CC
SCL1
SDA1
TO OTHER
SYSTEM 2
DEVICES
GND
V
CC
NOTE: APPLICATION ASSUMES BUS CAPACITANCES WITHIN “PROPER OPERATION” REGION OF FIGURE 4
Figure 9. Repeater/Bus Extender Application
PACKAGE DESCRIPTION
U
MS8 Package
8-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1660)
MSOP (MS8) 1001
0.53 ± 0.015
(.021 ± .006)
SEATING
PLANE
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
0.18
(.077)
0.254
(.010)
1.10
(.043)
MAX
0.22 – 0.38
(.009 – .015) 0.13 ± 0.05
(.005 ± .002)
0.86
(.034)
REF
0.65
(.0256)
BCS
0° – 6° TYP
DETAIL “A”
DETAIL “A”
GAUGE PLANE
12
34
4.88 ± 0.1
(.192 ± .004)
8765
3.00 ± 0.102
(.118 ± .004)
(NOTE 3)
3.00 ± 0.102
(.118 ± .004)
NOTE 4
0.52
(.206)
REF
5.23
(.206)
MIN
3.2 – 3.45
(.126 – .136)
0.889 ± 0.127
(.035 ± .005)
RECOMMENDED SOLDER PAD LAYOUT
0.42 ± 0.04
(.0165 ± .0015)
TYP
0.65
(.0256)
BSC
LTC4300-1/LTC4300-2
16
sn430012 430012fs
LINEAR TECHNOLOGY CORPORATION 2001
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
●
FAX: (408) 434-0507
●
www.linear.com
LT/TP 0602 2K • PRINTED IN USA
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ThinSOT is a trademark of Linear Technology Corporation.
Figure 10. System with Disparate VCC Voltages
R1
10k
V
CC
R2
10k
R
DROP
V
CC_LOW
SDA
SCL
4300-1/2 F08
R4
10k R5
10k
R3
10k
SDAIN
ENABLE
SCLIN
LTC4300-1
U1
V
CC
GND
SCL2
SDA2
SDAOUT
SCLOUT
READY
C2
0.01µF
NOTE: APPLICATION ASSUMES BUS CAPACITANCES WITHIN “PROPER OPERATION” REGION OF FIGURES 3 AND 4
Figure 11. 5V to 3.3V Level Translator
V
CC2
GND
SDAOUT
SCLOUT
SDAIN
SCLIN
ACC
V
CC
R2
10k
R3
10k
CARD_V
CC
, 3V
CARD_SCL
CARD_SDA
C2
0.01µFC1
0.01µF
R1
10k
V
CC
5V R4
10k
LTC4300-2
U1
SCL
SCL
4300-1/2 F09
NOTE: APPLICATION ASSUMES BUS CAPACITANCES WITHIN “PROPER OPERATION” REGION OF FIGURES 3 AND 4
TYPICAL APPLICATIO S
U
