Features
• Input voltage from 0.8 to 5.5 V
• Bias supply pin
• Ultra low-dropout voltage (120 mV max. at 500 mA load)
• Low ground current (27 μA typ. at no-load)
• Output voltage tolerance: ± 1.5% overtemperature, 0.5% at 25 °C
• 500 mA guaranteed output current
• 50 mV output voltage step available from 0.8 V to 3.6 V
• Logic-controlled electronic shutdown
• Internal current limit with foldback
• Thermal shutdown
• Output active discharge function
• Available in DFN4 1.2 x 1.2 mm package
• Temperature range: -40 °C to 85 °C
Applications
• Mobile phones
• Tablets
• Battery-powered systems
• Camera supply
Description
The LD56050 is a high accuracy voltage regulator, which provides 0.5 A of current. It
is equipped with an NMOS pass transistor, whose gate is biased by a dedicated pin,
thus allowing an ultra low-drop performance even at very low input voltages.
It is available in DFN4 1.2 x 1.2 package, allowing the maximum space saving.
The device is stabilized with a small ceramic capacitor on the output. The ultra low-
drop, low quiescent current and short circuit current foldback make the LD56050
suitable for low power battery-operated applications.
An enable logic control function puts the LD56050 in shutdown mode allowing a total
current consumption lower than 0.1 µA. Thermal protection is also included.
Maturity status link
LD56050
500 mA ultra-low dropout linear regulator with bias supply
LD56050
Datasheet
DS12441 - Rev 1 - February 2018
For further information contact your local STMicroelectronics sales office. www.st.com/
1 Diagram
Figure 2. Block diagram
+
_
VREF
Thermal
Protection
+
_||
VIN
VOU T
GND
EN
VBIAS
EN *
Note: (*) Output discharge MOSFET.
LD56050
Diagram
DS12441 - Rev 1 page 2/21
2 Pin configuration
Figure 3. Pin connection (top view)
1
5
43
2
Table 1. Pin description
Pin n° DFN8 Symbol Function
1 VOUT Output voltage
2 VBIAS Bias supply input
3 EN Enable pin logic input: low = shutdown, high = active.
Not internally pulled-up. Don't leave floating.
4 VIN Input voltage (power element)
5 GND Common ground
LD56050
Pin configuration
DS12441 - Rev 1 page 3/21
3 Typical application
Figure 4. Typical application circuit
VBIAS
EN
VOUT
GND
CIN COUT
LD56050
VOUT
VIN
CBIAS
VBIAS
VIN
VEN
Table 2. Typical bill of material
Symbol Value Description Note
CIN 1 µF Output voltage Ceramic type
CBIAS 100 nF Bias supply input
COUT 2.2 µF Input voltage (power element)
LD56050
Typical application
DS12441 - Rev 1 page 4/21
4 Maximum ratings
Table 3. Absolute maximum ratings
Symbol Parameter Value Unit
VIN Input voltage - 0.3 to 7 V
VOUT Output voltage - 0.3 to VIN + 0.3 V
VEN Enable input voltage - 0.3 to 7 V
IOUT Output current Internally limited mA
PDPower dissipation Internally limited mW
TSTG Storage temperature range - 40 to 150 °C
TOP Operating junction temperature range - 40 to 85 °C
Note: Absolute maximum ratings are those values beyond which damage to the device may occur. Functional
operation under these conditions is not implied. All values are referred to GND.
Table 4. Thermal data
Symbol Parameter Value Unit
RthJA Thermal resistance junction-ambient 170 °C/W
Table 5. ESD performance
Symbol Parameter Test conditions Value Unit
ESD ESD protection voltage HBM 2 kV
CDM 500 V
LD56050
Maximum ratings
DS12441 - Rev 1 page 5/21
5 Electrical characteristics
VBIAS = 2.7 V or VOUT + 1.6 V (whichever is greater); VIN = VOUT(NOM) + 0.3 V; IOUT = 1 mA; CIN = 1 µF, COUT =
2.2 µF; VEN = 1 V; typical values are at TJ = 25 °C; min./max. values are at -40 °C ≤ TJ ≤ 85 °C, unless otherwise
specified.
Table 6. Electrical characteristics
Symbol Parameter Test conditions Min. Typ. Max. Unit
VIN Operating input voltage VOUT +
VDROP
5.5 V
VBIAS Operating bias voltage VOUT ≤ 1 V 2.4 5.5 V
VOUT > 1 V VOUT +
1.4
5.5 V
VUVLO BIAS undervoltage
lockout
VBIAS rising 1.6 V
Hysteresis 0.2
VOUT Output voltage accuracy ±0.5 %
VOUT(NOM) + 0.3 V ≤ VIN ≤ VOUT(NOM) + 1.0 V;
2.7 V or VOUT(NOM) + 1.6 V (whichever is greater) ≤
VBIAS ≤ 5.5 V;
IOUT = 1 mA to 0.5 A; -40°C ≤ TJ ≤ 85°C
-1.5 +1.5 %
∆VOUT-IN VIN static regulation(1) VOUT(NOM) + 0.3 V ≤ VIN ≤ 5.0 V, IOUT = 1 mA 0.02 0.1 %/V
∆VOUT-BIAS VBIAS line regulation(1) 2.7 V or VOUT(NOM) + 1.6 V (whichever is greater) ≤
VBIAS ≤ 5.5 V; IOUT = 1 mA
0.01 0.1 %/V
∆VOUT Static load regulation IOUT = 1 mA to 500 mA 1.5 mV
VDROP Dropout voltage IOUT = 0.15 A; VOUT = 97% of VOUT(NOM) 13 25 mV
IOUT = 0.5 A; VOUT = 97% of VOUT(NOM) 80 120
VDROP-BIAS Dropout voltage VBIAS = VIN; IOUT = 0.5 A 0.9 1.5 V
eNOutput noise voltage VOUT(NOM) = 1.05 V; VIN = 1.5 V 10 Hz to 100 kHz,
IOUT = 1 mA
38 µVRMS
SVRIN VIN supply voltage
rejection
VIN = VOUT(NOM)+ 0.5 V +/- VRIPPLE
VRIPPLE = 0.2 V, freq=1 kHz, IOUT = 150 mA;
VBIAS = 2.7 V or VOUT + 1.6 V (whichever is
greater)
75 dB
SVRBIAS VBIAS supply voltage
rejection
VBIAS = 2.9 V or VOUT + 1.8 V (whichever is
greater) +/- VRIPPLE
VRIPPLE = 0.2 V freq = 1 kHz IOUT = 150 mA;
VIN = VOUT(NOM)+ 0.5 V
76 dB
IBIAS VBIAS operating current IOUT = 0 mA; VBIAS = 2.7 V 27 40 µA
IStandby-BIAS VBIAS standby current VBIAS input current in OFF MODE: VEN = GND 0.03 1 µA
IStandby-IN VIN standby current VIN input current in OFF MODE: VEN = GND 0.03 1 µA
ILIM Output current limit VOUT= 0.9 x VOUT(NOM) 550 700 1000 mA
ISC Short-circuit current VOUT = 0 (foldback protection) 365 450 mA
LD56050
Electrical characteristics
DS12441 - Rev 1 page 6/21
Symbol Parameter Test conditions Min. Typ. Max. Unit
RON Output voltage discharge
MOSFET
110 Ω
VEN Enable input logic low 0.4 V
Enable input logic high 0.9
IEN Enable pin input current VEN = 5.5 V 200 nA
TON (2) Turn on time VOUT(NOM) = 1.0 V 110 µs
TSHDN Thermal shutdown 160 °C
Hysteresis 20
COUT Output capacitor 1 2.2 22 µF
1. Not applicable for VOUT(NOM) ≥ 5.0 V.
2. Turn-on time is time measured between the enable input just exceeding VEN high value and the output voltage just reaching
98% of its nominal value.
Note: Values over the temperature range are guaranteed by design and correlation and not tested in production.
LD56050
Electrical characteristics
DS12441 - Rev 1 page 7/21
6 Application information
6.1 VBIAS pin voltage requirements
The bias input is the supply of the internal driving and control circuitry. In order to ensure proper biasing of the N-
channel power element, the bias pin must have a minimum voltage of 2.4 V and 1.6 V (typically) higher than the
output. If VIN supply voltage meets these requirements then the bias pin can be tied to VIN.
6.2 Output discharge function
The LD56050 integrates a MOSFET connected between VOUT and GND. This transistor is activated when the EN
pin goes to low logic level and has the function to quickly discharge the output capacitor when the device is
disabled by the user.
6.3 Short circuit and current limitation
The LD56050 is protected against short-circuit on the output. The load current is limited to the maximum value of
ILIM when VOUT is equal to 90% of its nominal value. If the VOUT decreases even more due to a lower output load
resistance then the foldback circuit starts operating limiting the current to ISC when VOUT = 0.
6.4 Thermal protection
Thermal protection acts when the junction temperature reaches 160 °C typical. At this point the output of the IC
shuts down. As soon as the junction temperature falls below the thermal hysteresis value the device starts
working again.
In order to calculate the maximum power that the device can dissipate, keeping the junction temperature below
the maximum operating value, the following formula is used:
PDMAX = (85 - TAMB) / RthJA
6.5 Input and output capacitors
The LD56050 requires external capacitors to assure the regulator control loop stability.
Any good quality ceramic capacitor can be used but, the X5R and the X7R are suggested since they guarantee a
very stable combination of capacitance and ESR across the temperature range.
Locating the input/output capacitors as close as possible to the relative pins is recommended. The LD56050
requires a VIN capacitor with a minimum value of 1 μF and a VBIAS capacitor of 100 nF minimum. These
capacitors must be located as close as possible to the input pins of the device and returned to a clean analog
ground.
The control loop is designed to be stable with any good quality output ceramic capacitor (such as X5R/X7R types)
with a minimum value of 1.0 μF and equivalent series resistance in the [3 – 300 mΩ] range. It is important to
highlight that the output capacitor must maintain its capacitance and ESR in the stable region over the full
operating temperature, load and input voltage ranges, to assure stability. Therefore, capacitance and ESR
variations must be taken into account in the design phase to ensure the device works in the expected stability
region.
LD56050
Application information
DS12441 - Rev 1 page 8/21
7 Typical characteristics
(VOUT = 1.05 V ; CIN = 1 µF, COUT = 2.2 µF; VEN = 1 V; unless otherwise specified.)
Figure 5. VDROP vs. temperature (VBIAS = 2.7 V)
0
10
20
30
40
50
60
70
80
90
100
110
120
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90
Dropout Voltage [mV]
Junction Temperature [°C]
Io=150 mA Io=300 mA Io=500 mA
Figure 6. VDROP-BIAS vs. temperature (IOUT = 500 mA;
VBIAS = VIN)
700
750
800
850
900
950
1000
1050
1100
1150
1200
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90
Dropout Voltage [mV]
Junction Temperature [°C]
Figure 7. VDROP vs. IOUT (VBIAS = 2.7 V)
0
10
20
30
40
50
60
70
80
90
100
0 50 100 150 200 250 300 350 400 450 500
Dropout Voltage [mV]
IOUT [mA]
Figure 8. VDROP vs. IOUT (VBIAS = VIN)
0
100
200
300
400
500
600
700
800
900
1000
0 50 100 150 200 250 300 350 400 450 500
Dropout Voltage [mV]
IOUT [mA]
Figure 9. ISC vs. temperature (VIN = 1.4 V; VBIAS = 2.7 V)
600
620
640
660
680
700
720
740
760
780
800
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90
Short Circuit Current [mA]
Junction Temperature [°C]
Figure 10. ILIM vs. temperature (VIN = 1.4 V; VBIAS = 2.7 V)
LD56050
Typical characteristics
DS12441 - Rev 1 page 9/21
Figure 11. IBIAS vs. temperature (IOUT = 0 mA;
VBIAS = 2.7 V)
0
5
10
15
20
25
30
35
40
45
50
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90
IBIAS [µA]
Junction Temperature [°C]
Figure 12. IBIAS vs. VIN (VBIAS = 2.7 V)
25
25.5
26
26.5
27
27.5
28
28.5
29
29.5
30
1 1.5 2 2.5 3 3.5 4 4.5 5 5.5
IBIAS Current [mA]
VIN [V]
Figure 13. SVRIN vs. frequency (VIN = 1.5 V; VBIAS = 2.7 V;
VOUT = 1.05 V)
0
10
20
30
40
50
60
70
80
90
100
110
120
10 100 1,000 10,000 100,000 1,000,000 10,000,000
SVR IN [dB]
Frequency [Hz]
Io=10 mA Io=50 mA Io=150 mA
Figure 14. SVRBIAS vs. frequency (VIN = 1.5 V;
VBIAS = 2.9 V; VOUT = 1.05 V)
0
10
20
30
40
50
60
70
80
90
100
110
120
10 100 1,000 10,000 100,000 1,000,000 10,000,000
SVR BIAS [dB]
Frequency [Hz]
Io=10 mA Io=50 mA Io=150 mA
Figure 15. Noise vs. frequency (VIN = 1.5 V; VBIAS = 2.7 V; VOUT = 1.05 V)
0.01
0.10
1.00
10.00
10 100 1,000 10,000 100,000
Output Noise Density [µV/√(Hz)]
Frequency [Hz]
Io=1 mA Io=10 mA
LD56050
Typical characteristics
DS12441 - Rev 1 page 10/21
Figure 16. Turn-on time (IOUT = 1 mA; VBIAS = 2.7 V) Figure 17. Turn-on time at full load (IOUT = 500 mA;
VBIAS = 2.7 V)
Figure 18. Line transient (VBIAS = 2.7 V, VIN from 1.35 V to
2.35 V; tR = 5 µs)
Figure 19. Load transient (VBIAS = 2.7 V, VIN = 1.35 V; IOUT
1 to 500 mA)
LD56050
Typical characteristics
DS12441 - Rev 1 page 11/21
8 Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK®
packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions
and product status are available at: www.st.com. ECOPACK® is an ST trademark.
LD56050
Package information
DS12441 - Rev 1 page 12/21
8.1 DFN4 1.2 x 1.2 package information
Figure 20. DFN4 1.2 x 1.2 package outline
LD56050
DFN4 1.2 x 1.2 package information
DS12441 - Rev 1 page 13/21
Table 7. DFN4 1.2 x 1.2 mechanical data
Dim. mm.
Min. Typ. Max.
A 0.41 0.45 0.50
A1 0.00 0.02 0.05
A3 0.127 Ref.
b 0.25 0.30 0.35
D 1.20 BSC
E 1.20 BSC
e 0.80 BSC
D2 0.58 0.63 0.68
E2 0.58 0.63 0.68
K 0.20 -- --
L 0.25 0.30 0.35
N 4
aaa 0.05
bbb 0.10
ccc 0.10
ddd 0.05
eee 0.08
ND 2
Figure 21. DFN4 1.2 x 1.2 recommended footprint
Note: All dimensions are in millimeters.
LD56050
DFN4 1.2 x 1.2 package information
DS12441 - Rev 1 page 14/21
Figure 22. DFN4 1.2 x 1.2 tape and reel
3
°
+/- 0.05
Measured from centreline of sprocket hole
to centreline of pocket.
Cumulative tolerance of 10 sprocket
holes is ± 0.20 .
Measured from centreline of sprocket
hole to centreline of pocket.
(I)
(II)
(III)
(IV) Other material available.
ALL DIMENSIONS IN MILLIMETRES UNLESS OTHERWISE STATED.
W
F
P1
+/- 0.05
+/- 0.10
+/- 0.10
3.50
4.00
8.00
Ao 1.40 +/- 0.05
Bo 1.40 +/- 0.05
Ko 0.64
W
0.05
R0.10
F (III) 1.75
E1
0.1
1
.
5
0
+
0
.
1
/ -
0
.
0
0.1
D
0
4.00
P1
MAX
P2 (I)
2.00
P0 (II)
Ao
D
1
0
.
8
0
m
i
n
Y
Y
SECTION Y-Y
SCALE 8 : 1
Bo
0.05
T
0.25
Ko
Note: Pin 1 orientation: bottom-left.
LD56050
DFN4 1.2 x 1.2 package information
DS12441 - Rev 1 page 15/21
9 Ordering information
Table 8. Order code
Order code Discharge function Output voltage (V) Marking
LD56050DPU100R Yes 1.00 UD
LD56050DPU105R Yes 1.05 UA
LD56050DPU110R Yes 1.10 UB
LD56050DPU115R Yes 1.15 UE
LD56050DPU120R Yes 1.20 UC
LD56050DPU150R Yes 1.50 UF
LD56050
Ordering information
DS12441 - Rev 1 page 16/21
Revision history
Table 9. Document revision history
Date Revision Changes
02-Feb-2018 1 Initial release.
LD56050
DS12441 - Rev 1 page 17/21
Contents
1Diagram ...........................................................................2
2Pin configuration ..................................................................3
3Typical application.................................................................4
4Maximum ratings ..................................................................5
5Electrical characteristics...........................................................6
6Application information ............................................................8
6.1 VBIAS pin voltage requirements ..................................................8
6.2 Output discharge function .......................................................8
6.3 Short circuit and current limitation ................................................8
6.4 Thermal protection .............................................................8
6.5 Input and output capacitors......................................................8
7Typical characteristics .............................................................9
8Package information ..............................................................12
8.1 DFN4 1.2 x 1.2 package information .............................................13
9Ordering information .............................................................16
Revision history .......................................................................17
LD56050
Contents
DS12441 - Rev 1 page 18/21
List of tables
Table 1. Pin description......................................................................3
Table 2. Typical bill of material .................................................................4
Table 3. Absolute maximum ratings .............................................................5
Table 4. Thermal data.......................................................................5
Table 5. ESD performance ...................................................................5
Table 6. Electrical characteristics ...............................................................6
Table 7. DFN4 1.2 x 1.2 mechanical data ........................................................14
Table 8. Order code ....................................................................... 16
Table 9. Document revision history .............................................................17
LD56050
List of tables
DS12441 - Rev 1 page 19/21
List of figures
Figure 2. Block diagram ....................................................................2
Figure 3. Pin connection (top view) .............................................................3
Figure 4. Typical application circuit .............................................................4
Figure 5. VDROP vs. temperature (VBIAS = 2.7 V) ....................................................9
Figure 6. VDROP-BIAS vs. temperature (IOUT = 500 mA; VBIAS = VIN)......................................9
Figure 7. VDROP vs. IOUT (VBIAS = 2.7 V) .........................................................9
Figure 8. VDROP vs. IOUT (VBIAS = VIN)..........................................................9
Figure 9. ISC vs. temperature (VIN = 1.4 V; VBIAS = 2.7 V) .............................................9
Figure 10. ILIM vs. temperature (VIN = 1.4 V; VBIAS = 2.7 V) .............................................9
Figure 11. IBIAS vs. temperature (IOUT = 0 mA; VBIAS = 2.7 V) .......................................... 10
Figure 12. IBIAS vs. VIN (VBIAS = 2.7 V) .......................................................... 10
Figure 13. SVRIN vs. frequency (VIN = 1.5 V; VBIAS = 2.7 V; VOUT = 1.05 V) ................................ 10
Figure 14. SVRBIAS vs. frequency (VIN = 1.5 V; VBIAS = 2.9 V; VOUT = 1.05 V) ............................... 10
Figure 15. Noise vs. frequency (VIN = 1.5 V; VBIAS = 2.7 V; VOUT = 1.05 V) ................................. 10
Figure 16. Turn-on time (IOUT = 1 mA; VBIAS = 2.7 V) ................................................ 11
Figure 17. Turn-on time at full load (IOUT = 500 mA; VBIAS = 2.7 V)....................................... 11
Figure 18. Line transient (VBIAS = 2.7 V, VIN from 1.35 V to 2.35 V; tR = 5 µs) ............................... 11
Figure 19. Load transient (VBIAS = 2.7 V, VIN = 1.35 V; IOUT 1 to 500 mA) .................................. 11
Figure 20. DFN4 1.2 x 1.2 package outline ....................................................... 13
Figure 21. DFN4 1.2 x 1.2 recommended footprint .................................................. 14
Figure 22. DFN4 1.2 x 1.2 tape and reel ......................................................... 15
LD56050
List of figures
DS12441 - Rev 1 page 20/21
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LD56050
DS12441 - Rev 1 page 21/21