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LP5904

LP5904 Ultra Low Noise, 200 mA Linear Regulator for RF/Analog Circuits -

Requires No Bypass Capacitor

Literature Number: SNVS637D

LP5904

September 14, 2011

Ultra Low Noise, 200 mA Linear Regulator for RF/Analog

Circuits - Requires No Bypass Capacitor

General Description

The LP5904 is a linear regulator capable of supplying 200 mA

output current. Designed to meet the requirements of RF/

Analog circuits, the LP5904 device provides low noise, high

PSRR, low quiescent current, and low line transient response

figures. Using new innovative design techniques the LP5904

offers class-leading device noise performance without a noise

bypass capacitor and the ability for remote output capacitor

placement. An internal pulldown resistor of 280Ω is wired from

the output to ground pins to facilitate discharging of the output

at device disable.

The device is designed to work with a 1.0 μF input and a

1.0 μF output ceramic capacitor. (No Bypass Capacitor is re-

quired.)

The device is available in a micro SMD package. For other

package options contact your local NSC sales office.

This device is available between 1.2V and 4.4V in 25 mV

steps. Please contact National Semiconductor Sales for spe-

cific voltage option needs.

Features

■Stable with 1.0 μF Ceramic Input and Output Capacitors

■No Noise Bypass Capacitor Required

■Remote Output Capacitor Placement

■Thermal-overload and short-circuit protection

■−40°C to +125°C junction temperature range for operation

Key Specifications

■Input voltage range 2.2V to 5.5V

■Output voltage range 1.2V to 4.4V

■Output current 200 mA

■Low output voltage noise @ 200 mA 6.5 μVRMS

■PSRR 75 dB at 1kHz

■Output voltage tolerance ± 2%

■Virtually zero IQ (disabled) <1 μA

■Very low IQ (enabled) 11 μA

■Startup time 55 μs

■Low dropout 95 mV typ.

Package

4-Bump micro SMD

(lead free)

0.815 mm x 0.815 mm x

0.600 mm

Applications

■Cellular phones

■PDA handsets

■Wireless LAN devices

Typical Application Circuit

30110401

LP5904 Ultra Low Noise, 200 mA Linear Regulator for RF/Analog Circuits - Requires No Bypass

Capacitor

Connection Diagrams

4-Bump Thin micro SMD Package

NS Package Number TMD04AAA

30110402

The actual physical placement of the package marking will vary from part to part.

Pin Descriptions

micro SMD Pin No. Symbol Name and Function

A1 VIN Input voltage supply. A 1.0 µF capacitor should be connected at this input.

A2 VOUT Output voltage. A 1.0 μF Low ESR capacitor should be connected to this pin.

Connect this output to the load circuit. An internal 280Ω discharge resistor prevents

a charge remaining on VOUT when disabled.

B1 VEN Enable input; disables the regulator when ≤ 0.4V. Enables the regulator when ≥

1.2V. An internal 1mΩ pulldown resistor connects this input to ground.

B2 GND Common ground.

Ordering Information

micro SMD Package (Lead Free)

Output Voltage (V) Supplied As

250 tape and reel 3000 tape and reel

1.8* LP5904TME-1.8/NOPB LP5904TMX-1.8/NOPB

2.5* LP5904TME-2.5/NOPB LP5904TMX-2.5/NOPB

2.6* LP5904TME-2.6/NOPB LP5904TMX-2.6/NOPB

2.8 LP5904TME-2.8/NOPB LP5904TMX-2.8/NOPB

2.85 LP5904TME-2.85/NOPB LP5904TMX-2.85/NOPB

3.0* LP5904TME-3.0/NOPB LP5904TMX-3.0/NOPB

3.1 LP5904TME-3.1/NOPB LP5904TMX-3.1/NOPB

3.2* LP5904TME-3.2/NOPB LP5904TMX-3.2/NOPB

*Not yet released — contact NSC sales office for sample availability.

**Contact your local NSC Sales Office for availability of other voltage options.

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LP5904

Absolute Maximum Ratings (Note 1, Note

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

VIN Pin: Input Voltage −0.3 to 6.0V

VOUT Pin: Output Voltage −0.3 to (VIN + 0.3V) to 6.0V

(max)

VEN Pin: Enable Input Voltage −0.3 to (VIN + 0.3V) to 6.0V

(max)

Continuous Power Dissipation

(Note 3) Internally Limited

Junction Temperature (TJMAX)150°C

Storage Temperature Range −65 to 150°C

Maximum Lead Temperature

(Soldering, 10 sec.) 260°C

ESD Rating (Note 4)

Human Body Model 2kV

Machine Model 200V

Operating Ratings (Note 1), (Note 2)

VIN: Input Voltage Range 2.2V to 5.5V

VEN: Enable Voltage Range 0 to (VIN + 0.3V) to

5.5V (max)

Recommended Load Current

(Note 5)

0 to 200 mA

Junction Temperature Range (TJ)−40°C to +125°C

Ambient Temperature Range (TA)

(Note 5)

−40°C to +85°C

Thermal Properties

Junction to Ambient Thermal Resistance θJA (Note 6)

JEDEC Board (micro SMD)

(Note 16)119.6°C/W

4L Cellphone Board (micro SMD) 186.5°C/W

Electrical Characteristics

Limits in standard typeface are for TA = 25ºC. Limits in boldface type apply over the full operating junction temperature range

(−40ºC ≤ TJ ≤ +125°C). Unless otherwise noted, specifications apply to the LP5904 Typical Application Circuit (pg. 1) with: VIN =

VOUT (NOM) + 1.0V, VEN = 1.2V, CIN = 1.0 μF, COUT = 1.0 μF, IOUT = 1.0 mA. (Note 2, Note 7)

Symbol Parameter Conditions Min Typ Max Units

VIN Input Voltage 2.2 5.5 V

ΔVOUT

Output Voltage Tolerance VIN = (VOUT(NOM) + 1.0V) to 5.5V,

IOUT = 1mA to 200 mA −2 2%

Line Regulation

VIN = (VOUT(NOM) + 1.0V) to 5.0V,

IOUT = 1 mA 0.06

VIN = (VOUT(NOM) + 1.0V) to 5.5V,

IOUT = 1 mA 0.16 %/V

Load Regulation IOUT = 1mA to 200 mA 0.002 %/mA

ILOAD

Load Current (Note 9) 0 200 mA

Maximum Output Current 200

IQQuiescent Current (Note 11)

VEN = 1.2V, IOUT = 0 mA 11 20

µA

VEN = 1.2V, IOUT = 200 mA 250 325

VEN = 0.3V (Disabled) 0.2 1.0

IGGround Current (Note 13)IOUT = 0 mA (VEN = 1.2V) 12.2 µA

VDO Dropout Voltage (Note 10)VOUT = 2.8V; IOUT = 100 mA 45 mV

VOUT = 2.8V; IOUT = 200 mA 95 150

ISC Short Circuit Current Limit (Note 12) 220 450 mA

PSRR Power Supply Rejection Ratio

(Note 15)

f = 100 Hz, IOUT = 200 mA 85

f = 1 kHz, IOUT = 200 mA 75

f = 10 kHz, IOUT = 200 mA 65

f = 100 kHz, IOUT = 200 mA 30

f = 2MHz, IOUT = 200 mA 30

eNOutput Noise Voltage (Note 15) BW = 10 Hz to 100 kHz IOUT = 1mA 10 µVRMS

IOUT = 200 mA 6.5

TSHUTDOWN Thermal Shutdown Temperature 160 °C

Hysteresis 15

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LP5904

Symbol Parameter Conditions Min Typ Max Units

VIL Low Input Threshold (VEN) VIN = 2.2V to 5.5V 0.4 V

VIH High Input Threshold (VEN) VIN = 2.2V to 5.5V 1.2 V

IEN

Input Current at VEN Pin

(Note 14)

VEN = 5.5V and VIN = 5.5V 5.5 μA

VEN = 0.0V and VIN = 5.5V 0.001

TRANSIENT CHARACTERISTICS

ΔVOUT

Line Transient

(Note 15)

VIN = (VOUT(NOM) + 1.0V) to (VOUT(NOM) + 1.6V)

in 30 μs, IOUT = 1mA −2

VIN = (VOUT(NOM) + 1.6V) to (VOUT(NOM) + 1.0V)

in 30 μs, IOUT = 1mA 2

Load Transient

(Note 15)

IOUT = 1mA to 200 mA in 10 μs−50 mV

IOUT = 200 mA to 1mA in 10 μs 50

Overshoot on Startup

(Note 15)Stated as a percentage of nominal VOUT 2%

Turn-on Time To 95% of VOUT(NOM) 55 300 µs

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under which operation

of the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions,

see the Electrical Characteristics tables.

Note 2: All voltages are with respect to the potential at the GND pin.

Note 3: Internal thermal shutdown circuitry protects the device from permanent damage.

Note 4: The Human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin. The machine model is a 200 pF capacitor discharged

directly into each pin. MIL-STD-883 3015.7

Note 5: In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be

derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP = 125°C), the maximum power

dissipation of the device in the application (PD-MAX), and the junction-to ambient thermal resistance of the part/package in the application (θJA), as given by the

following equation: TA-MAX = TJ-MAX-OP – (θJA × PD-MAX). See applications section.

Note 6: Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power dissipation exists,

special care must be paid to thermal dissipation issues in board design.

Note 7: Min and Max limits are guaranteed by design, test, or statistical analysis. Typical numbers are not guaranteed, but do represent the most likely norm.

Note 8: CIN, COUT: Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) used in setting electrical characteristics.

Note 9: The device maintains a stable, regulated output voltage without a load current.

Note 10: Dropout voltage is the voltage difference between the input and the output at which the output voltage drops to 100 mV below its nominal value.

Note 11: Quiescent current is defined here as the difference in current between the input voltage source and the load at VOUT.

Note 12: Short Circuit Current is measured with VOUT pulled to 0V and VIN worst case = 6.0V.

Note 13: Ground current is defined here as the total current flowing to ground as a result of all input voltages applied to the device.

Note 14: There is a 1MΩ resistor between VEN and ground on the device.

Note 15: This specification is guaranteed by design.

Note 16: Detailed description of the board can be found in JESD51-7

Output & Input Capacitors

Symbol Parameter Conditions Min Nom Max Units

CIN Input Capacitance (Note 15)Capacitance for stability 0.5 1.0 µF

COUT Output Capacitance (Note 15)0.5 1.0 10

ESR Output/Input Capacitance (Note

15)

5 500 mΩ

Note: The minimum capacitance should be greater than 0.5 µF over the full range of operating conditions. The capacitor tolerance should be 30% or better over

the full temperature range. The full range of operating conditions for the capacitor in the application should be considered during device selection to ensure this

minimum capacitance specification is met. X7R capacitors are recommended however capacitor types X5R, Y5V and Z5U may be used with consideration of the

application and conditions.

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LP5904

Block Diagram

30110406

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LP5904

Typical Performance Curves

Unless otherwise noted, VOUT = 2.8V, VIN = 3.8V, EN = 1.2V,

CIN = 1.0 µF, COUT = 1.0 µF, TA = 25°C.

Iq vs. VIN

2.2 2.7 3.2 3.7 4.2 4.7 5.2 5.7

IQ (μA)

VIN (V)

Dropout Region

30110460

Ground Current vs. Temperature

0 50 100 150 200 250

100

150

200

250

IIN (μA)

IOUT (mA)

-40°C

25°C

85°C

125°C

30110461

Ground Current vs. Voltage

0 50 100 150 200 250 300

100

150

200

250

300

350

VOUT (V)

IOUT (mA)

VIN = 3.0V

VIN = 3.8V

VIN = 4.2V

VIN = 5.5V

30110462

VOUT vs. Load Normalized to 100 mA

30110403

VOUT vs. VIN

3.5 4.0 4.5 5.0 5.5

2.740

2.760

2.780

2.800

2.820

2.840

VOUT (V)

VIN (V)

50 μA

500 μA

1mA

10 mA

100 mA

200 mA

30110463

VOUT vs. IOUT

0 50 100 150 200

2.740

2.760

2.780

2.800

2.820

2.840

VOUT (V)

IOUT (mA)

VIN = 3.8V

VIN = 5.0V

VIN = 5.5V

30110464

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LP5904

VOUT vs IOUT

0 50 100 150 200

2.740

2.760

2.780

2.800

2.820

2.840

VOUT (V)

IOUT OVER TEMPERATURE

-40°C

25°C

85°C

100°C

30110465

Startup, No Load

30110442

Startup, Load = 28Ω

30110443

Startup, Load = 14Ω

30110444

Load Transient

30110445

Line Transient

Load = 1mA, VOUT = 2.8 at VIN Rising Edge

30110412

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LP5904

Line Transient

Load = 1mA, VOUT = 2.8 at VIN Falling Edge

30110413

Line Transient

Load = 200 mA, VOUT = 2.8 at VIN Rising Edge

30110414

Line Transient

Load = 200 mA, VOUT = 2.8 at VIN Falling Edge

30110415

Dropout Voltage vs. Load Current

0 50 100 150 200

100

120

DROPOUT (mV)

IOUT (mA)

30110466

PSRR

30110446

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LP5904

Output Noise Spectral Density,

VOUT = 2.8V

10 100 1000 10000 100000

.001

.01

μV/√(Hz)

FREQUENCY (Hz)

Load = 0mA

Load = 1mA

Load = 50mA

30110467

Turn On Time, 1 mA Load

VOUT = 2.8V, VIN = 3.93V (Battery)

30110416

Turn OFF Time, no Load,

VOUT = 3.3V

30110418

Turn OFF Time, 1 mA Load

VOUT = 3.3V

30110419

Turn OFF Time, 200 mA Load

VOUT = 3.3V

30110420

Turn OFF Time, VEN = VIN at No Load

VOUT = 3.3V

30110421

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LP5904

Turn OFF Time, VEN = VIN at 200 mA

VOUT = 3.3V

30110422

Inrush, VIN = (VOUT(NOM)) + 1V,

VOUT = 3.3V, IOUT = 100 µA

30110423

Inrush, VIN = (VOUT(NOM)) + 1V,

VOUT = 3.3V, IOUT = 200 mA

30110424

VEN Ramp Down vs. VOUT at 1mA Load

VOUT = 3.3V

30110425

VEN Ramp Down vs. VOUT at 200 mA Load

VOUT = 3.3V

30110426

Inrush, VIN Ramp at 1mA Load

VOUT = 2.8V, VIN = 3.8V, TRISE = 100 ms

30110417

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LP5904

Supply Ramping VEN = VIN = (VOUT + 1V) vs.

VOUT at IOUT = 200 mA, VOUT = 3.3V

30110427

Supply Ramping VEN = VIN = (VOUT + 1V) vs.

VOUT at IOUT = 100 µA, VOUT = 3.3V

30110428

VEN Ramping vs VOUT at IOUT = 100 µA,

VIN = (VOUT + 1V), VOUT = 3.3V

30110429

VEN Ramping vs VOUT at IOUT = 200 mA,

VIN = (VOUT + 1V), VOUT = 3.3V

30110430

High Inrush due to Fast Power-On (VIN = VEN)

Such as in Hot-Plug

30110405

No Inrush Current in Normal Power-On due to

System Capacitance Showing VIN Ramping

30110409

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LP5904

Application Hints

POWER DISSIPATION AND DEVICE OPERATION

The permissible power dissipation for any package is a mea-

sure of the capability of the device to pass heat from the power

source, the junctions of the IC, to the ultimate heat sink, the

ambient environment. Thus the power dissipation is depen-

dent on the ambient temperature and the thermal resistance

across the various interfaces between the die and ambient

air. As stated in (Note 5) of the electrical characteristics, the

allowable power dissipation for the device in a given package

can be calculated using the equation:

The actual power dissipation across the device can be rep-

resented by the following equation:

PD = (VIN – VOUT) x IOUT

This establishes the relationship between the power dissipa-

tion allowed due to thermal consideration, the voltage drop

across the device, and the continuous current capability of the

device. These two equations should be used to determine the

optimum operating conditions for the device in the application.

EXTERNAL CAPACITORS

Like any low-dropout regulator, the LP5904 requires external

capacitors for regulator stability. The LP5904 is specifically

designed for portable applications requiring minimum board

space and smallest components. These capacitors must be

correctly selected for good performance.

INPUT CAPACITOR

An input capacitor is required for stability. The input capacitor

should be at least equal to, or greater than, the output capac-

itor for good load transient performance. At least a 1.0 μF

capacitor has to be connected between the LP5904 input pin

and ground for stable operation over full load current range.

Basically, it is ok to have more output capacitance than input,

as long as the input is at least 1.0 μF.

This capacitor must be located a distance of not more than

1cm from the input pin and returned to a clean analog ground.

Any good quality ceramic, tantalum, or film capacitor may be

used at the input.

Important: To ensure stable operation it is essential that

good PCB practices are employed to minimize ground

impedance and keep input inductance low. If these conditions

cannot be met, or if long leads are to be used to connect the

battery or other power source to the LP5904, then it is rec-

ommended to increase the input capacitor to at least 10 µF.

Also, tantalum capacitors can suffer catastrophic failures due

to surge current when connected to a low-impedance source

of power (like a battery or a very large capacitor). If a tantalum

capacitor is used at the input, it must be guaranteed by the

manufacturer to have a surge current rating sufficient for the

application. There are no requirements for the ESR (Equiva-

lent Series Resistance) on the input capacitor, but tolerance

and temperature coefficient must be considered when select-

ing the capacitor to ensure the capacitance will remain

1.0 μF ±30% over the entire operating temperature range.

OUTPUT CAPACITOR

The LP5904 is designed specifically to work with a very small

ceramic output capacitor, typically 1.0 µF. A ceramic capaci-

tor (dielectric types X5R or X7R) in the 0.5 μF to 10 μF range,

and with ESR between 5mΩ to 500 mΩ, is suitable in the

LP5904 application circuit. For this device the output capaci-

tor should be connected between the VOUT pin and a good

ground connection.

It may also be possible to use tantalum or film capacitors at

the device output, VOUT, but these are not as attractive for

reasons of size and cost (see CAPACITOR CHARACTERIS-

TICS below).

The output capacitor must meet the requirement for the min-

imum value of capacitance and have an ESR value that is

within the range 5mΩ to 500 mΩ for stability.

REMOTE CAPACITOR OPERATION

The LP5904 requires at least a 1µF capacitor at output pin,

but there is no strict requirements about the location of the

capacitor in regards the LDO output pin. In practical designs

the output capacitor may be located some 5-10 cm away from

the LDO. This means that there is no need to have a special

capacitor close to the output pin if there is already respective

capacitor(s) in the system (like a capacitor at the input of sup-

plied part). The Remote Capacitor feature helps user to min-

imize the number of capacitors in the system.

As a good design practice, it is good to keep the wiring para-

sitic inductance at a minimum, which means to use as wide

as possible traces from the LDO output to the capacitor(s),

keeping the LDO trace layer as close as possible to ground

layer and avoiding vias on the path. If there is a need to use

vias, implement as many as possible vias between the con-

nection layers. The recommendation is to keep parasitic

wiring inductance less than 35 nH. For the applications with

fast load transients, it is recommended to use an input ca-

pacitor equal to or larger to the sum of the capacitance at the

output node for the best load transient performance.

CAPACITOR CHARACTERISTICS

The LP5904 is designed to work with ceramic capacitors on

the input and output to take advantage of the benefits they

offer. For capacitance values in the range of 0.5 μF to 10 μF,

ceramic capacitors are the smallest, least expensive and

have the lowest ESR values, thus making them best for elim-

inating high frequency noise. The ESR of a typical 1.0 μF

ceramic capacitor is in the range of 20 mΩ to 40 mΩ, which

easily meets the ESR requirement for stability for the LP5904.

The temperature performance of ceramic capacitors varies by

type and manufacturer. Most large value ceramic capacitors

(≥2.2 µF) are manufactured with Z5U or Y5V temperature

characteristics, which results in the capacitance dropping by

more than 50% as the temperature goes from 25°C to 85°C.

A better choice for temperature coefficient in a ceramic ca-

pacitor is X7R. This type of capacitor is the most stable and

holds the capacitance within ±15% over the temperature

range. Tantalum capacitors are less desirable than ceramic

for use as output capacitors because they are more expen-

sive when comparing equivalent capacitance and voltage

ratings in the 0.5 μF to 10 μF range.

Another important consideration is that tantalum capacitors

have higher ESR values than equivalent size ceramics. This

means that while it may be possible to find a tantalum capac-

itor with an ESR value within the stable range, it would have

to be larger in capacitance (which means bigger and more

costly) than a ceramic capacitor with the same ESR value. It

should also be noted that the ESR of a typical tantalum will

increase about 2:1 as the temperature goes from 25°C down

to −40°C, so some guard band must be allowed.

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LP5904

NO-LOAD STABILITY

The LP5904 will remain stable and in regulation with no ex-

ternal load.

ENABLE CONTROL

The LP5904 may be switched ON or OFF by a logic input at

the ENABLE pin. A high voltage at this pin will turn the device

on. When the enable pin is low, the regulator output is off and

the device typically consumes 3nA. However if the application

does not require the shutdown feature, the VEN pin can be tied

to VIN to keep the regulator output permanently on.

A 1mΩ pulldown resistor ties the VEN input to ground, this en-

sures that the device will remain off when the enable pin is

left open circuit. To ensure proper operation, the signal source

used to drive the VEN input must be able to swing above and

below the specified turn-on/off voltage thresholds listed in the

Electrical Characteristics section under VIL and VIH.

MICRO SMD MOUNTING

The micro SMD package requires specific mounting tech-

niques, which are detailed in National Semiconductor Appli-

cation Note AN-1112.

For best results during assembly, alignment ordinals on the

PC board may be used to facilitate placement of the micro

SMD device.

MICRO SMD LIGHT SENSITIVITY

Exposing the micro SMD device to direct light may cause in-

correct operation of the device. Light sources such as halogen

lamps can affect electrical performance if they are situated in

proximity to the device.

Light with wavelengths in the red and infrared part of the

spectrum have the most detrimental effect; thus, the fluores-

cent lighting used inside most buildings has very little effect

on performance.

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LP5904

Physical Dimensions inches (millimeters) unless otherwise noted

4-Bump Thin micro SMD Package

NS Package Number TMD04AAA

The dimensions for X1, X2 and X3 are given as:

X1 = 0.815 mm ± 0.030 mm

X2 = 0.815 mm ± 0.030 mm

X3 = 0.600 mm ± 0.075 mm

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LP5904

Notes

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LP5904

Notes

LP5904 Ultra Low Noise, 200 mA Linear Regulator for RF/Analog Circuits - Requires No Bypass

Capacitor

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