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FEATURES
DControls Boost Preregulator to Near-Unity
Power Factor
DWorld Wide Line Operation
DOver-Voltage Protection
DAccurate Power Limiting
DAverage Current Mode Control
DImproved Noise Immunity
DImproved Feed-Forward Line Regulation
DLeading Edge Modulation
D150-µA Typical Start-Up Current
DLow-Power BiCMOS Operation
D10.8-V to 17-V Operation
DProgrammable Output Voltage (Tracking
Boost Topology)
DESCRIPTION
The UCC2819A/UCC3819A provides all the
functions necessary for active power factor
corrected preregulators. The controller achieves
near unity power factor by shaping the ac-input
line current waveform to correspond to that of the
ac-input line voltage. Average current mode
control maintains stable, low distortion sinusoidal
line current.
Designed i n Texas Instrument’s BiCMOS process,
the UCC3819A offers new features such as lower
start-up current, lower power dissipation,
overvoltage protection, a shunt UVLO detect
circuitry and a leading-edge modulation technique
to reduce ripple current in the bulk capacitor.
The UCC3819A allows the output voltage to be
programmed by bringing out the error amplifier
noninverting input.
BLOCK DIAGRAM
UDG-03124
VREF9
2
16
1
15
10
5
4
DRVOUT
GND
CAI
VCC
OVP/EN
VAOUT
1.9 V
PKLMT
7.5 V
REFERENCE
UVLO
VCC
3
OSCILLATOR
12
RT
14
CT
SQ
R
PWM
LATCH
+
−PWM
CAOUT
+
−
+
−
+
−
VOLTAGE
ERROR AMP 8.0 V
7
11VSENSE
VFF 8
IAC 6
MOUT
MIRROR
2:1
X2
+
−
ENABLE
OVP
÷
X
XMULT
OSC
CLK
CLK
CURRENT
AMP
+
−
0.33 V ZERO POWER
R
+
−
13VAI
10.2 V/9.7 V
! "#$ ! %#&'" ($)
(#"! " !%$""! %$ *$ $! $+! !#$!
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$!. '' %$$!)
Copyright 2003, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SLUS579 − O C TOBER, 2003
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DESCRIPTION (CONTINUED)
The UCC3819A is directly pin for pin compatible with the UCC3819. Only the output stage of UCC3819A has
been modified to allow use of a smaller external gate drive resistor values. For some power supply designs
where an adequately high enough gate drive resistor can not be used, the UCC3819A offers a more robust
output stage at the cost of increasing the internal gate resistances. The gate drive of the UCC3819A remains
strong at ±1.2 A of peak current capability.
Available in the 16-pin D, N, and PW packages.
PIN CONNECTION DIAGRAM
D, N, AND PW PACKAGES
(TOP VIEW)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
GND
PKLMT
CAOUT
CAI
MOUT
IAC
VAOUT
VFF
DRVOUT
VCC
CT
VAI
RT
VSENSE
OVP/EN
VREF
AVAILABLE OPTIONS TABLE
TA = TJ
PACKAGE DEVICES
T
A
= T
JSOIC (D) PACKAGE(1) PDIP (N) PACKAGE TSSOP (PW) PACKAGE(1)
0°C to 70°C UCC3819AD UCC3819AN UCC3819APW
−40°C to 85°C UCC2819AD UCC2819AN UCC2819APW
NOTES: (1) The D and PW packages are available taped and reeled. Add R suffix to the device type (e.g. UCC3819ADR) to order quantities
of 2,500 devices per reel (D package) and 2,000 devices per reel (for PW package). Bulk quantities are 40 units (D package) and
90 units (PW package) per tube.
THERMAL RESISTANCE TABLE
PACKAGE θjc(°C/W) θja(°C/W)
SOIC−16 (D) 22 40 to 70 (1)
PDIP−16 (N) 12 25 to 50 (1)
TSSOP−16 (PW) 14 (2) 123 to 147 (2)
NOTES: (1) Specified θja (junction to ambient) is for devices mounted to 5-inch2 FR4 PC board with one ounce copper
where noted. When resistance range is given, lower values are for 5 inch2 aluminum PC board. Test PWB
was 0.062 inch thick and typically used 0.635-mm trace widths for power packages and 1.3-mm trace
widths for non-power packages with a 100-mil x 100-mil probe land area at the end of each trace.
(2) Modeled data. If value range given for θja, lower value is for 3x3 inch. 1 oz internal copper ground plane,
higher value is for 1x1-inch. ground plane. All model data assumes only one trace for each non-fused
lead.
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ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature (unless otherwise noted)†
UCCx81xA UNIT
Supply voltage VCC 18 V
Gate drive current, continuous 0.2
A
Gate drive current 1.2 A
Input voltage, CAI, MOUT, SS 8
Input voltage, PKLMT 5V
Input voltage, VSENSE, OVP/EN, VAI 10
V
Input current, RT, IAC, PKLMT 10 mA
Maximum negative voltage, DRVOUT, PKLMT, MOUT −0.5 V
Power dissipation 1 W
Junction temperature, TJ−55 to 150
Storage temperature, Tstg −65 to 150 °C
Lead temperature, Tsol (soldering, 10 seconds) 300
C
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
TA = 0°C to 70°C for the UCC3819A, −40°C to 85°C for the UCC2819A, VCC = 12 V, RT = 22 kΩ, CT = 270 pF,
(unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
Supply Current
Supply current, off VCC = (VCC turnon threshold −0.3 V) 150 300 µA
Supply current, on VCC = 12 V, No load on DRVOUT 2 4 6 mA
UVLO
VCC turnon threshold 9.7 10.2 10.8
VCC turnoff threshold 9.4 9.7 V
UVLO hysteresis 0.3 0.5
V
Voltage Amplifier
VIO VAOUT = 2.75 V, VCM = 3.75 V −15 15 mV
VAI bias current VAOUT = 2.75 V, VCM = 3.75 V 50 200
nA
VSENSE bias current VSENSE = VREF, VAOUT = 2.5 V 50 200 nA
CMRR VCM = 1 V to 7.5 V 50 70
dB
Open loop gain VAOUT = 2 V to 5 V 50 90 dB
High-level output voltage IL = −150 µA 5.3 5.5 5.6 V
Low-level output voltage IL = 150 µA 0 50 150 mV
NOTES: 1. Ensured by design, Not production tested.
2. Reference variation for VCC < 10.8 V is shown in Figure 2.
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ELECTRICAL CHARACTERISTICS
TA = 0°C to 70°C for the UCC3819A, −40°C to 85°C for the UCC2819A, VCC = 12 V, RT = 22 kΩ, CT = 270 pF,
(unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
Over Voltage Protection and Enable
Over voltage reference VREF
+0.48 VREF
+0.50 VREF
+0.52 V
Hysteresis 300 500 600 mV
Enable threshold 1.7 1.9 2.1
V
Enable hysteresis 0.1 0.2 0.3 V
Current Amplifier
Input offset voltage VCM = 0 V, VCAOUT = 3 V −3.5 0 2.5 mV
Input bias current VCM = 0 V, VCAOUT = 3 V −50 −100
nA
Input offset current VCM = 0 V, VCAOUT = 3 V 25 100 nA
Open loop gain VCM = 0 V, VCAOUT = 2 V to 5 V 90
dB
Common-mode rejection ratio VCM = 0 V to 1.5 V, VCAOUT = 3 V 60 80 dB
High-level output voltage IL = −120 µA 5.6 6.5 6.8
V
Low-level output voltage IL = 1 mA 0.1 0.2 0.5 V
Gain bandwidth product See Note 1 2.5 MHz
Voltage Reference
Input voltage, (UCC3819A) TA = 0°C to 70°C 7.387 7.5 7.613
V
Input voltage, (UCC2819A) TA = −40°C to 85°C 7.369 7.5 7.631 V
Load regulation IREF = 1 mA to 2 mA 0 10
mV
Line regulation VCC = 10.8 V to 15 V, See Note 2 0 10 mV
Short-circuit current VREF = 0 V −20 −25 −50 mA
Oscillator
Initial accuracy TA = 25°C 85 100 115 kHz
Voltage stability VCC = 10.8 V to 15 V −1% 1%
Total variation Line, temp, See Note 1 80 120 kHz
Ramp peak voltage 4.5 5 5.5
Ramp amplitude voltage
(peak to peak) 3.5 4 4.5 V
Peak Current Limit
PKLMT reference voltage −15 15 mV
PKLMT propagation delay 150 350 500 ns
NOTES: (1) Ensured by design, Not production tested.
(2) Reference variation for VCC < 10.8 V is shown in Figure 2.
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ELECTRICAL CHARACTERISTICS
TA = 0°C to 70°C for the UCC3819A, −40°C to 85°C for the UCC2819A, VCC = 12 V, RT = 22 kΩ, CT = 270 pF,
(unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
Multiplier
IMOUT, high line, low power output
current, (0°C to 85°C) IAC = 500 µA, VFF = 4.7 V, VAOUT = 1.25 V 0 −6 −20
IMOUT, high line, low power output
current, (−40°C to 85°C) IAC = 500 µA, VFF = 4.7 V, VAOUT = 1.25 V 0 −23
IMOUT, high line, high power output
current IAC = 500 µA, VFF = 4.7 V, VAOUT = 5 V −70 −90 −105
µA
IMOUT, low line, low power output
current IAC = 150 µA, VFF = 1.4 V, VAOUT = 1.25 V −10 −19 −50
µA
IMOUT, low line, high power output
current IAC = 150 µA, VFF = 1.4 V, VAOUT = 5 V −268 −300 −346
IMOUT, IAC limited IAC = 150 µA, VFF = 1.3 V, VAOUT = 5 V −250 −300 −400
Gain constant (K) IAC = 300 µA, VFF = 3 V, VAOUT = 2.5 V 0.5 1 1.5 1/V
IMOUT, zero current
IAC = 150 µA, VFF = 1.4 V, VAOUT = 0.25 V 0 −2
IMOUT, zero current IAC = 500 µA, VFF = 4.7 V, VAOUT = 0.25 V 0 −2
A
IMOUT, zero current, (0°C to 85°C) IAC = 500 µA, VFF = 4.7 V, VAOUT = 0.5 V 0 −3 µA
IMOUT, zero current, (−40°C to 85°C) IAC = 500 µA, VFF = 4.7 V, VAOUT = 0.5 V 0 −3.5
Power limit (IMOUT x VFF) IAC = 150 µA, VFF = 1.4 V, VAOUT = 5 V −375 −420 −485 µW
Feed-Forward
VFF output current IAC = 300 µA −140 −150 −160 µA
Gate Driver
Pullup resistance IO = –100 mA to −200 mA 9 12
Ω
Pulldown resistance IO = 100 mA 4 10 Ω
Output rise time CL = 1 nF, RL = 10 Ω, VDRVOUT = 0.7 V to 9 V 25 50
ns
Output fall time CL = 1 nF, RL = 10 Ω, VDRVOUT = 9 V to 0.7 V 10 50 ns
Maximum duty cycle 93% 95% 100%
Minimum controlled duty cycle At 100 kHz 2%
Zero Power
Zero power comparator threshold Measured on VAOUT 0.20 0.33 0.50 V
NOTES: (1) Ensured by design, Not production tested.
(2) Reference variation for VCC < 10.8 V is shown in Figure 2.
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PIN ASSIGNMENTS
TERMINAL
I/O
DESCRIPTION
NAME NO.
I/O
DESCRIPTION
CAI 4 I Current amplifier noninverting input
CAOUT 3 O Current amplifier output
CT 14 I Oscillator timing capacitor
DRVOUT 16 O Gate drive
GND 1 − Ground
IAC 6 I Current proportional to input voltage
MOUT 5 I/O Multiplier output and current amplifier inverting input
OVP/EN 10 I Over-voltage/enable
PKLMT 2 I PFC peak current limit
RT 12 I Oscillator charging current
VAI 13 I Voltage amplifier non-inverting input
VAOUT 7 O Voltage amplifier output
VCC 15 I Positive supply voltage
VFF 8 I Feed-forward voltage
VSENSE 11 IVoltage amplifier inverting input
VREF 9 O Voltage reference output
Pin Descriptions
CAI: Place a resistor between this pin and the GND side of current-sense resistor. This input and the inverting
input (MOUT) remain functional down to and below GND.
CAOUT: This is the output of a wide bandwidth operational amplifier that senses line current and commands
the PFC pulse-width modulator (PWM) to force the correct duty cycle. Compensation components are placed
between CAOUT and MOUT.
CT: A capacitor from CT to GND sets the PWM oscillator frequency according to:
f[ǒ0.6
RT CTǓ
The lead from the oscillator timing capacitor to GND should be as short and direct as possible.
DRVOUT: The output drive for the boost switch is a totem-pole MOSFET gate driver on DRVOUT. To avo i d t h e
excessive overshoot of the DRVOUT while driving a capacitive load, a series gate current-limiting/damping
resistor is recommended to prevent interaction between the gate impedance and the output driver. The value
of the series gate resistor is based on the pulldown resistance (Rpulldown which is 4-Ω typical), the maximum
VCC voltage (VCC), and the required maximum gate drive current (Imax). Using the equation below, a series
gate resistance of resistance 11 Ω would be required for a maximum VCC voltage of 18 V and for 1.2 A of
maximum sink current. The source current will be limited to approximately 900 mA (based on the Rpullup of 9-Ω
typical).
RGATE +VCC *ǒIMAX RpulldownǓ
IMAX
GND: All voltages measured with respect to ground. VCC and REF should be bypassed directly to GND with
a 0.1-µF or larger ceramic capacitor.
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Pin Descriptions (continued)
IAC: This input to the analog multiplier is a current proportional to instantaneous line voltage. The multiplier is
tailored for very low distortion from this current input (IIAC) to multiplier output. The recommended maximum
IIAC is 500 µA.
MOUT: The output of the analog multiplier and the inverting input of the current amplifier are connected together
at MOUT. As the multiplier output is a current, this is a high-impedance input so the amplifier can be configured
as a differential amplifier. This configuration improves noise immunity and allows for the leading-edge
modulation operation. The multiplier output current is limited to ǒ2 IIACǓ. The multiplier output current is given
by the equation:
IMOUT +IIAC (VVAOUT *1)
VVFF2 K
where K +1
V is the multiplier gain constant.
OVP/EN: A window comparator input that disables the output driver if the boost output voltage is a programmed
level above the nominal or disables both the PFC output driver and resets SS if pulled below 1.9 V (typ).
PKLMT: The threshold for peak limit is 0 V. Use a resistor divider from the negative side of the current sense
resistor to VREF to level shift this signal to a voltage level defined by the value of the sense resistor and the
peak current limit. Peak current limit is reached when PKLMT voltage falls below 0 V.
RT: A resistor from RT to GND is used to program oscillator charging current. A resistor between 10 kΩ and
100 kΩ is recommended. Nominal voltage on this pin is 3 V.
VAI: This input can be tied to the VREF or any other voltage reference (≤7.5 V) to set the boost regulator output
voltage.
VAOUT: This is the output of the operational amplifier that regulates output voltage. The voltage amplifier output
is internally limited to approximately 5.5 V to prevent overshoot.
VCC: Connect to a stable source of at least 20 mA between 10 V and 17 V for normal operation. Bypass VCC
directly to GND to absorb supply current spikes required to charge external MOSFET gate capacitances. To
prevent inadequate gate drive signals, the output devices are inhibited unless VVCC exceeds the upper
under-voltage lockout voltage threshold and remains above the lower threshold.
VFF: The RMS voltage signal generated at this pin by mirroring 1/2 of the IIAC into a single pole external filter.
At low line, the VFF roll should be 14 V.
VSENSE: This is normally connected to a compensation network and to the boost converter output through a
divider network.
VREF: VREF is the output of an accurate 7.5-V voltage reference. This output is capable of delivering 20 mA
to peripheral circuitry and is internally short-circuit current limited. VREF is disabled and remains at 0 V when
VVCC is below the UVLO threshold. Bypass VREF to GND with a 0.1-µF or larger ceramic capacitor for best
stability. Please refer to Figures 8 and 9 for VREF line and load regulation characteristics.
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APPLICATION INFORMATION
The UCC3819A is based on the UCC3818 PFC preregulator. For a more detailed application information for
this part, please refer to the UCC3818 datasheet product folder.
The main difference between the UCC3818 and the UCC3819A is that the non-inverting input of the voltage
error amplifier is made available to the user through an external pin (VAI) in the UCC3819A. The SS pin and
function were eliminated to accommodate this change.
The benefit of VAI pin is that it can be used to dynamically change the PFC output voltage based on the line
voltage (RMS) level or other conditions. Figure 1 shows one suggested implementation of the tracking boost
PFC converter as this approach is sometimes referred to. The VAI pin is tied to the VFF pin and hence output
voltage scales up with the line voltage. The benefit of this approach is that at lower line voltages the output
voltage is lower and that leads to smaller boost inductor value, lower MOSFET conduction losses and reduced
component stresses. In order for this feature to work, the downstream converter has to operate over a wider
input range.
UDG−01008
1
11
7
16GND DRVOUT
R17
15
C3
C2
14
C1
13 C4
12 R1
R3 R2
R4
R5C5
9
4
10
VREF
VCC
CT
VAI
RT
VSENSE
OVP/EN
VREF
VAOUT
3
8
2
VFF
C6
C7
R7
6
5
R9
C8
R8
D6
R10
D5
R11
R12
R14
C13C14
R13
IAC
D2
D1
C12 VOUT
+
−
PKLIMIT
CAOUT
CAI
MOUT
IAC
VO
UCC3819A
VLINE
VREF C9
R6
D3 Q1
F1
VO
D4
R19
R20
R21
AC2
AC1
C15
VFF
VCC (FROM BIAS SUPPLY)
Figure 1. Suggested Implementation of UCC3819A in a Tracking Boost PFC Preregulator
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APPLICATION INFORMATION
Figure 2
141210
7.45
7.50
7.55
7.60
7.40
VCC − Supply Voltage − V
13119
VREF − Reference Voltage − V
REFERENCE VOLTAGE
vs
SUPPLY VOLTAGE
Figure 3
REFERENCE VOLTAGE
vs
REFERENCE CURRENT
0 5 10 15 20 25
7.495
7.500
7.505
7.510
7.490
VREF − Reference Voltage − V
IVREF − Reference Current − mA
Figure 4
MULTIPLIER OUTPUT CURRENT
vs
VOLTAGE ERROR AMPLIFIER OUTPUT
0.0 1.0 2.0 3.0 4.0 5.0
50
200
250
350
0
100
300
150
IAC = 150 µA
IAC = 300 µA
IAC = 500 µA
IMOUT - Multiplier Output Current − µA
VAOUT − Voltage Error Amplifier Output − V
Figure 5
MULTIPLIER GAIN
vs
VOLTAGE ERROR AMPLIFIER OUTPUT
1.0 2.0 3.0 4.0 5.0
0.7
1.1
1.3
1.5
0.5
0.9 IAC = 300 µA
IAC = 500 µA
IAC = 150 µA
Multiplier Gain − K
VAOUT − Voltage Error Amplifier Output − V
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APPLICATION INFORMATION
Figure 6
VFF − Feedforward Voltage − V
1.0 2.0 3.0 4.0 5.0
100
300
400
500
0
200
VAOUT = 3 V
VAOUT = 2 V
VAOUT = 4 V
VAOUT = 5 V
(VFF × IMOUT) − µW
MULTIPLIER CONSTANT POWER PERFORMANCE
0.0
References and Resources:
Application Note: Differences Between UCC3817A/18A/19A and UCC3817/18/19, Texas Instruments
Literature Number SLUA294
User’s Guide: UCC3817 BiCMOS Power Factor Preregulator Evaluation Board, Texas Instruments Literature
Number SLUU077
Application Note: Synchronizing a PFC Controller from a Down Stream Controller Gate Drive, Texas
Instruments Literature Number SLUA245
Seminar topic: High Power Factor Switching Preregulator Design Optimization, L.H. Dixon, SEM−700,1990.
Seminar topic: High Power Factor Preregulator for Off−line Supplie”, L.H. Dixon, SEM−600, 1988.
Related Products
DEVICE DESCRIPTION CONTROL METHOD TYPICAL POWER LEVEL
UCC3817/A,18/A BiCMOS PFC controller ACM(2) 75 W to 2 kW+
UC3854 PFC controller ACM(2) 200 W to 2 kW+
UC3854A/B Improved PFC controller ACM(2) 200 W to 2 kW+
UC3855A/B High performance soft switching PFC controller ACM(2) 400 W to 2 kW+
UCC38050/1 Transition mode PFC controller CRM(1) 50 W to 400 W
UCC28510/11/12/13 Advanced PFC+PWM combo controller ACM(2) 75 W to 1kW+
UCC28514/15/16/17 Advanced PFC+PWM combo controller ACM(2) 75 W to 1kW+
NOTES: (1). Critical conduction mode
(2). Average current mode
PACKAGE OPTION ADDENDUM
www.ti.com 17-Aug-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
UCC2819AD ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
UCC2819ADG4 ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
UCC2819ADR ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
UCC2819ADRG4 ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
UCC2819APW ACTIVE TSSOP PW 16 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
UCC2819APWG4 ACTIVE TSSOP PW 16 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
UCC2819APWR ACTIVE TSSOP PW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
UCC2819APWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
UCC3819AD ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
UCC3819ADG4 ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
UCC3819ADR ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
UCC3819ADRG4 ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
UCC3819APW ACTIVE TSSOP PW 16 TBD Call TI Call TI
UCC3819APWG4 ACTIVE TSSOP PW 16 TBD Call TI Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
PACKAGE OPTION ADDENDUM
www.ti.com 17-Aug-2012
Addendum-Page 2
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
UCC2819ADR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
UCC2819APWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
UCC3819ADR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
UCC2819ADR SOIC D 16 2500 333.2 345.9 28.6
UCC2819APWR TSSOP PW 16 2000 367.0 367.0 35.0
UCC3819ADR SOIC D 16 2500 333.2 345.9 28.6
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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