Ordering number : EN4988A CMOS LSI LC74781, 74781M On-Screen Display Controller LSI for VCR Products Overview Package Dimensions The LC74781 and LC74781M are on-screen display CMOS LSIs that display characters and patterns on a TV screen under microprocessor control. The LC74781 and LC74781M display up to 12 lines of 24 characters, each in a 12 x 18 dot matrix. unit: mm 3067-DIP24S [LC74781] Features * Display structure: 12 lines x 24 characters (up to 288 characters) * Character structure: 12 (horizontal) x 18 (vertical) dots * Character sizes: Three size settings each in the vertical and horizontal directions * Character set: 128 characters * Display start position: 64 position settings each in the vertical and horizontal directions * Blinking: In individual character units * Blinking types: Two types with periods of about 0.5 and 1.0 second * Blanking: Whole font area blanking (12 x 18 dots) * Background colors: 8 colors (in internal synchronization mode): 4fSC (NTSC/PAL/PAL-M/ PAL-N) Background colors: 4 colors (in internal synchronization mode): 2fSC (NTSC) Background colors: 1 color (blue) (in internal synchronization mode): 2fSC (PAL/PAL-M/PAL-N) * External control input: 8-bit serial input format * Built-in sync separator circuit * Character blanked data output * Video output: Compound NTSC, PAL, PAL-N and PAL-M output SANYO: DIP24S unit: mm 3045B-MFP24 [LC74781M] SANYO: MFP24 SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN 92595HA/63095TH (OT) No. 4988-1/16 LC74781, 74781M Pin Functions Pin No. Symbol 1 VSS1 Function Description Ground Ground connection (digital system ground) Crystal oscillator connection Used to connect the crystal oscillator and capacitor used to generate the internal synchronization signal, or to input an external clock (2fsc or 4fsc). 2 XtalIN 3 XtalOUT 4 CTRL1 Crystal oscillator input switching Switches between external clock input mode and crystal oscillator mode. Low = crystal oscillator mode, high = external clock mode 5 BLANK Blanking output Outputs the blank signal (the OR of the character and border signals). (Outputs a composite sync signal when MOD0 is high.) Outputs the crystal oscillator clock during reset (when the RST pin is low), but can be set up to not output this signal by microprocessor command. LC oscillator connection Connections for the coil and capacitor that form the oscillator that generates the character output dot clock. Character output Outputs the character signal. (Functions as the external synchronization signal discrimination signal output pin when MOD0 is high, and outputs the state of the judgment as to whether the external synchronization signal is present or not. Outputs a high level when the synchronization signal is present.) Outputs the dot clock (LC oscillator) during reset, but can be set up to not output this signal by microprocessor command. Enable input Serial data input enable input. Serial data input is enabled when low. A pull-up resistor is built in (hysteresis input). Clock input Serial data input clock input. A pull-up resistor is built in (hysteresis input). 6 OSCIN 7 OSCOUT 8 CHARA 9 CS 10 SCLK 11 SIN 12 VDD2 Data input Serial data input. A pull-up resistor is built in (hysteresis input). Power supply Composite video signal level adjustment power supply pin (analog system power supply). 13 CVOUT 14 NC Video signal output Composite video signal output 15 CVIN Video signal input Composite video signal input 16 VDD1 Power supply Power supply (+5 V: digital system power supply) 17 SYNIN Sync separator circuit input Video signal input for the built-in sync separator circuit (Used for either horizontal synchronization signal or composite sync signal input when the built-in sync separator circuit is not used.) 18 SEPC Sync separator circuit bias voltage Built-in sync separator circuit bias voltage monitor pin 19 SEPOUT Composite sync signal output Built-in sync separator circuit composite sync signal output. (When MOD1 is high, outputs a high level during internal synchronization and a low level during external synchronization.) (Outputs the SYNIN input signal when the internal sync separator circuit is not used.) 20 SEPIN Vertical synchronization signal input Inputs a vertical synchronization signal created by integrating the SEPOUT pin output signal. An integrator must be attached at the SEPOUT pin. This pin must be tied to VDD1 if unused. 21 CTRL2 NTSC/PAL-M switching input The setting indicated by this pin takes priority in switching between the NTSC, PAL, PAL-M and PAL-N formats. A low level selects NTSC after a reset. The microprocessor command NTSC, PAL, PAL-M, or PAL-N setting is valid. High = PAL-M format. 22 CTRL3 SEPIN input control Controls whether or not the VSYNC signal is input to the SEPIN input. Low = VSYNC input, high = VSYNC not input. Must be either connected to ground or left open. 23 RST Reset input System reset input. A pull-up resistor is built in (hysteresis input). 24 VDD1 Power supply (+5 V) Power supply (+5 V: digital system power supply) No. 4988-2/16 LC74781, 74781M Pin Assignment Specifications Absolute Maximum Ratings at Ta = 25C Ratings Unit Maximum supply voltage Parameter VDD max Symbol VDD1 and VDD2 pins VSS - 0.3 to VSS + 7.0 V Maximum input voltage VIN max All pins VSS - 0.3 to VDD + 0.3 V BLANK, CHARA and SEPOUT pins VSS - 0.3 to VDD + 0.3 Maximum output voltage VOUT max Allowable power dissipation Pd max Conditions Ta = 25C 350 V mW Operating temperature Topr -30 to +70 C Storage temperature Tstg -40 to +125 C max Unit Allowable Operating Ranges at Ta = -30 to +70C Parameter Supply voltage Input high level voltage Input low level voltage Pull-up resistance Composite video input voltage Input voltage Oscillator frequency Symbol Conditions min typ VDD1 VDD1 pin 4.5 5.0 5.5 V VDD2 VDD2 pin 4.5 5.0 1.27 VDD1 V VIH1 RST, CS, SIN and SCLK pins 0.8 VDD1 VDD1 + 0.3 V VIH2 CTRL1, CTRL2, CTRL3 and SEPIN pins 0.7 VDD1 VDD1 + 0.3 V VIL1 RST, CS, SIN and SCLK pins VSS - 0.3 0.2 VDD1 V VIL2 CTRL1, CTRL2, CTRL3 and SEPIN pins VSS - 0.3 0.3 VDD1 V RPU RST, CS, SIN and SCLK pins, applies to pins set by options. VIN1 CVIN pin: VDD1 = 5 V 2.0 VIN2 SYNIN pin: VDD1 = 5 V 2.0 VIN3 XtalIN pin (in external clock input mode), fin = 2fsc or 4fsc: VDD1 = 5 V 25 50 0.10 90 k Vp-p 2.5 Vp-p 5.0 Vp-p FOSC1 XtalIN and XtalOUT oscillator pins (2fsc: NTSC) 7.159 FOSC1 XtalIN and XtalOUT oscillator pins (4fsc: NTSC) 14.318 MHz FOSC1 XtalIN and XtalOUT oscillator pins (2fsc: PAL) 8.867 MHz FOSC1 XtalIN and XtalOUT oscillator pins (4fsc: PAL) 17.734 MHz FOSC1 XtalIN and XtalOUT oscillator pins (2fsc: PAL-M) 7.151 MHz FOSC1 XtalIN and XtalOUT oscillator pins (4fsc: PAL-M) 14.302 MHz FOSC1 XtalIN and XtalOUT oscillator pins (2fsc: PAL-N) 7.164 MHz FOSC1 XtalIN and XtalOUT oscillator pins (4fsc: PAL-N) FOSC2 OSCIN and OSCOUT oscillator pins (LC oscillator) MHz 14.328 5 MHz 10 MHz Note: If the XtalIN pin is used in clock input mode, be sure to prevent input noise from becoming a problem. No. 4988-3/16 LC74781, 74781M Electrical Characteristics at Ta = -30 to +70C, VDD1 = 5 V unless otherwise specified Parameter Symbol Conditions min typ max Unit Input off leakage current Ileak1 CVIN pin 1 A Output off leakage current Ileak2 CVOUT pin 1 A Output high level voltage VOH1 BLANK, CHARA and SEPOUT pins: VDD1 = 4.5 V, IOH = -1.0 mA Output low level voltage VOL1 BLANK, CHARA and SEPOUT pins: VDD1 = 4.5 V, IOH = 1.0 mA Input current Operating current drain Sync level IIH RST, CS, SIN, SCLK, CTRL1, CTRL3 and SEPIN pins: VIN = VDD1 IIL CTRL1, CTRL2, CTRL3 and OSCIN pins: VIN = VSS1 IDD1 VDD1 pin; all outputs: open, Xtal: 7.159 MHz, LC: 8 MHz IDD2 VDD2 pin: VDD2 = 5 V VSN Pedestal level VPD Color burst low level VCBL Color burst high level VCBH Background color low level VRSL Background color high level VRSH Border level 0 VBK0 Border level 1 VBK1 Character level VCHA 3.5 V 1.0 V 1 A -1 A 15 mA 20 mA CVOUT pin VDD1 = 5.0 V, VDD2 = 5.0 V *1 0.70 0.82 0.94 V *2 0.91 1.03 1.15 V CVOUT pin VDD1 = 5.0 V, VDD2 = 5.0 V *1 1.31 1.43 1.55 V *2 1.53 1.65 1.77 V CVOUT pin VDD1 = 5.0 V, VDD2 = 5.0 V *1 1.00 1.12 1.24 V *2 1.21 1.33 1.45 V CVOUT pin VDD1 = 5.0 V, VDD2 = 5.0 V *1 1.63 1.75 1.87 V *2 1.84 1.96 2.08 V CVOUT pin VDD1 = 5.0 V, VDD2 = 5.0 V *1 1.47 1.59 1.71 V *2 1.68 1.80 1.92 V CVOUT pin VDD1 = 5.0 V, VDD2 = 5.0 V *1 1.99 2.11 2.23 V *2 2.19 2.31 2.43 V CVOUT pin VDD1 = 5.0 V, VDD2 = 5.0 V *1 1.42 1.54 1.66 V *2 1.63 1.75 1.87 V CVOUT pin VDD1 = 5.0 V, VDD2 = 5.0 V *1 1.99 2.11 2.23 V *2 2.19 2.31 2.43 V CVOUT pin VDD1 = 5.0 V, VDD2 = 5.0 V *1 2.58 2.70 2.82 V *2 2.78 2.90 3.02 V min typ Note: 1. When the sync level is 0.8 V. 2. When the sync level is 1.0 V. Timing Characteristics at Ta = -30 to +70C, VDD1 = 5 0.5 V Parameter Minimum input pulse width Data setup time Data hold time One word write time Symbol tW (SCLK) Conditions SCLK pin max Unit 200 ns 1 s tW (CS) CS pin (the period when CS is high) tSU (CS) CS pin 200 ns tSU (SIN) SIN pin 200 ns th (CS) CS pin 2 s th (SIN) SIN pin 200 ns tword 8-bit data write time 4.2 s twt RAM data write time 1 s No. 4988-4/16 LC74781, 74781M Serial Data Input Timing No. 4988-5/16 LC74781, 74781M System Block Diagram No. 4988-6/16 LC74781, 74781M Display Control Commands The display control commands have a serial input format with 8-bit units. A command consists of a command identifier code in the first byte and data in the second and subsequent bytes. There are eight commands as listed below. COMMAND0: Display memory (VRAM) write address setup command COMMAND1: Display character data write command COMMAND2: Vertical display start position and vertical character size setup command COMMAND3: Horizontal display start position and horizontal character size setup command COMMAND4: Display control setup command COMMAND5: Display control setup command COMMAND6: Synchronization signal detection setup command COMMAND7: Display control setup command Display Control Command Table First byte Command Second byte Command identification code Data Data 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 COMMAND0 (Set write address) 1 0 0 0 V3 V2 V1 V0 0 0 0 H4 H3 H2 H1 H0 COMMAND1 (Write character) 1 0 0 1 0 0 0 at 0 c6 c5 c4 c3 c2 c1 c0 1 0 1 0 VS 21 VS 20 VS 11 VS 10 0 FS VP 5 VP 4 VP 3 VP 2 VP 1 VP 0 1 0 1 1 HS 21 HS 20 HS 11 HS 10 0 LC HP 5 HP 4 HP 3 HP 2 HP 1 HP 0 COMMAND4 (Display control) 1 1 0 0 TST MOD RAM ERS OSC STP SYS RST 0 BLK 2 BLK 1 BLK 0 BK 1 BK 0 RV DSP ON COMMAND5 (Display control) 1 1 0 1 NP 1 NP 0 NON INT 0 0 0 BCL CB PH 2 PH 1 PH 0 COMMAND6 (Synchronization signal detection) 1 1 1 0 DIS LIN MUT 0 RN 2 RN 1 RN 0 SN 3 SN 2 SN 1 SN 0 COMMAND7 (Display control) 1 1 1 1 EX 0 PD 0 0 0 0 VNP SEL VSP SEL MSK ERS MSK SEL EGL COMMAND2 (Set vertical display start position and vertical character size) COMMAND3 (Set horizontal display start position and horizontal character size) MOD MOD 1 0 EX 1 PD 1 Once written, the command identifier code in the first byte is stored until the next first byte is written. However, when the display character data write command (COMMAND1) is written, the LC74781/M locks into the display character data write mode, and another first byte cannot be written. When a high level is input to the CS pin, the LC74781/M is set to COMMAND0 (display memory write address setup mode). No. 4988-7/16 LC74781, 74781M COMMAND0 (Display memory write address setup command) First byte Register content DA0 to DA7 Register name State 7 -- 1 6 -- 0 5 -- 0 4 -- 3 2 1 0 V3 V2 V1 V0 Function Note Command 0 identification code Set the display memory write address. 0 0 1 0 1 0 Display memory address (0 to B hexadecimal) 1 0 1 Second byte Register content DA0 to DA7 Register name State 7 -- 0 6 -- 0 5 -- 0 4 H4 3 H3 2 H2 1 H1 0 H0 Function Note Second byte identification bit 0 1 0 1 0 1 Display memory address (0 to 17 hexadecimal) 0 1 0 1 Note: The register states are all set to zero when the LC74781/M is reset with the RST pin. COMMAND1 (Display character data write setup command) First byte Register content DA0 to DA7 Register name State 7 -- 1 6 -- 0 5 -- 0 4 -- 1 3 -- 0 2 -- 0 1 -- 0 0 at Function Command 1 identification code Set up display character data write. 0 Character attribute off 1 Character attribute on Note When this command is input, the LC74781/M locks into the display character data write mode until the CS pin goes high. No. 4988-8/16 LC74781, 74781M Second byte Register content DA0 to DA7 Register name 7 -- 6 c6 5 c5 4 c4 3 c3 2 c2 1 c1 0 c0 State Note Function 0 0 1 0 1 0 1 0 1 Character code (00 to 7F hexadecimal) 0 1 0 1 0 1 Note: The register states are all set to zero when the LC74781/M is reset with the RST pin. COMMAND2 (Vertical display start position and vertical character size setup command) First byte Register content DA0 to DA7 Register name State 7 -- 1 6 -- 0 5 -- 1 4 -- 0 3 VS21 2 VS20 1 VS11 0 VS10 Note Function Command 2 identification code Set the vertical display start position and vertical character size. 0 VS20 0 1 0 0 1H per dot 2H per dot 1 1 3H per dot 1H per dot 1 VS21 0 VS10 0 1 0 0 1H per dot 2H per dot 1 1 3H per dot 1H per dot 1 VS11 Second line vertical character size First line vertical character size Second byte Register content DA0 to DA7 Register name 7 -- 6 5 FS VP5 (MSB) 4 VP4 3 VP3 2 VP2 1 VP1 0 VP0 (LSB) State Function 0 Second byte identification bit 0 Crystal oscillator frequency: 2fsc 1 Crystal oscillator frequency: 4fsc 0 If VS is the vertical display start position then: 1 VS = H x (2 2nVPn) 0 1 Note 5 n=0 H: the horizontal synchronization pulse period 0 1 0 The vertical display start position is set by the 6 bits VP0 to VP5. The weight of bit 1 is 2H. 1 0 1 0 1 Note: The register states are all set to zero when the LC74781/M is reset with the RST pin. No. 4988-9/16 LC74781, 74781M COMMAND3 (Horizontal display start position and horizontal character size setup command) First byte Register content DA0 to DA7 Register name State 7 -- 1 6 -- 0 5 -- 1 4 -- 1 3 HS21 2 1 0 HS20 HS11 HS10 Command 3 identification code Set the horizontal display start position and horizontal character size. 0 1 Note Function HS20 HS21 0 1 0 0 1 Tc per dot 2 Tc per dot 1 1 3 Tc per dot 1 Tc per dot 0 1 HS10 HS11 0 Second line horizontal character size 1 0 0 1 Tc per dot 2 Tc per dot 1 1 3 Tc per dot 1 Tc per dot First line horizontal character size Second byte Register content DA0 to DA7 Register name 7 -- 6 LC 5 HP5 (MSB) 4 3 HP4 HP3 2 HP2 1 HP1 0 HP0 (LSB) State 0 Function Second byte identification bit 0 An LC oscillator is used for the dot clock. 1 A crystal oscillator is used for the dot clock. 0 If HS is the horizontal start position then: 1 0 1 0 Note Selects the dot clock used in horizontal character display. 5 HS = Tc x (2 2nHPn) n=0 Tc: Period of the oscillator connected to OSCIN/OSCOUT in operating mode. The horizontal display start position is set by the six bits HP5 to HP0. The weight of bit 1 is 2Tc. 1 0 1 0 1 0 1 Note: The register states are all set to zero when the LC74781/M is reset with the RST pin. COMMAND4 (Display control setup command) First byte Register content DA0 to DA7 Register name State 7 -- 1 6 -- 1 5 -- 0 4 -- 3 TSTMOD 2 RAMERS Function Command 4 identification code Display control 0 0 Normal operating mode 1 Test mode 0 1 1 OSCSTP 0 SYSRST Note Erase display RAM (set to 7F hexadecimal) This bit must be zero. The RAM erase operation requires about 500 s (It is executed in the DSPOFF state.) 0 Do not stop the crystal oscillator and LC oscillator circuits. 1 Stop the crystal oscillator and LC oscillator circuits. Valid when character display is off in external synchronization mode. Reset all registers and turn the display off. Reset occurs when the CS pin is low, and the reset is cleared when CS goes high. 0 1 No. 4988-10/16 LC74781, 74781M Second byte Register content DA0 to DA7 Register name 7 -- 6 BLK2 5 BLK1 BLK0 3 BK1 2 BK0 0 0 Second byte identification bit 0 Character display block 1 Video display block RV DSPON 1 Note Function 0 4 1 State BLK0 0 1 0 Blanking off Character size 1 Border size Full character size BLK1 0 1 Full character size specification 0 Blinking period: about 0.5 s 1 Blinking period: about 1.0 s 0 Blinking off 1 Blinking on 0 Reverse (character reversing) off 1 Reverse (character reversing) on 0 Character display off 1 Character display on Changes the blanking size. Switches the blinking period. When blinking is specified for reversed characters, the blinking will be between normal character and reversed character display. Note: The register states are all set to zero when the LC74781/M is reset with the RST pin. COMMAND5 (Display control setup command) First byte Register content DA0 to DA7 Register name State 7 -- 1 6 -- 1 5 -- 0 4 -- 1 3 NP1 2 NP0 1 NON 0 INT Command 5 identification code Display control 0 1 Note Function NP0 0 1 0 NTSC PAL-M 1 PAL PAL-N NP1 0 1 0 Interlaced 1 Non-interlaced 0 External synchronization 1 Internal synchronization Switches between NTSC, PAL, PAL-M and PAL-N Switches between interlaced and noninterlaced displays Switches between external and internal synchronization No. 4988-11/16 LC74781, 74781M Second byte Register content DA0 to DA7 Register name State 7 -- 0 6 -- 0 5 -- 0 4 BCL 3 CB 0 Background color present No background color (only the background level is set) 0 Outputs a color burst signal. 1 Stops color burst signal output. PH2 1 0 1 PH1 1 0 0 Second byte identification bit 1 0 2 Note Function PH0 1 Only valid with internal synchronization. Only valid when BCL is high. Background color (phase) Phase 2 Phase 1 Phase 0 NTSC PAL 0 0 0 /2* /2 In phase - /2 + 0 0 1 In phase* 0 1 0 3/2* 0 1 1 * 1 0 0 3/4 3/4 1 0 1 /4 1 1 0 7/4 /4 - /4 + 1 1 1 5/4 - 3/4 + Sample background color phase diagram for PAL mode color burst *: When 2fsc NTSC is used Note: The register states are all set to zero when the LC74781/M is reset with the RST pin. COMMAND6 (Synchronization signal detection setup command) First byte Register content DA0 to DA7 Register name State 7 -- 1 6 -- 1 5 -- 1 4 -- 3 2 MOD1 DISLIN 0 MUT Command 6 identification code Synchronization signal control settings 0 0 Sync separator circuit signal 1 High level output during internal synchronization 0 Pin 5: Blank signal Pin 8: Character signal 1 Pin 5: Composite synchronization signal Pin 8: External synchronization signal discrimination output signal MOD0 1 Note Function 0 12 lines 1 10 lines 0 Normal output 1 CVIN is cut and CVOUT is fixed at the pedestal level. Switches the SEPOUT (pin 19) output Switches the BLANK (pin 5) and CHARA (pin 8) outputs Switches the number of display lines. Switches CVOUT No. 4988-12/16 LC74781, 74781M Second byte Register content DA0 to DA7 Register name 7 -- 6 RN2 5 RN1 4 RN0 3 SN3 2 SN2 1 SN1 0 SN0 State 0 Note Function Second byte identification bit 0 1 RN2 RN1 RN0 Number of times HSYNC detected 0 0 0 0 0 times 1 0 0 1 4 times 0 0 1 0 8 times 1 1 0 0 16 times External synchronization signal detection control Signal absent to present transition recognition Setting for the sampling period when SYNC can be detected consecutively in the horizontal synchronization signal period (1H). 0 1 SN3 SN2 SN1 SN0 0 0 0 1 0 0 0 1 0 Number of times HSYNC detected 0 0 Not detected 0 0 1 32 times 0 1 0 64 times 0 1 0 0 128 times 1 0 0 0 256 times External synchronization signal detection control Signal present to absent transition recognition Setting for the sampling period when SYNC can not be detected consecutively in the horizontal synchronization signal period (1H). 1 Note: The register states are all set to zero when the LC74781/M is reset with the RST pin. COMMAND7 (Display control setup command) First byte Register content DA0 to DA7 Register name State 7 -- 1 6 -- 1 5 -- 1 4 -- 1 3 EX1 2 PD1 1 EX0 0 PD0 Function Note Command 7 identification code Display control setup 0 MODE1 setting output 1 PORT DATA1 setting output 0 The output is set low. 1 The output is set high. 0 MODE0 setting output 1 PORT DATA0 setting output 0 The output is set low. 1 The output is set high. Switches the SEPOUT (pin 19) output Switches the BLANK (pin 5) output Second byte Register content DA0 to DA7 Register name State 7 -- 0 6 -- 0 5 -- 0 4 VNPSEL 3 VSPSEL 2 MSKERS 1 MSKSEL 0 EGL Function Note Second byte identification bit 0 V falling edge detection 1 V rising edge detection 0 VSEP: about 8.9 s (for NTSC) 1 VSEP: about 17.8 s (for NTSC) 0 Mask valid 1 Mask invalid 0 3H (for NTSC) 1 20H (for NTSC) 0 Border level 0 only (VBK0) 1 Border level has two stages (VBK0, VBK1) Switches V acquisition polarity when internal V separation is used in external mode. Switches the internal V separation time. HSYNC and VSYNC mask release Switches the VSYNC mask. Switches the border level (Only valid for BLK0 = 0 and BLK1 = 1) Note: The register states are all set to zero when the LC74781/M is reset with the RST pin. No. 4988-13/16 LC74781, 74781M Display Screen Structure The display consists of 24 characters x 12 rows. The maximum number of displayed character is 288. The maximum number of characters is reduced to less than 288 when the character size is enlarged. Display memory addresses are specified as row (0 to 11 decimal) and column (0 to 23 decimal) addresses. Display Screen Structure (display memory addresses) No. 4988-14/16 LC74781, 74781M Composite Video Signal Output Level (internally generated level) CVOUT output level waveform (VDD2 = 5.00 V) Output voltage [V] Output voltage [V] VCHA: Character 2.70 2.90 VBK1: Border 2.11 2.31 VRSH: Background color high 2.11 2.31 Output level VCBH: Color burst high 1.75 1.96 VRSL: Background color low 1.59 1.80 VBK0: Border 1.54 1.75 VPD: Pedestal 1.43 1.65 VCBL: Color burst low 1.12 1.33 VSN: 0.82 1.03 Sync VDD2 = 5.00 V No. 4988-15/16 LC74781, 74781M No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. Anyone purchasing any products described or contained herein for an above-mentioned use shall: Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of Feburuary, 1997. Specifications and information herein are subject to change without notice. PS No. 4988-16/16 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: ON Semiconductor: LC74781M-9017-E C74781M-9017-L-E