AD7564
a
FEATURES
Four 12-Bit DACs in One Package
4-Quadrant Multiplication
Separate References
Single Supply Operation
Guaranteed Specifications with +3.3 V/+5 V Supply
Low Power
Versatile Serial Interface
Simultaneous Update Capability
Reset Function
28-Pin SOIC, SSOP and DIP Packages
APPLICATIONS
Process Control
Portable Instrumentation
General Purpose Test Equipment
FUNCTIONAL BLOCK DIAGRAM
V A
R B
DAC A
DAC A
LATCH
INPUT
LATCH A
INPUT
LATCH B
INPUT
LATCH C
INPUT
LATCH D
DAC B
LATCH
DAC C
LATCH
DAC D
LATCH
DAC B
DAC C
DAC D
V B
REF
V D
REF
R D
R C
FB
FB
R A
FB
REF
V C
REF
V
DD
DGND
LDAC
CLR
AD7564
12
12
12
12
12
12
12
CONTROL LOGIC
+
INPUT SHIFT
REGISTER
CLKIN
SDIN
SDOUT
12
FSIN
I A
I A
I B
I B
I C
I D
OUT1
OUT2
OUT1
OUT2
OUT1
FB
OUT1
A0 A1
12
NC AGND
I C
OUT2
I D
OUT2
PRODUCT HIGHLIGHTS
1. The AD7564 contains four 12-bit current output DACs with
separate V
REF
inputs.
2. The AD7564 can be operated from a single +3.3 V to +5 V
supply.
3. Simultaneous update capability and reset function are
available.
4. The AD7564 features a fast, versatile serial interface com-
patible with modern 3 V and 5 V microprocessors and
microcomputers.
5. Low power, 50 µW at 5 V and 33 µW at 3.3 V.
LC
2
MOS
+3.3 V/+5 V, Low Power, Quad 12-Bit DAC
One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A.
Tel: Fax:
REV.
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
GENERAL DESCRIPTION
The AD7564 contains four 12-bit DACs in one monolithic
device. The DACs are standard current output with separate
V
REF
, I
OUT1
, I
OUT2
and R
FB
terminals. These DACs operate from
a single +3.3 V to +5 V supply.
The AD7564 is a serial input device. Data is loaded using
FSIN, CLKIN and SDIN. Two address pins A0 and A1 set up
a device address, and this feature may be used to simplify device
loading in a multi-DAC environment. Alternatively, A0 and A1
can be ignored and the serial out capability used to configure a
daisy-chained system.
All DACs can be simultaneously updated using the asynchro-
nous LDAC input, and they can be cleared by asserting the
asynchronous CLR input.
The device is packaged in 28-pin SOIC, SSOP and DIP
packages.
781/329-4700
781/461-3113
B
Parameter B Grade
1
Units Test Conditions/Comments
ACCURACY
Resolution 12 Bits 1 LSB = V
REF
/2
12
= 2.44 mV when V
REF
= 10 V
Relative Accuracy ±0.5 LSB max
Differential Nonlinearity ±0.5 LSB max All Grades Guaranteed Monotonic Over Temperature
Gain Error
+25°C±4 LSBs max
T
MIN
to T
MAX
±5 LSBs max
Gain Temperature Coefficient
2
2 ppm FSR/°C typ
5 ppm FSR/°C max
Output Leakage Current
I
OUT1
@ +25°C 10 nA max
T
MIN
to T
MAX
50 nA max
REFERENCE INPUT
Input Resistance 6 kΩ min Typical Input Resistance = 9.5 kΩ
13 kΩ max
Ladder Resistance Mismatch 2 % max Typically 0.6%
DIGITAL INPUTS
V
INH
, Input High Voltage 2.4 V min
V
INL
, Input Low Voltage 0.8 V max
I
INH
, Input Current ±1µA max
C
IN
, Input Capacitance
2
10 pF max
DIGITAL OUTPUT (SDOUT)
Output Low Voltage (V
OL
) 0.4 V max Load Circuit as in Figure 2.
Output High Voltage (V
OH
) 4.0 V min
POWER REQUIREMENTS
V
DD
Range 4.75/5.25 V min/V max Part Functions from 3.3 V to 5.25 V
Power Supply Rejection
2
∆Gain/∆V
DD
–75 dB typ
I
DD
10 µA max V
INH
= V
DD
, V
INL
= 0 V
At Input Levels of 0.8 V and 2.4 V, I
DD
is
Typically 2 mA.
NOTES
1
Temperature range is as follows: B Version: –40°C to +85°C.
2
Not production tested. Guaranteed by characterization at initial product release.
Specifications subject to change without notice.
REV.
Normal Mode
AD7564–SPECIFICATIONS
(VDD = +4.75 V to +5.25 V; IOUT1A to IOUT1D = IOUT2A = IOUT2D = AGND = 0 V; VREF = +10 V; TA = TMIN to TMAX,
unless otherwise noted)
–2–
B
Parameter A Grade
2
Units Test Conditions/Comments
ACCURACY
Resolution 12 Bits 1 LSB = (V
IOUT2
– V
REF
)/2
12
= 300 µV when
V
IOUT2
= 1.23 V and V
REF
= 0 V
Relative Accuracy ±1 LSB max
Differential Nonlinearity ±0.9 LSB max All Grades Guaranteed Monotonic Over
Temperature
Gain Error
+25°C±4 LSBs max
T
MIN
to T
MAX
±5 LSBs max
Gain Temperature Coefficient
3
2 ppm FSR/°C typ
5 ppm FSR/°C max
Output Leakage Current See Terminology Section
I
OUT1
@ +25°C 10 nA max
T
MIN
to T
MAX
50 nA max
Input Resistance
@ I
OUT2
Pins 6 kΩ min This Varies with DAC Input Code
DIGITAL INPUTS
V
INH
, Input High Voltage @ V
DD
= +5 V 2.4 V min
V
INH
, Input High Voltage @ V
DD
= +3.3 V 2.1 V min
V
INL
, Input Low Voltage @ V
DD
= +5 V 0.8 V max
V
INL
, Input Low Voltage @ V
DD
= +3.3 V 0.6 V max
I
INH
, Input Current ±1µA max
C
IN
, Input Capacitance
3
10 pF max
DIGITAL OUTPUT (SDOUT) Load Circuit as in Figure 2.
Output Low Voltage (V
OL
) 0.4 V max V
DD
= +5 V
Output Low Voltage (V
OL
) 0.2 V max V
DD
= +3.3 V
Output High Voltage (V
OH
) 4.0 V min V
DD
= +5 V
Output High Voltage (V
OH
)V
DD
– 0.2 V min V
DD
= +3.3 V
POWER REQUIREMENTS
V
DD
Range 3/5.5 V min/V max
Power Supply Sensitivity
3
∆Gain/∆V
DD
–75 dB typ
I
DD
10 µA max V
INH
= V
DD
– 0.1 V min, V
INL
= 0.1 V max;
SDOUT Open Circuit
I
DD
is typically 2 mA with V
DD
= +5 V,
V
INH
= 2.4 V min, V
INL
= 0.8 V max;
SDOUT Open Circuit
NOTES
1
These specifications apply with the devices biased up at 1.23 V for single supply applications. The model numbering reflects this by means of a "-B" suffix
(for example: AD7564AR-B). Figure 19 is an example of Biased Mode Operation.
2
Temperature ranges is as follows: A Version: –40°C to +85°C.
3
Not production tested. Guaranteed by characterization at initial product release.
Specifications subject to change without notice.
Biased Mode
1
(VDD = +3 V to +5.5 V; VIOUT1 = VIOUT2 = 1.23 V; AGND = 0 V; VREF = 0 V to 2.45 V; TA = TMIN to
TMAX, unless otherwise noted)
–3–
REV.
AD7564
B
REV.
AD7564
–4–
Parameter A Grade Units Test Conditions/Comments
DYNAMIC PERFORMANCE
Output Voltage Settling Time 3.5 µs typ To 0.01% of Full-Scale Range. V
REF
= 0 V. DAC Latch Alter-
nately Loaded with all 0s and all 1s.
Digital to Analog Glitch Impulse 35 nV-s typ Measured with V
IOUT2
= 0 V and V
REF
= 0 V. DAC Register Alter-
nately Loaded with all 0s and all 1s.
Multiplying Feedthrough Error –70 dB max DAC Latch Loaded with all 0s.
Output Capacitance 100 pF max All 1s Loaded to DAC
40 pF max All 0s Loaded to DAC
Digital Feedthrough 5 nV-s typ Feedthrough to Any DAC Output with FSIN HIGH and a Square
Wave Applied to SDIN and CLKIN
Total Harmonic Distortion –76 dB typ
Output Noise Spectral Density
@ 1 kHz 20 nV/√Hz typ All 1s Loaded to DAC. V
IOUT2
= 0 V; V
REF
= 0 V
(VDD = +3 V to +5.5 V; VIOUT1 = VIOUT2 = 1.23 V; AGND = 0 V. VREF = 1 kHz, 2.45 V p-p, sine wave biased at 1.23 V; DAC
output op amp is AD820; TA = TMIN to TMAX, unless otherwise noted. These characteristics are included for Design
Guidance and are not subject to test.)
Biased Mode
AC Performance Characteristics
Parameter B Grade Units Test Conditions/Comments
DYNAMIC PERFORMANCE
Output Voltage Settling Time 550 ns typ To 0.01% of Full-Scale Range. DAC Latch Alternately Loaded
with All 0s and All 1s
Digital-to-Analog Glitch Impulse 35 nV-s typ Measured with V
REF
= 0 V. DAC Register Alternately Loaded
with All 0s and All 1s
Multiplying Feedthrough Error –70 dB max V
REF
= 20 V p-p, 10 kHz Sine Wave. DAC Latch Loaded
with All 0s
Output Capacitance 60 pF max All 1s Loaded to DAC
30 pF max All 0s Loaded to DAC
Channel-to-Channel Isolation –76 dB typ Feedthrough from Any One Reference to the Others with
20 V p-p, 10 kHz Sine Wave Applied
Digital Crosstalk 5 nV-s typ Effect of All 0s to All 1s Code Transition on Nonselected DACs
Digital Feedthrough 5 nV-s typ Feedthrough to Any DAC Output with FSIN High and Square
Wave Applied to SDIN and SCLK
Total Harmonic Distortion –83 dB typ V
REF
= 6 V rms, 1 kHz Sine Wave
Output Noise Spectral Density
@ 1 kHz 30 nV/√Hz typ All 1s Loaded to the DAC. V
REF
= 0 V. Output Op Amp Is
ADOP07
Normal Mode
(VDD = +4.75 V to +5.25 V; VIOUT1 = VIOUT2 = AGND = 0 V. VREF = 6 V rms, 1 kHz sine wave; DAC output op amp is
AD843; TA = TMIN to TMAX, unless otherwise noted. These characteristics are included for Design Guidance and are
not subject to test.)
AC Performance Characteristics
B
–5–
REV.
3
AD7564
Timing Specifications
1
(TA = TMIN to TMAX unless otherwise noted)
Limit at Limit at
Parameter V
DD
= +3 V to +3.6 V V
DD
= +4.75 V to +5.25 V Units Description
t
1
180 100 ns min CLKIN Cycle Time
t
2
80 40 ns min CLKIN High Time
t
3
80 40 ns min CLKIN Low Time
t
4
50 30 ns min FSIN Setup Time
t
5
50 30 ns min Data Setup Time
t
6
10 5 ns min Data Hold Time
t
7
125 90 ns min FSIN Hold Time
t
82
100 70 ns max SDOUT Valid After CLKIN Falling Edge
t
9
80 40 ns min LDAC, CLR Pulse Width
NOTES
1
Not
production tested. Guaranteed by characterization at initial product release. All input signals are specified with tr = tf = 5 ns (10% to 90% of V
DD
) and timed
from a voltage level of 1.6 V for a V
DD
of 5 V and from a voltage level 1.35 V for a V
DD
of 3.3 V.
2
t
8
is measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.4 V with a V
DD
of 5 V and 0.6 V or 2.1 V for a V
DD
of 3.3 V.
DB15
DB15 DB0
t 2
t 3
t 4
t 5
t7
t 8
t 9
DB0
t 6
t1
FSIN(I)
CLKIN(I)
SDIN(I)
SDOUT(O)
LDAC, CLR
Figure 1. Timing Diagram
1.6mA
+1.6V
200µA
C
L
50pF
TO OUTPUT
PIN
I
OL
I
OH
Figure 2. Load Circuit for Digital Output Timing Specifications
B
REV.
AD7564
–6–
ABSOLUTE MAXIMUM RATINGS
1
(T
A
= +25°C unless otherwise noted)
V
DD
to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V
I
OUT1
to DGND . . . . . . . . . . . . . . . . . . . –0.3 V to V
DD
+ 0.3 V
I
OUT2
to DGND . . . . . . . . . . . . . . . . . . . –0.3 V to V
DD
+ 0.3 V
AGND to DGND . . . . . . . . . . . . . . . . . –0.3 V to V
DD
+ 0.3 V
Digital Input Voltage to DGND . . . . . . –0.3 V to V
DD
+ 0.3 V
V
RFB
, V
REF
to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . .±15 V
Input Current to Any Pin Except Supplies
2
. . . . . . . . ±10 mA
Operating Temperature Range
Commercial Plastic (A, B Versions). . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
DIP Package, Power Dissipation . . . . . . . . . . . . . . . . . 875 mW
θ
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . . . 75°C/W
Lead Temperature, Soldering (10 sec) . . . . . . . . . . 260°C
SOIC Package, Power Dissipation . . . . . . . . . . . . . . . . 875 mW
θ
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . . . 75°C/W
Lead Temperature, Soldering (10 sec) . . . . . . . . . . 260°C
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . +220°C
SSOP Package, Power Dissipation . . . . . . . . . . . . . . . . 900 mW
θ
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . . 100°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . +220°C
NOTES
1
Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
2
Transient currents of up to 100 mA will not cause SCR latch-up.
PIN CONFIGURATION
DIP, SOIC and SSOP Packages
NC = NO CONNECT
DGND
I
OUT2
C
I
OUT2
B
AGND
R
FB
C
V
REF
C
I
OUT2
D
R
FB
B
V
REF
B
I
OUT2
A
V
DD
I
OUT1
C
NC
I
OUT1
B
I
OUT1
D I
OUT1
A
R
FB
D R
FB
A
V
REF
D V
REF
A
SDOUT A0
CLR A1
LDAC OCLKIN
FSIN SDIN
13
18
1
2
28
27
5
6
7
24
23
22
3
4
26
25
821
920
10 19
1111
12 17
16
14 15
TOP VIEW
(Not to Scale)
AD7564
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7564 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
B
AD7564
REV. B –7–
PIN DESCRIPTIONS
Pin
Number Mnemonic Description
1 DGND Digital Ground.
2 IOUT2C IOUT2 terminal for DAC C. This should normally connect to the signal ground of the system.
3 VDD Positive power supply. This is +5 V ± 5%.
4 IOUT1C IOUT1 terminal for DAC C.
5 RFBC Feedback resistor for DAC C.
6 VREFC DAC C reference input.
7 IOUT2D IOUT2 terminal for DAC D. This should normally connect to the signal ground of the system.
8 IOUT1D IOUT1 terminal for DAC D.
9 RFBD Feedback resistor for DAC D.
10 VREFD DAC D reference input.
11 SDOUT This shift register output allows multiple devices to be connected in a daisy chain configuration.
12 CLR Asynchronous CLR input. When this input is taken low, all DAC latches are loaded with all 0s.
13 LDAC Asynchronous LDAC input. When this input is taken low, all DAC latches are simultaneously updated with the
contents of the input latches.
14 FSIN Level-triggered control input (active low). This is the frame synchronization signal for the input data. When FSIN
goes low, it enables the input shift register, and data is transferred on the falling edges of CLKIN. If the address
bits are valid, the 12-bit DAC data is transferred to the appropriate input latch on the sixteenth falling edge after
FSIN goes low.
15 SDIN
Serial data input. The device accepts a 16-bit word. DB0 and DB1 are DAC select bits. DB2 and DB3 are device
address bits. DB4 to DB15 contain the 12-bit data to be loaded to the selected DAC.
16 CLKIN
Clock Input. Data is clocked into the input shift register on the falling edges of CLKIN. Add a pull-down resistor on
the clock line to avoid timing issues.
17 A1 Device address pin. This input in association with A0 gives the device an address. If DB2 and DB3 of the serial
input stream do not correspond to this address, the data which follows is ignored and not loaded to any input
latch. However, it will appear at SDOUT irrespective of this.
18 A0 Device address pin. This input in association with A1 gives the device an address.
19 VREFA DAC A reference input.
20 RFBA Feedback resistor for DAC A.
21 IOUT1A IOUT1 terminal for DAC A.
22 IOUT2A IOUT2 terminal for DAC A. This should normally connect to the signal ground of the system.
23 VREFB DAC B reference input.
24 RFBB Feedback resistor for DAC B.
25 IOUT1B IOUT1 terminal for DAC B.
26 N/C No Connect pin.
27 AGND
This pin connects to the back gates of the current steering switches. It should be connected to the signal ground
of the system.
28 IOUT2B IOUT2 terminal for DAC B. This should normally connect to the signal ground of the system.
B
–9–
REV.
0.5
0.0 10
0.3
0.1
4
0.2
2
0.4
8
6
V
REF
– Volts
DNL – LSBs
NORMAL MODE OF OPERATION
V
DD
= +5V
T
A
= +25°C
Figure 3. Differential Nonlinearity Error vs. V
REF
(Normal Mode)
0
–10
–90
–60
–70
–80
–50
–40
–30
–20
10
3
10
4
10
6
10
5
FREQUENCY – Hz
V
OUT
B/V
OUT
C – dBs
V
REF
C = 20V p-p SINE WAVE
ALL OTHER REFERENCE INPUTS = 0V
DAC C LOADED WITH ALL 1s
ALL OTHER DACs LOADED WITH ALL 0s
Figure 4. Channel-to-Channel Isolation (1 DAC to 1 DAC)
–50
–100
–90
–80
–70
–60
10
2
10
3
10
5
10
4
FREQUENCY – Hz
THD – dBs
NORMAL MODE OF OPERATION
VDD = +5V
VIN = +6V rms
OP AMP = AD713
TA = +25°C
Figure 5. Total Harmonic Distortion vs. Frequency
(Normal Mode)
0.5
0.0 10
0.3
0.1
4
0.2
2
0.4
8
6
V
REF
– Volts
INL – LSBs
NORMAL MODE OF OPERATION
V
DD
= +5V
T
A
= +25°C
Figure 6. Integral Nonlinearity Error vs. V
REF
(Normal Mode)
0
–10
–90
–60
–70
–80
–50
–40
–30
–20
10
3
10
4
10
6
10
5
FREQUENCY – Hz
V
OUT
B/V
OUT
C – dBs
V
REF
B = 0V
ALL OTHER REFERENCE INPUTS = 20V p-p SINE WAVE
DAC B LOADED WITH ALL 0s
ALL OTHER DACs LOADED WITH ALL 1s
Figure 7. Channel-to-Channel Isolation (1 DAC to All
Other DACs)
FREQUENCY – Hz
0
–30
–60
1k
–40
–50
–20
V
DD
= +5V
T
A
= +25°C
V
IN
= 20V p-p
OP AMP = AD711
GAIN – dB
DAC LOADED WITH ALL 1s
DAC LOADED WITH ALL 0s
–10
–70
–80
–90
–100 10k 100k 1M 10M
Figure 8. Multiplying Frequency Response vs. Digital
Code (Normal Mode)
Typical Performance Curves–AD7564
B
REV.
AD7564
–10–
2.0
0.0 1.4
0.6
0.2
0.4
0.4
0.2
1.2
0.8
1.0
1.4
1.6
1.8
1.21.00.80.6
|VREF – VBIAS| – Volts
INL – LSBs
VDD = +3.3V
TA = +25°C
OP AMP = AD820
VREF = +1.23V (AD589)
Figure 9. Integral Nonlinearity Error vs. V
REF
(Biased Mode)
2.0
0.0 1.4
0.6
0.2
0.4
0.4
0.2
1.2
0.8
1.0
1.4
1.6
1.8
1.21.00.80.6
|V
REF
– V
BIAS
| – Volts
V
DD
= +5V
T
A
= +25°C
OP AMP = AD820
V
BIAS
= +1.23V (AD589)
INL – LSBs
Figure 10. Integral Nonlinearity Error vs. V
REF
(Biased Mode)
0.2
–0.5 4095
–0.2
–0.4
1024
–0.3
0
0.1
–0.1
0.0
30722048
CODE – LSBs
LINEARITY ERROR – LSBs
V
DD
= +3.3V
T
A
= +25°C
V
BIAS
= 1.23V
V
REF
= 0V
Figure 11. All Codes Linearity Plot (Biased Mode)
2.0
0.0 1.4
0.6
0.2
0.4
0.4
0.2
1.2
0.8
1.0
1.4
1.6
1.8
1.21.00.80.6
|V
REF
– V
BIAS
| – Volts
DNL – LSBs
V
DD
= +3.3V
T
A
= +25°C
OP AMP = AD820
V
REF
= +1.23V (AD589)
Figure 12. Differential Nonlinearity Error vs. V
REF
(Biased Mode)
2.0
0.0 1.4
0.6
0.2
0.4
0.4
0.2
1.2
0.8
1.0
1.4
1.6
1.8
1.21.00.80.6
|V
REF
– V
BIAS
| – Volts
DNL – LSBs
V
DD
= +5V
T
A
= +25°C
OP AMP = AD820
V
BIAS
= +1.23V (AD589)
Figure 13. Differential Nonlinearity Error vs. V
REF
(Biased Mode)
LINEARITY ERROR – LSBs
0.4
–0.1
0.2
0.0
0.1
0.3
409510240 30722048
CODE – LSBs
NORMAL MODE
V
DD
= +5V
T
A
= +25°C
V
REF
= 10V
Figure 14. All Codes Linearity Plot (Normal Mode)
B
–11–
REV.
3
AD7564
GENERAL DESCRIPTION
D/A Section
The AD7564 contains four 12-bit current output D/A convert-
ers. A simplified circuit diagram for one of the D/A converters
is shown in Figure 15.
V
REF
2R 2R 2R 2R 2R 2R 2R
CBA S9 S8 S0 R
FB
I
OUT1
I
OUT2
RRR
R/2
SHOWN FOR ALL 1s ON DAC
Figure 15. Simplified D/A Circuit Diagram
A segmented scheme is used whereby the 2 MSBs of the 12-bit
data word are decoded to drive the three switches A, B and C.
The remaining 10 bits of the data word drive the switches S0 to
S9 in a standard R-2R ladder configuration.
Each of the switches A to C steers 1/4 of the total reference
current with the remaining current passing through the R-2R
section.
All DACs have separate V
REF
, I
OUT1
, I
OUT2
and R
FB
pins.
When an output amplifier is connected in the standard configu-
ration of Figure 17, the output voltage is given by:
V
OUT
=D×V
REF
where D is the fractional representation of the digital word
loaded to the DAC. Thus, in the AD7564, D can be set from 0
to 4095/4096.
Interface Section
The AD7564 is a serial input device. Three input signals con-
trol the serial interface. These are FSIN, CLKIN and SDIN.
The timing diagram is shown in Figure 1.
Data applied to the SDIN pin is clocked into the input shift reg-
ister on each falling edge of CLKIN. SDOUT is the shift regis-
ter output. It allows multiple devices to be connected in a daisy
chain fashion with the SDOUT pin of one device connected to
the SDIN of the next device. FSIN is the frame synchronization
for the device.
When the sixteen bits have been received in the input shift regis-
ter, DB2 and DB3 (A0 and A1) are checked to see if they corre-
spond to the state on pins A0 and A1. If it does, then the word
is accepted. Otherwise, it is disregarded. This allows the user
to address a number of AD7564s in a very simple fashion. DB1
and DB0 of the 16-bit word determine which of the four DAC
input latches is to be loaded. When the LDAC line goes low, all
four DAC latches in the device are simultaneously loaded with
the contents of their respective input latches and the outputs
change accordingly.
Bringing the CLR line low resets the DAC latches to all 0s. The
input latches are not affected so that the user can revert to the
previous analog output if desired.
16-BIT INPUT
SHIFT REGISTER
CLKIN
FSIN
SDIN SDOUT
Figure 16. Input Logic
UNIPOLAR BINARY OPERATION
(2-Quadrant Multiplication)
Figure 17 shows the standard unipolar binary connection dia-
gram for one of the DACs in the AD7564. When V
IN
is an ac
signal, the circuit performs 2-quadrant multiplication. Resistors
R1 and R2 allow the user to adjust the DAC gain error. Offset
can be removed by adjusting the output amplifier offset voltage.
Figure 17. Unipolar Binary Operation
A1 should be chosen to suit the application. For example, the
AD707 is ideal for very low bandwidth applications while the
AD843 and AD845 offer very fast settling time in wide band-
width applications. Appropriate multiple versions of these am-
plifiers can be used with the AD7564 to reduce board space
requirements.
The code table for Figure 17 is shown in Table III.
Table III. Unipolar Binary Code Table
Digital Input Analog Output
MSB . . . LSB (V
OUT
as Shown in Figure 17)
1111 1111 1111 –V
REF
(4095/4096)
1000 0000 0001 –V
REF
(2049/4096)
1000 0000 0000 –V
REF
(2048/4096)
0111 1111 1111 –V
REF
(2047/4096)
0000 0000 0001 –V
REF
(1/4096)
0000 0000 0000 –V
REF
(0/4096) = 0
NOTE
Nominal LSB size for the circuit of Figure 17 is given by: V
REF
(1/4096).
DAC A A1
AD7564
V
REF
A
V
IN
NOTES
1. ONLY ONE DAC IS SHOWN FOR CLARITY.
2. DIGITAL INPUT CONNECTIONS ARE OMITTED.
3. C1 PHASE COMPENSATION (5–15pF) MAY BE
REQUIRED WHEN USING HIGH SPEED AMPLIFIER.
R2 10Ω
R1 20Ω
SIGNAL
GND
A1: AD707
AD711
AD843
AD845
C1
R
FB
A
I
OUT2
A
I
OUT1
A
V
OUT
B
REV.
AD7564
–12–
In the current mode circuit of Figure 19, I
OUT2
and hence I
OUT1
,
is biased positive by an amount V
BIAS
. For the circuit to operate
correctly, the DAC ladder termination resistor must be con-
nected internally to I
OUT2
. This is the case with the AD7564.
The output voltage is given by:
V
OUT
=D×R
FB
R
DAC
×(V
BIAS
–V
IN
)
+V
BIAS
As D varies from 0 to 4095/4096, the output voltage varies
from V
OUT
= V
BIAS
to V
OUT
= 2 V
BIAS
– V
IN
. V
BIAS
should be a
low impedance source capable of sinking and sourcing all pos-
sible variations in current at the I
OUT2
terminal without any
problems.
Voltage Mode Circuit
Figure 20 shows DAC A of the AD7564 operating in the
voltage-switching mode. The reference voltage, V
IN
is applied
to the I
OUT1
pin, I
OUT2
is connected to AGND and the output
voltage is available at the V
REF
terminal. In this configuration, a
positive reference voltage results in a positive output voltage;
making single supply operation possible. The output from the
DAC is a voltage at a constant impedance (the DAC ladder re-
sistance). Thus, an op amp is necessary to buffer the output
voltage. The reference voltage input no longer sees a constant
input impedance, but one which varies with code. So, the volt-
age input should be driven from a low impedance source.
It is important to note that V
IN
is limited to low voltages be-
cause the switches in the DAC no longer have the same source-
drain voltage. As a result, their on-resistance differs and this
degrades the integral linearity of the DAC. Also, V
IN
must not
go negative by more than 0.3 volts or an internal diode will turn
on, causing possible damage to the device. This means that the
full-range multiplying capability of the DAC is lost.
A1
V
REF
A
R
FB
A
I
OUT1
A
V
IN
V
OUT
I
OUT2
A
R1 R2
AD7564
DAC A
1. ONLY ONE DAC IS SHOWN FOR CLARITY.
2. DIGITAL INPUT CONNECTIONS ARE OMITTED.
3. C1 PHASE COMPENSATION (5–15pF) MAY BE
REQUIRED WHEN USING HIGH SPEED AMPLIFIER.
NOTES
Figure 20. Single Supply Voltage Switching Mode
Operation
BIPOLAR OPERATION
4-Quadrant Multiplication)
Figure 18 shows the standard connection diagram for bipolar
operation of any one of the DACs in the AD7564. The coding
is offset binary as shown in Table IV. When V
IN
is an ac signal,
the circuit performs 4-quadrant multiplication. To maintain
the gain error specifications, resistors R3, R4 and R5 should be
ratio matched to 0.01%.
A1
DAC A
AD7564
VREFA
VIN
NOTES:
1. ONLY ONE DAC IS SHOWN FOR CLARITY.
2. DIGITAL INPUT CONNECTIONS ARE OMITTED.
3. C1 PHASE COMPENSATION (5–15pF) MAY BE
REQUIRED WHEN USING HIGH SPEED AMPLIFIER, A1.
R2 10Ω
R1 20Ω
SIGNAL
GND
C1
RFBA
IOUT1A
VOUT
R4 20kΩ
IOUT2A
20kΩ
R5
R4 20Ω
A2
R3
10kΩ
Figure 18. Bipolar Operation (4-Quadrant Multiplication)
Table IV. Bipolar (Offset Binary) Code Table
Digital Input Analog Output
MSB . . . LSB (V
OUT
as Shown in Figure 18)
1111 1111 1111 –V
REF
(2047/2048)
1000 0000 0001 –V
REF
(1/2048)
1000 0000 0000 –V
REF
(0/2048 = 0)
0111 1111 1111 –V
REF
(1/2048)
0000 0000 0001 –V
REF
(2047/2048)
0000 0000 0000 –V
REF
(2048/2048) = –V
REF
NOTE
Nominal LSB size for the circuit of Figure 18 is given by: V
REF
(1/2048).
SINGLE SUPPLY APPLICATIONS
The “–B” versions of the AD7564 are specified and tested for
single supply applications. Figure 19 shows a typical circuit for
operation with a single +3.3 V to +5 V supply.
A1
DAC A
AD7564
VREFA
RFBA
IOUT1A
IOUT2A
VIN
VBIAS
VOUT
NOTES:
1. ONLY ONE DAC IS SHOWN FOR CLARITY.
2. DIGITAL INPUT CONNECTIONS ARE OMITTED.
3. C1 PHASE COMPENSATION (5–15pF) MAY BE
REQUIRED WHEN USING HIGH SPEED AMPLIFIER, A1.
Figure 19. Single Supply Current Mode Operation
B
–13–
REV.
3
AD7564
MICROPROCESSOR INTERFACING
AD7564 to 80C51 Interface
A serial interface between the AD7564 and the 80C51 micro-
controller is shown in Figure 21. TXD of the 80C51 drives
SCLK of the AD7564 while RXD drives the serial data line of
the part. The FSIN signal is derived from the port line P3.3.
The 80C51 provides the LSB of its SBUF register as the first bit
in the serial data stream. Therefore, the user will have to ensure
that the data in the SBUF register is arranged correctly so that
the data word transmitted to the AD7564 corresponds to the
loading sequence shown in Table I. When data is to be trans-
mitted to the part, P3.3 is taken low. Data on RXD is valid on
the falling edge of TXD. The 80C51 transmits its serial data in
8-bit bytes with only eight falling clock edges occurring in the
transmit cycle. To load data to the AD7564, P3.3 is left low
after the first eight bits are transferred and a second byte of data
is then transferred serially to the AD7564. When the second
serial transfer is complete, the P3.3 line is taken high. Note that
the 80C51 outputs the serial data byte in a format which has the
LSB first. The AD7564 expects the MSB first. The 80C51
transmit routine should take this into account.
CLR
FSIN
SCLK
SDIN
LDAC
P3.5
P3.3
TXD
RXD
P3.4
80C51*
AD7564*
*ADDITIONAL PINS OMMITTED FOR CLARITY
Figure 21. AD7564 to 80C51 Interface
LDAC and CLR on the AD7564 are also controlled by 80C51
port outputs. The user can bring LDAC low after every two
bytes have been transmitted to update the DAC which has been
programmed. Alternatively, it is possible to wait until all the in-
put registers have been loaded (sixteen byte transmits) and then
update the DAC outputs.
AD7564 to 68HC11 Interface
Figure 22 shows a serial interface between the AD7564 and the
68HC11 microcontroller. SCK of the 68HC11 drives SCLK of
the AD7564 while the MOSI output drives the serial data line of
the AD7564. The FSIN signal is derived from a port line
(PC7 shown).
For correct operation of this interface, the 68HC11 should be
configured such that its CPOL bit is a 0 and its CPHA bit is a 1.
When data is to be transmitted to the part, PC7 is taken low.
When the 68HC11 is configured like this, data on MOSI is valid
on the falling edge of SCK. The 68HC11 transmits its serial
data in 8-bit bytes (MSB first), with only eight falling clock
edges occurring in the transmit cycle. To load data to the
AD7564 , PC7 is left low after the first eight bits are transferred
and a second byte of data is then transferred serially to the
AD7564. When the second serial transfer is complete, the PC7
line is taken high.
CLR
FSIN
SCLK
SDIN
LDAC
PC5
PC7
SCK
MOSI
PC6
64HC11*
AD7564*
*ADDITIONAL PINS OMMITTED FOR CLARITY
Figure 22. AD7564 to 64HC11 Interface
In Figure 22, LDAC and CLR are controlled by the PC6
and PC5 port outputs. As with the 80C51, each DAC of the
AD7564 can be updated after each two-byte transfer, or else
all DACs can be simultaneously updated. This interface
is suitable for both 3 V and 5 V versions of the 68HC11
microcontroller.
B
REV.
AD7564
–14–
AD7564 to ADSP-2101/ADSP-2103 Interface
Figure 23 shows a serial interface between the AD7564 and the
ADSP-2101/ADSP-2103 digital signal processors. The ADSP-
2101 operates from 5 V while the ADSP-2103 operates from
3 V supplies. These processors are set up to operate in the
SPORT Transmit Alternate Framing Mode.
The following DSP conditions are recommended: Internal
SCLK; Active low Framing Signal; 16-bit word length. Trans-
mission is initiated by writing a word to the TX register after the
SPORT has been enabled. The data is then clocked out on ev-
ery rising edge of SCLK after TFS goes low. TFS stays low un-
til the next data transfer.
CLR
FSIN
SDIN
CLKIN
LDAC
TFS
DT
SCLK
FO
ADSP-2101/
ADSP-2103
AD7564*
*ADDITIONAL PINS OMMITTED FOR CLARITY
+5V
Figure 23. AD7564 to ADSP-2101/ADSP-2103 Interface
AD7564 to TMS320C25 Interface
Figure 24 shows an interface circuit for the TMS320C25 digital
signal processor. The data on the DX pin is clocked out of
the processor’s Transmit Shift Register by the CLKX signal.
Sixteen-bit transmit format should be chosen by setting the FO
bit in the ST1 register to 0. The transmit operation begins
when data is written into the data transmit register of the
TMS320C25. This data will be transmitted when the FSX line
goes low while CLKX is high or going high. The data, starting
with the MSB, is then shifted out to the DX pin on the rising
edge of CLKX. When all bits have been transmitted, the user
can update the DAC outputs by bringing the XF output flag
low.
CLR
FSIN
SDIN
CLKIN
LDAC
FSX
DX
CLKX
XF
TMS320C25*
AD7564*
*ADDITIONAL PINS OMMITTED FOR CLARITY
+5V
CLOCK
GENERATION
Figure 24. AD7564 to TMS320C25 Interface
APPLICATION HINTS
Output Offset
CMOS D/A converters in circuits such as Figures 17, 18 and 19
exhibit a code dependent output resistance which in turn can
cause a code dependent error voltage at the output of the ampli-
fier. The maximum amplitude of this error, which adds to the
D/A converter nonlinearity, depends on V
OS
, where V
OS
is the
amplifier input offset voltage. For the AD7564 to maintain
specified accuracy with V
REF
at 10 V, it is recommended that
V
OS
be no greater than 500 µV, or (50 × 10
–6
) × (V
REF
), over
the temperature range of operation. Suitable amplifiers include
the ADOP-07, ADOP-27, AD711, AD845 or multiple versions
of these.
Temperature Coefficients
The gain temperature coefficient of the AD7564 has a maxi-
mum value of 5 ppm/°C and a typical value of 2 ppm/°C. This
corresponds to gain shifts of 2 LSBs and 0.8 LSBs respectively
over a 100°C temperature range. When trim resistors R1 and
R2 are used to adjust full scale in Figures 17 and 18, their tem-
perature coefficients should be taken into account. For further
information see “Gain Error and Gain Temperature Coefficient
of CMOS Multiplying DACs,” Application Note, Publication
Number E630c-5-3/86, available from Analog Devices.
High Frequency Considerations
The output capacitances of the AD7564 DACs work in con-
junction with the amplifier feedback resistance to add a pole to
the open loop response. This can cause ringing or oscillation.
Stability can be restored by adding a phase compensation ca-
pacitor in parallel with the feedback resistor. This is shown as
C1 in Figures 17 and 18.
B
–15–
REV.
3
AD7564
APPLICATIONS
Programmable State Variable Filter
The AD7564 with its multiplying capability and fast settling
time is ideal for many types of signal conditioning applications.
The circuit of Figure 25 shows its use in a state variable filter
design. This type of filter has three outputs: low pass, high pass
and bandpass. The particular version shown in Figure 25 uses
the AD7564 to control the critical parameters f
O
, Q and A
O
. In-
stead of several fixed resistors, the circuit uses the DAC equiva-
lent resistances as circuit elements.
Thus, R1 in Figure 25 is controlled by the 12-bit digital word
loaded to DAC A of the AD7564. This is also the case with R2,
R3 and R4. The fixed resistor R5 is the feedback resistor, R
FB
B.
DAC Equivalent Resistance, R
EQ
= (R
LADDER
×
4096)/N
where: R
LADDER
is the DAC ladder resistance
N is the DAC Digital Code in Decimal (0 < N < 4096)
In the circuit of Figure 25:
C1 = C2, R7 = R8, R3 = R4 (i.e., the same code is loaded to
each DAC).
Resonant Frequency, f
O
= 1/(2 π R3C1)
Quality Factor, Q = (R6/R8)
×
(R2/R5)
Bandpass Gain, A
O
= –R2/R1
Using the values shown in Figure 25, the Q range is 0.3 to 5 and
the f
O
range is 0 to 12 kHz.
R8
30kΩ
HIGH
PASS
OUTPUT
C1 1000pF C2 1000pF
LOW
PASS
OUTPUT
A2 A3 A4
A1
C3 10pF
BAND
PASS
OUTPUT
R6
10kΩ
VIN VREFA
IOUT1AI
OUT1BR
FBBV
REFCI
OUT1CV
REFDI
OUT1DVREFB
AD7564
IOUT2AI
OUT2BI
OUT2CI
OUT2D
DAC B
(R2) DAC C
(R3) DAC D
(R4)
R7
30kΩ
R5
DAC A
(R1)
AGND
NOTES
1. A1, A2, A3, A4, : 1/4 X AD713.
2. DIGITAL INPUT CONNECTIONS ARE OMITTED.
3. C3 IS A COMPENSATION CAPACITOR TO ELIMINATE Q AND GAIN VARIATIONS
CAUSED BY AMPLIFIER GAIN AND BANDWIDTH LIMITATIONS.
Figure 25. Programmable 2nd Order State Variable Filter
B
AD7564
–16– REV. B
OUTLINE DIMENSIONS
Figure 26. 28-Lead Plastic Dual In-Line Package [PDIP]
Wide Body
(N-28-2)
Dimensions shown in inches and (millimeters)
Figure 27. 28-Lead Standard Small Outline Package [SOIC_W]
Wide Body
(RW-28)
Dimensions shown in millimeters and (inches)
CONTROLLING DIMENSIO N S ARE IN INCHE S; M ILLIMET E R DIMENSIO NS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQ U IVALENT S FO R
REF E RENCE ONLY AND ARE N OT A PPROPRIATE F OR US E I N DE S IGN.
CORNE R LEADS MAY BE CO NFIG URE D AS W HOL E L EADS.
COMPLIA NT TO JEDE C STANDARDS MS- 011
071006-A
0.1 00 ( 2.54)
BSC
1.565 (39.75)
1.380 (35.05)
0.580 (14.73)
0.485 (12.31)
0.02 2 ( 0.56)
0.01 4 ( 0.36)
0.200 (5.08)
0.115 (2.92)
0.07 0 ( 1.78)
0.05 0 ( 1.27)
0.250 (6.35)
MAX
SEATING
PLANE
0.015
(0.38)
MIN
0.00 5 (0.13)
MIN
0.700 (17.78)
MAX
0.015 (0.38)
0.008 (0.20)
0.62 5 (15.88)
0.60 0 (15.24)
0.015 (0.38)
GAUGE
PLANE
0.1 95 ( 4.95)
0.1 25 ( 3.17)
28
114
15
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLYAND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-013-AE
18.10 (0.7126)
17.70 (0.6969)
0.30 (0.0118)
0.10 (0.0039)
2.65 (0.1043)
2.35 (0.0925)
10.65 (0.4193)
10.00 (0.3937)
7.60 (0.2992)
7.40 (0.2913)
0.75(0.0295)
0.25(0.0098)
45°
1.27 (0.0500)
0.40 (0.0157)
COPLANARITY
0.10 0.33 (0.0130)
0.20 (0.0079)
0.51 (0.0201)
0.31 (0.0122)
SEATING
PLANE
8°
0°
28 15
14
1
1.27 (0.0500)
BSC
06-07-2006-A
AD7564
REV. B –17–
Figure 28. 28-Lead Shrink Small Outline Package [SSOP]
(RS-28)
Dimensions shown in millimeters
ORDERING GUIDE
Model Temperature Range Package Description Package Option
AD7564AR-B −40°C to +85°C 28-Lead SOIC_W RW-28
AD7564ARS-B −40°C to +85°C 28-Lead SSOP RS-28
AD7564ARS-BREEL −40°C to +85°C 28-Lead SSOP RS-28
AD7564ARSZ-B −40°C to +85°C 28-Lead SSOP RS-28
AD7564ARSZ-BREEL −40°C to +85°C 28-Lead SSOP RS-28
AD7564ARZ-B −40°C to +85°C 28-Lead SOIC_W RW-28
AD7564ARZ-BREEL −40°C to +85°C 28-Lead SOIC_W RW-28
AD7564BN −40°C to +85°C 28-Lead PDIP N-28-2
AD7564BNZ −40°C to +85°C 28-Lead PDIP N-28-2
AD7564BR −40°C to +85°C 28-Lead SOIC_W RW-28
AD7564BR-REEL −40°C to +85°C 28-Lead SOIC_W RW-28
AD7564BRS −40°C to +85°C 28-Lead SSOP RS-28
AD7564BRS-REEL −40°C to +85°C 28-Lead SSOP RS-28
AD7564BRSZ −40°C to +85°C 28-Lead SSOP RS-28
AD7564BRSZ-REEL −40°C to +85°C 28-Lead SSOP RS-28
AD7564BRZ −40°C to +85°C 28-Lead SOIC_W RW-28
AD7564BRZ-REEL −40°C to +85°C 28-Lead SOIC_W RW-28
REVISION HISTORY
2/12—Rev. A to Rev. B
Changes to Pin 16 Description ....................................................... 7
Updated Outline Dimensions ....................................................... 17
Changes to Ordering Guide .......................................................... 17
COM P L IANT TO JEDE C S TANDARDS MO- 150- AH
060106-A
28 15
14
1
10.50
10.20
9.90
8.20
7.80
7.40
5.60
5.30
5.00
SEATING
PLANE
0.05 MIN
0.65 BSC
2.00 MAX
0.38
0.22
COPLANARITY
0.10
1.85
1.75
1.65
0.25
0.09
0.95
0.75
0.55
8°
4°
0°
©2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D10540-0-2/12(B)