LT8391
1
8391fa
For more information www.linear.com/LT8391
TYPICAL APPLICATION
FEATURES DESCRIPTION
60V Synchronous 4-Switch
Buck-Boost LED Controller
with Spread Spectrum
The LT
®
8391 is a synchronous 4-switch buck-boost LED
controller that regulates LED current from input voltage
above, below or equal to the output voltage. The propri-
etary peak-buck peak-boost current mode control scheme
allows adjustable and synchronizable 150kHz to 650kHz
fixed frequency operation, or internal ±15% triangle spread
spectrum operation for low EMI. With 4V to 60V input, 0V
to 60V output, and seamless low noise transitions between
operation regions, the LT8391 is ideal for LED driver and
battery charger applications in automotive, industrial and
battery-powered systems.
The LT8391 provides both internal (up to 128:1) and
external (up to 2000:1) LED current PWM dimming with
a high side PMOS switch. Two CTRL pins provide flexible
20:1 analog dimming with ±3% LED current accuracy at
100mV full scale. Fault protection is provided to detect
an open or short LED condition, during which the LT8391
retries, latches off, or keeps running.
98% Efficient 50W (25V, 2A) Buck-Boost LED Driver Efficiency vs VIN
APPLICATIONS
n 4-Switch Single Inductor Architecture Allows VIN
Above, Below or Equal to VOUT
n Synchronous Switching: Up to 98% Efficiency
n Proprietary Peak-Buck Peak-Boost Current Mode
n Wide VIN Range: 4V to 60V
n Wide VOUT Range: 0V to 60V (51V LED)
n ±3% LED Current Accuracy
n 2000:1 External and 128:1 Internal PWM Dimming
n High Side PMOS PWM Switch Driver
n Integrated Bootstrap Diodes
n No Top MOSFET Refresh Noise in Buck or Boost
n Adjustable and Synchronizable: 150kHz to 650kHz
n Flicker-Free Spread Spectrum for Low EMI
n Open and Short LED Protection with Fault Reporting
n Available in 28-Lead TSSOP with Exposed Pad and
28-Lead QFN (4mm × 5mm)
n Automotive Head Lamps/Running Lamps
n High Power LED Lighting
All registered trademarks and trademarks are the property of their respective owners.
221k
100k
0.1µF
4.7µF
100V
x2
0.1µF
0.004Ω
0.1µF
8391 TA01a
10µH
5.1Ω
33µF
63V
499k
4.7µF
100k
0.47µF
100k
10nF
2.2k
1M
34.8k
0.05Ω
10µF
50V
x2
EN/UVLO
V
REF
CTRL2
CTRL1
FAULT
GND
BG1
TG1
LT8391
LSN
LSP
SW1
BG2
SW2
TG2
BST1
BST2
V
IN
INTV
CC
PWM
FB
V
OUT
ISP
ISN
PWMTG
SYNC/SPRD
RP
RT
V
C
SS
25V
2A
LED
V
IN
400kHz
PWM DIM
ANALOG DIM
FAULT
6V TO 55V
INPUT VOLTAGE (V)
0
80
EFFICIENCY (%)
98
96
94
92
90
88
86
84
82
100
5040 602010
8391 TA01b
30
BOOST
BUCK
BUCK-BOOST
LT8391
2
8391fa
For more information www.linear.com/LT8391
PIN CONFIGURATION
ABSOLUTE MAXIMUM RATINGS
VIN, EN/UVLO, VOUT, ISP, ISN ...................................60V
(ISP-ISN) .........................................................–1V to 1V
BST1, BST2 ...............................................................66V
SW1, SW2, LSP, LSN .................................... –6V to 60V
INTVCC, (BST1-SW1), (BST2-SW2) .............................6V
(BST1-LSP), (BST1-LSN) ............................................6V
FB, PWM, SYNC/SPRD, CTRL1, CTRL2, FA U LT ...........6V
(Note 1)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
TOP VIEW
FE PACKAGE
28-LEAD PLASTIC TSSOP
28
27
26
25
24
23
22
21
20
19
18
17
16
15
BG1
BST1
SW1
TG1
LSP
LSN
VIN
INTVCC
EN/UVLO
RP
PWM
VREF
CTRL1
ISP
BG2
BST2
SW2
TG2
VOUT
PWMTG
SYNC/SPRD
RT
VC
FB
SS
FAULT
CTRL2
ISN
29
GND
θJA = 30°C/W, θJC = 5°C/W
EXPOSED PAD (PIN 29) IS GND, MUST BE SOLDERED TO PCB
9 10
TOP VIEW
UFD PACKAGE
28-LEAD (4mm × 5mm) PLASTIC QFN
11 12 13
28 27 26 25 24
14
23
6
5
4
3
2
1
TG1
LSP
LSN
VIN
INTVCC
EN/UVLO
RP
PWM
TG2
VOUT
PWMTG
SYNC/SPRD
RT
VC
FB
SS
SW1
BST1
BG1
BG2
BST2
SW2
VREF
CTRL1
ISP
ISN
CTRL2
FAULT
7
17
18
19
20
21
22
16
815
29
GND
θJA = 34°C/W, θJC = 3.4°C/W
EXPOSED PAD (PIN 29) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LT8391EFE#PBF LT8391EFE#TRPBF LT8391FE 28-Lead Plastic TSSOP –40°C to 125°C
LT8391IFE#PBF LT8391IFE#TRPBF LT8391FE 28-Lead Plastic TSSOP –40°C to 125°C
LT8391HFE#PBF LT8391HFE#TRPBF LT8391FE 28-Lead Plastic TSSOP –40°C to 150°C
LT8391EUFD#PBF LT8391EUFD#TRPBF 8391 28-Lead (4mm × 5mm) Plastic QFN –40°C to 125°C
LT8391IUFD#PBF LT8391IUFD#TRPBF 8391 28-Lead (4mm × 5mm) Plastic QFN –40°C to 125°C
LT8391HUFD#PBF LT8391HUFD#TRPBF 8391 28-Lead (4mm × 5mm) Plastic QFN –40°C to 150°C
Consult ADI Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through
designated sales channels with #TRMPBF suffix.
Operating Junction Temperature Range (Notes 2, 3)
LT8391E ............................................. –40°C to 125°C
LT8391I .............................................. –40°C to 125°C
LT8391H ............................................ –40°C to 150°C
Storage Temperature Range .................. –65°C to 150°C
(http://www.linear.com/product/LT8391#orderinfo)
LT8391
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8391fa
For more information www.linear.com/LT8391
ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VIN Operating Voltage Range l4 60 V
VIN Quiescent Current VEN/UVLO = 0.3V
VEN/UVLO = 1.1V
Not Switching
1
270
2.1
2
2.8
µA
µA
mA
VOUT Voltage Range l0 60 V
VOUT Quiescent Current VEN/UVLO = 0.3V, VOUT = 12V
VEN/UVLO = 1.1V, VOUT = 12V
Not Switching, VOUT = 12V
20
0.1
0.1
40
0.5
0.5
60
µA
µA
µA
Linear Regulators
INTVCC Regulation Voltage IINTVCC = 20mA 4.85 5.0 5.15 V
INTVCC Load Regulation IINTVCC = 0mA to 80mA 1 4 %
INTVCC Line Regulation IINTVCC = 20mA, VIN = 6V to 60V 1 4 %
INTVCC Current Limit VINTVCC = 4.5V 80 110 160 mA
INTVCC Dropout Voltage (VIN – INTVCC) IINTVCC = 20mA, VIN = 4V 160 mV
INTVCC Undervoltage Lockout Threshold Falling 3.44 3.54 3.64 V
INTVCC Undervoltage Lockout Hysteresis 0.24 V
VREF Regulation Voltage IVREF = 100µA l1.97 2.00 2.03 V
VREF Load Regulation IVREF = 0mA to 1mA 0.4 1 %
VREF Line Regulation IVREF = 100µA, VIN = 4V to 60V 0.1 0.2 %
VREF Current Limit VREF = 1.8V 2 2.5 3.2 mA
VREF Undervoltage Lockout Threshold Falling 1.78 1.84 1.90 V
VREF Undervoltage Lockout Hysteresis 50 mV
Control Inputs/Outputs
EN/UVLO Shutdown Threshold l0.3 0.6 1.0 V
EN/UVLO Enable Threshold Falling l1.190 1.214 1.238 V
EN/UVLO Enable Hysteresis 13 mV
EN/UVLO Hysteresis Current VEN/UVLO = 0.3V
VEN/UVLO = 1.1V
VEN/UVLO = 1.3V
–0.1
2.2
–0.1
0
2.5
0
0.1
2.8
0.1
µA
µA
µA
CTRL1, CTRL2 Input Bias Current VCTRL1/2 = 0.75V (Note 4), Current out of
Pin
0 20 50 nA
CTRL1, CTRL2 Dim-Off Threshold Falling l190 200 210 mV
CTRL1, CTRL2 Dim-Off Hysteresis 28 mV
PWM Dimming
External PWM Dimming Threshold Rising, RP = 30k l1.3 1.4 1.5 V
External PWM Dimming Hysteresis RP = 30k 220 mV
Internal PWM Dimming Duty Cycle VPWM = 1V, RP ≥ 51k
VPWM = 1.5V, RP ≥ 51k
VPWM = 2V, RP ≥ 51k
47
97
3
53
%
%
%
Switching Frequency to Internal PWM Dimming
Frequency Ratio
RP = 51k
RP = 82k
RP = 130k
RP = 200k
RP = 300k
256
512
1024
2048
4096
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 2). VIN = 12V, VEN/UVLO = 1.5V unless otherwise noted.
LT8391
4
8391fa
For more information www.linear.com/LT8391
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
RP Pin Current Limit VRP = 0V, Current out of Pin 40 µA
Minimum VOUT for PWMTG to be On PWM dimming on 2.4 3 V
PWMTG On Voltage V(VOUT-PWMTG) VOUT = 12V 4.6 5 5.4 V
PWMTG Off Voltage V(VOUT-PWMTG) VOUT = 12V –0.1 0 0.1 V
PWM to PWMTG Turn On Propagation Delay CPWMTG = 3.3nF to VOUT, 50% to 50% 90 ns
PWM to PWMTG Turn Off Propagation Delay CPWMTG = 3.3nF to VOUT, 50% to 50% 40 ns
PWMTG Turn On Fall Time
PWMTG Turn Off Rise Time
CPWMTG = 3.3nF to VOUT, 10% to 90%
CPWMTG = 3.3nF to VOUT, 90% to 10%
300
10
ns
ns
Error Amplifier
Full Scale LED Current Regulation V(ISP-ISN) VCTRL1/2 ≥ 1.35V (Note 4), VISP = 12V
VCTRL1/2 ≥ 1.35V (Note 4), VISP = 0V
l
l
97
97
100
100
103
103
mV
mV
9/10th LED Current Regulation V(ISP-ISN) VCTRL1/2 = 1.15V (Note 4), VISP = 12V
VCTRL1/2 = 1.15V (Note 4), VISP = 0V
l
l
87
87
90
90
93
93
mV
mV
1/2 LED Current Regulation V(ISP-ISN) VCTRL1/2 = 0.75V (Note 4), VISP = 12V
VCTRL1/2 = 0.75V (Note 4), VISP = 0V
l
l
47.5
47.5
50
50
52.5
52.5
mV
mV
1/20th LED Current Regulation V(ISP-ISN) VCTRL1/2 = 0.30V (Note 4), VISP = 12V
VCTRL1/2 = 0.30V (Note 4), VISP = 0V
l
l
3
3
5
5
7
7
mV
mV
Zero Scale LED Current Regulation V(ISP-ISN) VCTRL1/2 = 0.25V (Note 4), VISP = 12V
VCTRL1/2 = 0.25V (Note 4), VISP = 0V
l
l
–2
–2
0
0
2
2
mV
mV
ISP/ISN Input Common Mode Range l0 60 V
ISP/ISN Low Side to High Side Switchover
Voltage
VISP = VISN 1.8 V
ISP/ISN High Side to Low Side Switchover
Voltage
VISP = VISN 1.7 V
ISP Input Bias Current VPWM = 5V, VISP = VISN = 12V
VPWM = 5V, VISP = VISN = 0V
VEN/UVLO = 0V, VISP = VISN = 12V or 0V
23
–10
0
µA
µA
µA
ISN Input Bias Current VPWM = 5V, VISP = VISN = 12V
VPWM = 5V, VISP = VISN = 0V
VEN/UVLO = 0V, VISP = VISN = 12V or 0V
23
–10
0
µA
µA
µA
LED Current Regulation Amplifier gm2000 µS
FB Regulation Voltage VC = 1.2V l0.98 1.00 1.02 V
FB Line Regulation VIN = 4V to 60V 0.2 0.5 %
FB Load Regulation 0.2 0.8 %
FB Voltage Regulation Amplifier gm660 µS
FB Input Bias Current FB in Regulation, Current Out of Pin 10 40 nA
VC Output Impedance 10 MΩ
VC Standby Leakage Current VC = 1.2V, PWM Dimming Off –10 0 10 nA
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 2). VIN = 12V, VEN/UVLO = 1.5V unless otherwise noted.
LT8391
5
8391fa
For more information www.linear.com/LT8391
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 2). VIN = 12V, VEN/UVLO = 1.5V unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Current Comparator
Maximum Current Sense Threshold V(LSP-LSN) Buck, VFB = 0.8V
Boost, VFB = 0.8V
l
l
35
40
50
50
65
60
mV
mV
Reverse Current Sense Threshold V(LSP-LSN) Buck, VFB = 0.8V
Boost, VFB = 0.8V
–4
–4
mV
mV
LSP Pin Bias Current VLSP = VLSN = 12V 60 µA
LSN Pin Bias Current VLSP = VLSN = 12V 60 µA
Fault
FB Overvoltage Threshold (VFB) Rising l1.03 1.05 1.07 V
FB Overvoltage Hysteresis l15 25 35 mV
FB Open LED Threshold (VFB) Rising, V(ISP-ISN) = 0V l0.93 0.95 0.97 V
FB Open LED Hysteresis V(ISP-ISN) = 0V l35 50 65 mV
FB Short LED Threshold (VFB) Falling l0.24 0.25 0.26 V
FB Short LED Hysteresis Hysteresis l35 50 65 mV
ISP/ISN Over Current Threshold V(ISP-ISN) VISP = 12V 750 mV
ISP/ISN Open LED Threshold V(ISP-ISN) Falling, VFB = 1.0V l8 10 12 mV
ISP/ISN Open LED Hysteresis VFB = 1.0V l3 5 7 mV
FAULT Pull-Down Resistance 100 200 Ω
SS Hard Pull-Down Resistance VEN/UVLO = 1.1V 100 200 Ω
SS Pull-Up Current VFB = 0.8V, VSS = 0V 10.5 12.5 14.5 µA
SS Pull-Down Current VFB = 1.0V, VSS = 2V 1.05 1.25 1.45 µA
SS Fault Latch-Off Threshold Falling 1.7 V
SS Fault Latch-Off Hysteresis 50 mV
SS Fault Reset Threshold 0.2 V
Oscillator
RT Pin Voltage RT = 100kΩ 1.00 V
Switching Frequency VSYNC/SPRD = 0V, RT = 226k
VSYNC/SPRD = 0V, RT = 100k
VSYNC/SPRD = 0V, RT = 59.0k
l
l
l
190
380
570
200
400
600
210
420
630
kHz
kHz
kHz
SYNC Frequency 150 650 kHz
SYNC/SPRD Input Bias Current VSYNC/SPRD = 5V –0.1 0 0.1 µA
SYNC/SPRD Threshold Voltage 0.4 1.5 V
Highest Spread Spectrum Above Oscillator
Frequency
VSYNC/SPRD = 5V 12.5 14.5 16.5 %
Lowest Spread Spectrum Below Oscillator
Frequency
VSYNC/SPRD = 5V –17.7 –15.7 –13.7 %
LT8391
6
8391fa
For more information www.linear.com/LT8391
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 2). VIN = 12V, VEN/UVLO = 1.5V unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Region Transition
Buck-Boost to Boost (VIN/VOUT) 0.73 0.75 0.77
Boost to Buck-Boost (VIN/VOUT) 0.83 0.85 0.87
Buck to Buck-Boost (VIN/VOUT) 1.16 1.18 1.20
Buck-Boost to Buck (VIN/VOUT) 1.31 1.33 1.35
Peak-Buck to Peak-Boost (VIN/VOUT) 0.96 0.98 1.00
Peak-Boost to Peak-Buck (VIN/VOUT) 1.00 1.02 1.04
NMOS Drivers
TG1, TG2 Gate Driver On-Resistance
Gate Pull-Up
Gate Pull-Down
V(BST-SW) = 5V
2.6
1.4
Ω
Ω
BG1, BG2 Gate Driver On-Resistance
Gate Pull-Up
Gate Pull-Down
VINTVCC = 5V
3.2
1.2
Ω
Ω
TG1, TG2 Rise Time
TG1, TG2 Fall Time
CL = 3.3nF, 10% to 90%
CL = 3.3nF, 90% to 10%
25
20
ns
ns
BG1, BG2 Rise Time
BG1, BG2 Fall Time
CL = 3.3nF, 10% to 90%
CL = 3.3nF, 90% to 10%
25
20
ns
ns
TG Off to BG On Delay CL = 3.3nF 60 ns
BG Off to TG On Delay CL = 3.3nF 60 ns
TG1 Minimum Duty Cycle in Buck Region Peak-Buck Current Mode 10 %
TG1 Maximum Duty Cycle in Buck Region Peak-Buck Current Mode 95 %
TG1 Fixed Duty Cycle in Buck-Boost Region Peak-Boost Current Mode 85 %
BG2 Fixed Duty Cycle in Buck-Boost Region Peak-Buck Current Mode 15 %
BG2 Minimum Duty Cycle in Boost Region Peak-Boost Current Mode 10 %
BG2 Maximum Duty Cycle in Boost Region Peak-Boost Current Mode 95 %
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LT8391E is guaranteed to meet performance specifications
from 0°C to 125°C operating junction temperature. Specifications over
the –40°C to 125°C operating junction temperature range are assured by
design, characterization and correlation with statistical process controls.
The LT8391I is guaranteed over the –40°C to 125°C operating junction
temperature range. The LT8391H is guaranteed over the –40°C to 150°C
operating junction temperature range. High junction temperatures degrade
operating lifetimes. Operating lifetime is derated at junction temperatures
greater than 125°C.
Note 3: The LT8391 includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed 150°C when overtemperature protection is active.
Continuous operation above the specified absolute maximum operating
junction temperature may impair device reliability.
Note 4: VCTRL1/2 represents the condition of CTRL1 when CTRL2 is equal
to 2V or the condition of CTRL2 when CTRL1 is equal to 2V.
LT8391
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8391fa
For more information www.linear.com/LT8391
TYPICAL PERFORMANCE CHARACTERISTICS
Switching Waveforms
(Buck Region)
Switching Waveforms
(Buck-Boost Region)
Switching Waveforms
(Boost Region)
LED Current vs VIN VIN Shutdown Current VIN Quiescent Current
Efficiency vs LED Current
(Buck Region)
Efficiency vs LED Current
(Buck-Boost Region)
Efficiency vs LED Current
(Boost Region)
LED CURRENT (A)
0
20
EFFICIENCY (%)
90
80
70
60
50
40
30
100
1.5
VIN = 36V
20.5
8391 G01
1
LED CURRENT (A)
0
20
EFFICIENCY (%)
90
80
70
60
50
40
30
100
1.5
VIN = 24V
20.5
8391 G02
1
LED CURRENT (A)
0
20
EFFICIENCY (%)
90
80
70
60
50
40
30
100
1.5
VIN = 12V
20.5
8391 G03
1
2µs/DIV
VSW1
20V/DIV
VSW2
20V/DIV
IL
2A/DIV
8391 G04
VIN = 36V, ILED = 2A
2µs/DIV
VSW1
20V/DIV
VSW2
20V/DIV
IL
2A/DIV
8391 G05
VIN = 24V, ILED = 2A
2µs/DIV
VSW1
20V/DIV
VSW2
20V/DIV
IL
2A/DIV
8391 G06
VIN = 12V, ILED = 2A
INPUT VOLTAGE (V)
0
1.80
LED CURRENT (A)
2.15
2.10
2.05
2.00
1.95
1.90
1.85
2.20
5040 6010
8391 G07
3020
TEMPERATURE (°C)
–50
0.0
IQ (µA)
2.5
2.0
1.5
1.0
0.5
3.0
125100 150–25 0 25
8391 G08
7550
VIN = 60V
VIN = 12V
VIN = 4V
TEMPERATURE (°C)
–50
1.8
IQ (mA)
2.6
2.4
2.2
2.0
2.8
125100 150–25 0 25
8391 G09
7550
VIN = 60V
VIN = 12V
VIN = 4V
TA = 25°C, unless otherwise noted.
LT8391
8
8391fa
For more information www.linear.com/LT8391
TYPICAL PERFORMANCE CHARACTERISTICS
INTVCC Voltage vs Temperature INTVCC Voltage vs VIN INTVCC UVLO Threshold
VREF Voltage vs Temperature VREF Voltage vs VIN VREF UVLO Threshold
TA = 25°C, unless otherwise noted.
EN/UVLO Enable Threshold EN/UVLO Hysteresis Current CTRL1/CTRL2 Dim-Off Threshold
TEMPERATURE (°C)
–50
4.85
VINTVCC (V )
5.10
5.05
5.00
4.95
4.90
5.15
125100 150–25 0 25
8391 G10
7550
IINTVCC = 0mA
IINTVCC = 80mA
VIN (V)
0
4.85
VINTVCC (V)
5.10
5.05
5.00
4.95
4.90
5.15
5040 6010 20
8391 G11
30
IINTVCC = 20mA
TEMPERATURE (°C)
–50
3.2
VINTVCC (V)
3.8
3.9
3.7
3.5
3.6
3.4
3.3
4.0
125100 150–25 0 25 50
8391 G12
75
RISING
FALLING
TEMPERATURE (°C)
–50
1.96
VREF (V)
2.02
2.03
2.01
1.99
2.00
1.98
1.97
2.04
125100 150–25 0 25 50
8391 G13
75
IVREF = 0mA
IVREF = 1mA
VIN (V)
0
1.96
VREF (V)
2.02
2.03
2.01
1.99
2.00
1.98
1.97
2.04
5040 6010 20
8391 G14
30
IVREF = 100µA
TEMPERATURE (°C)
–50
1.70
VREF (V)
1.90
1.95
1.85
1.80
1.75
2.00
125100 150–25 250 50
8391 G15
75
RISING
FALLING
TEMPERATURE (°C)
–50
1.200
VEN/UVLO (V)
1.230
1.235
1.225
1.220
1.215
1.210
1.205
1.240
125100 150–25 250 50
8391 G16
75
RISING
FALLING
TEMPERATURE (°C)
–50
2.0
IHYS (µA)
2.8
2.6
2.4
2.2
3.0
125100 150–25 250 50
8391 G17
75
TEMPERATURE (°C)
–50
0.10
VCTRL (V)
0.25
0.20
0.15
0.30
125100 150–25 250 50
8391 G18
75
RISING
FALLING
LT8391
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For more information www.linear.com/LT8391
TA = 25°C, unless otherwise noted.
TYPICAL PERFORMANCE CHARACTERISTICS
V(ISP-ISN) Regulation vs VCTRL V(ISP-ISN) Regulation vs VISP
V(ISP-ISN) Regulation
vs Temperature
V(ISP-ISN) Regulation vs VFB FB Regulation vs Temperature
Maximum Current Sense
vs Temperature
VCTRL (V)
0.00
0
V(ISP-ISN) (mV)
100
75
50
25
125
1.751.50 2.000.25 0.750.50 1.00
8391 G19
1.25
VISP (V)
0
94
V(ISP-ISN) (mV)
102
104
100
98
96
106
5040 6010 20
8391 G20
30
TEMPERATURE (°C)
–50 –25
94
V(ISP-ISN) (mV)
102
104
100
98
96
106
125100 1500 25
8391 G21
7550
ISP = 60V
ISP = 12V
ISP = 0V
VFB (V)
0.96 0.97
0
V(ISP-ISN) (mV)
80
100
60
40
20
120
1.031.02 1.040.98 0.99
8391 G22
1.011.00
TEMPERATURE (°C)
–50 –25
0.97
VFB (V)
1.01
1.02
1.00
0.99
0.98
1.03
125100 1500 25
8391 G23
7550
VIN = 60V
VIN = 12V
VIN = 4V
TEMPERATURE (°C)
–50 –25
30
CURRENT LIMIT (mV)
60
65
55
50
45
40
35
70
125100 1500 25
8391 G24
7550
BOOST
BUCK
TEMPERATURE (°C)
–50 –25
0.80
VFB (V)
1.00
1.05
0.95
0.90
0.85
1.10
125100 1500 25
8391 G25
7550
RISING
FALLING
TEMPERATURE (°C)
–50 –25
0.80
VFB (V)
1.00
1.05
0.95
0.90
0.85
1.10
125100 1500 25
8391 G26
7550
RISING
FALLING
TEMPERATURE (°C)
–50 –25
0.10
VFB (V)
0.30
0.35
0.25
0.20
0.15
0.40
125100 1500 25
8391 G27
7550
RISING
FALLING
FB Overvoltage Threshold FB Open LED Threshold FB Short LED Threshold
LT8391
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For more information www.linear.com/LT8391
TYPICAL PERFORMANCE CHARACTERISTICS
ISP/ISN Open LED Threshold SS Current vs Temperature
Oscillator Frequency
vs Temperature
TEMPERATURE (°C)
–50 –25
0
V(ISP-ISN) (mV)
20
25
15
10
5
30
125100 1500 25
8391 G28
7550
RISING
FALLING
TEMPERATURE (°C)
–50 –25
0.0
ISS (µA)
10.0
12.5
7.5
5.0
2.5
15.0
125100 1500 25
8391 G29
7550
PULL-UP
PULL-DOWN
TEMPERATURE (°C)
–50 –25
100
SWITCHING FREQUENCY
(kHz)
500
600
400
300
200
700
125100 1500 25
8391 G30
7550
RT = 59.0k
RT = 100k
RT = 226k
TA = 25°C, unless otherwise noted.
LT8391
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For more information www.linear.com/LT8391
PIN FUNCTIONS
BG1: Buck Side Bottom Gate Drive. Drives the gate of buck
side bottom N-channel MOSFET with a voltage swing from
ground to INTVCC.
BST1: Buck Side Bootstrap Floating Driver Supply. The
BST1 pin has an integrated bootstrap Schottky diode from
the INTVCC pin and requires an external bootstrap capacitor
to the SW1 pin. The BST1 pin swings from a diode voltage
drop below INTVCC to (VIN + INTVCC).
SW1: Buck Side Switch Node. The SW1 pin swings from
a Schottky diode voltage drop below ground up to VIN.
TG1: Buck Side Top Gate Drive. Drives the gate of buck
side top N-channel MOSFET with a voltage swing from
SW1 to BST1.
LSP: Positive Terminal of the Buck Side Inductor Current
Sense Resistor (RSENSE). Ensure accurate current sense
with Kelvin connection.
LSN: Negative Terminal of the Buck Side Inductor Current
Sense Resistor (RSENSE). Ensure accurate current sense
with Kelvin connection.
VIN: Input Supply. The VIN pin must be tied to the power
input to determine the buck, buck-boost, or boost operation
regions. Locally bypass this pin to ground with a minimum
1µF ceramic capacitor.
INTVCC: Internal 5V Linear Regulator Output. The INTVCC
linear regulator is supplied from the VIN pin, and powers
the internal control circuitry and gate drivers. Locally
bypass this pin to ground with a minimum 4.7µF ceramic
capacitor.
EN/UVLO: Enable and Undervoltage Lockout. Force the
pin below 0.3V to shut down the part and reduce VIN qui-
escent current below 2µA. Force the pin above 1.227V for
normal operation. The accurate 1.214V falling threshold
can be used to program an undervoltage lockout (UVLO)
threshold with a resistor divider from VIN to ground. An
accurate 2.5µA pull-down current allows the programming
of VIN UVLO hysteresis. If neither function is used, tie this
pin directly to VIN.
RP: Internal PWM Dimming Frequency Setting. The RP pin
is used to set the internal PWM dimming frequency with
a resistor to ground. Neither uses a resistor larger than
1MΩ nor leaves this pin open. If an external PWM dimming
pulse is available at the PWM pin, tie this pin to ground.
PWM: PWM Dimming Input. The PWM pin can be used
in two ways: external PWM dimming and internal PWM
dimming. For external PWM dimming, drive this pin with
a digital pulse from 0V to a voltage higher than 1.5V to
control PWM dimming of the LED string. Make sure the
RP pin is tied to ground in this case. For internal PWM
dimming, apply an analog voltage between 1V and 2V to
generate an internal digital pulse by comparing with the
internal ramp. If PWM dimming is not used, tie this pin to
INTVCC. Forcing the pin low turns off TG1 and TG2, turns
on BG1 and BG2, disconnects the VC pin from all internal
loads, and turns off PWMTG.
VREF: Voltage Reference Output. The VREF pin provides an
accurate 2V reference capable of supplying 1mA current.
Locally bypass this pin to ground with a 0.47µF ceramic
capacitor.
CTRL1: Control Input for LED Current Sense Threshold. The
CTRL1 pin is used to program the LED regulation current:
ILED =Min VCTRL1 – 0.25V,VCTRL2 – 0.25,1V
( )
10 •R
LED
The VCTRL1 can be set by an external voltage reference
or a resistor divider from VREF to ground. For 0.25V ≤
VCTRL1 ≤ 1.15V, the current sense threshold linearly goes
up from 0mV to 90mV. For VCTRL1 ≥ 1.35V, the current
sense threshold is constant at 100mV full scale value.
For 1.15V ≤ VCTRL1 ≤ 1.35V, the current sense threshold
smoothly transitions from the linear function of VCTRL1
to the 100mV constant value. Tie CTRL1 to VREF for the
100mV full scale threshold. Force the pin below 0.2V to
stop switching.
ISP: Positive Terminal of the LED Current Sense Resistor
(RLED). Ensure accurate current sense with Kelvin con-
nection.
ISN: Negative Terminal of the LED Current Sense Resis-
tor (RLED). Ensure accurate current sense with Kelvin
connection.
LT8391
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For more information www.linear.com/LT8391
PIN FUNCTIONS
CTRL2: Thermal Control Input for LED Current Sense
Threshold. The CTRL2 pin is used to program LED current
derating versus temperature. The VCTRL2 with a negative
temperature coefficient can be set by an external tem-
perature dependent resistor divider from VREF to ground.
For 0.25V ≤ VCTRL2 ≤ 1.15V, the current sense threshold
linearly goes up from 0mV to 90mV. For VCTRL2 ≥ 1.35V,
the current sense threshold is constant at 100mV full
scale value. For 1.15V ≤ VCTRL2 ≤ 1.35V, the current sense
threshold smoothly transitions from the linear function of
VCTRL2 to the 100mV constant value. Tie CTRL2 to VREF
for the 100mV full scale threshold. Force the pin below
0.2V to stop switching.
FAULT: LED Fault Open Drain Output. The FAULT pin is
pulled low when any of the following conditions happens:
1. Open LED (VFB > 0.95V & V(ISP-ISN) < 10mV)
2. Short LED (VFB < 0.25V)
To function, the pin requires an external pull-up resistor.
The FAULT status is updated only during PWM high state
and latched during PWM low state.
SS: Soft-Start Timer Setting. The SS pin is used to set
soft-start timer by connecting a capacitor to ground. An
internal 12.5µA pull-up current charging the external SS
capacitor gradually ramps up FB regulation voltage. A
0.1µF capacitor is recommended on this pin. Any UVLO or
thermal shutdown immediately pulls SS pin to ground and
stops switching. Using a single resistor from SS to VREF,
the LT8391 can be set in three different fault protection
modes during open or short LED fault conditions: hiccup
(no resistor), latchoff (499k), and keep-running (100k).
See more details in the Application Information section.
FB: Voltage Loop Feedback Input. The FB pin is used for
constant-voltage regulation and LED fault protection. The
internal error amplifier with its output VC regulates VFB
to 1.00V through the DC/DC converter. During open LED
(VFB > 0.95V & V(ISP-ISN) < 10mV) or short LED (VFB <
0.25V) fault conditions, the part pulls the FAULT pin low
and gets into one fault mode per customer setting. During
an overvoltage (VFB > 1.05V) condition, the part turns off
all TG1, BG1, TG2, BG2, and PWMTG.
VC: Error Amplifier Output to Set Inductor Current Com-
parator Threshold. The VC pin is used to compensate the
control loop with an external RC network. During PWM
low state, the VC pin is disconnected from all internal
loads to store its voltage information for the highest PWM
dimming performance.
RT: Switching Frequency Setting. Connect a resistor from
this pin to ground to set the internal oscillator frequency
from 150kHz to 650kHz.
SYNC/SPRD: Switching Frequency Synchronization or
Spread Spectrum. Ground this pin for switching at inter-
nal oscillator frequency. Apply a clock signal for external
frequency synchronization. Tie to INTVCC for ±15% triangle
spread spectrum around internal oscillator frequency.
PWMTG: PWM Dimming Top Gate Drive. A buffered and
inverted version of the PWM input signal, the PWMTG
pin drives an external high side PMOS PWM switch with
a voltage swing from the higher voltage of (VOUT –5V)
and 1.2V to VOUT. Leave this pin unconnected if not used.
VOUT: Output Supply. The VOUT pin must be tied to the
power output to determine the buck, buck-boost, or boost
operation regions. The VOUT pin also serves as positive rail
for the PWMTG drive. Locally bypass this pin to ground
with a minimum 1µF ceramic capacitor.
TG2: Boost Side Top Gate Drive. Drives the gate of boost
side top N-Channel MOSFET with a voltage swing from
SW2 to BST2.
SW2: Boost Side Switch Node. The SW2 pin swings from
a Schottky diode voltage drop below ground to VOUT.
BST2: Boost Side Bootstrap Floating Driver Supply. The
BST2 pin has an integrated bootstrap Schottky diode from
the INTVCC pin and requires an external bootstrap capacitor
to the SW2 pin. The BST2 pin swings from a diode voltage
drop below INTVCC to (VOUT + INTVCC).
BG2: Boost Side Bottom Gate Drive. Drives the gate of
boost side bottom N-Channel MOSFET with a voltage
swing from ground to INTVCC.
GND (Exposed Pad): Ground. Solder the exposed pad
directly to the ground plane.
LT8391
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For more information www.linear.com/LT8391
BLOCK DIAGRAM
+
–
+
–
–
+
+
+
EA2
+
–
+
–
+
–
+
–
–
+
+
–
+
–
+
–
+
–
+
+
–
EA1
+
–
A2=10
A1
A3
5V LDO
2V REF
INTVCC
VREF
RT
SYNC/SPRD
CTRL1
0.2V
FBOV
ISOC
FB
OSC VOS
1.05V
VISP-ISN
0.75V PEAK_BOOST
PWMON
VOUT/BST2
VIN/BST1
CTRL2
PWM
SS GND
ISN
8391 BD
ISP
0.25V
CTRL1
CTRL2
1.25V
1V FB
BST2
D2
TG2
SW2
BG2
BG1
SW1
TG1
BST1
GND
GND
VCVIS
PWMON
0.1V
0.95V
1.25µA
12.5µA
10µA
0.25V
FB
LED
FAULT
LOGIC
INHIBIT
SWITCH
FB
OPEN
SHORT
VIS
PWMTG
FAULT
RP
VOUT
PWMON VREF
VOUT –5V
0.2V
EN/UVLO
1.214V
2.5µA
VIN LSN LSP
INT/EXT
PWM
+
–
A4
INTVCC
INTVCC
INTVCC
D1
INTVCC
PWMON
PEAK_BUCK
BOOST
LOGIC
BUCK
LOGIC
CHARGE
CONTROL
LT8391
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For more information www.linear.com/LT8391
OPERATION
The LT8391 is a current mode LED controller that can
regulate LED current from input voltage above, below,
or equal to the LED string voltage. The LTC proprietary
peak-buck peak-boost current mode control scheme uses a
single inductor current sense resistor and provides smooth
transition between buck region, buck-boost region, and
boost region. Its operation is best understood by referring
to the Block Diagram.
Power Switch Control
Figure 1 shows a simplified diagram of how the four power
switches A, B, C, and D are connected to the inductor L,
the current sense resistor RSENSE, power input VIN, power
output VOUT, and ground. The current sense resistor RSENSE
connected to the LSP and LSN pins provides inductor
current information for both peak current mode control
and reverse current detection in buck region, buck-boost
region, and boost region. Figure 2 shows the current mode
control as a function of VIN/VOUT ratio and Figure 3 shows
the operation region as a function of VIN/VOUT ratio. The
power switches are properly controlled to smoothly transi-
tion between modes and regions. Hysteresis is added to
prevent chattering between modes and regions.
Figure 1. Simplified Diagram of the Power Switches
VOUT
DA
SW1 SW2
TG2
BG2
8391 F01
TG1
BG1 B C
L
VIN
RSENSE
There are total four states: (1) peak-buck current mode
control in buck region, (2) peak-buck current mode con-
trol in buck-boost region, (3) peak-boost current mode
control in buck-boost region, and (4) peak-boost current
mode control in boost region. The following sections give
detailed description for each state with waveforms, in
which the shoot-through protection dead time between
switches A and B, between switches C and D are ignored
for simplification.
Peak-Buck in Buck Region (VIN >> VOUT)
When VIN is much higher than VOUT, the LT8391 uses
peak-buck current mode control in buck region (Figure 4).
Switch C is always off and switch D is always on. At the
beginning of every cycle, switch A is turned on and the
inductor current ramps up. When the inductor current hits
the peak buck current threshold commanded by VC voltage
at buck current comparator A3 during (A+D) phase, switch
A is turned off and switch B is turned on for the rest of
the cycle. Switches A and B will alternate, behaving like a
typical synchronous buck regulator.
Figure 2. Current Mode vs VIN/VOUT Ratio
Figure 3. Operation Region vs VIN/VOUT Ratio
PEAK-BUCK
PEAK-BOOST
VIN/VOUT
0.98 1.00 1.02 8391 F02
BUCK
(1)
(2)
(2)(3)
BOOST
BUCK-BOOST
VIN/VOUT
0.850.75 1.00 1.18 1.33
8391 F03
(4)
LT8391
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For more information www.linear.com/LT8391
Figure 4. Peak-Buck in Buck Region (VIN >> VOUT) Figure 5. Peak-Buck in Buck-Boost Region (VIN ~> VOUT)
Figure 6. Peak-Boost in Buck-Boost Region (VIN <~ VOUT)
OPERATION
Peak-Buck in Buck-Boost Region (VIN ~> VOUT)
When VIN is slightly higher than VOUT, the LT8391 uses
peak-buck current mode control in buck-boost region
(Figure 5). Switch C is always turned on for the beginning
15% cycle and switch D is always turned on for the remain-
ing 85% cycle. At the beginning of every cycle, switches
A and C are turned on and the inductor current ramps
up. After 15% cycle, switch C is turned off and switch D
is turned on, and the inductor keeps ramping up. When
the inductor current hits the peak buck current threshold
commanded by VC voltage at buck current comparator A3
during (A+D) phase, switch A is turned off and switch B
is turned on for the rest of the cycle.
Peak-Boost in Buck-Boost Region (VIN <~ VOUT)
When VIN is slightly lower than VOUT, the LT8391 uses
peak-boost current mode control in buck-boost region
(Figure 6). Switch A is always turned on for the begin-
ning 85% cycle and switch B is always turned on for the
remaining 15% cycle. At the beginning of every cycle,
switches A and C are turned on and the inductor current
ramps up. When the inductor current hits the peak boost
current threshold commanded by VC voltage at boost
current comparator A4 during (A+C) phase, switch C is
turned off and switch D is turned on for the rest of the
cycle. After 85% cycle, switch A is turned off and switch
B is turned on for the rest of the cycle.
100% OFF
100% ON
A
B
C
D
IL
A+D A+D
B+D B+D
8391 F04
A
B
C15%
85% 85%
15%
D
ILA+D
A+C B+D
A+D
A+C B+D
8391 F05
A
B
C
15%
85% 85%
15%
D
ILA+D
A+C
B+D
A+D
A+C
B+D
8391 F06
Peak-Boost in Boost Region (VIN << VOUT)
When VIN is much lower than VOUT, the LT8391 uses peak-
boost current mode control in boost region (Figure 7).
Switch A is always on and switch B is always off. At the
beginning of every cycle, switch C is turned on and the
inductor current ramps up. When the inductor current hits
the peak boost current threshold commanded by VC voltage
at boost current comparator A4 during (A+C) phase, switch
C is turned off and switch D is turned on for the rest of
LT8391
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For more information www.linear.com/LT8391
OPERATION
the cycle. Switches C and D will alternate, behaving like a
typical synchronous boost regulator.
Figure 7. Peak-Boost in Boost Region (VIN << VOUT)
A
B
C
100% ON
100% OFF
D
IL
A+DA+C A+DA+C
8391 F07
Main Control Loop
The LT8391 is a fixed frequency current mode control-
ler. The inductor current is sensed through the inductor
sense resistor between the LSP and LSN pins. The current
sense voltage is gained up by amplifier A1 and added to
a slope compensation ramp signal from the internal os-
cillator. The summing signal is then fed into the positive
terminals of the buck current comparator A3 and boost
current comparator A4. The negative terminals of A3 and
A4 are controlled by the voltage on the VC pin, which is
the diode-OR of error amplifiers EA1 and EA2.
Depending on the state of the peak-buck peak-boost cur-
rent mode control, either the buck logic or the boost logic
is controlling the four power switches so that either the
FB voltage is regulated to 1V or the current sense voltage
between the ISP and ISN pins is regulated by the CTRL1
or CTRL2 pin during normal operation. The gains of EA1
and EA2 have been balanced to ensure smooth transition
between constant-voltage and constant-current operation
with the same compensation network.
Light Load Current Operation
At light load, the LT8391 typically still runs at its full
switching frequency in either continuous conduction
mode or discontinuous conduction mode because both the
buck and boost reverse current sense thresholds are set
to –4mV. The negative reverse current sense thresholds
allow a small amount of energy flowing from the output
to the input in every cycle, thereby preventing the pulse-
skip frequency from going below 100Hz, which causes
the LED string to flicker.
In the buck region, switch B is turned off whenever the
buck reverse current threshold is triggered during (B+D)
phase. In the boost region, switch D is turned off whenever
the boost reverse current threshold is triggered during
(A+D) phase. In the buck-boost region, switch D is turned
off whenever the boost reverse current threshold is trig-
gered during (A+D) phase, and both switches B and D are
turned off whenever the buck reverse current threshold is
triggered during (B+D) phase.
However, when a smaller value inductor is used and the
inductor current ripple is bigger, the LT8391 may run in
pulse-skip mode, where the switches are held off for mul-
tiple cycles (i.e., skipping pulses) to maintain the regulation.
Internal Charge Path
Each of the two top MOSFET drivers is biased from its
floating bootstrap capacitor, which is normally recharged
by INTVCC through the integrated bootstrap diode D1 or
D2 when the top MOSFET is turned off. When the LT8391
operates exclusively in the buck or boost regions, one
of the top MOSFETs is constantly on. An internal charge
path, from VOUT and BST2 to BST1 or from VIN and BST1
to BST2, charges the bootstrap capacitor to 4.6V so that
the top MOSFET can be kept on.
LT8391
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Shutdown and Power-On-Reset
The LT8391 enters shutdown mode and drains less than
2µA quiescent current when the EN/UVLO pin is below its
shutdown threshold (0.3V minimum). Once the EN/UVLO
pin is above its shutdown threshold (1V maximum), the
LT8391 wakes up startup circuitry, generates bandgap
reference, and powers up the internal INTVCC LDO. The
INTVCC LDO supplies the internal control circuitry and
gate drivers. Now the LT8391 enters undervoltage lockout
(UVLO) mode with a hysteresis current (2.5µA typical)
pulled into the EN/UVLO pin. When the INTVCC pin is
charged above its rising UVLO threshold (3.78V typi-
cal), the EN/UVLO pin passes its rising enable threshold
(1.227V typical), and the junction temperature is less than
its thermal shutdown (165°C typical), the LT8391 enters
enable mode, in which the EN/UVLO hysteresis current is
turned off and the voltage reference VREF is being charged
up from ground. From the time of entering enable mode to
the time of VREF passing its rising UVLO threshold (1.89V
typical), the LT8391 is going through a power-on-reset
(POR), waking up the entire internal control circuitry and
settling to the right initial conditions. After the POR, the
LT8391 is ready and waiting for the signals on the CTRL1,
CTRL2, and PWM pins to start switching.
Start-Up and Fault Protection
Figure 8 shows the start-up and fault sequence for the
LT8391. During the POR state, the SS pin is hard pulled
down with a 100Ω to ground. In a pre-biased condition,
the SS pin has to be pulled below 0.2V to enter the INIT
state, where the LT8391 wait 10µs so that the SS pin
can be fully discharged to ground. After the 10µs, the
LT8391 enters the UP/PRE state when the PWMON signal
goes high. The PWMON high signal happens when both
the CTRL1 and CTRL2 pins are above their rising dim-off
thresholds (0.228V typical) and the external or internal
PWM dimming is on.
During the UP/PRE state, the SS pin is charged up by a
12.5µA pull-up current while the switching is disabled
and the PMWTG is turned off. Once the SS pin is charged
above 0.25V, the LT8391 enters the UP/TRY state, where
the PMWTG is turned on first while the switching is still
disabled. This is to check whether the voltage on the out-
put capacitor is not too high for the LED string before any
switching energy delivery. In the case of a higher voltage
output capacitor connected to a lower voltage LED string,
the excessive current flowing through the LED string and
current sense resistor triggers the ISP/ISN over current
(ISOC) signal and resets the LT8391 back into the POR
state. So the LT8391 will hiccup with SS pin between 0V
and 0.25V and go around the POR, INIT, UP/PRE, and UP/
TRY states to slowly discharge the higher voltage output
capacitor until its voltage gets closer to the lower voltage
LED string. After 10µs in the UP/TRY state without trigger-
ing the ISOC signal, the LT8391 enters the UP/RUN state.
Figure 8. Start-Up and Fault Sequence
INIT
SS < 0.2V • SS HARD PULL DOWN
• SWITCHING DISABLED
• PWMTG TURNED OFF
• NO OPEN/SHORT DETECTION
WAIT 10µs AND
PWMON = HI
WAIT 10µs
POR = HI OR
ISOC = HI
OPEN LED OR
SHORT LED
8391 TA08
SS < 0.2V AND
PWMON = HI
SS > 0.25V
SS > 1.75V
SS < 1.7V
UP/PRE
• SS 12.5µA PULL UP
• SWITCHING DISABLED
• PWMTG TURNED OFF
• NO OPEN/SHORT DETECTION
OK/RUN
• SS 12.5µA PULL UP
• SWITCHING ENABLED
• PWMTG TURNED ON
• OPEN/SHORT DETECTION
FAULT/RUN
• SS 1.25µA PULL DOWN
• SWITCHING ENABLED
• PWMTG TURNED ON
• OPEN/SHORT DETECTION
POR
• SS HARD PULL DOWN
• SWITCHING DISABLED
• PWMTG TURNED OFF
• NO OPEN/SHORT DETECTION
UP/TRY
• SS 12.5µA PULL UP
• SWITCHING DISABLED
• PWMTG TURNED ON
• NO OPEN/SHORT DETECTION
UP/RUN
• SS 12.5µA PULL UP
• SWITCHING ENABLED
• PWMTG TURNED ON
• NO OPEN/SHORT DETECTION
DOWN/STOP
• SS 1.25µA PULL DOWN
• SWITCHING DISABLED
• PWMTG TURNED ON
• NO OPEN/SHORT DETECTION
OPERATION
LT8391
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OPERATION
During the UP/RUN state, the switching is enabled and
the start-up of the output voltage VOUT is controlled by
the voltage on the SS pin. When the SS pin voltage is less
than 1V, the LT8391 regulates the FB pin voltage to the
SS pin voltage instead of the 1V reference. This allows the
SS pin to be used to program soft-start by connecting an
external capacitor from the SS pin to GND. The internal
12.5µA pull-up current charges up the capacitor, creating
a voltage ramp on the SS pin. As the SS pin voltage rises
linearly from 0.25V to 1V (and beyond), the output voltage
VOUT rises smoothly to its final LED string voltage.
Once the SS pin is charged above 1.75V, the LT8391
enters the OK/RUN state, where the LED fault (both open
LED and short LED) detection is activated. The open LED
means that VFB > 0.95V and V(ISP-ISN) < 10mV, and the
short LED means that VFB < 0.25V. Both the open LED and
short LED faults are combined to the FAULT pin. When
either fault happens, the LT8391 enters the FAULT/RUN
state, where a 1.25µA pull-down current slowly discharges
the SS pin with the other conditions the same as the OK/
RUN state. Once the SS pin is discharged below 1.7V, the
LT8391 enters the DOWN/STOP state, where the switching
is disabled and the LED fault detection is deactivated with
the previous fault latched. Once the SS pin is discharged
below 0.2V and the PWMON signal is still high, the LT8391
goes back to the UP/RUN state.
In an open or short LED condition, the LT8391 can be set
to hiccup, latch-off, or keep-running fault protection mode
with a resistor between the SS and VREF pins. Without any
resistor, the LT8391 will hiccup with SS pin between 0.2V
and 1.75V and go around the UP/RUN, OK/RUN, FAULT/
RUN, and DOWN/STOP states until the fault condition is
cleared. With a 499k resistor, the LT8391 will latch off until
the EN/UVLO is toggled. With a 100k resistor, the LT8391
will keep running regardless of the fault.
APPLICATIONS INFORMATION
The front page shows a typical LT8391 application circuit.
This Applications Information section serves as a guideline
of selecting external components for typical applications.
The examples and equations in this section assume
continuous conduction mode unless otherwise specified.
Switching Frequency Selection
The LT8391 uses a constant frequency control scheme
between 150kHz and 650kHz. Selection of the switching
frequency is a tradeoff between efficiency and component
size. Low frequency operation improves efficiency by
reducing MOSFET switching losses, but requires larger
inductor and capacitor values. For high power applica-
tions, consider operating at lower frequencies to minimize
MOSFET heating from switching losses. For low power
applications, consider operating at higher frequencies to
minimize the total solution size.
In addition, the specific application also plays an important
role in switching frequency selection. In a noise-sensitive
system, the switching frequency is usually selected to keep
the switching noise out of a sensitive frequency band.
Switching Frequency Setting
The switching frequency of the LT8391 can be set by the
internal oscillator. With the SYNC/SPRD pin pulled to
ground, the switching frequency is set by a resistor from
the RT pin to ground. Table 1 shows RT resistor values
for common switching frequencies.
Table 1. Switching Frequency vs RT Value (1% Resistor)
fosc (kHz) RT (k)
150 309
200 226
300 140
400 100
500 75
600 59
650 51.1
Spread Spectrum Frequency Modulation
Switching regulators can be particularly troublesome for
applications where electromagnetic interference (EMI) is
a concern. To improve the EMI performance, the LT8391
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implements a triangle spread spectrum frequency modu-
lation scheme. With the SYNC/SPRD pin tied to INTVCC,
the LT8391 starts to spread its switching frequency ±15%
around the internal oscillator frequency. Figures 9 and 10
show the noise spectrum comparison of the front page
application between spread spectrum enabled and disabled.
APPLICATIONS INFORMATION
Figure 9. Conducted Average EMI Comparison
Figure 10. Conducted Peak EMI Comparison
smaller inductor and capacitor values. The inductor value
has a direct effect on ripple current. The highest current
ripple ∆IL% happens in the buck region at VIN(MAX), and the
lowest current ripple ∆IL% happens in the boost region at
VIN(MIN). For any given ripple allowance set by customers,
the minimum inductance can be calculated as:
LBUCK >
V
OUT
•(V
IN(MAX)
−V
OUT
)
f•ILED(MAX)•ΔIL%•VIN(MAX)
LBOOST >VIN(MIN)
2
•(VOUT −VIN(MIN))
f•ILED(MAX)•ΔIL%•VOUT2
where:
f is switching frequency
∆IL% is allowable inductor current ripple
VIN(MIN) is minimum input voltage
VIN(MAX) is maximum input voltage
VOUT is output voltage
ILED(MAX) is maximum LED current
Slope compensation provides stability in constant fre-
quency current mode control by preventing subharmonic
oscillations at certain duty cycles. The minimum inductance
required for stability can be calculated as:
L>
10•V
OUT
•R
SENSE
f
For high efficiency, choose an inductor with low core
loss, such as ferrite. Also, the inductor should have low
DC resistance to reduce the I2R losses, and must be able
to handle the peak inductor current without saturating. To
minimize radiated noise, use a shielded inductor.
RSENSE Selection and Maximum Output Current
RSENSE is chosen based on the required output current.
The duty cycle independent maximum current sense
thresholds (50mV in peak-buck and 50mV in peak-boost)
set the maximum inductor peak current in buck region,
buck-boost region, and boost region.
FREQUENCY (kHz)
80
70
60
50
40
EMI (dBµV)
30
20
10
0
150 2000
8391 F09
SPREAD ON
SPREAD OFF
CISPR25
CONDUCTED EMI
AVERAGE LIMIT
80
70
60
50
40
30
20
10
0
8391 F10
CISPR25
CONDUCTED EMI
PEAK LIMIT
SPREAD ON
SPREAD OFF
FREQUENCY (kHz)
EMI (dBµV)
150 2000
Frequency Synchronization
The LT8391 switching frequency can be synchronized to an
external clock using the SYNC/SPRD pin. Driving the SYNC/
SPRD with a 50% duty cycle waveform is always a good
choice, otherwise maintain the duty cycle between 10% and
90%. Due to the use of a phase-locked loop (PLL) inside,
there is no restriction between the synchronization frequency
and the internal oscillator frequency. The rising edge of the
synchronization clock represents the beginning of a switch-
ing cycle, turning on switches A and C, or switches A and D.
Inductor Selection
The switching frequency and inductor selection are inter-
related in that higher switching frequencies allow the use of
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APPLICATIONS INFORMATION
In boost region, the lowest maximum average load current
happens at VIN(MIN) and can be calculated as:
IOUT(MAX_BOOST) =50mV
RSENSE
−
ΔI
L(BOOST)
2
⎛
⎝
⎜⎞
⎠
⎟•
V
IN(MIN)
VOUT
where ∆IL(BOOST) is peak-to-peak inductor ripple current
in boost region and can be calculated as:
ΔIL(BOOST) =
V
IN(MIN)
•(V
OUT
−V
IN(MIN)
)
f•L•V
OUT
In buck region, the lowest maximum average load current
happens at VIN(MAX) and can be calculated as:
IOUT(MAX_BUCK) =50mV
RSENSE
−
ΔI
L(BUCK)
2
⎛
⎝
⎜⎞
⎠
⎟
where ∆IL(BUCK) is peak-to-peak inductor ripple current in
buck region and can be calculated as:
ΔIL(BUCK) =
V
OUT
•(V
IN(MAX)
−V
OUT
)
f•L•VIN(MAX)
The maximum current sense RSENSE in boost region is:
R
SENSE(BOOST)
=
2•50mV•VIN(MIN)
2•ILED(MAX)•VOUT +ΔIL(BOOST)•VIN(MIN)
The maximum current sense RSENSE in buck region is
RSENSE(BUCK) =
2•50mV
2•ILED(MAX)+ΔIL(BUCK)
The final RSENSE value should be lower than the calculated
RSENSE in both buck and boost regions. A 20% to 30%
margin is usually recommended.
Power MOSFET Selection
The LT8391 requires four external N-channel power MOS-
FETs, two for the top switches (switches A and D shown
in Figure 1) and two for the bottom switches (switches B
and C shown in Figure 1). Important parameters for the
power MOSFETs are the breakdown voltage VBR(DSS),
threshold voltage VGS(TH), on-resistance RDS(ON), reverse
transfer capacitance CRSS and maximum current IDS(MAX).
Since the gate drive voltage is set by the 5V INTVCC supply,
logic-level threshold MOSFETs must be used in LT8391
applications. Switching four MOSFETs at certain frequency,
the gate charge current from INTVCC can be estimated as:
IINTVCC = f • (QgA + QgB + QgC + QgD)
where:
f is the switching frequency
QgA, QgB, QgC, QgD are the total gate charges of MOSFETs
A, B, C, D
Make sure the total required INTVCC current not exceeding
the INTVCC current limit in the data sheet.
The LT8391 uses the VIN/VOUT ratio to transition between
modes and regions. Bigger IR drop in the power path
caused by improper MOSFET and inductor selection may
prevent the LT8391 from making smooth transitions. To
ensure smooth transitions between buck, buck-boost, and
boost modes of operation, choose low RDS(ON) MOSFETs
and low DCR inductors to satisfy:
ILED(MAX) ≤
0.025 • V
OUT
RA,B +RC,D +RSENSE +RL
where:
RA,B is the maximum RDS(ON) of MOSFETs A or B at
25°C
RC,D is the maximum RDS(ON) of MOSFETs C or D at
25°C
RL is the maximum DCR resistor of inductor at 25°C
The RDS(ON) increase at higher junction temperatures and
the process variation have been considered and included
in the calculation above.
In order to select the power MOSFETs, the power dis-
sipated by the device must be known. For switch A, the
maximum power dissipation happens in boost region, when
it remains on all the time. Its maximum power dissipation
at maximum output current is given by:
PA(BOOST) =ILED(MAX)•VOUT
VIN
⎛
⎝
⎜⎞
⎠
⎟
2
•ρT•RDS(ON)
where ρT is a normalization factor (unity at 25°C) ac-
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APPLICATIONS INFORMATION
counting for the significant variation in on-resistance with
temperature, typically 0.4%/°C as shown in Figure 11. For
a maximum junction temperature of 125°C, using a value
of ρT = 1.5 is reasonable.
Figure 11. Normalized RDS(ON) vs Temperature
For the same output voltage and current, typically switch
A has the highest power dissipation in buck region at
VIN(MAX) and switch C has the highest power dissipation
in boost region at VIN(MIN).
From a known power dissipated in the power MOSFET, its
junction temperature can be obtained using the following
formula:
TJ = TA + P • RTH(JA)
The junction-to-ambient thermal resistance RTH(JA) in-
cludes the junction-to-case thermal resistance RTH(JC)
and the case-to-ambient thermal resistance RTH(CA). This
value of TJ can then be compared to the original, assumed
value used in the iterative calculation process.
Optional Schottky Diode (DB, DD) Selection
The optional Schottky diodes DB (in parallel with switch B)
and DD (in parallel with switch D) conduct during the
dead time between the conduction of the power MOSFET
switches. They are intended to prevent the body diode of
synchronous switches B and D from turning on and storing
charge during the dead time. In particular, DB significantly
reduces reverse recovery current between switch B turn-
off and switch A turn-on, and DD significantly reduces
reverse recovery current between switch D turn-off and
switch C turn-on. They improve converter efficiency and
reduce switch voltage stress. In order for the diode to be
effective, the inductance between it and the synchronous
switch must be as small as possible, mandating that these
components be placed adjacently.
CIN and COUT Selection
Input and output capacitance is necessary to suppress
voltage ripple caused by discontinuous current moving
in and out the regulator. A parallel combination of capaci-
tors is typically used to achieve high capacitance and low
equivalent series resistance (ESR). Dry tantalum, special
polymer, aluminum electrolytic and ceramic capacitors are
all available in surface mount packages. Capacitors with
low ESR and high ripple current ratings, such as OS-CON
and POSCAP are also available.
Ceramic capacitors should be placed near the regulator
input and output to suppress high frequency switching
JUNCTION TEMPERATURE (°C)
–50
T
NORMALIZED ON-RESISTANCE (Ω)
1.0
1.5
150
8391 F11
0.5
0050 100
2.0
Switch B operates in buck region as the synchronous
rectifier. Its power dissipation at maximum output cur-
rent is given by:
P
B(BUCK) =
V
IN−
V
OUT
VIN
•ILED(MAX)2•ρT•RDS(ON)
Switch C operates in boost region as the control switch.
Its power dissipation at maximum current is given by:
PC(BOOST) =
(V
OUT−
V
IN
)
•
V
OUT
VIN2•ILED(MAX)2•ρT
•RDS(ON)+k•VOUT3•ILED(MAX)
V
IN
•CRSS•f
where CRSS is usually specified by the MOSFET manufac-
turers. The constant k, which accounts for the loss caused
by reverse recovery current, is inversely proportional to
the gate drive current and has an empirical value of 1.7.
For switch D, the maximum power dissipation happens in
boost region, when its duty cycle is higher than 50%. Its
maximum power dissipation at maximum output current
is given by:
P
D(BOOST) =
V
OUT
V
IN
•ILED(MAX)2•ρT•RDS(ON)
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APPLICATIONS INFORMATION
spikes. Ceramic capacitors, of at least 1µF, should also
be placed from VIN to GND and VOUT to GND as close to
the LT8391 pins as possible. Due to their excellent low
ESR characteristics, ceramic capacitors can significantly
reduce input ripple voltage and help reduce power loss in
the higher ESR bulk capacitors. X5R or X7R dielectrics are
preferred, as these materials retain their capacitance over
wide voltage and temperature ranges. Many ceramic ca-
pacitors, particularly 0805 or 0603 case sizes, have greatly
reduced capacitance at the desired operating voltage.
Input Capacitance CIN
Discontinuous input current is highest in buck region due
to the switch A toggling on and off. Make sure that the
CIN capacitor network has low enough ESR and is sized
to handle the maximum RMS current. In buck region, the
input RMS current is given by:
IRMS ≈ILED(MAX)•VOUT
VIN
•VIN
VOUT
−1
The formula has a maximum at VIN = 2VOUT, where IRMS
= ILED(MAX)/2. This simple worst-case condition is com-
monly used for design because even significant deviations
do not offer much relief.
Output Capacitance COUT
Discontinuous current shifts from the input to the output
in the boost region. Make sure that the COUT capacitor
network is capable of reducing the output voltage ripple.
The effects of ESR and the bulk capacitance must be
considered when choosing the right capacitor for a given
output ripple voltage. The maximum steady state ripple
due to charging and discharging the bulk capacitance is
given by:
ΔVCAP(BOOST) =
I
LED
•(V
OUT
−V
IN(MIN)
)
COUT•VOUT•f
ΔVCAP(BUCK) =
VOUT•(1−
V
OUT
VIN(MAX)
)
8•L•f2•C
OUT
The maximum steady ripple due to the voltage drop across
the ESR is given by:
ΔVESR(BOOST) =
V
OUT
•I
LED(MAX)
VIN(MIN)
•ESR
ΔVESR(BUCK) =
VOUT•(1−
V
OUT
VIN(MAX)
)
L•f
•ESR
INTVCC Regulator
An internal P-channel low dropout regulator produces
5V at the INTVCC pin from the VIN supply pin. The INTVCC
powers internal circuitry and gate drivers in the LT8391.
The INTVCC regulator can supply a peak current of 110mA
and must be bypassed to ground with a minimum of
4.7µF ceramic capacitor. Good local bypass is necessary
to supply the high transient current required by MOSFET
gate drivers.
Higher input voltage applications with large MOSFETs
being driven at higher switching frequencies may cause
the maximum junction temperature rating for the LT8391
to be exceeded. The system supply current is normally
dominated by the gate charge current. Additional external
loading of the INTVCC also needs to be taken into account
for the power dissipation calculation. The total LT8391
power dissipation in this case is VIN • IINTVCC, and overall
efficiency is lowered. The junction temperature can be
estimated by using the equation:
TJ = TA + PD • θJA
where θJA (in °C/W) is the package thermal resistance.
To prevent maximum junction temperature from being
exceeded, the input supply current must be checked op-
erating in continuous mode at maximum VIN.
Top Gate MOSFET Driver Supply (CBST1, CBST2)
The top MOSFET drivers, TG1 and TG2, are driven between
their respective SW and BST pin voltages. The boost
voltages are biased from floating bootstrap capacitors
CBST1 and CBST2, which are normally recharged through
internal bootstrap diodes D1 and D2 when the respective
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APPLICATIONS INFORMATION
top MOSFET is turned off. Both capacitors are charged
to the same voltage as the INTVCC voltage. The bootstrap
capacitors CBST1 and CBST2, need to store about 100 times
the gate charge required by the top switches A and D. In
most applications, a 0.1µF to 0.47µF, X5R or X7R dielectric
capacitor is adequate.
Programming VIN UVLO
A resistor divider from VIN to the EN/UVLO pin implements
VIN undervoltage lockout (UVLO). The EN/UVLO enable
falling threshold is set at 1.214V with 10mV hysteresis. In
addition, the EN/UVLO pin sinks 2.5µA when the voltage
on the pin is below 1.214V. This current provides user
programmable hysteresis based on the value of R1. The
programmable UVLO thresholds are:
VIN(UVLO+)=1.227 V•
R1
+
R2
R2
+2.5µA•R1
VIN(UVLO−)=1.214V•
R1
+
R2
R2
Figure 12 shows the implementation of external shut-down
control while still using the UVLO function. The NMOS
grounds the EN/UVLO pin when turned on, and puts the
LT8391 in shutdown with quiescent current less than 2µA.
Figure 12. VIN Undervoltage Lockout (UVLO)
LT8391
GND
EN/UVLO
R1
RUN/STOP
CONTROL
(OPTIONAL)
R2
VIN
8391 F12
Programming LED Current
The LED current is programmed by placing an appropriate
value current sense resistor, RLED, in series with the LED
string. The voltage drop across RLED is (Kelvin) sensed by
the ISP and ISN pins. The CTRL1 and CTRL2 pins should
be tied to a voltage higher than 1.35V to get the full-scale
100mV (typical) threshold across the sense resistor. Ei-
ther the CTRL1 or CTRL2 pin can be used to dim the LED
current to zero, although relative accuracy decreases with
the decreasing sense threshold. When either the CTRL1 or
CTRL2 pin voltage is less than 1.15V, the LED current is:
ILED =
Min(V
CTRL1
,V
CTRL2
)−250mV
10•R
LED
where Min(VCTRL1, VCTRL2) is the minimum value of CTRL1
and CTRL2 pin voltages. When Min(VCTRL1, VCTRL2) is
between 1.15V and 1.35V, the LED current varies with the
Min(VCTRL1, VCTRL2), but departs from the equation above
by an increasing amount as Min(VCTRL1, VCTRL2) increases.
Ultimately, when Min(VCTRL1, VCTRL2) > 1.35V, the LED
current no longer varies. The typical V(ISP-ISN) threshold
vs Min(VCTRL1, VCTRL2) is listed in Table 2.
Table 2. V(ISP-ISN) Threshold vs Min(VCTRL1, VCTRL2)
Min(VCTRL1, VCTRL2) (V) V(ISP-ISN) (mV)
1.15 90
1.20 94.5
1.25 98
1.30 99.5
1.35 100
When Min(VCTRL1, VCTRL2) is higher than 1.35V, the LED
current is regulated to:
ILED =
100mV
R
LED
The CTRL1/CTRL2 pin should not be left open (tie to VREF
if not used). The CTRL1/CTRL2 pin can also be used in
conjunction with a thermistor to provide overtemperature
protection for the LED load, or with a resistor divider to VIN
to reduce output power and switching current when VIN
is low. The presence of a time varying differential voltage
ripple signal across ISP and ISN at the switching frequency
is expected. The amplitude of this signal is increased by
higher LED load current, lower switching frequency, or
smaller value output filter capacitor. Some level of ripple
signal is acceptable, and the compensation capacitor on the
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APPLICATIONS INFORMATION
VC pin filters the signal so the average difference between
ISP and ISN is regulated to the user-programmed value.
The ripple voltage amplitude (peak-to-peak) in excess of
20mV should not cause mis-operation, but may lead to
noticeable offset between the average value and the user-
programmed value.
Dimming Control
There are two methods to control the LED current for dim-
ming using the LT8391. One method uses the CTRL1 or
CTRL2 pin to adjust the current regulated in the LEDs. A
second method uses the PWM pin to modulate the LED
current between zero and full current to achieve a precisely
programmed average current.
Compared to the analog dimming method, the PWM dim-
ming method offers much higher dimming ratio without
any color shift. To make PWM dimming more accurate, the
switch demand current is stored on the VC node when the
PWM signal is low. This feature minimizes recovery time
when the PWM signal goes high. To further improve the
recovery time, a high side PMOS PWM switch should be
used in the LED current path to prevent the output capaci-
tor from discharging during the PWM signal low phase.
The choice of switching frequency, inductor value, and
loop compensation affects the minimum PWM on time,
below which the LT8391 loses the LED current regulation.
For the same application, the LT8391 achieves the highest
PWM dimming ratio (up to 2000:1) in buck region, the
medium PWM dimming ratio (up to 1000:1) in buck-boost
region, and the lowest PWM dimming ratio (up to 400:1)
in boost region.
In either fixed frequency operation set by RT resistor or
spread spectrum frequency operation, the internal oscillator
is synchronized to the PWM signal rising edge, thereby
providing flicker-free PWM dimming performance. In
external frequency synchronization operation, both SYNC
and PWM signals must have synchronized rising edges to
achieve flicker-free PWM dimming performance.
The LT8391 provides both external PWM dimming and
internal PWM dimming. For external PWM dimming, choose
RP resistor less than 30k and apply external PWM clock
signal on the PWM pin. For internal PWM dimming, choose
RP resistor to one of the five resistor values in Table 3 and
apply analog DC voltage or a resistor divider from VREF
to the PWM pin. The RP resistor sets the internal PWM
dimming frequency, and the analog DC voltage on the
PWM pin from 1V to 2V sets the internal PWM dimming
duty ratio from 0% to 100% with a discrete 1/128 step
size in Figure 13. A 1µF ceramic capacitor on the PWM pin
is recommended to minimize the internal PWM dimming
duty ratio jitter caused by switching noise.
Table 3. Internal PWM Dimming Frequency vs RP Value (5%
Resistor)
RP (k) fSW fSW = 200kHz fSW = 400kHz fSW = 600kHz
≤ 30 External External External External
51 fSW/256 781Hz 1563Hz 2344Hz
82 fSW/512 391Hz 781Hz 1172Hz
130 fSW/1024 195Hz 391Hz 586Hz
200 fSW/2048 98Hz 195Hz 293Hz
300 fSW/4096 49Hz 98Hz 146Hz
Figure 13. Internal PWM Dimming Duty Ratio vs PWM Voltage
PWMTG DUTY RATIO (%)
ALWAYS
ON
ALWAYS
OFF
PWMTG DUTY
RATIO (%)
PWM (V)
3.0
8391 F13
2.52.01.51.00.50.0
0
50
100
High Side PMOS PWM Switch Selection
A high side PMOS PWM switch is recommended in most
LT8391 applications to maximize the PWM dimming
ratio and protect the LED string during fault conditions.
Compared to a low side NMOS PWM switch, the high side
PMOS PWM switch allows a single wire to the LED string
and ground return path through chassis. The high side
PMOS PWM switch is typically selected for drain-source
voltage VDS, gate-source threshold voltage VGS(TH), and
continuous drain current ID. For proper operations, VDS
rating should exceed the open LED regulation voltage set
by the FB pin, the absolute value of VGS(TH) should be less
than 3V, and ID rating should be above ILED(MAX).
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APPLICATIONS INFORMATION
Programming Output Voltage and Thresholds
The LT8391 has a voltage feedback pin FB that can be
used to program a constant-voltage output. The output
voltage can be set by selecting the values of R3 and R4
(Figure 14) according to the following equation:
VOUT =1.00V•
R3+R4
R4
Figure 14. Feedback Resistor Connection
LT8391
VOUT
R3
R4
8391 F14
FB
In addition, the FB pin also sets output overvoltage thresh-
old, open LED threshold, and short LED threshold. For an
LED driver application with small output capacitors, the
output voltage usually overshoots a lot during an open
LED event. Although the 1.00V FB regulation loop tries to
regulate the output, the loop is usually too slow to prevent
the output from overshooting. Once the FB pin hits its
overvoltage threshold 1.05V, the LT8391 stops switching
by turning off TG1, BG1, TG2, and BG2, and also turns off
PWMTG to disconnect the LED string for protection. The
output overvoltage threshold can be set as:
VOUT(OVP) =1.05V•
R3+R4
R4
Make sure the expected VFB during normal operation stays
between the short LED rising threshold 0.3V and the open
LED falling threshold 0.9V:
0.3V ≤VLED•
R4
R3+R4
≤0.9V
These equations set the maximum LED string voltage
with full open LED protection for the LT8391 to be 51V.
FAULT Pin
The LT8391 provides an open-drain status pin, FAULT,
which is pulled low during either open LED or short LED
conditions. The open LED condition happens when the FB
pin is above 0.95V and the voltage across V(ISP-ISN) is less
than 10mV. The short LED condition happens when the
FB pin is below 0.25V. The FAULT status is updated when
the SS pin is above 1.75V and the PWM signal is high.
Soft-Start and Fault Protection
As shown in Figure 8 and explained in the Operation
section, the SS pin can be used to program soft-start
by connecting an external capacitor from the SS pin to
ground. The internal 12.5µA pull-up current charges up
the capacitor, creating a voltage ramp on the SS pin. As
the SS pin voltage rises linearly from 0.25V to 1V (and
beyond), the output voltage rises smoothly and transitions
into LED current regulation. The soft-start range is defined
to be the voltage range from 0V to the FB voltage in LED
current regulation. The soft-start time can be calculated as:
tSS =VLED•R4
R3+R 4 •
C
SS
12.5µA
Make sure the CSS is at least five to ten times larger
than the compensation capacitor on the VC pin. A 0.1µF
ceramic capacitor is a good starting point.
The SS pin is also used as a fault timer. Once an open
LED or a short LED fault is detected, a 1.25µA pull-down
current source is activated. Using a single resistor from
the SS pin to the VREF pin, the LT8391 can be set to three
different fault protection modes: hiccup (no resistor),
latch-off (499k), and keep-running (100k).
With a 100k resistor in keep-running mode, the LT8391
continues switching normally, either regulating the pro-
grammed VOUT during open LED fault or regulating the
current during short LED fault. With a 499k resistor in
latch-off mode, the LT8391 stops switching until the EN/
UVLO pin is pulled low and high to restart. With no resistor
in hiccup mode, the LT8391 enters low duty cycle auto-retry
operation. The 1.25µA pull-down current discharges the
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SS pin to 0.2V and then 12.5µA pull-up current charges
the SS pin up. If the fault condition has not been removed
when the SS pin reaches 1.75V, the 1.25µA pull-down
current turns on again, initiating a new hiccup cycle. This
will continue until the fault is removed.
Loop Compensation
The LT8391 uses an internal transconductance error am-
plifier, the output of which, VC, compensates the control
loop. The external inductor, output capacitor, and the
compensation resistor and capacitor determine the loop
stability.
The inductor and output capacitor are chosen based on
performance, size and cost. The compensation resistor
and capacitor on the VC pin are set to optimize control
loop response and stability. For a typical LED application,
a 10nF compensation capacitor on the VC pin is adequate,
and a series resistor should always be used to increase
the slew rate on the VC pin to maintain tighter regulation
of LED current during fast transients on the input supply
of the converter.
Efficiency Considerations
The power efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Although all dissipative
elements in circuits produce losses, four main sources
account for most of the losses in LT8391 circuits:
1. DC I2R losses. These arise from the resistances of
the MOSFETs, sensing resistor, inductor and PC board
traces and cause the efficiency to drop at high output
currents.
2. Transition loss. This loss arises from the brief amount
of time switch A or switch C spends in the saturated
region during switch node transitions. It depends upon
the input voltage, load current, driver strength and
MOSFET capacitance, among other factors.
3. INTVCC current. This is the sum of the MOSFET driver
and control currents.
4. CIN and COUT loss. The input capacitor has the dif-
ficult job of filtering the large RMS input current to the
regulator in buck region. The output capacitor has the
difficult job of filtering the large RMS output current in
boost region. Both CIN and COUT are required to have
low ESR to minimize the AC I2R loss and sufficient
capacitance to prevent the RMS current from causing
additional upstream losses in fuses or batteries.
5. Other losses. Schottky diode DB and DD are respon-
sible for conduction losses during dead time and light
load conduction periods. Inductor core loss occurs
predominately at light loads. Switch A causes reverse
recovery current loss in buck region, and switch C
causes reverse recovery current loss in boost region.
When making adjustments to improve efficiency, the input
current is the best indicator of changes in efficiency. If you
make a change and the input current decreases, then the
efficiency has increased. If there is no change in the input
current, then there is no change in efficiency.
PC Board Layout Checklist
The basic PC board layout requires a dedicated ground
plane layer. Also, for high current, a multilayer board
provides heat sinking for power components.
n The ground plane layer should not have any traces
and it should be as close as possible to the layer with
power MOSFETs.
n Place CIN, switch A, switch B and DB in one com-
pact area. Place COUT, switch C, switch D and DD in
one compact area.
n Use immediate vias to connect the components to
the ground plane. Use several large vias for each
power component.
n Use planes for VIN and VOUT to maintain good voltage
filtering and to keep power losses low.
LT8391
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For more information www.linear.com/LT8391
n Flood all unused areas on all layers with copper.
Flooding with copper will reduce the temperature rise
of power components. Connect the copper areas to
any DC net (VIN or GND).
n Separate the signal and power grounds. All small-
signal components should return to the exposed
GND pad from the bottom, which is then tied to the
power GND close to the sources of switch B and
switch C.
n Place switch A and switch C as close to the control-
ler as possible, keeping the power GND, BG and SW
traces short. For low Qg MOSFET’s a 5.1Ω gate resis-
tor is required for switch C.
n Keep the high dV/dT SW1, SW2, BST1, BST2, TG1
and TG2 nodes away from sensitive small-signal
nodes.
n The path formed by switch A, switch B, DB and the
CIN capacitor should have short leads and PCB trace
lengths. The path formed by switch C, switch D, DD
and the COUT capacitor also should have short leads
and PCB trace lengths.
n The output capacitor (–) terminals should be con-
nected as close as possible to the (–) terminals of the
input capacitor.
APPLICATIONS INFORMATION
n Connect the top driver bootstrap capacitor CBST1
closely to the BST1 and SW1 pins. Connect the top
driver bootstrap capacitor CBST2 closely to the BST2
and SW2 pins.
n Connect the input capacitors CIN and output capaci-
tors COUT closely to the power MOSFETs. These
capacitors carry the MOSFET AC current.
n Route LSP and LSN traces together with minimum
PCB trace spacing. Avoid sense lines pass through
noisy areas, such as switch nodes. The filter capaci-
tor between LSP and LSN should be as close as pos-
sible to the IC. Ensure accurate current sensing with
Kelvin connections at the RSENSE resistor.
n Connect the VC pin compensation network close
to the IC, between VC and the signal ground. The
capacitor helps to filter the effects of PCB noise and
output voltage ripple voltage from the compensation
loop.
n Connect the INTVCC bypass capacitor, CINTVCC, close
to the IC, between the INTVCC and the power ground.
This capacitor carries the MOSFET drivers’ current
peaks.
LT8391
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For more information www.linear.com/LT8391
TYPICAL APPLICATIONS
98% Efficient 50W (25V 2A) Buck-Boost LED Driver
+
EN/UVLO
CTRL2
CTRL1
PWM
SYNC/SPRD
SS RT
PWMTG
ISN
ISP
FB
TG2
BST2
BG2
GND
BG1
LSN
LSP
SW1
BST1
LT8391
499k
221k
33µF
63V
1µF
4.7µF
0.47µF
100k
100k
100k
OFF
EXT
SYNC
NO
SPREAD
INTVCC
SPREAD
ON
0.1µF
1µF
8391 TA02a
5.1Ω
0.05Ω
M5
25V
2A
LED
LED+
0.004Ω
M2
0.1µF
M1
M3
M4 1M
34.8k
0.1µF
4.7µF
100V
×210µF
50V
×2
(OPTIONAL)
D1
2.2k
10nF
100k
400kHz
200k
195Hz
ANALOG DIM
EXT PWM
TG1
SW2
VOUT
FAULT
VIN
INTVCC
INTVCC
V
IN
6V TO 55V
VREF
VREF
VREF
RP
VC
L1
10µH
L1: COOPER HC9-100R 10µH
M1, M2: INFINEON BSC100N06LS3
M3, M4: INFINEON BSC093N04LS
M5: VISHAY Si7611DN
D1: NXP PMEG6010CEJ
5µs/DIV
VPWM
5V/DIV
IL
5A/DIV
ILED
2A/DIV
8391 TA02b 5µs/DIV
VPWM
5V/DIV
IL
5A/DIV
ILED
2A/DIV
8391 TA02c 5µs/DIV
VPWM
5V/DIV
IL
5A/DIV
ILED
2A/DIV
8391 TA02d
10µs/DIV
VPWM
1V/DIV
VIN = 24V
IL
5A/DIV
ILED
2A/DIV
8391 TA02e 2ms/DIV
VPWM
1V/DIV
IL
5A/DIV
ILED
2A/DIV
8391 TA02f
VIN = 24V
2ms/DIV
VPWM
1V/DIV
IL
5A/DIV
ILED
2A/DIV
8391 TA02g
VIN = 24V
100Hz 1000:1 External PWM
Dimming (VIN = 36V)
195Hz 128:1 Internal PWM
Dimming (VPWM = 1V)
100Hz 500:1 External PWM
Dimming (VIN = 24V)
195Hz 20% Internal PWM
Dimming (VPWM = 1.2V)
100Hz 250:1 External PWM
Dimming (VIN = 12V)
195Hz 80% Internal PWM
Dimming (VPWM = 1.8V)
LT8391
29
8391fa
For more information www.linear.com/LT8391
TYPICAL APPLICATIONS
95% Efficient 12W (12V 1A) Buck-Boost LED Driver with Dual Package MOSFETs
Efficiency vs VIN
+
EN/UVLO
CTRL2
CTRL1
PWM
SYNC/SPRD
SS RT
PWMTG
ISN
ISP
FB
BST2
TG2
BG2
GND
BG1
LSN
LSP
SW1
TG1
LT8391
332k
121k
22µF
63V
1µF
4.7µF
0.47µF
100k
100k
100k
OFF
EXT
SYNC
NO
SPREAD
INTVCC
SPREAD
ON
0.1µF
1µF
8391 TA03a
5.1Ω
0.1Ω
M3
12V
1A
LED
LED+
0.015Ω
M1
0.1µF
M2
1M
75k
0.1µF
2.2µF
100V
×2
10µF
25V
2.0k
4.7nF
100k
400kHz
200k
195Hz
ANALOG DIM
EXT PWM
BST1
SW2
VOUT
FAULT
VIN
INTVCC
INTVCC
V
IN
5V TO 56V
VREF
VREF
VREF
RP
VC
L1
10µH
L1: WURTH 74437336100
M1: INFINEON IPG20N06S4L-11
M2: VISHAY SiZ342DT
M3: VISHAY Si2307DS
D1: NXP PMEG6010CEJ
(OPTIONAL)
D1
INPUT VOLTAGE (V)
0
80
EFFICIENCY (%)
98
96
94
92
90
88
86
84
82
100
20 30 40 50 60
8391 TA03b
10
LT8391
30
8391fa
For more information www.linear.com/LT8391
TYPICAL APPLICATIONS
93% Efficient 84W Buck-Boost LED Driver from 24VAC
EN/UVLO
CTRL2
CTRL1
PWM
M7
M8
24VAC
60Hz
M6
M5
IN1
IN2
OUTP
LT4320
OUTN
BG2 BG1
TG2 TG1
ISN
PWMTG
ISP
FB
TG2
BST2
BG2
GNDSS SYNC/SPRDVCRTRP
BG1
LSN
LSP
SW1
BST1
LT8391
TG1
SW2
VOUT
FAULT
VIN
INTVCC
INTVCC
VREF
1M
M1
M2 M3
5.1Ω
M4
L1 7.8µH
0.1µF 0.1µF
1µF
50V
75.0k
500kHz
3k
10nF
100k
100k
0.1µF
24VRMS PULSATING 120Hz PVIN
37.4k
68.1k
30.1k
4.7µF
10V
0.47µF
1µF
50V
CIN
1µF
50V
COUT
4.7µF
50V
×4
RLED
0.015Ω
RSENSE
0.004Ω
1M
36.5k
15V–25V
0A–6A
PULSATING
LEDs
120Hz
L1: WURTH 744325780 7.8µH
M1, M2: INFINEON BSC067N06LS3
M3, M4: INFINEON BSC032N04LS
M5–M8: INFINEON BSZ100N06LS3
8391 TA04a
5ms/DIV
IIN
2A/DIV
VIN
20V/DIV
8391 TA04b 5ms/DIV
VLED
5V/DIV
ILED
2A/DIV
8391 TA04c
98% Power Factor from 60Hz
24VAC Input 84W 120Hz AC LED Output
LT8391
31
8391fa
For more information www.linear.com/LT8391
TYPICAL APPLICATIONS
97% Efficient 8A Buck-Boost SLA Battery Charger
Efficiency vs VIN Charge Profile
+
33µF
100V
1µF
VIN
8V TO 60V
EN/UVLO
0.1µF 22nF
8391 TA05a
1µF
5.1Ω 10Ω
2.2µF 10Ω 0.012Ω
BATT+
7.8A
VCHRG = 14.6V
VFLOAT = 13.6V
CTRL1
CTRL2
RP
GND
RT
PWM
ISN
ISP
FB
TG2
BG2
BST2
SS
SYNC/SPRD VC
BG1
LSN
LSP
SW1
BST1
LT8391
TG1
SW2
VOUT
FAULT C/10
C/10
VIN
INTVCC
VREF
VREF
VREF
4.7µF
10k
10k
10k
100k
15k
CURRENT
ADJUST
374k
68.1k INTVCC
EXT
SYNC
NO
SPREAD
INTVCC
SPREAD
174k
250kHz
0.47µF
0.002Ω
M1
M2
M4
M3
M5
0.1µF 0.1µF
L1
4.2µH
100k
7.87k 100k
4.7µF
100V
×2
4.7µF
50V
×4
100µF
25V
×4
+
L1: WURTH 7443630420
M1, M2: INFINEON BSC100N06LS
M3, M4: INFINEON BSZ014NE2LS5IF
M5: NXP 2N7002
INPUT VOLTAGE (V)
8
80
EFFICIENCY (%)
98
96
94
92
90
88
86
84
82
100
20 24 2812 16
8391 TA05b
TIME (MINUTES)
0
11.8
BATT VOLTAGE (V)
BATT CURRENT (A)
14.6
14.2
13.8
13.4
13.0
12.6
12.2
15.0
0
7
5
4
6
3
2
1
8
150 200 25050 100
8391 TA05c
LT8391
32
8391fa
For more information www.linear.com/LT8391
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/product/LT8391#packaging for the most recent package drawings.
FE28 (EB) TSSOP REV K 0913
0.09 – 0.20
(.0035 – .0079)
0° – 8°
0.25
REF
0.50 – 0.75
(.020 – .030)
4.30 – 4.50*
(.169 – .177)
1 3 4 5678 9 10 11 12 13 14
192022 21 151618 17
9.60 – 9.80*
(.378 – .386)
4.75
(.187)
2.74
(.108)
28 27 26 2524 23
1.20
(.047)
MAX
0.05 – 0.15
(.002 – .006)
0.65
(.0256)
BSC 0.195 – 0.30
(.0077 – .0118)
TYP
2
RECOMMENDED SOLDER PAD LAYOUT
EXPOSED
PAD HEAT SINK
ON BOTTOM OF
PACKAGE
0.45 ±0.05
0.65 BSC
4.50 ±0.10
6.60
±0.10
1.05 ±0.10
4.75
(.187)
2.74
(.108)
MILLIMETERS
(INCHES) *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
SEE NOTE 4
4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
6.40
(.252)
BSC
FE Package
28-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663 Rev K)
Exposed Pad Variation EB
UFD Package
28-Lead Plastic QFN (4mm × 5mm)
(Reference LTC DWG # 05-08-1712 Rev C)
4.00 ±0.10
(2 SIDES)
2.50 REF
5.00 ±0.10
(2 SIDES)
NOTE:
1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGHD-3).
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
PIN 1
TOP MARK
(NOTE 6)
0.40 ±
0.10
27 28
1
2
BOTTOM VIEW—EXPOSED PAD
3.50 REF
0.75 ±0.05 R = 0.115
TYP
R = 0.05
TYP
PIN 1 NOTCH
R = 0.20 OR 0.35
× 45° CHAMFER
0.25 ±0.05
0.50 BSC
0.200 REF
0.00 – 0.05
(UFD28) QFN 0816 REV C
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
0.70 ±0.05
0.25 ±0.05
0.50 BSC
2.50 REF
3.50 REF
4.10 ±0.05
5.50 ±0.05
2.65 ±0.05
3.10 ±0.05
4.50
±0.05
PACKAGE
OUTLINE
2.65 ±0.10
3.65 ±0.10
3.65 ±0.05
LT8391
33
8391fa
For more information www.linear.com/LT8391
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER
A 12/17 Minor grammatical edits.
Added H-Grade version.
Clarified INTVCC Load and Line Regulation parameters.
Clarified VREF Load and Line Regulation parameters.
Clarified FB Load and Line Regulation parameters.
Clarified Highest and Lowest Spread Spectrum Above/Below Oscillator Frequency parameters.
Clarified Region Transition specifications.
Clarified TG1 Minimum/Maximum Duty Cycle Region.
Clarified BG2 Minimum/Maximum Duty Cycle Region.
Added H-Grade to Note 2.
Clarified EN/ULVO paragraph.
Clarified Block Diagram.
Clarified Shutdown and Power-On Reset and Start-Up Fault Protection sections.
Clarified Inductor Selection paragraph.
Clarified Power MOSFET Selection section.
Clarified Typical Application.
Clarified Typical Application.
Clarified Typical Application
1
2
3
3
4
5
6
6
6
6
11
13
17
19
20
28
29
34
LT8391
34
8391fa
For more information www.linear.com/LT8391
ANALOG DEVICES, INC. 2016
LT 1217 REV A • PRINTED IN USA
www.linear.com/LT8391
RELATED PARTS
TYPICAL APPLICATION
PART NUMBER DESCRIPTION COMMENTS
LT3791 60V, 700kHz 4-Switch Synchronous
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VIN: 4.7V to 60V, VOUT: 0V to 60V, ±6% Current Accuracy, TSSOP-38
LT3743 36V, 1MHz Synchronous Buck LED
Controller with Three-State Control
VIN: 6V to 36V, VOUT: 0V to VIN –2V, ±6% Current Accuracy, Fast Three-State Current
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LT3744 36V, 1MHz Synchronous Buck LED
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VIN: 3.3V to 36V, VOUT: 0V to 36V, ±2% Current Accuracy, Fast Four-State Current Control,
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VIN: 6V to 60V, VOUT: 0V to VIN –2V, ±6% Current Accuracy, TSSOP-28
LT3755/LT3755-1/
LT3755-2
40VIN, 75VOUT, 1MHz Non-Synchronous
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VIN: 4.5V to 40V, VOUT: VIN to 75V, ±4% Current Accuracy, 3mm × 3mm QFN-16 and
MSE-16
LT3756/LT3756-1/
LT3756-2
100V, 1MHz Non-Synchronous Boost
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VIN: 6V to 100V, VOUT: VIN to 100V, ±4% Current Accuracy, 3mm × 3mm QFN-16 and
MSE-16
LT3761 60VIN, 80VOUT, 1MHz Non-Synchronous
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Generator
VIN: 4.5V to 60V, VOUT: VIN to 80V, ±3% Current Accuracy, External and Internal PWM
dimming, MSE-16
LT3795 110V, 1MHz Non-Synchronous Boost
LED Controller with Spread Spectrum
Frequency Modulation
VIN: 4.5V to 110V, VOUT: VIN to 110V, ±3% Current Accuracy, Internal Spread Spectrum,
TSSOP-28
LT3797 Triple, 40VIN, 100VOUT, 1MHz Non-
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VIN: 2.5V to 40V (60V Ride-Through), VOUT: VIN to 100V, ±3% Current Accuracy,
7mm × 8mm QFN-52(47)
98% Efficient 100W (33.3V 3A) Buck-Boost LED Driver
+
EN/UVLO
CTRL2
CTRL1
PWM
SYNC/SPRD
SS RT
PWMTG
ISN
ISP
FB
TG2
BST2
BG2
GND
BG1
LSN
LSP
SW1
BST1
LT8391
499k
52.3k
33µF
63V
1µF
4.7µF
0.47µF
100k
100k
100k
OFF
EXT
SYNC
NO
SPREAD
INTVCC
SPREAD
ON
0.1µF
1µF
8391 TA06
5.1Ω
0.033Ω
M5
33.3V
3A
LED
LED+
0.004Ω
M2
0.1µF
M1
M3
M4 1M
26.7k
0.1µF
4.7µF
100V
×210µF
50V
×2
2.2k
10nF
140k
300kHz
200k
195Hz
ANALOG DIM
EXT PWM
TG1
SW2
VOUT
FAULT
VIN
INTVCC
INTVCC
V
IN
15V TO 58V
VREF
VREF
VREF
RP
VC
L1
10µH
L1: COOPER HC9-100R 10µH
M1, M2: INFINEON BSC100N06LS3
M3, M4: INFINEON BSC093N04LS
M5: VISHAY Si7611DN
D1: NXP PMEG6010CEJ
(OPTIONAL)
D1
