NJUG3S5S5 Series SERIAL [70 REAL TIME CLOCK Mi GENERAL DESCRIPTION The NJU6355 series is a serial 1/0 Real Time Clock suitable for 4 bits microprocessor. It contains quartz crystal oscillator, counter, shift register, voltage regulator, voltage detector and in- terface controller. The NJU6355 required only 4-port of microprocessor for data transfer, and the microprocessor can receive the data at any time when the microprocessor requires. The operating voltage is as wide as 2.0V to 5.5V, consequently, the NJUG355 can count accurate time data even if the back up period. Furthermore, the long time back up is available as the current consumption during the back up period is less than 3A. WH PACKAGE OUTLINE K WJU63S5X0 WSOGS5SXM i PIN CONFIGURATION Lodi 8 [9 Vuo xT 2 710 DATA XT C3 60 CLK ed 4 spice Wi FEATURES @ Operating Voltage > 2.0 ~ 5.5 @ Low operating current :3 wA (Typ.) at 3.0V 4 wA (Typ.) at 5.0V @ BCD Counts of Seconds, Minutes, Hours, Date, Days of Week, Month and Year @ Required only 4-port (DATA,CLK, CE and 1/0) @ Low Battery Detector (Low voltage alarm signal output) @ Automatic Leap Year Compensation @ Package Outline -~ DIP 8/DMP 8 @ C-MS Technology @ Line uP VERSION OUTPUT DATA OSC. GAPACITOR F Seconds, Minutes, Hours, Days of Week H | Seconds, Minutes, Hours, Days of Week 6355 E |Seconds, Minutes, Hours, Days of Week, Date, Month, Year | C,/Ca on chip G | Seconds, Minutes, Hours, Days of Week, Date, Month, Year Ca on chip C./Ca on chip Ca on chip 11- 1 _ New Japan Radio Co, Lid.NJIUGS3SS5 5 Series Wi BLOCK DIAGRAN Xt e} Q66) I lator/ Timer Counter XT 1 Divider Sec. | Min. | Hr. | Date| Day [Mont Year P0000 [ Shift Register Te LO Control ler/ Low Vol tage Clock Counter C CLK Detector <] ; CE I TERMINAL DESCRIPTION NO. | SYMBOL FoU iN FJ {| g iN Input/Output Select Terminal for DATA Terminal 1 1/0 "H": Input, "L: Output During the CE terminal is "L, the Data terminal is high impedance. 2 XT Quartz Crystal Connecting Terminal (f=32.768kHz) 3 XT Refer to the Line-Up Table for internal Cg, Cd value. Chip Enable Input Terminal (with pull-down resistance) 5 CE "H" > Data Input/Output is available "L > Data terminal is high impedance When the CE signal is which raising edge or falling edge, the CLK signal should be fixed to "L. 6 CLK Clock Input Terminal The Data Input/Output is synchronized by this clock. When the CE terminal is "L the data terminal is high impedance. Serial Timer Data {nput/Output 1/0} CE DATA Terminal H H Input 7 DATA L H Output H L High-Impedance L L High- Impedance 8 Vpp Power Supply (+5V) Vee GND New Japan Radio Co,Lid }1-2NJU6355 series MM FUNCTIONAL DESCRIPTION 1. Timer Data structure The NJU6355 using BCD code which consisting of 4 bits per 1 digit. The calendar function including the last date of each month and the leap year calculation is executed automatically. The unused bit for the timer data is "0". < Timer Data Bit Map > MSB LSBs Range Second 0 | 8% | Sh | S4793 | 82 | St 0 - 59 Minute 0} mG | m5 | m4 fd | m2 | ot 0 - 59 Hour 0 0 | Ho | H4 | Days of Week Wi o = nN Date 0 0; DS | D4 | D8 | D2 | D1 50 n0 H2 | Hi | HO 0 - 23 WO DO MO Month 0 0 0 | M4 7 MB] M2 | Mt Year YT | Ye | Y5 | 4 | Y3 | 2 | 1 | YO 0 - 99 2. Timer Data Reading When the 1/0 terminal is "L and the CE terminal is "H", timer data can read out. The output is LSB first and the output data strings (depending on the version) is shown below. The timer data is transferred from timer counter to shift register at rising edge of the chip enable on the CE terminal, and output the LSB of the timer data from the Data terminal. Afterward the timer data in the shift register shift by synchronized at the falling edge of clock signal on CLK termina! and output from the DATA terminal. If the timer data is updated in the data output, there are one second difference between timer data and output data. < E & G Version > | Year | Month| Date | Day | Hour | Minute | Second | The data is read out from LSB of Year, and first 52-bit is effective. <F & H Version > | Day | Hour | Minute | Second | The data is read out from LSB of Days of Week, and first 28-bit is effective. If the low voltage detector detect the low battery, (EE): is written into each digit of timer data and read out. The code of (EE)x is a warning for the data broken. 11-3 New Japan Radio Co,Ltd.NJIUG355 Series < Read-Out Timing > Data Ovtout K0 XX 2X aXeX XX Kee XeXeX? - Year or Day settee Second 2h ORB OERC IBOOA The timer data is transferred to the shift register at rising edge of the CE(@) and LSB of the timer data is output to the Data terminal. Afterward the timer data in the shift register shift by synchronized at falling edge of the CLK(@) then output to the Data terminal time-to-time. @ note ) When the CE signal is which raising edge or falling edge, the CLK signal should be fixed to "L. And so, before the CE signal is raised, the 1/0 signal should be fixed to "L. 3. Timer Data Writing When both of 1/0 terminal and CE terminal are H", update is-stopped, Oscillator divider is cleared, and the timer data can be written to the NJU6355. The timer data is written into the shift register from the Data terminal by synchronized with rising edge of the clock signal input from the CLK terminal, and the data is transferred from the shift register to the timer counter by synchronized with falling edge of the CE signal. In this time the second-counter is cleared to "0", and the oscillator divider start the operation. The input data strings are LSB first of each digit as shown below (the data format is depend on the version): <E & G Version > | Year | Month] Date | Day | Hour | Minute | The data is written from LSB of Year and last 44-bit is effective. < F & H Version > The data is written from LSB of Days of Week and last 20-bit is effective. New Japan Radio Co,Ltd -___ 1-4NJIUGS3S55 Series < Write-Down Timing > Data Input |] a aye meister XXX OXYQACG se The data ts input into The data in the shift register the shift register at is transferred to the timer rising edge of the CLK. counter at this falling edge of the CE, then the oscil lator divider start the operation. note ) When the CE signal is which raising edge or falling edge, the CLK signal should be fixed to "L. And so, before the CE signal is raised, the 1/0 signa! should be fixed to "H. 4. Low Voltage Detector The NJU6355 series incorporate the low battery detector. If the supply voltage reduce to the detection level, (EE)x is written into each digit of the shift register as warning code for the CPU. 5. Data Access The NJUG355 series can operate from 2.0V to 5.5. However, it is not allow the data access out of the range of 5V:10%. It may be broken the data unless 5V10%. Thus, when the data access, CE terminal should be "H after the power supply rise to 5V10%, then start the operation. WE ABSOLUTE MAXIMUM RATINGS ( Ta=25C ) PARAMETER SYMBOL RATINGS UNIT Supply Vol tage Vop -~0.3 ~ + 6.0 V Input Voltage Vin Vss-0.3 ~ Vovt0.3 V Power Dissipation Pp a (MY nl Operating Temperature Toor -30 ~ + 8 Cc Storage Temperature Toes - 55 ~ +150 c 11-5 - New Japan Radio Co.,Ltd.ME ELECTRICAL CHARACTERISTICS DC Characteristics NJIUUGS3SS5 5 Series ( Vonv=2.0V, Ta=25C ) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT Operating Current lop XT=32. 768kHz,CE=0V 3.0 4.0 uA LowBattery Detegt Itage Ver 1.1 1.7 V DC Characteristics Voo=5.0VE10%, Ta=25 ) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT Operating Voltage Vop 4.5 5.5 V Operating Current Ipp XT=32. 768kHz, CE=OV 4.0 15 uA 3-st Leakage Current Ira. | DATA Terminal (CE=0V) -2.0 2.0 [aA Input Leakage Current bea 1/0, CLK Terminals -1.0 1.0 uA Input Current lee CE Terminal (CE=Ypp) 20 aa Input Volt Vix 1/0,CE,CLK,DATA Terminals | Voox0.8 Vop y npuy vonage Vi. | 1/0,CE.CLK,DATA Terminals | Vss Voox0 .2 Vou DATA Terminal (1on=-0. 4mA) 4.1 Output Yol tage Vou | DATA Terminal (1o.=1-OmA) 04 | AC CHARACTERISTICS ( Von=5.0VE10%, Ta=25C, Ciz50pF ) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT CLK Pulse "H Period town 0.47 5000 ks GLK Pulse "L Period teow: 0.47 5000 us CE Set-up Time Before CLK Rising tes 470 ns CE Hold Time After CLK Falling tex 20 ns 1/0 Set-up Time Before CLK Rising tos 60 ns 1/0 Hold Time After CLK Fal ling tos 20 ns Write-Down Data Set-Up Time twos 100 ns Write-Down Data Hold Time twon 20 ns Data Delay Time After CLK Falling taop ao ps Rise/Fali Time tre 50 ns New Japan Radio Co.,ltd. 11-6NJIUGS35 5S Series wT Cin). cLK 507% 30% Input Data % 80% - Output Data 70s @ APPLICATION CIRCUIT . Main Power Vow Supply NJU6355 tT Vow DATA g 6 CPU CLK + cE Vss j | [tee 11-7 New Japan Radio Co.Ltd.