PRELIMINARY FullFlexTM Synchronous DDR Dual-Port SRAM Features * True dual-ported memory allows simultaneous access to the shared array from each port * Synchronous pipelined operation with selectable Double Data Rate (DDR) or Single Data Rate (SDR) operation on each port -- Selectable LVTTL (3.3V), Extended HSTL (1.4V-1.9V), 1.8V LVCMOS, or 2.5V LVCMOS I/O on each port -- Burst counters for sequential memory access -- Mailbox with interrupt flags for message passing -- Dual Chip Enables for easy depth expansion -- DDR SRAM interface (data transferred at 400 Mbps) @ 200 MHz Functional Description -- SDR interface at 250 MHz The FullFlex Dual-Port SRAM families consist of 4-Mbit, 9-Mbit, 18-Mbit, and 36-Mbit synchronous, true dual-port static RAMs that are high-speed, low-power 1.8V/1.5V CMOS. Two ports are provided, allowing the array to be accessed simultaneously. Simultaneous access to a location triggers deterministic access control. For FullFlex72, these ports can operate independently in DDR mode with 36-bit bus widths or in SDR mode with 72-bit bus widths. For FullFlex36 and FullFlex18, the ports operate in DDR mode only. Each port can be independently configured for two pipeline stages for SDR mode or 2.5 stages in DDR mode. Each port can also be configured to operate in pipeline or flow-through mode in SDR mode. -- Up to 36-Gb/s bandwidth (250 MHz * 72 bit * 2 ports) * Selectable pipeline or flow-through mode * Selectable 1.5V or 1.8V core power supply * Commercial and Industrial temperature ranges * IEEE 1149.1 JTAG boundary scan * Available in 484-ball PBGA Packages and 256-ball FBGA Packages * FullFlex72 family -- 36 Mbit: 512K x 72 (CYDD36S72V18) Advanced features include built-in deterministic access control to manage address collisions during simultaneous access to the same memory location, variable impedance Matching (VIM) to improve data transmission by matching the output driver impedance to the line impedance, and echo clocks to improve data transfer. -- 18 Mbit: 256K x 72 (CYDD18S72V18) -- 9 Mbit: 128K x 72 (CYDD09S72V18) -- 4 Mbit: 64K x 72 (CYDD04S72V18) * FullFlex36 family -- 36 Mbit: 512K x 72 (CYDD36S36V18) To reduce the static power consumption, chip enables can be used to power down the internal circuitry. The number of cycles of latency before a change in CE0 or CE1 will enable or disable the databus matches the number of cycles of read latency selected for the device. In order for a valid write or read to occur, both chip enable inputs on a port must be active. -- 18 Mbit: 256K x 72 (CYDD18S36V18) -- 9 Mbit: 128K x 72 (CYDD09S36V18) -- 4 Mbit: 64K x 72 (CYDD04S36V18) * FullFlex18 family Each port contains an optional burst counter on the input address register. After externally loading the counter with the initial address, the counter will increment the address internally. -- 36 Mbit: 1M x 36 (CYDD36S18V18) -- 18 Mbit: 512K x 36 (CYDD18S18V18) -- 9 Mbit: 256K x 36 (CYDD09S18V18) -- 4 Mbit: 128K x 36 (CYDD04S18V18) * Built-in deterministic access control to manage address collisions -- Deterministic flag output upon collision detection -- Collision detection on back-to-back clock cycles -- First Busy Address readback * Advanced features for improved high-speed data transfer and flexibility -- Variable impedance Matching (VIM) -- Echo clocks Cypress Semiconductor Corporation Document #: 38-06072 Rev. *E * Additional features of this device include a mask register and a mirror register to control counter increments and wrap-around, counter-interrupt (CNTINT) flags to notify that the counter will reach the maximum value on the next clock cycle, readback of the burst-counter internal address, mask register address, and BUSY address on the address lines, retransmit functionality, mailbox interrupt flags for message passing, JTAG for boundary scan, and asynchronous Master Reset (MRST). The logic block diagram in Figure 1 displays these features. The FullFlex72 DDR family of devices is offered in a 484-ball plastic BGA package. The FullFlex36 and FullFlex18 DDR only families of devices are offered in a 256-ball fine pitch BGA package. 198 Champion Court * San Jose, CA 95134-1709 * 408-943-2600 Revised October 11, 2005 FullFlex PRELIMINARY FTSELL FTSELR CQENL CQENR PORTSTD[1:0]L CONFIG Block CONFIG Block PORTSTD[1:0]R DQ[71:0]L BE [7:0]L CE0L CE1L OEL IO Control DQ [71:0]R BE [7:0]R CE0R CE1R OER IO Control R/WR CQ0R CQ0R CQ1R CQ1R R/WL CQ0L CQ0L CQ1L CQ1L VC_SEL Dual Ported Array Collision Detection Logic BUSYL A [19:0]L CNT/MSKL ADSL CNTENL CNTRSTL RETL CNTINTL CL CL WRPL Address & Counter Logic BUSYR Address & Counter Logic A [19:0]R CNT/MSKR ADSR CNTENR CNTRSTR RETR CNTINTR CR CR WRPR Mailboxes INTL INTR READYL LowSPDL ZQ0L ZQ1L JTAG RESET LOGIC TRST TMS TDI TDO TCK MRST READYR LowSPDR ZQ0R ZQ1R Figure 1. Block Diagram[1,2,3] Notes: 1. The CYDD36S18V18 device has 20 address bits. The CYDD36S36V18, CYDD36S72V18, and the CYDD18S18V18 devices have 19 address bits. The CYDD18S72V18, CYDD18S36V18, and the CYDD09S18V18 devices have 18 address bits. The CYDD09S72V18, CYDD04S18V18, and the CYDD09S36V18 devices have 17 address bits. The CYDD04S36V18 and the CYDD04S72V18 devices have 16 address bits. 2. The FullFlex72 family of devices has 72 data lines. The FullFlex36 family of devices has 36 data lines. The FullFlex18 family of devices has 18 data lines. 3. The FullFlex72 family of devices has eight byte enables. The FullFlex36 family of devices has four byte enables. The FullFlex18 family of devices has two byte enables. Document #: 38-06072 Rev. *E Page 2 of 48 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Document #: 38-06072 Rev. *E NC VSS VSS VSS VSS VSS VSS VSS VSS VSS DQ16L DQ14L DQ12L DQ9L DQ42L DQ39L DQ36L DQ6L DQ7L DQ8L DQ3L DQ4L DQ5L Note: 4. Leaving this pin NC disables VIM 5. Leave this ball unconnected for CYDD18S72V18, CYDD09S72V18 and CYDD04S72V18. 6. Leave this ball unconnected for CYDD09S72V18 and CYDD04S72V18 7. Leave this ball unconnected for CYDD04S72V18 AB CQ1R VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC VSS VTTL VTTL VTTL VDDIO VDDIO R R VDDIO VDDIO R R VCORE VCORE VCORE VCORE VDDIO R VDDIO VDDIO R R VDDIO VDDIO R R VREFR VDDIO VDDIO R R VSS VSS VSS VSS VSS VSS VSS VSS VREFR VDDIO VDDIO R R VDDIO VDDIO VDDIO VDDIO R R R R CQ1R VTTL VTTL DQ0L DQ1L DQ2L DQ0R DQ1R DQ2R DQ3R DQ4R DQ5R VSS TRST OER READY R WRPR RETR ADSR CR CR INTR BE0R A14R A12R A10R A8R A6R A4R A2R A0R CNTRS TR A18R[5] TMS TDI TCK TDO DQ46R DQ47R DQ48R DQ49R VDDIO FTSEL DQ50R DQ51R R R DQ52R DQ53R NC CNTEN A17R[6] A16R[7] R A15R A13R A11R A9R A7R A5R A3R A1R CE1R DQ70R[ DQ71R BE4R CNTMS KR BE1R BE5R DQ66R DQ67R VDDIO DQ68R DQ69R R VSS BE7R ZQ1R[4] BE3R BE6R BE2R CE0R VSS VSS DQ64R DQ65R DQ6R DQ36R DQ39R DQ42R DQ9R DQ12R DQ14R DQ16R NC DQ7R DQ37R DQ40R DQ43R DQ10R DQ13R DQ15R DQ17R DQ45R DQ8R DQ38R DQ41R DQ44R DQ11R CQ0R VDDIO VDDIO VDDIO VDDIO VDDIO R R R R R VC_SE PORTS CNTINT BUSYR ZQ0R[4] PORTS LOWSP DDRON CQ0R L TD1R TD0R R R DR DQ45L DQ17L DQ15L DQ13L DQ10L DQ43L DQ40L DQ37L CQ0L AA VSS CQ0L DQ47L DQ46L VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDIOL VDDIOL VDDIOL VDDIOL VTTL DQ11L DQ44L DQ41L DQ38L VSS MRST DQ49L DQ48L VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VTTL NC VSS CQENL VDDIOL VDDIOL VDDIOL VDDIOL VDDIOL VCORE VCORE VCORE VCORE VDDIO VDDIO VDDIO VDDIO VDDIO CQENR R/WR R R R R R NC R/WL DQ51L DQ50L FTSELL VDDIOL DQ53L DQ52L[ VSS VSS VSS VSS VSS VDDIOL VDDIOL VREFL INTL CNTRS TL A18L[5] NC BE0L VDDIOL VDDIOL BE1L VDDIOL VCORE VCORE VCORE A16L[7] A17L[6] CNTEN L ADSL VTTL VTTL VSS VSS VSS VSS Y W V U T R P A14L N OEL BE5L BE4L VDDIOL VDDIOL A13L A15L A12L M CL CL VCORE BE7L ZQ1L[4] VTTL BE3L VDDIOL VDDIOL BE6L VDDIOL VDDIOL BE2L VDDIOL VDDIOL VREFL READY L WRPL RETL CNTMS KL A9L A7L A6L A11L A5L A4L A8L A3L A2L A10L A1L A0L VTTL BUSYL CNTINT PORTS TD1L L CE0L VDDIOL VDDIOL VDDIOL VDDIOL VDDIOL VCORE VCORE VCORE VCORE VDDIO VDDIO VDDIO VDDIO VDDIO R R R R R CE1L VDDIOL VDDIOL VDDIOL VDDIOL VDDIOL VTTL CQ1L DDRON LOWSP PORTS L TD0L DL DQ71L DQ70L[ VSS CQ1L VSS VSS DQ69L DQ68L VDDIOL L K J H G F E VSS VSS VSS ZQ0L[4][ DQ29L DQ62L DQ59L DQ56L DQ26L DQ23L DQ20L DQ20R DQ23R DQ26R DQ56R DQ59R DQ62R DQ29R DQ67L DQ66L D VSS VSS DQ65L DQ64L C NC DQ63L DQ35L DQ33L DQ31L DQ28L DQ61L[ DQ58L DQ55L DQ25L DQ22L DQ19L DQ19R DQ22R DQ25R DQ55R DQ58R DQ61R DQ28R DQ31R DQ33R DQ35R DQ63R DQ34L DQ32L DQ30L DQ27L DQ60L DQ57L DQ54L DQ24L DQ21L DQ18L DQ18R DQ21R DQ24R DQ54R DQ57R[ DQ60R DQ27R DQ30R DQ32R DQ34R B A 1 NC FullFlex72 SDR/DDR 484-ball BGA Pinout (Top View) PRELIMINARY FullFlex Page 3 of 48 FullFlex PRELIMINARY FullFlex36 DDR 484-ball BGA Pinout (Top View)[8] 1 A B C 2 3 4 F G H J K L M N P R T U V AA AB 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 DQ34 DQ32 DQ30 DQ27 L L L L NC NC NC DQ24 DQ21 DQ18 DQ18 DQ21 DQ24 L L L R R R NC NC NC DQ27 DQ30 DQ32 DQ34 R R R R NC NC DQ35 DQ33 DQ31 DQ28 L LNC L L NC NC NC DQ25 DQ22 DQ19 DQ19 DQ22 DQ25 L L L R R R NC NC NC DQ28 DQ31 DQ33 DQ35 R R R R NC NC NC NC DQ26 DQ23 DQ20 DQ20 DQ23 DQ26 L L L R R R NC NC NC DQ29 VSS R VSS CQ1L CQ1L DDR LOW PORT ZQ0L[ BUSY CNTI PORT 4] L NTL STD1 ONL SPDL STD0 L L NC NC NC VSS VSS DQ29 L VSS NC NC NC NC VSS VSS VSS NC NC NC NC VDDI VSS OL VSS VDDI OR NC NC NC NC CE1L CE0L VDDI VDDI VDDI VDDI VDDI VCO VCO VCO VCO VDDI VDDI VDDI VDDI VDDI CE0R CE1R OL OL OL OL OL RE RE RE RE OR OR OR OR OR NC NC A0L A1L RETL BE2L VDDI VDDI VREF VSS OL OL L VSS VSS VSS VSS VSS VSS VSS VREF VDDI VDDI BE2R RETR A1R R OR OR A0R A2L A3L VDDI VDDI VSS OL OL VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDI VDDI OR OR A3R A2R A4L A5L READ BE3L VDDI VDDI VSS OL OL YL VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDI VDDI BE3R READ A5R OR OR YR A4R A6L A7L ZQ1L[ NC VTTL VCO RE VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VCO VDDI RE OR A6R A8L A9L CL OEL VTTL VCO RE VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VCO VTTL OER RE CR A9R A10L A11L CL NC VTTL VCO RE VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VCO VTTL RE CR A11R A10R A12L A13L ADSL BE1L VDDI VCO OL RE VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VCO VTTL BE1R ADSR A13R A12R RE VDDI VDDI VSS OL OL VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDI VDDI OR OR A16L A17L CNTE BE0L VDDI VDDI VSS OL OL NL VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDI VDDI BE0R CNTE A17R A16R OR OR NR VSS VSS VSS VSS VSS VSS WRP L 4] A14L A15L CNT MSKL NC NC CQ1R CQ1R VSS VSS VDDI VDDI VDDI VDDI VDDI VTTL VTTL VTTL VDDI VDDI VDDI VDDI OL OL OL OL OL OR OR OR OR NC VSS NC NC NC NC WRP R ZQ1R A7R [4] A8R CNT A15R A14R MSK R A18L NC CNTR INTL VDDI VDDI VREF VSS OL OL L STL VSS VREF VDDI VDDI INTR CNTR R OR OR STR NC A18R NC NC R/WL CQE VDDI VDDI VDDI VDDI VDDI VCO VCO VCO VCO VDDI VDDI VDDI VDDI VDDI CQE R/WR NL OL OL OL OL OL RE RE RE RE OR OR OR OR OR NR NC NC NC NC FTSE VDDI OL LL NC NC NC NC VSS MRST VSS CQ0L CQ0L VC_S PORT CNTI BUSY ZQ0R PORT LOW DDR CQ0R CQ0R VSS [4] EL STD1 NTR R STD0 SPDR ONR R R NC NC VSS W Y 6 NC D E 5 NC VDDI VDDI VDDI VDDI VTTL VTTL VTTL VDDI VDDI VDDI VDDI VDDI TRST VDDI FTSE OL OL OL OL OR OR OR OR OR OR LR TDI TDO NC NC TCK NC NC VSS DQ11 L NC NC NC DQ8L DQ5L DQ2L DQ2R DQ5R DQ8R NC NC NC DQ11 TMS R NC DQ17 DQ15 DQ13 DQ10 L L L L NC NC NC DQ7L DQ4L DQ1L DQ1R DQ4R DQ7R NC NC NC DQ10 DQ13 DQ15 DQ17 R R R R NC NC DQ16 DQ14 DQ12 DQ9L L L L NC NC NC DQ6L DQ3L DQ0L DQ0R DQ3R DQ6R NC NC NC DQ9R DQ12 DQ14 DQ16 R R R NC Note: 8. Use this pinout only for device CYDD36S36V18 of the FullFlex36 famiy. Document #: 38-06072 Rev. *E Page 4 of 48 PRELIMINARY FullFlexTM Synchronous DDR Dual-Port SRAM FullFlex18 DDR 484-ball BGA Pinout (Top View) 15 16 17 18 19 20 21 22 DQ15 DQ12 DQ9L DQ9R DQ12 DQ15 L L R R NC NC NC NC NC NC NC NC NC DQ16 DQ13 DQ10 DQ10 DQ13 DQ16 L L L R R R NC NC NC NC NC NC NC NC NC DQ17 DQ14 DQ11 DQ11 DQ14 DQ17 L L L R R R NC NC NC NC VSS VSS NC NC VSS CQ1L CQ1L DDR LOW PORT ZQ0L[ BUSY CNTI PORT 4] L NTL STD1 ONL SPDL STD0 L L NC CQ1R CQ1R VSS VSS VSS NC NC VSS VDDI OR NC NC CE1L CE0L VDDI VDDI VDDI VDDI VDDI VCO VCO VCO VCO VDDI VDDI VDDI VDDI VDDI CE0R CE1R OL OL OL OL OL RE RE RE RE OR OR OR OR OR NC NC VSS VSS VREF VDDI VDDI BE1R RETR A1R R OR OR A0R VSS VSS VSS VSS VDDI VDDI OR OR NC WRP R A3R A2R VSS VSS VSS VSS VSS VDDI VDDI OR OR NC READ A5R YR A4R VSS VSS VSS VSS VSS VSS VCO VDDI RE OR NC ZQ1R A7R A6R VSS VSS VSS VSS VSS VSS VSS VCO VTTL OER RE CR A9R VSS VSS VSS VSS VSS VSS VSS VSS VCO VTTL RE NC CR A11R A10R VSS VSS VSS VSS VSS VSS VSS VSS VSS VCO VTTL RE NC ADSR A13R A12R VDDI VDDI VSS OL OL VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDI VDDI OR OR NC CNT A15R A14R MSK R R A16L A17L CNTE BE0L VDDI VDDI VSS OL OL NL VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDI VDDI BE0R CNTE A17R A16R OR OR NR T A18L A19L CNTR INTL VDDI VDDI VREF VSS OL OL L STL VSS VSS VSS VSS VSS VSS VSS VREF VDDI VDDI INTR CNTR A19R A18R R OR OR STR A B C 1 2 3 4 5 6 7 8 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC VSS VSS NC NC NC NC NC VSS VSS NC NC VDDI VSS OL NC NC A0L A1L RETL BE1L VDDI VDDI VREF VSS OL OL L VSS VSS VSS VSS VSS A2L A3L WRP L NC VDDI VDDI VSS OL OL VSS VSS VSS VSS VSS A4L A5L READ YL NC VDDI VDDI VSS OL OL VSS VSS VSS VSS A6L A7L ZQ1L[ NC VTTL VCO RE VSS VSS VSS VSS A8L A9L CL OEL VTTL VCO RE VSS VSS VSS A10L A11L CL NC VTTL VCO RE VSS VSS A12L A13L ADSL NC VDDI VCO OL RE VSS A14L A15L CNT MSKL NC D E F G H J K L M N P U V 4] 9 10 11 12 13 14 VSS VDDI VDDI VDDI VDDI VDDI VTTL VTTL VTTL VDDI VDDI VDDI VDDI OL OL OL OL OL OR OR OR OR NC [4] A8R A20L NC R/WL CQE VDDI VDDI VDDI VDDI VDDI VCO VCO VCO VCO VDDI VDDI VDDI VDDI VDDI CQE R/WR NL OL OL OL OL OL RE RE RE RE OR OR OR OR OR NR NC A20R NC NC FTSE VDDI LL OL NC NC NC NC VSS MRST VSS CQ0L CQ0L VC_S PORT CNTI BUSY ZQ0R PORT LOW DDR CQ0R CQ0R VSS [4] EL STD1 NTR STD0 SPDR ONR R R R TDI TDO NC NC W NC VDDI VDDI VDDI VDDI VTTL VTTL VTTL VDDI VDDI VDDI VDDI VDDI TRST VDDI FTSE LR OL OL OL OL OR OR OR OR OR OR Y NC NC VSS VSS NC NC NC NC DQ8L DQ5L DQ2L DQ2R DQ5R DQ8R NC NC NC NC TMS TCK NC NC AA NC NC NC NC NC NC NC NC DQ7L DQ4L DQ1L DQ1R DQ4R DQ7R NC NC NC NC NC NC NC NC AB NC NC NC NC NC NC NC NC DQ6L DQ3L DQ0L DQ0R DQ3R DQ6R NC NC NC NC NC NC NC NC Cypress Semiconductor Corporation Document #: 38-06072 Rev. *E * 198 Champion Court * San Jose, CA 95134-1709 * 408-943-2600 Revised October 11, 2005 FullFlex PRELIMINARY FullFlex36 DDR 256 Ball BGA (Top View) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A DQ32L DQ30L DQ28L DQ26L DQ24L DQ22L DQ20L DQ18L DQ18R DQ20R DQ22R DQ24R DQ26R DQ28R DQ30R DQ32R B DQ33L DQ31L DQ29L DQ27L DQ25L DQ23L DQ21L DQ19L DQ19R DQ21R DQ23R DQ25R DQ27R DQ29R DQ31R DQ33R C DQ34L DQ35L RETL INTL CQ1L CQ1L VC_SEL TRST MRST ZQ0R[4] CQ1R CQ1R INTR RETR DQ35R DQ34R D A0L A1L WRPL VREF VDDIOL LOWSP DL VSS VTTL VTTL VSS LOWSP DR VDDIO R VREF WRPR A1R A0R E A2L A3L CE0L CE1L VDDIOL VDDIOL VDDIOL VCORE VCORE VDDIO R VDDIO R VDDIO R CE1R CE0R A3R A2R F A4L A5L CNINTL BE3L VDDIOL VDDIOL VSS VSS VSS VSS VSS VDDIO R BE3R CNINTR A5R A4R G A6L A7L BUSYL BE2L ZQ0L[4] VSS VSS VSS VSS VSS VSS VDDIO R BE2R BUSYR A7R A6R H A8L A9L CL VTTL VCORE VSS VSS VSS VSS VSS VSS VCORE VTTL CR A9R A8R J A10L A11L CL PORTS VCORE TD1L VSS VSS VSS VSS VSS VSS VCORE PORTS TD1R CR A11R A10R K A12L A13L OEL BE1L VDDIOL VSS VSS VSS VSS VSS VSS VDDIO R BE1R OER A13R A12R L A14L A15L ADSL BE0L VDDIOL VSS VSS VSS VSS VSS VDDIO R VDDIO R BE0R ADSR A15R A14R VDDIO R VDDIO R VDDIO R CQENR RWR VREF CNTMS KR M A16L[10] A17L[9] RWL CQENL VDDIOL VDDIOL VDDIOL VCORE VCORE PORTS READY ZQ1L[4] TD0L L N NC NC P DQ16L DQ17L CNTEN CNTRS L TL CQ0L CQ0L R DQ15L DQ13L DQ11L DQ9L DQ7L T DQ14L DQ12L DQ10L DQ8L DQ6L CNTMS KL VREF ZQ1R[4] READY PORTS R TD0R VTTL VTTL TCK TMS TDO TDI CQ0R CQ0R DQ5L DQ3L DQ1L DQ1R DQ3R DQ5R DQ7R DQ9R DQ4L DQ2L DQ0L DQ0R DQ2R DQ4R DQ6R DQ8R A17R[9] A16R[10] NC NC DQ17R DQ16R DQ11R DQ13R DQ15R DQ10R DQ12R DQ14R CNTRS CNTEN TR R Notes: 9. Leave this ball unconnected for CYDD09S36V18 and CYDD04S36V18. 10. Leave this ball unconnected for CYDD04S36V18. Document #: 38-06072 Rev. *E Page 6 of 48 FullFlex PRELIMINARY FullFlex18 DDR 256 Ball BGA (Top View) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A NC NC NC DQ17L DQ16L DQ13L DQ12L DQ9L DQ9R DQ12R DQ13R DQ16R DQ17R NC NC NC B NC NC NC NC DQ15L DQ14L DQ11L DQ10L DQ10R DQ11R DQ14R DQ15R NC NC NC NC C NC NC RETL INTL CQ1L CQ1L VC_SEL TRST MRST ZQ0R[4] CQ1R CQ1R INTR RETR NC NC D A0L A1L WRPL VREF VDDIOL LOWSP DL VSS VTTL VTTL VSS LOWSP VDDIOR DR VREF WRPR A1R A0R E A2L A3L CE0L CE1L VDDIOL VDDIOL VDDIOL VCORE VCORE VDDIOR VDDIOR VDDIOR CE1R CE0R A3R A2R F A4L A5L CNINTL NC VDDIOL VDDIOL VSS VSS VSS VSS VSS VDDIOR NC CNINTR A5R A4R G A6L A7L BUSYL NC ZQ0L[4] VSS VSS VSS VSS VSS VSS VDDIOR NC BUSYR A7R A6R H A8L A9L CL VTTL VCORE VSS VSS VSS VSS VSS VSS VCORE VTTL CR A9R A8R J A10L A11L CL PORTST VCORE D1L VSS VSS VSS VSS VSS VSS VCORE PORTST D1R CR A11R A10R K A12L A13L OEL BE1L VDDIOL VSS VSS VSS VSS VSS VSS VDDIOR BE1R OER A13R A12R L A14L A15L ADSL BE0L VDDIOL VSS VSS VSS VSS VSS VDDIOR VDDIOR BE0R ADSR A15R A14R M A16L A17L[12] RWL RWR A17R[12] A16R N A18L[11] NC CNTMS KL CNTMS KR NC A18R[11] P NC NC CNTENL CNTRST L CNTRST CNTEN R R NC NC R NC NC NC T NC NC NC CQENL VDDIOL VDDIOL VDDIOL VCORE VCORE VDDIOR VDDIOR VDDIOR CQENR VREF PORTST READYL ZQ1L[4] D0L VTTL VTTL ZQ1R[4] READY PORTST R D0R VREF CQ0L CQ0L TCK TMS TDO TDI CQ0R CQ0R NC DQ6L DQ5L DQ2L DQ1L DQ1R DQ2R DQ5R DQ6R NC NC NC NC DQ8L DQ7L DQ4L DQ3L DQ0L DQ0R DQ3R DQ4R DQ7R DQ8R NC NC NC Note: 11. Leave this ball unconnected for CYDD09S18V18 and CYDD04S18V18. 12. Leave this ball unconnected for CYDD04S18V18. Table 1. Selection Guide -250[13,15,17] -200[13,14,16,17 ] -167[13,14] Unit fMAX 250 200 167 MHz SDR Max. Access Time (Clock to Data) 2.64 3.3 4.0 ns DDR Max. Access Time (Clock to Data) 0.50 0.50 0.50 ns Typical Operating Current ICC TBD TBD TBD mA Typical Standby Current for ISB3 (Both Ports CMOS Level) TBD TBD TBD mA Notes: 13. SDR mode with two pipeline stages. 14. DDR mode with 2.5 pipeline stages. 15. In SDR mode, these parameters apply for the 1.8V LVCMOS and HSTL. 16. In DDR mode, these parameters apply for the 1.8V LVCMOS and HSTL. 17. There is a speed bin drop for a 1.5V Core voltage. 18. These parameters apply for the 1.5V Core voltage only. Document #: 38-06072 Rev. *E Page 7 of 48 FullFlex PRELIMINARY Pin Definitions Left Port Right Port Description A[20:0]L A[20:0]R Address Inputs.[1] DQ0L-DQ71L DQ0R-DQ71R Data Bus Input/Output.[2] BE0L-BE7L BE0R-BE7R Byte Select Inputs.[3] Asserting these signals enables Read and Write operations to the corresponding bytes of the memory array. BUSYL BUSYR Port Busy Output. When there is an address match and both chip enables are active for both ports, an external BUSY signal is asserted on the fifth clock cycle from when the collision occurs. C/CL C/CR Clock Signal.[19] Maximum clock input rate is fMAX. Tie C to VSS when operating in SDR mode. CE0L CE0R Active LOW Chip Enable Input. CE1L CE1R Active HIGH Chip Enable Input. CQENL CQENR Echo Clock Enable Input. Assert HIGH to enable echo clocking on respective port. CQ0L, CQ0L CQ0R, CQ0R Echo Clock Signal Output for DQ[35:0] for FullFlex72 devices. Echo Clock Signal Output for DQ[17:0] for FullFlex36 devices. Echo Clock Signal Output for DQ[8:0] for FullFlex18 devices. CQ1L, CQ1L CQ1R, CQ1R Echo Clock Signal Output for DQ[71:36] for FullFlex72 devices. Echo Clock Signal Output for DQ[35:18] for FullFlex36 devices. Echo Clock Signal Output for DQ[17:9] for FullFlex18 devices. DDRONL DDRONR DDR Enable Input. Assert HIGH to enable DDR clocking on respective port. ZQ<1:0>L ZQ<1:0>R VIM Output Impedance Matching Input. To use, connect a calibrating resistor between ZQ and ground. The resistor must be five times larger than the intended line impedance driven by the dual-port. Assert HIGH to disable Variable Impedance Matching. OEL OER Output Enable Input. This asynchronous signal must be asserted LOW to enable the DQ data pins during Read operations. INTL INTR Mailbox Interrupt Flag Output. The mailbox permits communications between ports. The upper two memory locations can be used for message passing. INTL is asserted LOW when the right port writes to the mailbox location of the left port, and vice versa. An interrupt to a port is deasserted HIGH when it reads the contents of its mailbox. LowSPDL LowSPDR Port Low Speed Select Input. Assert this pin LOW to disable the DLL. For operation at less than 100 MHz, assert this pin LOW. PORTSTD[1:0]L PORTSTD[1:0]R Port Clock/Address/Control/Data/Echo Clock/ I/O Standard Select Input. Assert these [20] [20] pins LOW/LOW for LVTTL, LOW/HIGH for HSTL, HIGH/LOW for 2.5V LVCMOS, and HIGH/HIGH for 1.8V LVCMOS, respectively. Connect these pins to a VTTL supply. R/WL R/WR Read/Write Enable Input. Assert this pin LOW to Write to, or HIGH to Read from the dual-port memory array. READYL READYR Port DLL Ready Output. This signal will be asserted LOW when the DLL and Variable Impedance Matching circuits have completed calibration. This is a wired OR capable output. CNT/MSKL CNT/MSKR Port Counter/Mask Select Input. Counter control input. ADSL ADSR Port Counter Address Load Strobe Input. Counter control input. CNTENL CNTENR Port Counter Enable Input. Counter control input. CNTRSTL CNTRSTR Port Counter Reset Input. Counter control input. CNTINTL CNTINTR Port Counter Interrupt Output. This pin is asserted LOW one cycle before the unmasked portion of the counter is incremented to all "1s". WRPL WRPR Port Counter Wrap Input. When the burst counter reaches the maximum count, on the next counter increment WRP can be set LOW to load the unmasked counter bits to 0 or set HIGH to load the counter with the value stored in the mirror register. RETL RETR Port Counter Retransmit Input. Assert this pin LOW to reload the initial address for repeated access to the same segment of memory. Notes: 19. C and C are complimentary for DDR operation. 20. Pins D14 and W9 of the FullFlex72 have an internal pull-down resistor. Document #: 38-06072 Rev. *E Page 8 of 48 FullFlex PRELIMINARY Pin Definitions (continued) Left Port Right Port Description VREFL VREFR Port External HSTL I/O Reference Input. VDDIOL VDDIOR Port Data I/O Power Supply. FTSELL FTSELR Port Flow-Through Mode Select Input. Assert this pin LOW to select Flow-Through mode. Assert this pin HIGH to select Pipeline mode. Selection for SDR only. MRST Master Reset Input. MRST is an asynchronous input signal and affects both ports. Asserting MRST LOW performs all of the reset functions as described in the text. A MRST operation is required at power-up. This pin must be driven by VDDIO referenced levels. VC_SEL Core Power Supply Select. Assert this pin LOW to select 1.8V Core operation. Assert this pin HIGH to select 1.5V Core operation. This pin must be driven by VTTL referenced levels. TMS JTAG Test Mode Select Input. It controls the advance of JTAG TAP state machine. State machine transitions occur on the rising edge of TCK. Operation for LVTTL or 2.5V LVCMOS. TDI JTAG Test Data Input. Data on the TDI input will be shifted serially into selected registers. Operation for LVTTL or 2.5V LVCMOS. TRST JTAG Reset Input. Operation for LVTTL or 2.5V LVCMOS. TCK JTAG Test Clock Input. Operation for LVTTL or 2.5V LVCMOS. TDO JTAG Test Data Output. TDO transitions occur on the falling edge of TCK. TDO is normally three-stated except when captured data is shifted out of the JTAG TAP. Operation for LVTTL or 2.5V LVCMOS. VSS Ground Inputs. VCORE Device Core Power Supply. VTTL LVTTL Power Supply. Selectable I/O Standard Clocking The FullFlex families of devices also offer the option of choosing one of four port standards for the device. Each port can independently select standards from single-ended HSTL class I, single-ended LVTTL, 2.5V LVCMOS, or 1.8V LVCMOS. The selection of the standard is determined by the PORTSTD pins for each port. These pins must be connected to a VTTL power supply. This will determine the input clock, address, control, data, and Echo clock standard for each port as shown in Table 2. Separate clocks synchronize the operations on each port. Each port has two clock inputs C and C. In SDR mode only the C input clock is used and C should be tied to VSS. In this mode, all the transactions on the address, control, and data will be on the C rising edge. In DDR mode, both C and C will be used and these signals are complementary. In this mode, all transactions on the address and control, except for the byte enables, will occur on the C rising edge. Transactions on the data input, output, and byte enables will be on the C and C rising edges. Table 2. Port Standard Selection PORTSTD1 VSS VSS VTTL VTTL PORTSTD0 VSS VTTL VSS VTTL I/O Standard LVTTL HSTL 2.5V LVCMOS 1.8V LVCMOS Operating mode with different IO standards combined with different core power supply will result in different maximum speed as shown in Table 3. Document #: 38-06072 Rev. *E Double Data Rate (DDR) In DDR mode with a x36 bus width, the input data is sampled on both edges of the input clock. During a write, on the rising edge of C, the first 36 bits (DQ[71:36]) will be latched into a register. On the rising edge of C, the next 36 bits (DQ[35:0]) will be latched into a register. During a read, the first 36 bits are driven out first on the rising edge of C. The next 36 bits will be driven out on the rising edge of C. The internal bus width of the FullFlex72 family is still x72. All counter operation is based upon the x72 word width. The DDR option is set on a per port basis by the configuration of the DDRON pin. Table 4 shows the data assignment for SDR and DDR configuration. The column on the right (Data Pin Name) shows the pins on which data is presented on the data lines. Page 9 of 48 FullFlex PRELIMINARY Table 3. Operating Mode vs. Speed, I/O Standard and Pipeline Stages Operating Mode Maximum Speed (MHz) Core Voltage (V) SDR 250 1.8 HSTL/1.8V LVCMOS I/O Standard Latency Cycles SDR 200 1.8 LVTTL/2.5V LVCMOS 2 SDR 200 1.5 HSTL/LVTTL/2.5V LVCMOS/1.8V LVCMOS 2 DDR 200 1.8 HSTL/1.8V LVCMOS 2.5 DDR 167 1.5 HSTL/LVTTL/2.5V LVCMOS/1.8V LVCMOS 2.5 2 Table 4. Data Pin Assignment for SDR and DDR Configuration x72 SDR Mode BE Pin Name for DDR BE Pin Name for SDR BE[3] BE[7] x36 DDR Mode Data Pin Name Related Rising Edge Clock for Write Related Rising Edge Clock for Read Data Pin Name DQ[71] C C DQ[35] BE[3] BE[3] DQ[35] C C BE[3] BE[7] DQ[70] C C BE[3] BE[3] DQ[34] C C BE[3] BE[7] DQ[69] C C BE[3] BE[3] DQ[33] C C BE[3] BE[7] DQ[68] C C BE[3] BE[3] DQ[32] C C BE[3] BE[7] DQ[67] C C BE[3] BE[3] DQ[31] C C BE[3] BE[7] DQ[66] C C BE[3] BE[3] DQ[30] C C BE[3] BE[7] DQ[65] C C BE[3] BE[3] DQ[29] C C BE[3] BE[7] DQ[64] C C BE[3] BE[3] DQ[28] C C BE[3] BE[7] DQ[63] C C BE[3] BE[3] DQ[27] C C BE[2] BE[6] DQ[62] C C BE[2] BE[2] DQ[26] C C BE[2] BE[6] DQ[61] C C BE[2] BE[2] DQ[25] C C BE[2] BE[6] DQ[60] C C BE[2] BE[2] DQ[24] C C BE[2] BE[6] DQ[59] C C BE[2] BE[2] DQ[23] C C BE[2] BE[6] DQ[58] C C BE[2] BE[2] DQ[22] C C BE[2] BE[6] DQ[57] C C BE[2] BE[2] DQ[21] C C BE[2] BE[6] DQ[56] C C BE[2] BE[2] DQ[20] C C Document #: 38-06072 Rev. *E DQ[34] DQ[33] DQ[32] DQ[31] DQ[30] DQ[29] DQ[28] DQ[27] DQ[26] DQ[25] DQ[24] DQ[23] DQ[22] DQ[21] DQ[20] Page 10 of 48 FullFlex PRELIMINARY Table 4. Data Pin Assignment for SDR and DDR Configuration (continued) x72 SDR Mode BE Pin Name for DDR BE Pin Name for SDR BE[2] x36 DDR Mode Data Pin Name Related Rising Edge Clock for Write Related Rising Edge Clock for Read Data Pin Name BE[6] DQ[55] C C DQ[19] BE[2] BE[2] DQ[19] C C BE[2] BE[6] DQ[54] C C BE[2] BE[2] DQ[18] C C BE[1] BE[5] DQ[53] C C BE[1] BE[1] DQ[17] C C BE[1] BE[5] DQ[52] C C BE[1] BE[1] DQ[16] C C BE[1] BE[5] DQ[51] C C BE[1] BE[1] DQ[15] C C BE[1] BE[5] DQ[50] C C BE[1] BE[1] DQ[14] C C BE[1] BE[5] DQ[49] C C BE[1] BE[1] DQ[13] C C BE[1] BE[5] DQ[48] C C BE[1] BE[1] DQ[12] C C BE[1] BE[5] DQ[47] C C BE[1] BE[1] DQ[11] C C BE[1] BE[5] DQ[46] C C BE[1] BE[1] DQ[10] C C BE[1] BE[5] DQ[45] C C BE[1] BE[1] DQ[9] C C BE[0] BE[4] DQ[44] C C BE[0] BE[0] DQ[8] C C BE[0] BE[4] DQ[43] C C BE[0] BE[0] DQ[7] C C BE[0] BE[4] DQ[42] C C BE[0] BE[0] DQ[6] C C BE[0] BE[4] DQ[41] C C BE[0] BE[0] DQ[5] C C BE[0] BE[4] DQ[40] C C BE[0] BE[0] DQ[4] C C BE[0] BE[4] DQ[39] C C BE[0] BE[0] DQ[3] C C BE[0] BE[4] DQ[38] C C BE[0] BE[0] DQ[2] C C BE[0] BE[4] DQ[37] C C BE[0] BE[0] DQ[1] C C BE[0] BE[4] DQ[36] C C BE[0] BE[0] DQ[0] C C Document #: 38-06072 Rev. *E DQ[18] DQ[17] DQ[16] DQ[15] DQ[14] DQ[13] DQ[12] DQ[11] DQ[10] DQ[9] DQ[8] DQ[7] DQ[6] DQ[5] DQ[4] DQ[3] DQ[2] DQ[1] DQ[0] Page 11 of 48 PRELIMINARY Selectable Pipeline/Flow-Through Mode To meet data rate and throughput requirements, the FullFlex families offer selectable pipeline or flow-through mode. Flow-through mode is only supported in the FullFlex72 devices when the port is configured in SDR mode. Echo clocks are not supported in flow-through mode and the DLL must be disabled. Flow-Through mode is selected by the FTSEL pin. Strapping this pin HIGH selects pipeline mode. Strapping this pin LOW selects flow-through mode. DLL The FullFlex families of devices have an on-chip DLL. Enabling the DLL reduces the clock to data valid time allowing more setup time for the receiving device. For operation at or below 100 MHz, the DLL must be disabled. This is selectable by strapping LowSPD LOW. For information on DLL lock and reset time, please see the Master Reset section below. Echo Clocking As the speed of data increases, on-board delays caused by parasitics make providing accurate clock trees extremely difficult. To counter this problem, the FullFlex families incorporate Echo Clocks. Echo Clocks are enabled on a per port basis. The dual-port receives input clocks (C and C for DDR mode, C for SDR mode) that are used to clock in the address and control signals for a read operation. The dual-port retransmits the input clocks relative to the data output. The buffered clocks are provided on the CQ1, CQ1, CQ0, and CQ0 outputs. Each port has two pairs of Echo clocks. Each clock is associated with half the data bits. The output clock will match the corresponding ports I/O configuration. FullFlex If both ports are accessing the same location at the same time and only one port is doing a write, if tCCS is met, then the data being written to and read from the address is valid data. For example, if the right port is reading and the left port is writing and the left ports clock meets tCCS, then the data being read from the address by the right port will be the old data. In the same case, if the right ports clock meets tCCS, then the data being read out of the address from the right port will be the new data. In the above case, if tCCS is violated by the either ports clock with respect to the other port and the right port gets the external BUSY flag, the data from the right port is corrupted. Table 5 shows the tCCS timing that must be met to guarantee the data. Table 6 shows that in the case of the left port writing and the right port reading, when an external BUSY flag is asserted on the right port, the data read out of the device will not be guaranteed. The value in the busy address register can be read back to the address lines. The required input control signals for this function are shown in Table 9. The value in the busy address register will be read out to the address lines tCA after the same amount of latency as a data read operation in SDR mode. In DDR mode, the address latency is only 2 cycles instead of 2.5 which is the data latency. After an initial address match, the address under contention is saved in the busy address register. All following address matches cause the BUSY flag to be generated, however, none of the addresses are saved into the busy address register. Once a busy readback is performed, the address of the first match which happens at least two clock cycles after the busy readback, is saved into the busy address register. To enable Echo clock outputs, tie CQEN HIGH. To disable Echo clock outputs, tie CQEN LOW. Input Clock Data Out Echo Clock Figure 2. SDR Echo Clock Delay Input Clock Input Clock Data Out Echo Clock Echo Clock Figure 3. DDR Echo Clock Delay Deterministic Access Control Deterministic Access Control is provided for ease of design. The circuitry detects when both ports are accessing the same location and provides an external BUSY flag to the port on which data may be corrupted. The collision detection logic saves the address in conflict (Busy Address) to a readable register. In the case of multiple collisions, the first Busy address will be written to the Busy Address register. Document #: 38-06072 Rev. *E Page 12 of 48 FullFlex PRELIMINARY Table 5. tCCS Timing for All Operating Modes Port A - Early Arriving Port Port B - Late Arriving Port Mode Active Edge tCCS C/C Rise to Opposite C/C Rise Set-up Time Mode Active Edge Unit SDR C SDR C tCYC(min) - 1 ns SDR C DDR C tCYC(min) - 1 ns DDR C SDR C 0.55 * tCYC + tCYC(min) - 1 ns DDR C DDR C 0.55 * tCYC + tCYC(min) - 1 ns for Non-corrupt Data Table 6. Deterministic Access Control Winning Port Clock Timing Left Port Right Port Read Write Read Read Read Write Left Clock X >tCCS 0 <tCCS Right Clock X 0 >tCCS BUSYL H H H BUSYR H H H 0 0 <tCCS >tCCS 0 <tCCS 0 >tCCS 0 0 <tCCS 0 0 >-tCCS & <tCCS >tCCS 0 H H H H H H H L H L L L H H L H L H H H H H H L H L Write Write >tCCS Variable Impedance Matching (VIM) Each port contains a Variable Impedance Matching circuit to set the impedance of the I/O driver to match the impedance of the on board traces. The impedance is set for all outputs except JTAG and is done on a per port basis. To take advantage of the VIM feature, connect a calibrating resistor (RQ) that is five times the value of the intended line impedance from the ZQ pin to VSS. The output impedance is then adjusted to account for drifts in supply voltage and temperature every 1024 clock cycles. If a port's clock is suspended, the VIM circuit will retain its last setting until the clock is restarted where it will then resume periodic adjustment. In the case of a significant change in device temperature or supply voltage, the recalibration period is multiples of 1024 clock cycles. A Master Reset will initialize the VIM circuitry. Table 7 shows the VIM parameters and Table 8 describes the VIM operation modes. In order to disable VIM, the ZQ pin must be connected to VDDIO of the relative supply for the I/Os before a Master Reset. Description No Collision Read OLD Data Read NEW Data Read OLD Data Data Not Guaranteed Read NEW Data Data Not Guaranteed Read NEW Data Read OLD Data Read NEW Data Data Not Guaranteed Read OLD Data Data Not Guaranteed Array Data Corrupted Array Stores Right Port Data Array Stores Left Port Data Table 7. Variable Impedance Matching Parameters Parameter Min. Max. Unit Tolerance RQ Value 100 275 2% Output Impedance 20 55 15% Reset Time N/A 1024 Cycles N/A Update Time N/A 1024 Cycles N/A Table 8. Variable Impedance Matching Operation RQ Connection Output Configuration 100-275 to VSS Output Driver Impedance = RQ/5 15% at Vout = VDDIO/2 ZQ to VDDIO VIM Disabled. Rout < 20 at Vout = VDDIO/2 Address Counter and Mask Register Operations[1] Each port of the FullFlex families contains a programmable burst address counter. The burst counter contains four registers: a counter register, a mask register, a mirror register, and a busy address register. The counter register contains the address used to access the RAM array. It is changed only by the master reset (MRST), Counter Reset, Counter Load, Retransmit, and Counter Increment operations. Document #: 38-06072 Rev. *E Page 13 of 48 FullFlex PRELIMINARY Counter Load Operation[1] The mask register value affects the Counter Increment and Counter Reset operations by preventing the corresponding bits of the counter register from changing. It also affects the counter interrupt output (CNTINT). The mask register is only changed by Mask Reset, Mask Load, and MRST. The Mask Load operation loads the value of the address bus into the mask register. The mask register defines the counting range of the counter register. It divides the counter register into two or three consecutive regions. Zero or more "0s" define the masked region and one or more "1s" define the unmasked portion of the counter register. The counter register may only be divided into up to three regions. The region containing the least significant bits must be no more than two bits. Bits one and zero may be "10" respectively, masking the least significant counter bit and causing the counter to increment by two instead of one. If bits one and zero are "00", the two least significant bits are masked and the counter will increment by four instead of one. For example, in the case of a 256Kx72 configuration, a mask register value of 003FC divides the mask register into three regions. With bit 0 being the least significant bit and bit 17 being the most significant bit, the two least significant bits are masked, the next eight bits are unmasked, and the remaining bits are masked. The address counter and mirror registers are both loaded with the address value presented on the address lines. This value ranges from 0 to FFFFF. Mask Load Operation[1] The mask register is loaded with the address value presented on the address bus. This value ranges from 0 to FFFFF though not all values permit correct increment operations. Permitted values are in the form of 2n-1, 2n-2, or 2n-4. The counter register can only be segmented in up to three regions. From the most significant bit to the least significant bit, permitted values have zero or more "0s", one or more "1s", and the least significant two bits can be "11", "10", or "00". Thus FFFFE, 7FFFF, and 03FFC are permitted values but 2FFFF, 03FFA, and 7FFE4 are not. Counter Readback Operation The internal value of the counter register can be read out on the address lines. The address will be valid tCA after the selected number of latency cycles configured by FTSEL. This is the same as data in SDR mode and one half cycle earlier than data latency for DDR mode. The data bus (DQ) is tri-stated on the cycle that the address is presented on the address lines. Figure 4 shows a block diagram of the operation. The mirror register is used to reload the counter register on retransmit operations (see "retransmit" below) and wrap functions (see "counter increment" below). The last value loaded into the counter register is stored in the mirror register. The mirror register is only changed by master reset (MRST), Counter Reset, and Counter Load. Mask Readback Operation The internal value of the mask register can be read out on the address lines. The address will be valid tCA after the selected number of latency cycles configured by FTSEL. For pipelined SDR and DDR mode this is two cycles. The data bus (DQ) is tri-stated on the cycle that the address is presented on the address lines. Figure 4 shows a block diagram of the operation. Table 9 summarizes the operations of these registers and the required input control signals. All signals except MRST are synchronized to the ports clock. Table 9. Burst Counter and Mask Register Control Operation (Any Port) [21,22] C X MRST CNTRST CNT/MSK CNTEN ADS RET Operation Description L X X X X X Master Reset Reset address counter to all 0s, mask register to all 1s, and BUSY address to all 0's. H L H X X X Counter Reset Reset counter and mirror unmasked portion to all 0s. H L L X X X Mask Reset Reset mask register to all 1s. H H H L L X Counter Load Load burst counter and mirror with external address value presented on address lines. H H L L L X Mask Load Load mask register with value presented on the address lines. H H H L H L Retransmit Load counter with value in the mirror register H H H L H H Counter Increment Internally increment address counter value. H H H H H H Counter Hold Constantly hold the address value for multiple clock cycles. H H H H L H Counter Readback Read out counter internal value on address lines. H H L H L H Mask Readback Read out mask register value on address lines. Notes: 21. X" = "Don't Care," "H" = HIGH, "L" = LOW. 22. Counter operation and mask register operation is independent of chip enables. Document #: 38-06072 Rev. *E Page 14 of 48 FullFlex PRELIMINARY Table 9. Burst Counter and Mask Register Control Operation (Any Port) (continued)[21,22] C MRST CNTRST CNT/MSK CNTEN ADS RET Operation H H L H H L Busy Address Readback H H L L H X Reserved H H L H L L Reserved H H L H H H Reserved H H H H L L Reserved H H H H H L Reserved Description Read out first busy address after last busy address readback Counter Reset Operation Hold Operation All unmasked bits of the counter are reset to "0". All masked bits remain unchanged. The new burst counter value is loaded into the mirror registers. A mask reset followed by a counter reset will reset the counter and mirror registers to 00000. The value of all three registers can be constantly maintained unchanged for an unlimited number of clock cycles. Such operation is useful in applications where wait states are needed, or when address is available a few cycles ahead of data in a shared bus interface. Mask Reset Operation The mask register is reset to all "1s", which unmasks every bit of the burst counter. Increment Operation[1] Once the address counter is initially loaded with an external address, the counter can internally increment the address value and address the entire memory array. Only the unmasked bits of the counter register are incremented. In order for a counter bit to change, the corresponding bit in the mask register must be "1". If the two least significant bits of the mask register are "11", the burst counter will increment by one. If the two least significant bits are "10", the burst counter will increment by two, and if they are "00", the burst counter will increment by four. If all unmasked counter bits are incremented to "1" and WRP is deasserted, the next increment will wrap the counter back to the initially loaded value. The cycle before an increment will result in the unmasked counter bits being "1s", a counter interrupt flag (CNTINT) is asserted if the counter is continuously incrementing. The next increment will cause the counter to reach its maximum value and the second increment will return the counter register to its initial value which was stored in the mirror register when WRP is deasserted. When WRP is asserted, the second increment after CNTINT is asserted will load the unmasked counter bits with "0". The example shown in Figure 5 shows an example of the CYDD36S18V18 device with the mask register loaded with a mask value of 0007F unmasking the seven least significant bits. Setting the mask register to this value allows the counter to access the entire memory space. The address counter is then loaded with an initial value of 00005 assuming WRP is deasserted. The base address bits (in this case, the seventh address through the twentieth address) do not increment once the counter is configured for increment operation. The counter address will start at address 00005 and will increment its internal address value until it reaches the mask register value of 0007F. The counter wraps around the memory block to location 00005 at the next count. CNTINT is issued when the counter reaches the maximum -1 count. Document #: 38-06072 Rev. *E Retransmit Retransmit allows repeated access to the same block of memory without the need to reload the initial address. An internal mirror register stores the address counter value last loaded. When the burst counter reaches its maximum value set by the mask register, it wraps back to the initial value stored in the mirror register as long as WRP is deasserted. The unmasked counter bits will be loaded with "0" if WRP is asserted. If the counter is configured to continuously be in increment mode, it increments once again to the maximum value and wraps back to the value initially stored in the mirror register as long as WRP is deasserted. While RET is asserted low, the counter will continue to wrap back to the value in the mirror register independent of the state of WRP. Counter Interrupt The counter interrupt (CNTINT) is asserted LOW one clock cycle before an increment operation that results in the unmasked portion of the counter register being all "1s". It is deasserted by counter reset, counter load, mask reset, mask load, counter increment, re-transmit, and MRST. Counting by Two When the two least significant bits of the mask register are "10," the counter increments by two. Counting by Four When the two least significant bits of the mask register are "00," the counter increments by four. Mailbox Interrupts The upper two memory locations can be used for message passing and permit communications between ports. Table 10 shows the interrupt operation for both ports. The highest memory location is the mailbox for the right port and the maximum address-1 is the mailbox for the left port. When one port Writes to the other ports mailbox, the INT flag of the port that the mailbox belongs to is asserted LOW. The INT flag remains asserted until the mailbox location is read by the other port. When a port reads it's mailbox, the INT flag is Page 15 of 48 FullFlex PRELIMINARY deasserted HIGH after one cycle of latency with respect to the input clock of the port to which the mailbox belongs and is independent of OE. LOW. A valid Read of the FFFFF location by the right port will reset INTR HIGH after one cycle of latency with respect to the right port's clock. At least one byte enable has to be activated to set or reset the mailbox interrupt. Table 10 shows that in order to set the INTR flag, a Write operation by the left port to address FFFFF will assert INTR CNT/MSK CNTEN Decode Logic A CNTRST RET MRST Bidirectional Address Lines Mask Register Counter/ Address Register Address Decode RAM Array C From Address Lines Load/Increment 21 Mirror 1 From Mask Register Increment Logic Wrap 21 From Mask From Counter 21 To Readback and Address Decode 0 0 21 Counter 1 21 21 +1 +2 +4 Bit 0 and 1 Wrap Detect 1 Wrap 0 1 21 To Counter 0 Figure 4. Counter, Mask, and Mirror Logic Block Diagram[1] Document #: 38-06072 Rev. *E Page 16 of 48 FullFlex PRELIMINARY CNTINT Example: Load Counter-Mask H Register = 00007F 0 0 0s 219 218 0 1 1 1 H X X Xs 219 218 Max Address Value L H 1 1 Unmasked Address X 0 0 0 0 1 0 X X Xs X 1 1 1 1 Mask Register LSB 1 6 5 4 3 2 1 0 27 2 2 2 2 2 2 2 219 218 Max + 1 Address Value 1 6 5 4 3 2 1 0 27 2 2 2 2 2 2 2 Masked Address Load Address Counter = 000005 1 1 1 1 Address Counter LSB 6 5 4 3 2 1 0 27 2 2 2 2 2 2 2 X X Xs X 0 0 0 0 1 0 1 219 218 6 5 4 3 2 1 0 27 2 2 2 2 2 2 2 [1,26] Figure 5. Programmable Counter-Mask Register Operation Table 10.Interrupt Operation Example [1, 22, 23, 24, 25] Left Port Function R/WL Right Port CEL A0L-19L INTL R/WR CER A0R-19R INTR Set Right INTR Flag L L Max. Address X X X X L Reset Right INTR Flag X X X X H L Max. Address H Set Left INTL Flag X X X L L L Max. Address-1 X Reset Left INTL Flag H L Max. Address-1 H X X X X Master Reset The FullFlex family of dual-ports undergo a complete reset by asserting MRST. MRST must be connected to VDDIO. The MRST can be asserted asynchronously to the clocks and must remain asserted for at least tRS. Once asserted MRST deasserts READY, initializes the internal burst counters, internal mirror registers, and internal Busy Addresses to zero, and initializes the internal mask register to all "1s". All mailbox interrupts (INT), Busy Address Outputs (BUSY), and burst counter interrupts (CNTINT) are deasserted upon master reset. Releasing MRST also signifies that the power supplies and all port clocks are stable. This begins calibration of the DLL and VIM circuits. READY will be asserted within 1024 clock cycles. READY is a wired OR capable output with a strong pull-up and weak pull-down. Up to four outputs may be connected together. For faster pull-down of the signal, connect a 250-Ohm resistor to VSS. If the DLL and VIM circuits are disabled for a port, the port will be operational within five clock cycles. However, the READY will be asserted within 160 clock cycles. IEEE 1149.1 Serial Boundary Scan (JTAG) The FullFlex families incorporate an IEEE 1149.1 serial boundary scan test access port (TAP). The TAP operates using JEDEC-standard 3.3V or 2.5V I/O logic levels depending on the VTTL power supply. It is composed of four input connections and one output connection required by the test logic defined by the standard. Notes: 23. CE is internal signal. CE = LOW if CE0 = LOW and CE1 = HIGH. For a single Read operation, CE only needs to be asserted once at the rising edge of the C and can be deasserted after that. Data will be out after the following C edge and will be tri-stated after the next C edge. 24. OE is "Don't Care" for mailbox operation. 25. At least one of BE0, BE1, BE2, BE3, BE4, BE5, BE6, or BE7 must be LOW. 26. The "X" in this diagram represents the counter upper bits. Document #: 38-06072 Rev. *E Page 17 of 48 FullFlex PRELIMINARY Table 12.Scan Registers Sizes Table 11.Identification Register Definitions Part Number Register Name Bit Size Configuration Value 512Kx72 0C040069h Instruction CYDD36S36V18 512Kx72 0C041069h Bypass 1 CYDD36S18V18 1024Kx36 0C042069h Identification 32 CYDD18S72V18 256Kx72 0C043069h Boundary Scan CYDD18S36V18 256Kx72 0C044069h CYDD18S18V18 512Kx36 0C045069h CYDD09S72V18 128Kx72 0C046069h CYDD09S36V18 128Kx72 0C047069h CYDD09S18V18 256Kx36 0C048069h CYDD36S72V18 CYDD04S72V18 64Kx72 0C049069h CYDD04S36V18 64Kx72 0C04A069h CYDD04S18V18 128Kx36 0C04B069h 4 n[27] Table 13.Instruction Identification Codes Instruction Code Description EXTEST 0000 Captures the Input/Output ring contents. Places the BSR between the TDI and TDO. BYPASS 1111 Places the BYR between TDI and TDO. IDCODE 1011 Loads the IDR with the vendor ID code and places the register between TDI and TDO. HIGHZ 0111 Places BYR between TDI and TDO. Forces all FullFlex72 and FullFlex36 output drivers to a High-Z state. CLAMP 0100 Controls boundary to 1/0. Places BYR between TDI and TDO. SAMPLE/PRELOAD 1000 Captures the input/output ring contents. Places BSR between TDI and TDO. RESERVED All other codes Other combinations are reserved. Do not use other than the above. Note: 27. Details of the boundary scan length can be found in the BSDL file for the device. Document #: 38-06072 Rev. *E Page 18 of 48 FullFlex PRELIMINARY Maximum Ratings Operating Range (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................ -65C to + 150C Range Ambient Temperature VCORE Commercial 0C to +70C 1.8V 100 mV 1.5V 80 mV Industrial -40C to +85C 1.8V 100 mV 1.5V 80 mV Ambient Temperature with Power Applied............................................ -55C to + 125C Supply Voltage to Ground Potential .............. -0.5V to + 4.1V DC Voltage Applied to Outputs in High-Z State......................-0.5V to VCORE + 0.5V Power Supply Requirements Min. Typ. Max. 3.0V 3.3V 3.6V DC Input Voltage............................... -0.5V to VCORE + 0.5V LVTTL VDDIO Output Current into Outputs (LOW) ............................ 20 mA 2.5V LVCMOS VDDIO 2.3V 2.5V 2.7V Static Discharge Voltage ...........................................> 2200V HSTL VDDIO 1.4V 1.5V 1.9V (JEDEC JESD8-6, JESD8-B) 1.8V LVCMOS VDDIO 1.7V 1.8V 1.9V Latch-up Current .....................................................> 200 mA 3.3V VTTL 3.0V 3.3V 3.6V 2.5V VTTL 2.3V 2.5V 2.7V HSTL VREF 0.68V 0.75V 0.95V Electrical Characteristics Over the Operating Range -250[15,17] Parameter VOH Description Output HIGH Voltage (VCORE = Min., IOH = -8 mA) Configuration LVTTL Min. 2.4 Typ. -200[16,17] Max. [28] (VCORE = Min., IOH = -4 mA) HSTL (DC)[29] VDDIO - 0.4[28] (VCORE = Min., IOH = -4 mA) HSTL VOL VIL VDDIO - 0.5[28] Typ. Max. Unit 2.4[28] V VDDIO - 0.4[28] V 0.5[28] V VDDIO - (VCORE = Min., IOH = -6 mA) 2.5V LVCMOS 1.7[28] 1.7[28] (VCORE = Min., IOH = -4 mA) 1.8V LVCMOS 1.6[28] 1.6[28] V V Output HIGH Voltage (VCORE = Min., IOL = 8 mA) LVTTL 0.4[28] (VCORE = Min., IOL = 4 mA) HSTL (DC) 0.4[28] 0.4[28] V (VCORE = Min., IOL = 4 mA) HSTL (AC) 0.5[28] 0.5[28] V (VCORE = Min., IOL = 6 mA) 2.5V LVCMOS 0.7[28] 0.7[28] V 1.8V LVCMOS 0.2[28] 0.2[28] V (VCORE = Min., IOL = 4 mA) VIH (AC)[29] Min. Input HIGH Voltage Input LOW Voltage 0.4[28] V LVTTL 2 VDDIO + 0.3 2 VDDIO + 0.3 V HSTL (DC) VREF + 0.1 VDDIO + 0.3 VREF + 0.1 VDDIO + 0.3 V HSTL (AC) VREF + 0.2 VREF + 0.2 V 2.5V LVCMOS 1.7 1.7 V 1.8V LVCMOS 1.26 1.26 V LVTTL -0.3 0.8 -0.3 0.8 V HSTL (DC) -0.3 VREF - 0.1 -0.3 VREF - 0.1 V VREF - 0.2 V HSTL (AC) VREF - 0.2 2.5V LVCMOS 0.7 0.7 V 1.8V LVCMOS 0.36 0.36 V Notes: 28. These parameters are met with VIM disabled. 29. The (DC) specifications are measured under steady state conditions. The (AC) specifications are measured while switching at speed. Document #: 38-06072 Rev. *E Page 19 of 48 FullFlex PRELIMINARY Electrical Characteristics Over the Operating Range (continued) -250[15,17] Parameter READY VOH Description Configuration Min. Output HIGH Voltage (VCORE = Min., IOH = -24 mA) LVTTL 2.7[28] Typ. -200[16,17] Max. (VCORE = Min., IOH = -12 mA) HSTL (DC)[29] VDDIO - 0.4[28] (VCORE = Min., IOH = -12 mA) HSTL (AC) [29] (VCORE = Min., IOH = -15 mA) 2.5V LVCMOS (VCORE = Min., IOH = -12 mA) 1.8V LVCMOS READY VOL VDDIO - 0.5 2.0 [28] [28] Min. Typ. Max. Unit 2.7[28] V VDDIO - 0.4[28] V VDDIO - 0.5[28] V [28] 2.0 VDDIO - 0.45[28] V VDDIO - 0.45[28] V Output HIGH Voltage (VCORE = Min., IOL = 0.12 mA) LVTTL 0.4[28] 0.4[28] V (VCORE = Min., IOL = 0.12 mA) HSTL (DC) 0.4[28] 0.4[28] V HSTL (AC) [28] [28] (VCORE = Min., IOL = 0.12 mA) 0.5 V (VCORE = Min., IOL = 0.15 mA) 2.5V LVCMOS 0.5 0.7[28] 0.7[28] V (VCORE = Min., IOL = 0.08 mA) 1.8V LVCMOS 0.2[28] 0.2[28] V IOZ Output Leakage Current -10 10 -10 10 A IIX1 Input Leakage Current -10 10 -10 10 A IIX2 Input Leakage Current TDI, TMS, MRST, TRST, TCK -300 10 -300 10 A IIX3 Input Leakage Current PORTSTD, DDRON, VC_SEL -10 300 -10 300 A ICC Operating Current (VCORE = Max.,IOUT = 0 mA) Outputs Disabled TBD TBD TBD mA ISB1 Standby Current (Both Ports TTL Level) CEL and CER VIH, f = fMAX Document #: 38-06072 Rev. *E 512Kx72 TBD TBD TBD 1024Kx36 TBD TBD TBD TBD TBD TBD mA 256Kx72 TBD TBD TBD TBD TBD TBD mA 512Kx36 TBD TBD TBD TBD TBD TBD mA 128Kx72 TBD TBD TBD TBD TBD TBD mA 256Kx36 TBD TBD TBD TBD TBD TBD mA 64Kx72 TBD TBD TBD TBD TBD TBD mA 128Kx36 TBD TBD TBD TBD TBD TBD mA 512Kx72 TBD TBD TBD TBD TBD TBD mA 1024Kx36 TBD TBD TBD TBD TBD TBD mA 256Kx72 TBD TBD TBD TBD TBD TBD mA 512Kx36 TBD TBD TBD TBD TBD TBD mA 128Kx72 TBD TBD TBD TBD TBD TBD mA 256Kx36 TBD TBD TBD TBD TBD TBD mA 64Kx72 TBD TBD TBD TBD TBD TBD mA 128Kx36 TBD TBD TBD TBD TBD TBD mA Page 20 of 48 FullFlex PRELIMINARY Electrical Characteristics Over the Operating Range (continued) -250[15,17] Parameter ISB2 ISB3 ISB4 Description Standby Current (One Port TTL Level) CEL | CER VIH, f = fMAX Standby Current (Both Ports CMOS Level) CEL and CER VCORE - 0.2V, f = 0 Standby Current (One Port CMOS Level) CEL | CER VIH, f = fMAX Document #: 38-06072 Rev. *E -200[16,17] Configuration Min. Typ. Max. Min. Typ. Max. Unit 512Kx72 TBD TBD TBD TBD TBD TBD mA 1024Kx36 TBD TBD TBD TBD TBD TBD mA 256Kx72 TBD TBD TBD TBD TBD TBD mA 512Kx36 TBD TBD TBD TBD TBD TBD mA 128Kx72 TBD TBD TBD TBD TBD TBD mA 256Kx36 TBD TBD TBD TBD TBD TBD mA 64Kx72 TBD TBD TBD TBD TBD TBD mA 128Kx36 TBD TBD TBD TBD TBD TBD mA 512Kx72 TBD TBD TBD TBD TBD TBD mA 1024Kx36 TBD TBD TBD TBD TBD TBD mA 256Kx72 TBD TBD TBD TBD TBD TBD mA 512Kx36 TBD TBD TBD TBD TBD TBD mA 128Kx72 TBD TBD TBD TBD TBD TBD mA 256Kx36 TBD TBD TBD TBD TBD TBD mA 64Kx72 TBD TBD TBD TBD TBD TBD mA 128Kx36 TBD TBD TBD TBD TBD TBD mA 512Kx72 TBD TBD TBD TBD TBD TBD mA 1024Kx36 TBD TBD TBD TBD TBD TBD mA 256Kx72 TBD TBD TBD TBD TBD TBD mA 512Kx36 TBD TBD TBD TBD TBD TBD mA 128Kx72 TBD TBD TBD TBD TBD TBD mA 256Kx36 TBD TBD TBD TBD TBD TBD mA 64Kx72 TBD TBD TBD TBD TBD TBD mA 128Kx36 TBD TBD TBD TBD TBD TBD mA Page 21 of 48 FullFlex PRELIMINARY Electrical Characteristics Over the Operating Range (continued) -167 Parameter VOH Description Configuration Min. Output HIGH Voltage (VCORE = Min., IOH = -8 mA) LVTTL 2.4[28] (VCORE = Min., IOH = -4 mA) HSTL (DC) VDDIO - 0.4[28] V HSTL (AC) [28] V (VCORE = Min., IOH = -4 mA) VOL VIL 2.5V LVCMOS 1.7 (VCORE = Min., IOH = -4 mA) 1.8V LVCMOS 1.6[28] V V Output HIGH Voltage (VCORE = Min., IOL = 8 mA) LVTTL 0.4[28] (VCORE = Min., IOL = 4 mA) HSTL (DC) 0.4[28] V (VCORE = Min., IOL = 4 mA) HSTL (AC) 0.5[28] V (VCORE = Min., IOL = 6 mA) 2.5V LVCMOS 0.7[28] V 1.8V LVCMOS 0.2[28] V Input HIGH Voltage Input LOW Voltage V LVTTL 2 VDDIO + 0.3 V HSTL (DC) VREF + 0.1 VDDIO + 0.3 V HSTL (AC) VREF + 0.2 V 2.5V LVCMOS 1.7 V 1.8V LVCMOS 1.26 V LVTTL -0.3 0.8 HSTL (DC) -0.3 VREF - 0.1 V VREF - 0.2 V 2.5V LVCMOS V 0.7 V 1.8V LVCMOS 0.36 V Output HIGH Voltage (VCORE = Min., IOH = -24 mA) LVTTL 2.7[28] V (VCORE = Min., IOH = -12 mA) HSTL (DC)[29] VDDIO - 0.4[28] V (VCORE = Min., IOH = -12 mA) (AC)[29] VDDIO - 0.5[28] V 2.0[28] V (VCORE = Min., IOH = -15 mA) READY VOL Unit V HSTL (AC) READY VOH Max. [28] (VCORE = Min., IOH = -6 mA) (VCORE = Min., IOL = 4 mA) VIH VDDIO - 0.5 Typ. HSTL 2.5V LVCMOS 0.45[28] (VCORE = Min., IOH = -12 mA) 1.8V LVCMOS Output HIGH Voltage (VCORE = Min., IOL = 0.12 mA) LVTTL 0.4[28] V (VCORE = Min., IOL = 0.12 mA) HSTL (DC) 0.4[28] V (VCORE = Min.,IOL = 0.12 mA) HSTL (AC) 0.5[28] V 2.5V LVCMOS 0.7[28] V 1.8V LVCMOS 0.2[28] V (VCORE = Min., IOL = 0.15 mA) (VCORE = Min., IOL = 0.08 mA) VDDIO - V IOZ Output Leakage Current -10 10 A IIX1 Input Leakage Current -10 10 A IIX2 Input Leakage Current TDI, TMS, MRST, TRST, TCK -300 10 A IIX3 Input Leakage Current PORTSTD, DDRON, VC_SEL -10 300 A Document #: 38-06072 Rev. *E Page 22 of 48 FullFlex PRELIMINARY Electrical Characteristics Over the Operating Range (continued) (continued) -167 Parameter ICC ISB1 ISB2 ISB3 ISB4 Description Operating Current (VCORE = Max.,IOUT = 0 mA) Outputs Disabled Standby Current (Both Ports TTL Level) CEL and CER VIH, f = fMAX Standby Current (One Port TTL Level) CEL | CER VIH, f = fMAX Standby Current (Both Ports CMOS Level) CEL and CER VCORE - 0.2V, f=0 Standby Current (One Port CMOS Level) CEL | CER VIH, f = fMAX Document #: 38-06072 Rev. *E Configuration Min. Typ. Max. Unit 512Kx72 TBD TBD TBD mA 1024Kx36 TBD TBD TBD mA 256Kx72 TBD TBD TBD mA 512Kx36 TBD TBD TBD mA 128Kx72 TBD TBD TBD mA 256Kx36 TBD TBD TBD mA 64Kx72 TBD TBD TBD mA 128Kx36 TBD TBD TBD mA 512Kx72 TBD TBD TBD mA 1024Kx36 TBD TBD TBD mA 256Kx72 TBD TBD TBD mA 512Kx36 TBD TBD TBD mA 128Kx72 TBD TBD TBD mA 256Kx36 TBD TBD TBD mA 64Kx72 TBD TBD TBD mA 128Kx36 TBD TBD TBD mA 512Kx72 TBD TBD TBD mA 1024Kx36 TBD TBD TBD mA 256Kx72 TBD TBD TBD mA 512Kx36 TBD TBD TBD mA 128Kx72 TBD TBD TBD mA 256Kx36 TBD TBD TBD mA 64Kx72 TBD TBD TBD mA 128Kx36 TBD TBD TBD mA 512Kx72 TBD TBD TBD mA 1024Kx36 TBD TBD TBD mA 256Kx72 TBD TBD TBD mA 512Kx36 TBD TBD TBD mA 128Kx72 TBD TBD TBD mA 256Kx36 TBD TBD TBD mA 64Kx72 TBD TBD TBD mA 128Kx36 TBD TBD TBD mA 512Kx72 TBD TBD TBD mA 1024Kx36 TBD TBD TBD mA 256Kx72 TBD TBD TBD mA 512Kx36 TBD TBD TBD mA 128Kx72 TBD TBD TBD mA 256Kx36 TBD TBD TBD mA 64Kx72 TBD TBD TBD mA 128Kx36 TBD TBD TBD mA Page 23 of 48 FullFlex PRELIMINARY Table 14.Capacitance Parameter CIN[30] COUT Description Test Conditions Input Capacitance [30, 31] TA = 25C, f = 1MHz, VDD = 3V[32] Output Capacitance Max. Unit 10 pF 12 pF AC Test Load and Waveforms V REF = 0V V REF 50 O hm 50 O hm O u tp u t T e s t P o in t R =250 O hm READY C = 10pF ZQ D e v ic e u n d e r te s t VTH RQ =250 O hm V T H = 1 .5 V fo r L V T T L V T H = 5 0 % V D D IO fo r 2 .5 V C M O S V T H = 5 0 % V D D IO fo r 1 .8 V C M O S Figure 6. Output Test Load for LVTTL/CMOS V V R E F = 0 .7 5 V R E F 50 O hm 50 O hm O u tp u t T e s t P o in t R = 250 O hm R E A D Y Z Q D e v ic e u n d e r te s t R Q = 250 O hm V T H C = 0 p F fo r D D R C = 1 0 p F fo r S D R V T H = 50% V D D IO Figure 7. Output Test Load for HSTL Notes: 30. Capacitance for the 36M x18 device is 20 pF, capacitance for all other 36M or x18 devices is 12 pF. 31. Cout also references to CI/O. 32. Input and Output switch from 0V to 3V or from 3V to 0V. Document #: 38-06072 Rev. *E Page 24 of 48 FullFlex PRELIMINARY Switching Characteristics Over the Operating Range Table 15.DDR Mode with 2.5 Pipeline Stages and DLL Enabled (LOWSPD-HIGH)[36] -200[16,17,34] Parameter Min. Max. Min. Max. Unit fMAX Maximum Operating Frequency 159 200 127 167 MHz tCYC C/C Clock Cycle Time 5.00 6.3 6.00 7.88 ns tCH C/C Clock HIGH Time 2.00 2.40 ns tCL C/C Clock LOW Time 2.00 2.40 ns tCHCH C/C Clock Rise to C/C Clock Rise 2.20 2.70 ns tSD Description -167[17] Data Input Set-up Time to C/C Rise [35] 0.40 [35] ns [35] 0.50 [35] Data Input Hold Time after C/C Rise 0.40 0.50 ns tSBE Byte enable Set-up Time to C/C Rise 0.40[35] 0.50[35] ns tHBE Byte enable Hold Time after C/C Rise 0.40[35] 0.50[35] ns tSAC Address & Control Input except BE Set-up Time to C Rise 1.50 1.70 ns tHAC Address & Control Input except BE Hold Time after C Rise 0.50 tHD tOE Output Enable to Data Valid tOLZ[33] OE to Low Z 1.00 OE to High Z 1.00[35] tOHZ[33] 0.60 4.40[35] 1.00 4.40[35] 1.00[35] 0.50[35] tCD C/C Rise to DQ Valid tDC DQ Output Hold after C/C Rise -0.50 tCCQ C/C Rise to CQ/CQ Rise -0.50 tCQHQV Echo Clock (CQ/CQ) High to Output Valid, SC = LOW tCQHQX Echo Clock (CQ/CQ) High to Output Hold, SC = LOW ns 5.00[35] ns 5.00[35] ns 0.60[35] ns 0.60 ns 0.40[35] ns -0.60 0.50 -0.60 0.35[35] -0.35 ns ns -0.40 ns tCKHZ[33] tCKLZ[33] C Rise to DQ Output High Z tCA C Rise to Address Readback Valid tAC Address Output Hold after C Rise tCKHZA[33] tCKLZA[33] C Rise to Address Output High Z 1.00 C Rise to Address Output Low Z 1.00 tSCINT C Rise to CNTINT Low 1.00 3.30 1.00 4.00 ns tRCINT C Rise to CNTINT High 1.00 3.30 1.00 4.00 ns tSINT C Rise to INT Low 0.50 7.00 0.50 8.00 ns tRINT C Rise to INT High 0.50 7.00 0.50 8.00 ns tBSY C Rise to BUSY Valid 1.00 3.30 1.00 4.00 ns C Rise to DQ Output Low Z 0.50[35] -0.50 0.60[35] -0.60 5.00 1.00 ns 6.00 1.00 5.00 1.00 ns ns ns 6.00 1.00 ns ns Notes: 33. Parameters specified with the load capacitance in Figure 6 and Figure 7. 34. These parameters apply for the HSTL and 1.8V LVCMOS standards. 35. For the x18 devices, add 200 ps to this parameter in the table above. 36. Test conditions assume a signal transition time of 2 V/ns Document #: 38-06072 Rev. *E Page 25 of 48 FullFlex PRELIMINARY Table 16.SDR Mode with DLL Enabled (LOWSPD-HIGH) [36] -250[15,17] Parameter Description fMAX (PIPELINED) Maximum Operating Frequency for Pipelined Mode fMAX (FLOW-THROUGH) Maximum Operating Frequency for Flow-through Mode -200[15,17] -167[17] Min. Max. Min. Max. Min. Max. Unit 100 250 100 200 100 167 MHz 66.7 MHz 100 tCYC (PIPELINED) C Clock Cycle Time for Pipelined mode 4.00 tCYC (FLOW-THROUGH) C Clock Cycle Time for Flow-through mode 10.00 tCKD C Clock Duty Time 45 tCHCH C/C Clock Rise to C/C Clock Rise N/A 10.00 77 5.00 10.00 13.00 55 45 55 N/A [35] 6.00 10.00 15.00 45 55 N/A [35] [35] ns ns % ns tSD Data Input Set-up Time to C Rise 1.20 1.50 1.70 ns tHD Data Input Hold Time after C Rise 0.50[35] 0.50[35] 0.50[35] ns tSAC Address & Control Input Set-up Time to C Rise 1.20 1.50 1.70 ns tHAC Address & Control Input Hold Time after C Rise 0.50 0.50 0.60 ns tOE Output Enable to Data Valid tOLZ[33] tOHZ[33] OE to Low Z tCD1 C Rise to DQ Valid for Flow-through Mode (LowSPD = 1) tCD2 OE to High Z 3.40[35] 1.00 4.40[35] 5.00[35] ns 1.00 ns 4.40[35] 1.00[35] 5.00[35] ns 1.00 1.00[35] 3.40 [35] 1.00[35] 7.20 9.00 11.00 ns C Rise to DQ Valid for Pipelined Mode (LowSPD = 1) 2.6 [35] 3.30[35] 4.00[35] ns tCA1 C Rise to Address Readback Valid for Flow-through Mode 7.20 9.00 11.00 ns tCA2 C Rise to Address Readback Valid for Pipelined Mode 4.00 5.00 6.00 ns tDC DQ Output Hold after C Rise 1.00 tCCQ C Rise to CQ Rise 1.00 1.00 2.64 1.00 0.70[35] 1.00 3.30 1.00 0.76[35] Echo Clock (CQ) High to Output Valid tCQHQX Echo Clock (CQ) High to Output Hold -0.66 tCKHZ1[33] C Rise to DQ Output High Z in Flow-through Mode 1.00 tCKLZ1[33] C Rise to DQ Output Low Z in Flow-Through Mode 1.00 tCKHZ2[33] C Rise to DQ Output High Z in Flow-through Mode tCKLZ2[33] C Rise to DQ Output Low Z in Flow-Through Mode 1.00 1.00 1.00 tAC 1.00 1.00 7.20 1.00 -0.76 9.00 1.00 1.00[35] 2.64 [35] 1.00[35] 4.00 0.80[35] tCQHQV -0.72 ns 1.00 ns ns ns 11.00 1.00 ns ns 3.30[35] 1.00[35] 4.00[35] Address Output Hold after C Rise 1.00 [33] C Rise to Address Output High Z for flow-through mode 1.00 7.20 1.00 9.00 1.00 11.00 ns tCKHZA2[33] C Rise to Address Output High Z for pipelined mode 1.00 4.00 1.00 5.00 1.00 6.00 ns tCKLZA[33] C Rise to Address Output Low Z 1.00 tSCINT C Rise to CNTINT Low 1.00 2.64 1.00 3.30 1.00 4.00 ns tRCINT C Rise to CNTINT High 1.00 2.64 1.00 3.30 1.00 4.00 ns tCKHZA1 Document #: 38-06072 Rev. *E 1.00 ns 1.00 ns Page 26 of 48 FullFlex PRELIMINARY Table 16.SDR Mode with DLL Enabled (LOWSPD-HIGH) (continued)[36] -250[15,17] Parameter Description -200[15,17] -167[17] Min. Max. Min. Max. Min. Max. Unit tSINT C Rise to INT Low 0.50 6.00 0.50 7.00 0.50 8.00 ns tRINT C Rise to INT High 0.50 6.00 0.50 7.00 0.50 8.00 ns tBSY C Rise to BUSY Valid 1.00 2.64 1.00 3.30 1.00 4.00 ns Table 17.SDR Mode with DLL Disabled (LOWSPD-LOW)[36] -100 Parameter Description Min. Max. Unit fMAX (PIPELINED) Maximum Operating Frequency for Pipelined mode 100 MHz fMAX (FLOW-THROUGH) Maximum Operating Frequency for Flow-through mode 55.6 MHz tCYC (PIPELINED) C Clock Cycle Time for Pipelined mode 7.00 10.00 ns tCYC (FLOW-THROUGH) C Clock Cycle Time for Flow-through mode 18.00 tCKD C Clock Duty Time 45 tCHCH C/C Clock Rise to C/C Clock Rise N/A ns tSD Data Input Set-up Time to C Rise 1.80[35] ns tHD Data Input Hold Time after C Rise 0.50[35] ns tSAC Address & Control Input Set-up Time to C Rise 1.80 ns tHAC Address & Control Input Hold Time after C Rise 0.70 ns tOE Output Enable to Data Valid tOLZ[33] tOHZ[33] OE to Low Z 1.00 OE to High Z 1.00[35] tCD1 C Rise to DQ Valid for Flow-through Mode (LowSPD = 0) tCD2 C Rise to DQ Valid for Pipelined Mode (LowSPD = 0) tCA1 C Rise to Address Readback Valid for Flow-through Mode tCA2 C Rise to Address Readback Valid for Pipelined Mode tDC DQ Output Hold after C Rise 1.00 tCCQ C Rise to CQ Rise 1.00 ns 55 5.50[35] Echo Clock (CQ) High to Output Valid tCQHQX Echo Clock (CQ) High to Output Hold -0.90 tCKHZ1[33] C Rise to DQ Output High Z in Flow-through Mode 1.00 tCKLZ1[33] C Rise to DQ Output Low Z in Flow-Through Mode 1.00 ns ns 13.00 ns 6.00[35] ns 13.00 ns 7.50 ns ns 6.00 0.90 [35] ns 5.50[35] [35] tCQHQV % ns ns ns 13.00 ns ns [35] [33] C Rise to DQ Output High Z in Flow-through Mode [33] C Rise to DQ Output Low Z in Flow-Through Mode 1.00 Address Output Hold after C Rise 1.00 tCKHZA1 [33] C Rise to Address Output High Z for flow-through mode 1.00 13.00 ns tCKHZA2 [33] C Rise to Address Output High Z for pipelined mode 1.00 7.50 ns tCKHZ2 tCKLZ2 tAC 1.00 6.00 ns tCKLZA[33] C Rise to Address Output Low Z 1.00 tSCINT C Rise to CNTINT Low 1.00 4.50 ns tRCINT C Rise to CNTINT High 1.00 4.50 ns tSINT C Rise to INT Low 0.50 8.50 ns tRINT C Rise to INT High 0.50 8.50 ns tBSY C Rise to BUSY Valid 1.00 4.50 ns Document #: 38-06072 Rev. *E ns Page 27 of 48 FullFlex PRELIMINARY Table 18.Master Reset Timing -250[15,17] Parameter Description Min. Max. -200[16,17] Min. Max. -167 Min. Max. Unit tPUP Power-up Time tRS Master Reset Pulse Width 5 5 5 cycles tRSR Master Reset Recovery Time 5 5 5 cycles tRSF Master Reset to Outputs Inactive/Hi-Z 10 10 10 ns tRDY[37] Master Reset Release to Port Ready 1024 1024 1024 cycles tCORDY[38] C Rise to Port Ready 8 9.5 11 ns 1 1 1 ms Table 19.JTAG Timing -250[15,17] Parameter Description Min. Max. -200[16,17] Min. Max. -167[17] Min. Max. Unit 20 MHz fJTAG JTAG TAP Controller Frequency tTCYC TCK Cycle Time 50 50 50 ns tTH TCK High Time 20 20 20 ns tTL TCK Low Time 20 20 20 ns tTMSS TMS Set-up to TCK Rise 10 10 10 ns tTMSH TMS Hold to TCK Rise 10 10 10 ns tTDIS TDI Set-up to TCK Rise 10 10 10 ns tTDIH TDI Hold to TCK Rise 10 10 10 ns tTDOV TCK Low to TDO Valid tTDOX TCK Low to TDO Invalid tJXZ TCK Low to TDO hi-Z 15 15 15 ns tJZX TCK Low to TDO Active 15 15 15 ns 20 20 10 0 10 0 10 0 ns ns Notes: 37. READY is a wired OR capable output with a weak pull-down. For a decreased falling delay, connect a 250 Ohm resistor to VSS. 38. Add this propagation delay after tRDY for all Master Reset Operations Document #: 38-06072 Rev. *E Page 28 of 48 FullFlex PRELIMINARY Switching Waveforms (continued) READ Cycle for Pipelined Mode, DDRON = LOW tCYC C tSAC tHAC R/W A An An+1 2 pipeline stages DQ DQx-1 An+2 DQx DQn An+3 An+4 DQn+1 tDC An+5 An+6 DQn+2 DQn+3 DQn+4 tCD WRITE Cycle for Pipelined and Flow-Through Modes, DDRON = LOW tCYC C R/W A An An+1 An+2 An+3 An+4 An+5 An+6 DQn+1 DQn+2 DQn+3 DQn+4 DQn+5 DQn+6 2 pipeline stages DQ DQn tSD Document #: 38-06072 Rev. *E tHD Page 30 of 48 FullFlex PRELIMINARY Switching Waveforms (continued) READ with Address Counter Advance for Pipelined Mode, DDRON = LOW tCYC C An A Internal Address An An+1 An+2 An+3 ADS CNTEN DQ DQx-1 DQx DQn DQn+1 DQn+2 DQn+3 READ with Address Counter Advance for Flow-Through Mode, DDRON = LOW t CYC C tSAC t HAC A An ADS tSAC tH AC CNTEN t CD1 DQ DQx DQn DQ n + 1 DQn + 2 DQn + 3 DQn + 4 tDC READ EXTERNAL ADDRESS Document #: 38-06072 Rev. *E READ W ITH COUN TER COUN TER H OLD READ W ITH CO UNTER Page 31 of 48 FullFlex PRELIMINARY Switching Waveforms (continued) Mailbox Interrupt Output, DDRON = LOW tCYC CL AL AMAX R/WL DQL INTR tSINT tRINT CR AR AMAX R/WR DQR Document #: 38-06072 Rev. *E DQMAX Page 32 of 48 FullFlex PRELIMINARY Switching Waveforms (continued) Port-to-Port WRITE-READ for Pipelined Mode, DDRON = LOW tCYC Left Port CL AL An R/WL DQL DQn Right Port CR tCCS tCYC AR An R/WR tSAC tHAC DQR DQn tCD2 tDC Chip Enable READ for Pipelined Mode, DDRON = LOW tCYC C CE0 CE1 R/W tSAC tHAC A An An+1 An+3 An+4 tCD2 An+5 An+6 DQn+3 DQn DQ Document #: 38-06072 Rev. *E An+2 tCKHZ2 tCKLZ2 Page 33 of 48 FullFlex PRELIMINARY Switching Waveforms (continued) OE Controlled WRITE for Pipelined Mode, DDRON = LOW tCYC C A Ax+1 Ax+2 Ax+3 An An+1 An+2 An+3 DQn DQn+1 DQn+2 DQn+3 An An+1 An+2 An+3 DQn DQn+1 DQn+2 DQn+3 R/W OE tOHZ DQx+1 DQ DQx-1 DQx OE Controlled WRITE for Flow-Through Mode, DDRON = LOW tCYC C A Ax+1 Ax+2 Ax+3 R/W OE tOHZ DQx+2 DQ DQx DQx+1 Document #: 38-06072 Rev. *E Page 34 of 48 FullFlex PRELIMINARY Switching Waveforms (continued) Byte-Enable READ for Pipelined Mode, DDRON = LOW tCYC C A An An+1 An+2 An+3 R/W BE7 BE6 BE5 BE4 BE3 BE2 BE1 BE0 tCKLZ2 t DQn+1(63:71) CKHZ2 DQ63:71 DQ54:62 DQn+1(54:62) DQn+2(45:53) DQ45:53 DQn+2(36:44) DQ36:44 DQn+1(27:35) DQ27:35 DQ18:26 DQ9:17 DQ0:8 Document #: 38-06072 Rev. *E DQn+2(18:26) DQn+3(9:17) DQn+3(0:8) Page 35 of 48 FullFlex PRELIMINARY Switching Waveforms (continued) Port-to-Port WRITE-to-READ for Flow-Through Mode, DDRON = LOW CL R/W L t SAC AL t HAC NO MATCH MATCH t SD t HD VALID DQ L t CCS CR t CD1 R/W R t HAC t SAC AR NO MATCH MATCH t CD1 VALID DQ R VALID t DC t DC Busy Address Readback for Pipelined and Flow-Through Modes, DDRON = LOW[39] tCYC ~ C Internal Address Amatch+2 Amatch+3 Amatch+4 ~ BUSY ~ CNTEN ~ ADS External Address ~ ~ Amatch tCA tAC Note: 39. Amatch is the matching address which will be reported on the address bus of the losing port. The counter operation selected for reporting the address is "Busy Address Readback." Document #: 38-06072 Rev. *E Page 36 of 48 FullFlex PRELIMINARY Switching Waveforms (continued) Read Cycle for Flow-Through Mode, DDRON = LOW t CYC C CE 0 tSAC t HAC CE 1 BEn R/W tSAC A t HAC An + 1 An tCD1 An + 2 An + 3 t CKHZ1 tDC DQ DQn DQn + 1 t CKLZ1 DQn + 2 tDC t OLZ tOHZ OE t OE READ-to-WRITE for Pipelined Mode, DDRON = LOW (OE = VIL)[40, 41, 42] tCYC tCL C A tCH Ax An An+1 tSAC tHAC An+2 tSAC tHAC R/W DQ DQx-2 DQx-1 tCD2 DQx tDC DQn tCKHZ2 DQn+1 DQn+2 tSD tHD Notes: 40. When OE = VIL, the last read operation is allowed to complete before the DQ bus is tri-stated and the user is allowed to drive write data. 41. Two dummy writes should be issued to accomplish bus turnaround. The third instruction is the first valid write. 42. Chip enable or all byte enables should be held inactive during the two dummy writes to avoid data corruption. Document #: 38-06072 Rev. *E Page 37 of 48 FullFlex PRELIMINARY Switching Waveforms (continued) READ-to-WRITE for Pipelined Mode, DDRON = LOW (OE Controlled)[43, 44] tCYC C A Ax Ax+1 Ax+2 An An+1 An+2 An+3 DQn+1 DQn+2 DQn+3 tSAC tHAC R/W OE tOHZ tSD tHD DQx DQ DQx-2 DQx-1 DQn READ-to-WRITE-to-READ for DDR, DDRON = HIGH[40,41,45,46] tCH tCL C tCYC C A tSAC t HAC tCHCH tCHCH An Ax tSAC An+2 An+1 tHAC R/W tCKHZ DQ DQx-2[0] DQn[1] DQn[0] DQ [0] DQ [0] DQn+1[1] n+1 DQn+2[1] n+2 DQ [1] n+2 DQx-1[1] DQx-1[0] DQx[1] DQx[0] tCD tDC tSD tHD Notes: 43. OE should be deasserted and tOHZ allowed to elapse before the first write operation is issued. 44. Any write scheduled to complete after OE is deasserted will be preempted. 45. The address should be held constant during the two dummy writes and first valid write to avoid data corruption. 46. D[1] / Q [1] contains data [71:36]; D[0] / Q[0] contains data [35:0]. Document #: 38-06072 Rev. *E Page 38 of 48 FullFlex PRELIMINARY Switching Waveforms (continued) Read-to-Write-to-Read for Flow-Through Mode, DDRON = LOW (OE = LOW) tCYC C tSAC tHAC CE 0 CE 1 BEn t SAC t HAC R/W A An An + 1 An + 2 An + 2 tSD DQ IN An + 3 An + 4 tHD DQn + 2 tCD1 tCD1 DQn DQ OUT tCD1 DQn + 1 t CD1 DQn + 3 t CKHZ1 tCKLZ1 tDC READ Document #: 38-06072 Rev. *E tDC NOP W RITE READ Page 39 of 48 FullFlex PRELIMINARY Switching Waveforms (continued) Read-to-Write-to-Read for Flow-Through Mode, DDRON = LOW (OE Controlled) tCYC C tSAC tHAC CE0 CE1 BEn tSAC tHAC R/W A An An + 1 An + 2 tSD DQIN DQOUT An + 4 An + 5 tHD DQn + 2 tCD1 An + 3 DQn + 3 tDC tOE tCD1 tCD1 DQn DQn + 4 tCKLZ1 tOHZ tDC OE READ Document #: 38-06072 Rev. *E WRITE READ Page 40 of 48 FullFlex PRELIMINARY Switching Waveforms (continued) BUSY Timing, WRITE-WRITE Collision for Pipelined and Flow-Through Modes, Clock Timing Violates tCCS. (Flag Both Ports) Port A C A R/W BUSY < tCCS tBSY tBSY Port B C A R/W tBSY BUSY tBSY BUSY Timing, WRITE-WRITE Collision for Pipelined and Flow-Through Modes, Clock Timing Meets tCCS. (Flag Losing Port) Losing Port C A R/W BUSY tccs tBSY tBSY Winning Port C A Match R/W BUSY Document #: 38-06072 Rev. *E Page 41 of 48 FullFlex PRELIMINARY Switching Waveforms (continued) Read with Echo Clock for Pipelined and Flow-Through Modes (CQEN = HIGH) C tSAC tHAC R/W A An An+1 An+2 An+3 An+4 An+5 An+6 CQ0 CQ0 tCCQ CQ1 CQ1 tCQHQX tCQHQV DQ DQx-1 DQx Document #: 38-06072 Rev. *E DQn DQn+1 DQn+2 DQn+3 DQn+4 Page 42 of 48 PRELIMINARY FullFlex Ordering Information 512K x 72 (36 Mbit) 1.8V Synchronous CYDD36S72V18 Dual-Port SRAM (SDR and DDR I/O) Speed (MHz) Ordering Code Package Name 200 CYDD36S72V18-200BBC BY484 484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (PBGA) Commercial CYDD36S72V18-200BBI BY484 484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (PBGA) Industrial CYDD36S72V18-167BBC BY484 484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (PBGA) Commercial CYDD36S72V18-167BBi BY484 484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (PBGA) Industrial 167 Package Type Operating Range 256K x 72 (18 Mbit) 1.8V Synchronous CYDD18S72V18 Dual-Port SRAM (SDR and DDR I/O) Speed (MHz) Ordering Code Package Name Package Type Operating Range 250 CYDD18S72V18-250BBC BY484 484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (PBGA) Commercial 200 CYDD18S72V18-200BBC BY484 484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (PBGA) Commercial CYDD18S72V18-200BBI BY484 484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (PBGA) Industrial 167 CYDD18S72V18-167BBC BY484 484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (PBGA) Commercial CYDD18S72V18-167BBI BY484 484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (PBGA) Industrial 128K x 72 (9 Mbit) 1.8V Synchronous CYDD09S72V18 Dual-Port SRAM (SDR and DDR I/O) Speed (MHz) Ordering Code Package Name 200 CYDD09S72V18-200BBC BY484 484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (PBGA) Commercial CYDD09S72V18-200BBI BY484 484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (PBGA) Industrial CYDD09S72V18-167BBC BY484 484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (PBGA) Commercial CYDD09S72V18-167BBI BY484 484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (PBGA) Industrial 167 Package Type Operating Range 64K x 72 (4 Mbit) 1.8V Synchronous CYDD04S72V18 Dual-Port SRAM (SDR and DDR I/O) Speed (MHz) Ordering Code Package Name Package Type Operating Range 250 CYDD04S72V18-250BBC BY484 484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (PBGA) Commercial 200 CYDD04S72V18-200BBC BY484 484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (PBGA) Commercial CYDD04S72V18-200BBI BY484 484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (PBGA) Industrial 167 CYDD04S72V18-167BBC BY484 484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (PBGA) Commercial CYDD04S72V18-167BBI BY484 484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (PBGA) Industrial 1024K x 36 (36 Mbit) 1.8V Synchronous CYDD36S36V18 Dual-Port SRAM (DDR only I/O) Speed (MHz) Ordering Code Package Name Package Type Operating Range 200 CYDD36S36V18-200BBC BY484 484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (PBGA) Commercial 167 CYDD36S36V18-167BBC BY484 484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (PBGA) Commercial CYDD36S36V18-167BBI BY484 484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (PBGA) Industrial 512K x 36 (18 Mbit) 1.8V Synchronous CYDD18S36V18 Dual-Port SRAM (DDR only I/O) Speed (MHz) Ordering Code Package Name 200 CYDD18S36V18-200BBC BW256C 256-ball Grid Array 19 mm x 19 mm with 1.0 mm pitch (FBGA) Commercial 167 CYDD18S36V18-167BBC BW256C 256-ball Grid Array 19 mm x 19 mm with 1.0 mm pitch (FBGA) Commercial CYDD18S36V18-167BBI BW256C 256-ball Grid Array 19 mm x 19 mm with 1.0 mm pitch (FBGA) Industrial Document #: 38-06072 Rev. *E Package Type Operating Range Page 43 of 48 PRELIMINARY FullFlex Ordering Information (continued) 256K x 36 (9 Mbit) 1.8V Synchronous CYDD09S36V18 Dual-Port SRAM (DDR only I/O) Speed (MHz) Ordering Code Package Name 200 CYDD09S36V18-200BBC BB256 256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (FBGA) Commercial 167 CYDD09S36V18-167BBC BB256 256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (FBGA) Commercial CYDD09S36V18-167BBI BB256 256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (FBGA) Industrial Package Type Operating Range 128K x 36 (4 Mbit) 1.8V Synchronous CYDD04S36V18 Dual-Port SRAM (DDR only I/O) Speed (MHz) Ordering Code Package Name 200 CYDD04S36V18-200BBC BB256 256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (FBGA) Commercial 167 CYDD04S36V18-167BBC BB256 256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (FBGA) Commercial CYDD04S36V18-167BBI BB256 256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (FBGA) Industrial Package Type Operating Range 2048K x 18 (36 Mbit) 1.8V Synchronous CYDD36S18V18 Dual-Port SRAM (DDR only I/O) Speed (MHz) Ordering Code Package Name Package Type Operating Range 200 CYDD36S18V18-200BBC BY484 484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (PBGA) Commercial 167 CYDD36S18V18-167BBC BY484 484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (PBGA) Commercial CYDD36S18V18-167BBI BY484 484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (PBGA) Industrial 1024K x 18 (18 Mbit) 1.8V Synchronous CYDD18S18V18 Dual-Port SRAM (DDR only I/O) Speed (MHz) Ordering Code Package Name 200 CYDD18S18V18-200BBC BW256C 256-ball Grid Array 19 mm x 19 mm with 1.0 mm pitch (FBGA) Commercial 167 CYDD18S18V18-167BBC BW256C 256-ball Grid Array 19 mm x 19 mm with 1.0 mm pitch (FBGA) Commercial CYDD18S18V18-167BBI BW256C 256-ball Grid Array 19 mm x 19 mm with 1.0 mm pitch (FBGA) Industrial Package Type Operating Range 512K x 18 (9 Mbit) 1.8V Synchronous CYDD09S18V18 Dual-Port SRAM (DDR only I/O) Speed (MHz) Ordering Code Package Name 200 CYDD09S18V18-200BBC BB256 256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (FBGA) Commercial 167 CYDD09S18V18-167BBC BB256 256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (FBGA) Commercial CYDD09S18V18-167BBI BB256 256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (FBGA) Industrial Package Type Operating Range 256K x 18 (4 Mbit) 1.8V Synchronous CYDD04S18V18 Dual-Port SRAM (DDR only I/O) Speed (MHz) Ordering Code Package Name 200 CYDD04S18V18-200BBC BB256 256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (FBGA) Commercial 167 CYDD04S18V18-167BBC BB256 256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (FBGA) Commercial CYDD04S18V18-167BBI BB256 256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (FBGA) Industrial Document #: 38-06072 Rev. *E Package Type Operating Range Page 44 of 48 FullFlex PRELIMINARY Package Diagrams TOP VIEW 256-Ball FBGA (17 x 17 mm) BB256 BOTTOM VIEW O0.05 M C O0.25 M C A B PIN 1 CORNER O0.450.05(256X)-CPLD DEVICES (37K & 39K) PIN 1 CORNER 1 2 3 4 5 6 7 8 9 +0.10 -0.05 O0.50 (256X)-ALL OTHER DEVICES 10 11 12 13 14 15 16 16 15 14 13 12 11 10 9 8 7 6 5 4 2 1 A A B B C D 1.00 C D E E F F G H J K H 15.00 17.000.10 G J K L M 7.50 L M N N P P R R T T 1.00 7.50 0.15 C 0.700.05 B 0.25 C 3 15.00 A 17.000.10 A 0.20(4X) SEATING PLANE +0.10 -0.05 C A1 0.36 0.56 A 1.40 MAX. 1.70 MAX. Document #: 38-06072 Rev. *E REFERENCE JEDEC MO-192 0.35 A1 51-85108-*F Page 45 of 48 FullFlex PRELIMINARY Package Diagrams (continued) 256 FBGA (19 x 19 x 1.7 mm) BW256C BOTTOM VIEW TOP VIEW A1 CORNER O0.05 M C O0.25 M C A B PIN A1 CORNER 1 O0.50 (256 X) 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 B C C D D E E F F G G 19.00 +/- 0.10 H J K L 1.00 (REF) A B 15.00 (REF) A H J K L M M N N P P R R T T 1.00 (REF) -B- 15.00 (REF) -A- 19.00 +/- 0.10 Package Weight - 1.1 grams 0.15 C 0.70 (REF) 0.25 C 0.15(4X) 001-00915-*A Document #: 38-06072 Rev. *E 1.70 MAX. 0.35 +0.10/-0.05 SEATING PLANE 0.56 (REF) -C- Jedec Outline - Design Guide 4.14 Page 46 of 48 FullFlex PRELIMINARY Package Diagrams (continued) 484-ball PBGA (23 mm x 23 mm x 2.03 mm) BY484 O0.50~O0.70(484X) PIN #1 CORNER 1 3 2 5 4 7 6 9 8 10 15 13 11 12 14 19 17 16 18 21 20 21 22 22 O1.00(3X) REF. 20 18 16 14 9 11 13 15 12 10 7 8 1 3 5 6 4 2 A B C D E F G H J K L M N P R T U V W Y AA AB 21.00 23.000.20 20.00 REF. 1.00 A B C D E F G H J K L M N P R T U V W Y AA AB 17 19 1.00 -B- 21.00 3.20*45(4x) -A20.00 REF. 23.000.20 0.35 C 0.20 C f 0.25 C 30 TYP. f 0.97 REF. 0.20(4X) 2.03 0.13 0.40~0.60 SEATING PLANE 0.56 REF. -C- Package Weight - 2.0 grams Jedec Outline - Design Guide 4.14 51-85218-** FullFlex is a trademark of Cypress Semiconductor Corporation. All product and company names mentioned in this document are trademarks of their respective holders. Document #: 38-06072 Rev. *E Page 47 of 48 (c) Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. PRELIMINARY FullFlex Document History Page Document Title: FullFlexTM Synchronous DDR Dual-Port SRAM Document Number: 38-06072 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 274729 See ECN SPN New data sheet *A 294239 See ECN SPN Updated VIM section Added notes 7 Added timing for 100 MHz with DLL Disabled Removed tPS *B 301331 See ECN SPN Added note 19 Updates Selectable I/O Standard Section *C 318834 See ECN SPN Updated Block Diagram Updated 484 pinouts, changed pins D11, W12, K3, K20 Added note 4 - Leaving pin NC disables VIM Updated 256 pinout, changed pins C10, G5, N7, N10 Added note 18, 19, 20, 21 Updated parameters in table 16 Updated note 1 *D 386692 See ECN SPN Updated ordering information Added statement about no echo clocks for flow-through mode Updated electrical characteristics Added note 27 (timing for x18 devices) Updated address readback latency to 2 cycles for DDR mode Updated DDR timing numbers for tCD, tDC, tCCQ, tCQHQV, tCQHQX, tCKHZ, tCKLZ Updated input edge rate Removed -133 speed bin electrical characteristics and timing columns Updated Table 5 on collision detection to be the same as the one found in the EROS Added description of busy readback in collision detection section Changed dummy write descriptions Updated PORTSTD[1:0] connection details Updated ZQ pins connection details Updated address count notes Updated note 17, BO to BEO Added power supply requirements to MRST and VC_SEL Updated 484 ball package Changed name from FLEX72-E, FLEX36-E, AND FLEX18-E to FullFlex72, FullFlex36, and FullFlex18 *E 401662 See ECN KGH Updated READY description to include Wired OR note Updated master reset to include wired OR note for READY Updated electrical characteristics to include IOH and IOL values Updated electrical characteristics to include READY Added IIX3 Updated maximum input capacitance Added note 29 Updated Pin Definitions for CQ0, CQ0, CQ1, and CQ1 Changed voltage name from VDDQ to VDDIO Changed voltage name from VDD to VCORE Updated the Package Type for the CYDXXS36V18 parts Updated the Package Type for the CYDXXS18V18 parts Included the Package Diagram for the 256-Ball FBGA (19 x 19 mm) BW256 Included an OE Controlled Write for Flow-Through Mode Switching Waveform Included a Read with Echo Clock Switching Waveform Included a Unit column for Table 5 Removed Switching Characteristic tCA from chart Included tOHZ in Switching Waveform OE Controlled Write for Pipelined Mode Included tCKLZ2 in Waveform Read-to-Write-to-Read for Flow-Through Mode Updated AC Test Load and Waveforms Included FullFlex36 DDR 484-ball BGA Pinout (Top View) Included FullFlex18 DDR 484-ball BGA Pinout (Top View)Included Timing Parameter tCORDY Document #: 38-06072 Rev. *E Page 48 of 48