Enpirion
®
Power Datasheet
EV1340QI 5A PowerSoC
Synchronous Highly Integrated DC-DC
DDR2/3/4/QDR
TM
Memory Termination
And Low VIN Operation
www.altera.com/enpirion
Description
The EV1340 is a Power System on a Chip
(PowerSoC) DC to DC converter in a 54 pin QFN
that is optimized for DDR2, DDR3, DDR4 and
QDR
TM
VTT applications. It requires a nominal
3.3V power supply (AVIN) for the controller, and
an input supply (VDDQ) voltage range of 1.0V to
1.8V. It provides a tightly regulated and very
stable output voltage (VTT) which tracks VDDQ
while sinking and sourcing up to 5A of output
current. In addition, the EV1340 is an excellent
solution for general low V
IN
applications where
high efficiency is critical.
The EV1340 utilizes innovative circuit
techniques, high-density circuit integrations and
optimized switching frequency along with Altera
Enpirion’s proprietary inductor technology to
deliver high-quality, ultra compact, non-isolated
DC-DC conversion.
The complete power converter solution enhances
productivity by offering greatly simplified board
design, layout and manufacturing requirements.
Figure 1: EV1340 Total Solution Size ~ 125mm
2
(not to scale)
Features
High Efficiency, Up to 91%
Output Voltage Can Track VDDQ to within
+/- 1.5%
Source and Sink Capability up to 5A
125mm
2
Total Solution Size
VDDQ Range (1.0V to 1.8V )
Monotonic Startup With Pre-bias
Programmable Soft-Start Time
Thermal Shutdown Protection
Over Current and Short Circuit Protection
Under-Voltage Protection
RoHS Compliant, MSL level 3, 260°C reflow
Applications
Bus Termination: DDR2, DDR3, DDR4 &
QDR™ Memory
General Low V
IN
Applications
V
TT
V
DDQ
C
OUT 1 ,2
C
IN
VOUT
ENABLE
AGND
VREF
VDDQ
AVIN
PGND PGND
EV1340
C
SS
R
A
V
CNTRL
VFB
R
B
R
C
R
D
SW
FQADJ
R
FS
R
1
C
A
SCHOTTKY
C1
C
AVIN
Figure 2: Typical V
TT
Application Schematic (V
DDQ
is
the memory core voltage; V
TT
is memory
termination voltage that tracks V
DDQ
)
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Ordering Information
Part Number Temp Rating
(°C) Package
EV1340QI -40 to +85 54-pin QFN T&R
EVB-EV1340QI QFN Evaluation Board
Pin Assignments (Top View)
Figure 3: Pinout Diagram (Top View).
All pins must be soldered to PCB
NOTE: There are specific keep-out areas underneath the
EV1340 to consider when laying out a PCB for this device.
Please see Figures 8, 10, and 11 for more layout d etails.
Pin Description
PIN NAME FUNCTION
1-9, 18,
36, 37, 53,
54
NC
NO CONNECT: These pins must be soldered to PCB but not electrically connected to each
other or to any external signal, voltage, or ground. These pins may be connected internally.
Failure to follow this guideline may result in device damage.
10 -17 VOUT Regulated converter output. Decouple with output filter capacitor to PGND. Refer to layout
section for specific layout requirements
19, 20, SW
These pins are internally connected to the common switching node of the internal MOSFETs.
The anode of a Schottky diode needs to be connected to these pins. The cathode of the
diode needs to be connected to VDDQ.
21-27 PGND Input and output power ground. Refer to layout section for specific layout requirements.
28-31 VDDQ
In DDR applications the input to this pin is the DDR core voltage. This is the input power
supply to the power train which will be divided by two to create an output voltage that tracks
with the input voltage applied to this pin. Decouple with input capacitor to PGND. Refer to
layout section for specific layout requirements
32 AGND2 Ground for the gate driver supply. Connect to the GND plane with a via next to the pin.
33, 39 AVIN1,
AVIN2
Analog input voltage for the controller circuits. Each of these pins needs to be separately
connected to the 3.3V input supply. Decouple with a capacitor to AGND.
34 VDDB
Internal regulated voltage used for the internal control circuitry. This pin is reserved for Altera
Enpirion testing, and should be left floating.
35 BGND This pin is reserved for Altera Enpirion testing, and should be left floating.
38 ENABLE
This is the Device Enable pin. Floating this pin or a high level enables the device while a low
level disables the device.
40 AGND This is the quiet ground for the controller. Connect to the GND plane with a via next to the pin.
41 POK
POK is a logical AND of VDDQOK and the internally generated POK of the EV1340. POK is
an open drain logic output that requires an external pull-up resistor. This pin guarantees a
logic low even when the EV1340 is completely un-powered. This pin can sink a maximum
4mA. The pull-up resistor may be connected to a power supply other than AVIN or VDDQ but
the voltage should be <3.6Volts.
42 VFB
This is the feedback input pin which is always active. A resistor divider connects from the
output to AGND. The mid-point of the resistor divider is connected to VFB. (A feed-forward
capacitor and a resistor are required across the upper resistor.) The output voltage regulates
so as to make the VFB node voltage = 600mV.
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PIN NAME FUNCTION
43 EAOUT Optional Error Amplifier Output. Allows for customization of the control loop.
44 VREF
External voltage reference input. A resistor divider connects from VDDQ to AGND. The mid-
point of the resistor divider is connected to VREF. The resistor divider has to be chosen to
make the voltage applied to this pin 600mV. An optional capacitor (for soft-start) may be
connected from VREF to AGND.
45 VSENSE
This pin senses the output voltage when the device is in pre-bias (or backfeed) mode.
Connect to VOUT if EN_PB is high. Leave this pin floating if EN_PB is pulled to GND.
46 EN_PB
Monotonic start-up with pre-bias is enabled by either pulling this pin high or letting it float. A
logical low on this pin will disable pre-bias mode operation.
47 FQADJ
Optimized frequency adjust pin. Connect a 3.57k resistor from this pin to AGND to optimize
on switching frequency.
48 VDDQOK
This is an active high input pin that indicates the externally supplied VDDQ input has reached
its POK level. This pin should be tied to the VDDQ regulator POK output. It has an internal
pull-up, and can be left floating if not needed.
49-52 NC(SW)
No Connect – these pins are internally connected to the common switching node of the
internal MOSFETs. They are not to be electrically connected to any external signal, ground,
or voltage. Failure to follow these guidelines may result in damage to the device.
55
Thermal
Pad
(PGND)
Not a perimeter pin. Device thermal pad and PGND. Connected to the system ground plane.
See Layout Recommendations section.
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Absolute Maximum Rati ngs
CAUTION: Absolute Maximum ratings are stress ratings only. Functional operation beyond the recommended operating
conditions is not implied. Stress beyond the absolute maximum ratings may impair device life. Exposure to absolute
maximum rated conditions for extended periods may affect device reliability.
PARAMETER SYMBOL MIN MAX UNITS
Input Supply Voltage: AVIN1, AVIN2 VIN -0.5 4.0 V
Voltages on: ENABLE, EN_PB, VDDQOK -0.5 VIN V
Voltages on: VFB, VREF, EAOUT, VDDQ, VOUT, VSENSE,
FQADJ -0.5 2.7 V
Voltage on: POK 3.6 V
Voltage on: SW -0.5 VDDQ+0.5 V
Storage Temperature Range TSTG -65 150 °C
Maximum Operating Junction Temperature TJ-ABS Max 150 °C
Reflow Temp, 10 Sec, MSL3 JEDEC J-STD-020A 260 °C
ESD Rating (based on Human Body Model) 2000 V
ESD Rating (based on CDM) 500 V
Recommended Operating Conditions
PARAMETER SYMBOL MIN MAX UNITS
Input Voltage Range: AVIN1, AVIN2 2.9 3.7 V
Input Voltage Range: VDDQ 1.0 1.8 V
Input Voltage Range: VREF VEXTREF 0.4 0.72 V
EN_PB, VDDQOK, EN 0 AVIN V
Operating Ambient Temperature TA - 40 +85 °C
Operating Junction Temperature TJ - 40 +125 °C
Thermal Characteristics
PARAMETER SYMBOL TYP UNITS
Thermal Resistance: Junction to Ambient (0 LFM) (Note 1) JA 22 °C/W
Thermal Resistance: Junction to Case (0 LFM) JC 2 °C/W
Thermal Shutdown TSD 150 °C
Thermal Shutdown Hysteresis TSDH 20 °C
Note 1: Based on 2oz. external copper layers and proper thermal design in line with EIA/JEDEC JESD51-7
standard for high thermal conductivity boards.
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Electrical Characteristics
NOTE: AVIN1, AVIN2 = 3.3V, over operating temperature range unless otherwise noted. Typical values are at TA = 25°C.
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Input Power Supply
Voltage VDDQ 1.0 1.8 V
Controller Supply
Voltage AVIN 2.9 3.3 3.7 V
Under Voltage Lock-out
– AVIN Rising VUVLOR Voltage above which UVLO is not
asserted 2.3 V
Under Voltage Lock-out
– AVIN Falling VUVLOF Voltage below which UVLO is asserted 2.1 V
Controller Input Current IAVIN AVIN = 3.3V 12 20 mA
Shut-Down VDDQ
Current ISD_VDDQ ENABLE = 0 150 µA
Shut-Down AVIN
Current ISD_AVIN ENABLE = 0 900 µA
VREF Pin Current 20nA
Output Voltage
Accuracy – Initial VOUT
VOUT =1/2 VDDQ
(e.g. @ VDDQ = 1.500V), 0.1% VREF
and VOUT resistor dividers)
0.740 0.750 0.760 V
VFB Pin Voltage VVFB 2.9V AVIN 3.7V, VREF=600mV,
0A ILOAD 5A 591 600 609 mV
VFB Pin Input Leakage
Current IVFB VFB pin input leakage current 20 nA
Continuous Output
Sourcing Current IOUT_SRC 0 5 A
Continuous Output
Sinking Current IOUT_SNK 0 5 A
Over Current Trip Level IOCPH Sourcing. VDDQ = 1.35V 11 A
Switching Frequency FSW R
FQADJ = 3.57kOhms 1.5 MHz
Frequency Adjust
Resistor RFQADJ 3.57 k
Pre-Bias Level VPB
Allowable pre-bias as a fraction of
programmed output voltage for monotonic
start up
20 85 %
Non-Monotonicity VPB_NM Allowable non-monotonicity under pre-
bias start up 50 mV
VOUT Range for POK =
High Range of output voltage as a fraction of
programmed value when POK is asserted 92 110 %
POK Deglitch Delay Falling edge deglitch delay after output
crossing 90% level 64 Clock
cycles
VPOK Output Low Level With 4mA current sink into POK pin 0.6 V
VPOK Output High Level
When pulled up to AVIN (3.3V) with RPOK
= 100k;
VPOK = AVIN * (196k/(RPOK + 196k);
2.2 V
POK Current Sink
Capability 2.9V AVIN 3.7V 4 mA
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PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Enable Threshold VENABLE 2.9V AVIN 3.7 V; Min voltage to
ensure the converter is enabled 1.3 V
Disable Threshold VDISABLE Max voltage to ensure the converter is
disabled 0.8 V
Enable Pin Current IEN AVIN = 3.6V 50 A
Binary Pin Logic Low
Threshold VB-LOW VDDQOK, EN_PB 0.8 V
Binary Pin Logic High
Threshold VB-HIGH VDDQOK, EN_PB 1.8 V
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Typical Performance Curves
0
10
20
30
40
50
60
70
80
90
100
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
EFFICIENCY (%)
OUTPUT CURRENT (A)
EFFICIENCY vs. OUTPUT CURRENT
VOUT = 0.6V
CONDITIONS
AVIN = 3.3V
VDDQ = 2*V
OUT
CONDITIONS
AVIN = 3.3V
VDDQ = 1.8V
CONDITIONS
AVIN = 3.3V
VDDQ = 1.5V
CONDITIONS
AVIN = 3.3V
VDDQ = 1.8V
0
10
20
30
40
50
60
70
80
90
100
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EFFICIENCY (%)
OUTPUT CURRENT (A)
EF FICIENCY vs. OUTPUT CURRENT
VOUT = 0.675V
CONDITIONS
AVIN = 3.3V
VDDQ = 2*V
OUT
CONDITIONS
AVIN = 3.3V
VDDQ = 1.8V
0
10
20
30
40
50
60
70
80
90
100
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
EFFICIENCY (%)
OUTPUT CURRENT (A)
EFFI CIENCY vs. OUTPUT CURRENT
VOUT = 0.75V
CONDITIONS
AVIN = 3.3V
VDDQ = 2*V
OUT
0
10
20
30
40
50
60
70
80
90
100
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EFFICIENCY (%)
OUTPUT CURRENT (A)
EFF ICIENCY vs. OUTPUT CURRENT
VOUT = 1.5V
CONDITIONS
AVIN = 3.3V
VDDQ = 1.8V
0
10
20
30
40
50
60
70
80
90
100
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EFFICIENCY (%)
OUTPUT CURRENT (A)
EFFICIENCY vs. OUTPUT CURRENT
VOUT = 1.2V
CONDITIONS
AVIN = 3.3V
VDDQ = 1.5V
CONDITIONS
AVIN = 3.3V
VDDQ = 1.8V
0.56
0.57
0.58
0.59
0.6
0.61
0.62
0.63
0.64
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
OUTPUT VOLTAGE (V)
OUTPUT CURRENT (A)
VO UT v s. IOU T
VOUT = 0.6V
CONDITIONS
VDDQ = 2*V
OUT
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Typical Performance Curves (Continued)
0.63
0.645
0.66
0.675
0.69
0.705
0.72
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
OUTPUT VOLT AGE (V)
OUTPUT CURRENT (A)
VO UT v s. IOU T
VOUT = 0.675V
CONDITIONS
VDDQ = 2*V
OUT
CONDITIONS
VDDQ = 2*V
OUT
0.705
0.72
0.735
0.75
0.765
0.78
0.795
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
OUTPUT VOLTAGE (V)
OUTPUT CURRENT (A)
VO UT v s. IOU T
VOUT = 0.75V
CONDITIONS
VDDQ = 2*V
OUT
1.16
1.17
1.18
1.19
1.20
1.21
1.22
1.23
1.24
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
OUTPUT VOLTAGE (V)
OUTPUT CURRENT (A)
VO UT v s. IOU T
VOUT = 1.2V
CONDITIONS
VDDQ = 1.5V
AVIN = 3.3V
1.46
1.47
1.48
1.49
1.5
1.51
1.52
1.53
1.54
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
OUTPUT VOLT AGE (V)
OUTPUT CURRENT (A)
VO UT v s. IOU T
VOUT = 1.5V
CONDITIONS
VDDQ = 1.8V
AVIN = 3.3V
0.635
0.645
0.655
0.665
0.675
0.685
0.695
0.705
0.715
-40 -25 -10 5 20 35 50 65 80 95 110 125
OUTPUT VOLT AGE (V)
JU NCTION TEMPER AT URE ( C)
VOUT v s. TEMPERATURE
LOAD = 0A CONDITIONS
VOUT = 0.675V
VDDQ = 2*V
OUT
AVIN = 3.3V
0.635
0.645
0.655
0.665
0.675
0.685
0.695
0.705
0.715
-40 -25 -10 5 20 35 50 65 80 95 110 125
OUTPUT VOLT AGE (V)
JUNCTION TEMPERA TURE ( C)
VOU T v s. TEMPER ATUR E
LOAD = 1A CONDITIONS
VOUT = 0.675V
VDDQ = 2*V
OUT
AVIN = 3.3V
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Typical Performance Characteristics
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Typical Performance Characteristics (Continued)
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Functional Block Diagram
(+)
(-)
Error
Amp
VOUT
HS-Drive
LS-Drive
UVLO
Thermal Limit
Current Limit
Soft Start
Pre-bias
Sawtooth
Generator
(+)
(-)
PWM
Comp
VDDQ
ENABLE
Compensation
Network
Bandgap
Reference
PGND
VFB
EAOUT
VREF
Power
Good
Logic
POK
EAOUT
EN_PB
NC(SW)
AVIN
AVIN
VSENSE
EV1340QI
FQADJ
AVINAGND
VDDB
VDDQOK
VDDQ
2.5V
196k
94k
2k
18.8k
Figure 4: Functional Block Diagram
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Functional Description
Synchronous Buck Converte r
The EV1340 is a synchronous, programmable
buck power supply with integrated power
MOSFET switches and integrated inductor.
The switching supply uses voltage mode
control and a low noise PWM topology. Two
power sources are required to operate this
device; a power supply for the controller (AVIN)
with a nominal input voltage range of 2.9-3.7V.
The second supply (VDDQ) is the supply that
is tracked - the recommended operating range
is 1.0 to 1.8V. With the right choice of input and
output dividers, the output voltage of the
EV1340 will produce an output voltage which
tracks to ½ VDDQ. The EV1340 can
continuously source or sink currents up to 5A.
The 1.5MHz nominal switching frequency
enables small-size input and output capacitors.
Enable Operation
The ENABLE pin provides a means to enable
normal operation or to shut down the device.
When the ENABLE pin is asserted (high) the
device will undergo a normal soft-start. A logic
low on this pin will power the device down.
Soft-Start and Soft-Shutdown
The EV1340 can operate with the controller
power supply (AVIN) ON, ENABLE High, and
VDDQ ramped up and down at a relatively
slow rate (~1V/ms). It is also expected that
VDDQ may be dynamically scaled within a
small voltage range. If, however, VDDQ should
ramp up at a high rate, or if the device is
enabled with a stable VDDQ, a capacitor
connected between VREF and AGND provides
the soft-start function to limit in-rush current.
The soft-start time constant is determined by
the input voltage divider and the soft-start
capacitor. See Figure 5.
Pre-Bias Start-up
The EV1340 supports start up into a pre-
biased load. A proprietary circuit ensures the
output voltage ramps up monotonically from
the pre-bias value to the programmed output
voltage. Monotonic start-up is guaranteed for
pre-bias voltages in the range of >20% to
<85% of the programmed output voltage.
Outside of this range, the output voltage may
not rise monotonically. The Pre-Bias feature is
controlled by the EN_PB pin. For the pre-Bias
feature to function properly, VDDQ must be
stable, and the device must be turned on and
off using the ENABLE pin.
VDDQOK Operation
The VDDQOK pin can be used to indicate that
the VDDQ voltage is in regulation by tying it to
an upstream POK signal. The upstream device
is assumed to be driving the EV1340QI.
VDDQOK is internally pulled up to 2.5V
through a 94k resistor and is AND’ed with the
POK of the EV1340QI. The VDDQOK’s high
logic level voltage is clamped at a diode drop
above 2.5V. VDDQOK signal must be high in
order for the POK of the EV1340QI to be high.
POK Operation
The internal EV1340 POK is AND’ed with the
VDDQOK input. POK is meant to be used with
VDDQOK in a tracking application with VDDQ
ramping. The VDDQOK input is assumed to be
driven by the upstream VDDQ regulator’s POK
output. Normally the VDDQOK input indicates
that VDDQ has settled to the required level. If
VDDQ is dynamically switched, VDDQOK is
expected to mask the EV1340 POK during the
voltage transition. POK is de-asserted low 64
clock cycles (~43µs at 1.5MHz) after the falling
VOUT voltage crosses 45% (nominal) of
VDDQ. POK is also de-asserted if VOUT
exceeds 55% (nominal) of VDDQ. For proper
POK thresholds, the input voltage divider must
generate VREF nominally set to 0.4*VDDQ.
Over-Current Prote ction
The current limit function is achieved by
sensing the current flowing in the hi-Side FET.
When the sensed current exceeds the current
limit, the PWM pulse is terminated for the rest
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of the switching cycle. If the over-current
condition lasts only a few switching cycles,
normal PWM operation is resumed. If the over-
current condition persists, the circuit will
continue to protect the load by entering a
hiccup mode. In the hiccup mode, the output is
disabled for approximately 20ms and then it
goes through a soft-start. The output will no
longer track the input voltage briefly as a result
of the fault condition. This cycle can continue
indefinitely as long as the over current
condition persists.
Thermal Overload Protection
Temperature sensing circuits in the controller
will disable operation when the Junction
temperature exceeds approximately 150ºC.
When the junction temperature drops by
approx 20ºC, the converter will re-start with a
normal soft-start cycle.
Input Under-Voltage Lock-Out
When the AVIN pin voltage is below a required
voltage level (VUVLOR) for normal operation,
converter switching is inhibited. The lock-out
threshold has hysteresis to prevent chatter.
When the device is operating normally, the
AVIN voltage must fall below the lower
threshold (VUVLOF) for the device to stop
switching.
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Application Information
Soft-Start Capacitor Selection
A soft-start capacitor is recommended on the
EV1340’s VREF pin to ground. The soft-start
capacitor (CSS) serves as a slew rate limiter for
fast VDDQ input ramps or for turning the
device ON using the ENABLE pin. It is also a
noise filter for noise coming from VDDQ. The
soft-start time constant is determined by the
value of this capacitor and the input divider
resistors RC and RD. See Figure 5. Altera
recommends a starting value of 3300pF for the
soft-start capacitor on the VREF node.
Output Voltage Programming and Loop
Compensation
The output voltage of EV1340QI is determined
by the two voltage dividers as shown in the
simplified application diagram below:
Figure 5: Typical Application Schematic
The input voltage divider consisting of RC and
RD should be selected to make VREF = 0.4 *
VDDQ for proper POK operation. Altera
recommends RC = 15k and RD = 10k. This
resistor ratio is essential for proper operation of
POK. In steady state, VREF = VFB, and VOUT
= 0.5*VDDQ given the recommended values
for RA RD.
Although the EV1340 integrates most of the
compensation network, a phase lead capacitor
and a resistor are required in parallel with the
upper resistor RA of the external feedback
network. See Figure 6 for all the component
values in the compensation circuit, which has
been optimized for use with 2X100F, 1206,
X5R or X7R ceramic output capacitors.
In rare cases, modifications to the
compensation might be required. The EV1340
compensation can be modified for specific
applications. For more information, contact
Power Applications support.
Figure 6: External Feedback and Compensation Network
Input Capacitor Selection
The EV1340 requires a minimum of 47µF of
input capacitance for VDDQ. Additional
capacitors (CAVIN and C1) of 10µF is
recommended for AVIN and the resistor divider
network of VREF (RC, RD). Low ESR ceramic
capacitors are required with X5R or X7R
dielectric formulation. Y5V or equivalent
dielectric formulations must not be used
because these dielectrics lose capacitance
with frequency, temperature and bias voltage.
In some applications, lower value ceramic
capacitors maybe needed in parallel with the
larger capacitors in order to provide high
frequency decoupling.
The table below shows some typical
recommended input capacitors for the EV1340.
Other capacitors with similar characteristics
may also be used in the input circuit.
Typical Recommended Input Capacitors
Description MFG P/N
47µF, 10V,
X5R, 1206 Taiyo
Yuden LMK316BJ476ML-T
47µF, 4V,
X5R, 0805 Murata GRM21BR60G476M
AB
A
A
A
RR
kR
R
C
VDDQR
4
3
value.calculated
than lower valuestandard
closest todown C Round
)F/in /R(C
105
)kin (value100
1
A
AA
6
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Output Capacitor Selection
The EV1340 has been optimized for use with
200µF of output capacitance. Low ESR
ceramic capacitors are required with X5R or
X7R dielectric formulation. Y5V or equivalent
dielectric formulations must not be used as
these lose capacitance with frequency,
temperature and bias voltage. The capacitors
shown in the table below are some typical
output capacitors. Other capacitors with similar
characteristics may also be used.
Typical Recommended Output Capacitors
Description MFG P/N
47µF, 10V,
X5R, 1206 Taiyo
Yuden LMK316BJ476ML-T
47µF, 6.3V,
X5R, 1206
Taiyo
Yuden
Murata JMK316BJ476ML-T
GRM31CR60J476ME19L
100µF, 6.3V,
X5R, 1206
Murata
GRM31CR60J107M
Output ripple voltage is primarily determined by
the aggregate output capacitor impedance. At
the 1.5MHz switching frequency output
impedance, denoted as Z, is comprised mainly
of effective series resistance, ESR, and
effective series inductance, ESL:
Z = ESR + ESL
Placing multiple capacitors in parallel reduces
the impedance and hence will result in lower
ripple voltage.
nTotal ZZZZ 1
...
111
21
Typical Ripple Voltages
Output Capacitor
Configuration Typical Output Ripple (mVp-p)
VDDQ = 1.5V, VOUT = 0.75V
2 x 100 µF <10mV
Schottky Diode Selection
The EV1340 requires a Schottky diode from
the SW pin to the VDDQ pin. The anode
should be facing the SW pin and the cathode
facing the VDDQ pin. Altera has characterized
the ST Microelectronics TMBYV10-40FILM
diode with the EV1340. Contact Power
Applications support for alternate options for
this diode.
Low VIN Applications
The EV1340 is an excellent solution for low VIN
applications where highest efficiency is very
critical. Reference the low VIN efficiency chart
in the Typical Performance Characteristics
section for estimated efficiencies at several use
cases. In these applications, a precision
voltage reference is required for the VREF
input of the EV1340. Figure 7 shows a
schematic for a typical low VIN application.
Figure 7: Typical Low VIN Application Schematic
Power-Up Sequencing
During power up, neither ENABLE nor VDDQ
should be asserted before AVIN. There are two
common acceptable turn-on/off sequences for
the device. ENABLE can be tied to AVIN and
come up with it, and VDDQ can be ramped up
and down as needed. Alternatively, VDDQ can
be brought high after AVIN is asserted, and the
device can be turned on and off by toggling the
ENABLE pin.
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Layout Recommendations
Figure 8 and Figure 9 shows critical
components along with top and bottom traces
of a recommended minimum footprint of the
EV1340QI layout with ENABLE tied to VIN.
Alternate ENABLE configurations and other
small signal pins need to be connected and
routed according to specific customer
application. Please see the Gerber files at
www.altera.com/enpirion for exact dimensions
and other layers. Please refer to Figures 8 and
9 while reading the layout recommendations in
this section.
Recommendation 1: Input and output filter
capacitors should be placed on the same side
of the PCB, and as close to the EV1340QI
package as possible. They should be
connected to the device with very short and
wide traces. Do not use thermal reliefs or
spokes when connecting the capacitor pads to
the respective nodes. The +V and GND traces
between the capacitors and the EV1340QI
should be as close to each other as possible
so that the gap between the two nodes is
minimized, even under the capacitors.
Recommendation 2: There are a total of
seven PGND pins dedicated to the input and
output circuits. The input and output ground
currents should be separated with a slit until
they reach the seven PGND pins to help
minimize noise coupling between the converter
input and output switching loops.
Recommendation 3: The system ground
plane should be the first layer immediately
below the surface layer. This ground plane
should be continuous and un-interrupted below
the converter and the input/output capacitors.
Please see the Gerber files at
www.altera.com/enpirion.
Recommendation 4: The large thermal pad
underneath the component must be connected
to the system ground plane through as many
vias as possible.
Figure 8: Top PCB Layer with Critical
Components and Copper for
Minimum Footprint (Top View)
Figure 9: Bottom PCB Layer with Critical
Components and Copper for
Minimum Footprint (Top View)
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The drill diameter of the vias should be
0.33mm, and the vias must have at least 1 oz.
copper plating on the inside wall, making the
finished hole size around 0.20-0.26mm. Do not
use thermal reliefs or spokes to connect the
vias to the ground plane. This connection
provides the path for heat dissipation from the
converter. Please see Figures 8, 9, 10, and 11.
Recommendation 5: Multiple small vias (the
same size as the thermal vias discussed in
recommendation 4 should be used to connect
ground terminal of the input capacitor and
output capacitors to the system ground plane.
It is preferred to put these vias under the
capacitors along the edge of the GND copper
closest to the +V copper. Please see Figure 8
and Figure 9. These vias connect the
input/output filter capacitors to the GND plane
and help reduce parasitic inductances in the
input and output current loops. If the vias
cannot be placed under CIN and COUT, then put
them just outside the capacitors along the GND
slit separating the two components. Do not use
thermal reliefs or spokes to connect these vias
to the ground plane.
Recommendation 6: AVIN1 and AVIN2 are
the power supplies for the internal small-signal
control circuits. AVIN1 and AVIN2 should be
powered by an external supply. In Figure 8,
the filter capacitor CAVIN is connected closely
from the AVIN1 and AVIN2 pins to AGND for
proper filtering of the control circuit.
Recommendation 7: The layer 1 metal under
the device must not be more than shown in
Figure 8. See the section regarding exposed
metal on bottom of package. As with any
switch-mode DC/DC converter, try not to run
sensitive signal or control lines underneath the
converter package on other layers.
Recommendation 8: The VOUT sense trace to
RA should come just after the last output filter
capacitor COUT2. Keep the sense trace as
short as possible in order to avoid noise
coupling into the control loop.
Recommendation 9: Keep RA, CA, R1 and RB
close to the VFB pin (see Figure 8). The VFB
pin is a high-impedance, sensitive node. Keep
the trace to this pin as short as possible.
Whenever possible, connect RB directly to the
AGND pin instead of going through the GND
plane.
Recommendation 10: Connect AGND to the
ground plane through a single via as close to
the AGND pin as possible. This establishes the
connection between AGND and PGND.
Recommendation 11: The VREF pin sets the
reference voltage for VOUT and should be as
clean as possible. The connection from VDDQ
to VREF should begin from the CIN input
capacitor to VREF through a resistor voltage
divider (RC, RD). The soft-start capacitor CSS,
RC, and RD form a low-pass RC filter for the
VREF pin. A bypass capacitor C1 should be
placed close to the RC resistor for additional
filtering. The long trace from VDDQ to C1
forms a low-pass LC filter with C1 and helps
further reduce noise coupling to VREF.
Recommendation 12: The Schottky diode D1
should be connected with anode to SW and
cathode to VDDQ with very low inductance
traces. Place D1 directly under the device as
shown in Figure 9. Vias near SW and VDDQ
connect these pins to the D1 terminals. The
recommended diode for this layout is ST
Microelectronics TMBYV10-40FILM. Contact
Power Applications support for alternate
options for this diode.
Recommendation 13: Altera provides
schematic and layout reviews for all customer
designs. It is highly recommended for all
customers to take advantage of this service.
Please send pdf schematic files and Gerber
layout files of the power section to your local
sales contact or to Power Applications support.
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Design Considerations for Lead-Frame Based Modules
Exposed Metal on Bottom of Pac ka ge
Package lead frames offer advantages in
thermal performance, in reduced electrical lead
resistance, and in overall foot print. They do,
however, require some special considerations.
In the assembly process, lead-frame
construction requires-for mechanical support-
that some of the lead-frame cantilevers be
exposed at the point where wire-bonds or
internal passives are attached. Because of this
lead frame requirement, several small pads are
exposed on the bottom of the package. Only
the large thermal pad and the perimeter pads
should be mechanically or electrically
connected to the PC board. The PCB top layer
under the EV1340 should be clear of any metal
except for the large thermal pad. The hatched
area in Figure 10 represents the area that
should be clear of all metal (traces, vias, or
planes) on the top layer of the PCB.
Figure 10: Lead-Frame Exposed Metal (Bottom View). The dimensioned hatched area highlights
exposed metal below the device which should not be soldered down. There should not be any metal
(traces, vias, or planes) on the top layer of the PCB below the hatched area.
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Recommended PCB Footprint
Figure 11: EV1340QI PCB Footprint (Top View)
The solder stencil aperture for the thermal pad is shown in blue and is based on Enpirion power product manufacturing
specifications.
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Package and Mechanical
Figure 12: EV1340 Package Dimensions
Contact Information
Altera Corporation
101 Innovation Drive
San Jose, CA 95134
Phone: 408-544-7000
www.altera.com/
© 2013 Altera Corporation—Confidential. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, HARDCOPY, MAX, MEGACORE, NIOS,
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countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at
www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's
standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or
liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera.
Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders
for products or services.
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